1 /* 2 * ASPEED GPIO Controller 3 * 4 * Copyright (C) 2017-2019 IBM Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include <assert.h> 10 11 #include "qemu/osdep.h" 12 #include "qemu/host-utils.h" 13 #include "qemu/log.h" 14 #include "hw/gpio/aspeed_gpio.h" 15 #include "include/hw/misc/aspeed_scu.h" 16 #include "qapi/error.h" 17 #include "qapi/visitor.h" 18 #include "hw/irq.h" 19 #include "migration/vmstate.h" 20 21 #define GPIOS_PER_REG 32 22 #define GPIOS_PER_SET GPIOS_PER_REG 23 #define GPIO_PIN_GAP_SIZE 4 24 #define GPIOS_PER_GROUP 8 25 #define GPIO_GROUP_SHIFT 3 26 27 /* GPIO Source Types */ 28 #define ASPEED_CMD_SRC_MASK 0x01010101 29 #define ASPEED_SOURCE_ARM 0 30 #define ASPEED_SOURCE_LPC 1 31 #define ASPEED_SOURCE_COPROCESSOR 2 32 #define ASPEED_SOURCE_RESERVED 3 33 34 /* GPIO Interrupt Triggers */ 35 /* 36 * For each set of gpios there are three sensitivity registers that control 37 * the interrupt trigger mode. 38 * 39 * | 2 | 1 | 0 | trigger mode 40 * ----------------------------- 41 * | 0 | 0 | 0 | falling-edge 42 * | 0 | 0 | 1 | rising-edge 43 * | 0 | 1 | 0 | level-low 44 * | 0 | 1 | 1 | level-high 45 * | 1 | X | X | dual-edge 46 */ 47 #define ASPEED_FALLING_EDGE 0 48 #define ASPEED_RISING_EDGE 1 49 #define ASPEED_LEVEL_LOW 2 50 #define ASPEED_LEVEL_HIGH 3 51 #define ASPEED_DUAL_EDGE 4 52 53 /* GPIO Register Address Offsets */ 54 #define GPIO_ABCD_DATA_VALUE (0x000 >> 2) 55 #define GPIO_ABCD_DIRECTION (0x004 >> 2) 56 #define GPIO_ABCD_INT_ENABLE (0x008 >> 2) 57 #define GPIO_ABCD_INT_SENS_0 (0x00C >> 2) 58 #define GPIO_ABCD_INT_SENS_1 (0x010 >> 2) 59 #define GPIO_ABCD_INT_SENS_2 (0x014 >> 2) 60 #define GPIO_ABCD_INT_STATUS (0x018 >> 2) 61 #define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2) 62 #define GPIO_EFGH_DATA_VALUE (0x020 >> 2) 63 #define GPIO_EFGH_DIRECTION (0x024 >> 2) 64 #define GPIO_EFGH_INT_ENABLE (0x028 >> 2) 65 #define GPIO_EFGH_INT_SENS_0 (0x02C >> 2) 66 #define GPIO_EFGH_INT_SENS_1 (0x030 >> 2) 67 #define GPIO_EFGH_INT_SENS_2 (0x034 >> 2) 68 #define GPIO_EFGH_INT_STATUS (0x038 >> 2) 69 #define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2) 70 #define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2) 71 #define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2) 72 #define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2) 73 #define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2) 74 #define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2) 75 #define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2) 76 #define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2) 77 #define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2) 78 #define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2) 79 #define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2) 80 #define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2) 81 #define GPIO_IJKL_DATA_VALUE (0x070 >> 2) 82 #define GPIO_IJKL_DIRECTION (0x074 >> 2) 83 #define GPIO_MNOP_DATA_VALUE (0x078 >> 2) 84 #define GPIO_MNOP_DIRECTION (0x07C >> 2) 85 #define GPIO_QRST_DATA_VALUE (0x080 >> 2) 86 #define GPIO_QRST_DIRECTION (0x084 >> 2) 87 #define GPIO_UVWX_DATA_VALUE (0x088 >> 2) 88 #define GPIO_UVWX_DIRECTION (0x08C >> 2) 89 #define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2) 90 #define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2) 91 #define GPIO_IJKL_INT_ENABLE (0x098 >> 2) 92 #define GPIO_IJKL_INT_SENS_0 (0x09C >> 2) 93 #define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2) 94 #define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2) 95 #define GPIO_IJKL_INT_STATUS (0x0A8 >> 2) 96 #define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2) 97 #define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2) 98 #define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2) 99 #define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2) 100 #define GPIO_ABCD_DATA_READ (0x0C0 >> 2) 101 #define GPIO_EFGH_DATA_READ (0x0C4 >> 2) 102 #define GPIO_IJKL_DATA_READ (0x0C8 >> 2) 103 #define GPIO_MNOP_DATA_READ (0x0CC >> 2) 104 #define GPIO_QRST_DATA_READ (0x0D0 >> 2) 105 #define GPIO_UVWX_DATA_READ (0x0D4 >> 2) 106 #define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2) 107 #define GPIO_AC_DATA_READ (0x0DC >> 2) 108 #define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2) 109 #define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2) 110 #define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2) 111 #define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2) 112 #define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2) 113 #define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2) 114 #define GPIO_MNOP_INT_STATUS (0x0F8 >> 2) 115 #define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2) 116 #define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2) 117 #define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2) 118 #define GPIO_MNOP_INPUT_MASK (0x108 >> 2) 119 #define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2) 120 #define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2) 121 #define GPIO_QRST_INT_ENABLE (0x118 >> 2) 122 #define GPIO_QRST_INT_SENS_0 (0x11C >> 2) 123 #define GPIO_QRST_INT_SENS_1 (0x120 >> 2) 124 #define GPIO_QRST_INT_SENS_2 (0x124 >> 2) 125 #define GPIO_QRST_INT_STATUS (0x128 >> 2) 126 #define GPIO_QRST_RESET_TOLERANT (0x12C >> 2) 127 #define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2) 128 #define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2) 129 #define GPIO_QRST_INPUT_MASK (0x138 >> 2) 130 #define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2) 131 #define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2) 132 #define GPIO_UVWX_INT_ENABLE (0x148 >> 2) 133 #define GPIO_UVWX_INT_SENS_0 (0x14C >> 2) 134 #define GPIO_UVWX_INT_SENS_1 (0x150 >> 2) 135 #define GPIO_UVWX_INT_SENS_2 (0x154 >> 2) 136 #define GPIO_UVWX_INT_STATUS (0x158 >> 2) 137 #define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2) 138 #define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2) 139 #define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2) 140 #define GPIO_UVWX_INPUT_MASK (0x168 >> 2) 141 #define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2) 142 #define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2) 143 #define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2) 144 #define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2) 145 #define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2) 146 #define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2) 147 #define GPIO_YZAAAB_INT_STATUS (0x188 >> 2) 148 #define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2) 149 #define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2) 150 #define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2) 151 #define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2) 152 #define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2) 153 #define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2) 154 #define GPIO_AC_INT_ENABLE (0x1A8 >> 2) 155 #define GPIO_AC_INT_SENS_0 (0x1AC >> 2) 156 #define GPIO_AC_INT_SENS_1 (0x1B0 >> 2) 157 #define GPIO_AC_INT_SENS_2 (0x1B4 >> 2) 158 #define GPIO_AC_INT_STATUS (0x1B8 >> 2) 159 #define GPIO_AC_RESET_TOLERANT (0x1BC >> 2) 160 #define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2) 161 #define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2) 162 #define GPIO_AC_INPUT_MASK (0x1C8 >> 2) 163 #define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2) 164 #define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2) 165 #define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2) 166 #define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2) 167 #define GPIO_AC_DATA_VALUE (0x1E8 >> 2) 168 #define GPIO_AC_DIRECTION (0x1EC >> 2) 169 #define GPIO_3_6V_MEM_SIZE 0x1F0 170 #define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2) 171 172 static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) 173 { 174 uint32_t falling_edge = 0, rising_edge = 0; 175 uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1) 176 | extract32(regs->int_sens_1, gpio, 1) << 1 177 | extract32(regs->int_sens_2, gpio, 1) << 2; 178 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); 179 uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1); 180 181 if (!gpio_int_enabled) { 182 return 0; 183 } 184 185 /* Detect edges */ 186 if (gpio_curr_high && !gpio_prev_high) { 187 rising_edge = 1; 188 } else if (!gpio_curr_high && gpio_prev_high) { 189 falling_edge = 1; 190 } 191 192 if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) || 193 ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) || 194 ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) || 195 ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) || 196 ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge))) 197 { 198 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); 199 return 1; 200 } 201 return 0; 202 } 203 204 #define nested_struct_index(ta, pa, m, tb, pb) \ 205 (pb - ((tb *)(((char *)pa) + offsetof(ta, m)))) 206 207 static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs) 208 { 209 return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs); 210 } 211 212 static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, 213 uint32_t value) 214 { 215 uint32_t input_mask = regs->input_mask; 216 uint32_t direction = regs->direction; 217 uint32_t old = regs->data_value; 218 uint32_t new = value; 219 uint32_t diff; 220 int gpio; 221 222 diff = old ^ new; 223 if (diff) { 224 for (gpio = 0; gpio < GPIOS_PER_REG; gpio++) { 225 uint32_t mask = 1 << gpio; 226 227 /* If the gpio needs to be updated... */ 228 if (!(diff & mask)) { 229 continue; 230 } 231 232 /* ...and we're output or not input-masked... */ 233 if (!(direction & mask) && (input_mask & mask)) { 234 continue; 235 } 236 237 /* ...then update the state. */ 238 if (mask & new) { 239 regs->data_value |= mask; 240 } else { 241 regs->data_value &= ~mask; 242 } 243 244 /* If the gpio is set to output... */ 245 if (direction & mask) { 246 /* ...trigger the line-state IRQ */ 247 ptrdiff_t set = aspeed_gpio_set_idx(s, regs); 248 size_t offset = set * GPIOS_PER_SET + gpio; 249 qemu_set_irq(s->gpios[offset], !!(new & mask)); 250 } else { 251 /* ...otherwise if we meet the line's current IRQ policy... */ 252 if (aspeed_evaluate_irq(regs, old & mask, gpio)) { 253 /* ...trigger the VIC IRQ */ 254 s->pending++; 255 } 256 } 257 } 258 } 259 qemu_set_irq(s->irq, !!(s->pending)); 260 } 261 262 static uint32_t aspeed_adjust_pin(AspeedGPIOState *s, uint32_t pin) 263 { 264 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 265 /* 266 * The 2500 has a 4 pin gap in group AB and the 2400 has a 4 pin 267 * gap in group Y (and only four pins in AB but this is the last group so 268 * it doesn't matter). 269 */ 270 if (agc->gap && pin >= agc->gap) { 271 pin += GPIO_PIN_GAP_SIZE; 272 } 273 274 return pin; 275 } 276 277 static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx, 278 uint32_t pin) 279 { 280 uint32_t reg_val; 281 uint32_t pin_mask = 1 << pin; 282 283 reg_val = s->sets[set_idx].data_value; 284 285 return !!(reg_val & pin_mask); 286 } 287 288 static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, 289 uint32_t pin, bool level) 290 { 291 uint32_t value = s->sets[set_idx].data_value; 292 uint32_t pin_mask = 1 << pin; 293 294 if (level) { 295 value |= pin_mask; 296 } else { 297 value &= !pin_mask; 298 } 299 300 aspeed_gpio_update(s, &s->sets[set_idx], value); 301 } 302 303 /* 304 * | src_1 | src_2 | source | 305 * |-----------------------------| 306 * | 0 | 0 | ARM | 307 * | 0 | 1 | LPC | 308 * | 1 | 0 | Coprocessor| 309 * | 1 | 1 | Reserved | 310 * 311 * Once the source of a set is programmed, corresponding bits in the 312 * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and 313 * debounce registers can only be written by the source. 314 * 315 * Source is ARM by default 316 * only bits 24, 16, 8, and 0 can be set 317 * 318 * we don't currently have a model for the LPC or Coprocessor 319 */ 320 static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value, 321 uint32_t value) 322 { 323 int i; 324 int cmd_source; 325 326 /* assume the source is always ARM for now */ 327 int source = ASPEED_SOURCE_ARM; 328 329 uint32_t new_value = 0; 330 331 /* for each group in set */ 332 for (i = 0; i < GPIOS_PER_REG; i += GPIOS_PER_GROUP) { 333 cmd_source = extract32(regs->cmd_source_0, i, 1) 334 | (extract32(regs->cmd_source_1, i, 1) << 1); 335 336 if (source == cmd_source) { 337 new_value |= (0xff << i) & value; 338 } else { 339 new_value |= (0xff << i) & old_value; 340 } 341 } 342 return new_value; 343 } 344 345 static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = { 346 /* Set ABCD */ 347 [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value }, 348 [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction }, 349 [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable }, 350 [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 }, 351 [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 }, 352 [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 }, 353 [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status }, 354 [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant }, 355 [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 }, 356 [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 }, 357 [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 }, 358 [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 }, 359 [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read }, 360 [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask }, 361 /* Set EFGH */ 362 [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value }, 363 [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction }, 364 [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable }, 365 [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 }, 366 [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 }, 367 [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 }, 368 [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status }, 369 [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant }, 370 [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 }, 371 [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 }, 372 [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 }, 373 [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 }, 374 [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read }, 375 [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask }, 376 /* Set IJKL */ 377 [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value }, 378 [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction }, 379 [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable }, 380 [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 }, 381 [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 }, 382 [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 }, 383 [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status }, 384 [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant }, 385 [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 }, 386 [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 }, 387 [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 }, 388 [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 }, 389 [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read }, 390 [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask }, 391 /* Set MNOP */ 392 [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value }, 393 [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction }, 394 [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable }, 395 [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 }, 396 [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 }, 397 [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 }, 398 [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status }, 399 [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant }, 400 [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 }, 401 [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 }, 402 [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 }, 403 [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 }, 404 [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read }, 405 [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask }, 406 /* Set QRST */ 407 [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value }, 408 [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction }, 409 [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable }, 410 [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 }, 411 [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 }, 412 [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 }, 413 [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status }, 414 [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant }, 415 [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 }, 416 [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 }, 417 [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 }, 418 [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 }, 419 [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read }, 420 [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask }, 421 /* Set UVWX */ 422 [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value }, 423 [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction }, 424 [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable }, 425 [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 }, 426 [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 }, 427 [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 }, 428 [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status }, 429 [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant }, 430 [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 }, 431 [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 }, 432 [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 }, 433 [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 }, 434 [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read }, 435 [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask }, 436 /* Set YZAAAB */ 437 [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value }, 438 [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction }, 439 [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable }, 440 [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 }, 441 [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 }, 442 [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 }, 443 [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status }, 444 [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant }, 445 [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 }, 446 [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 }, 447 [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 }, 448 [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 }, 449 [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read }, 450 [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask }, 451 /* Set AC (ast2500 only) */ 452 [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value }, 453 [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction }, 454 [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable }, 455 [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 }, 456 [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 }, 457 [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 }, 458 [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status }, 459 [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant }, 460 [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 }, 461 [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 }, 462 [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 }, 463 [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 }, 464 [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read }, 465 [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, 466 }; 467 468 static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) 469 { 470 AspeedGPIOState *s = ASPEED_GPIO(opaque); 471 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 472 uint64_t idx = -1; 473 const AspeedGPIOReg *reg; 474 GPIOSets *set; 475 476 idx = offset >> 2; 477 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 478 idx -= GPIO_DEBOUNCE_TIME_1; 479 return (uint64_t) s->debounce_regs[idx]; 480 } 481 482 reg = &agc->reg_table[idx]; 483 if (reg->set_idx >= agc->nr_gpio_sets) { 484 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 485 HWADDR_PRIx"\n", __func__, offset); 486 return 0; 487 } 488 489 set = &s->sets[reg->set_idx]; 490 switch (reg->type) { 491 case gpio_reg_data_value: 492 return set->data_value; 493 case gpio_reg_direction: 494 return set->direction; 495 case gpio_reg_int_enable: 496 return set->int_enable; 497 case gpio_reg_int_sens_0: 498 return set->int_sens_0; 499 case gpio_reg_int_sens_1: 500 return set->int_sens_1; 501 case gpio_reg_int_sens_2: 502 return set->int_sens_2; 503 case gpio_reg_int_status: 504 return set->int_status; 505 case gpio_reg_reset_tolerant: 506 return set->reset_tol; 507 case gpio_reg_debounce_1: 508 return set->debounce_1; 509 case gpio_reg_debounce_2: 510 return set->debounce_2; 511 case gpio_reg_cmd_source_0: 512 return set->cmd_source_0; 513 case gpio_reg_cmd_source_1: 514 return set->cmd_source_1; 515 case gpio_reg_data_read: 516 return set->data_read; 517 case gpio_reg_input_mask: 518 return set->input_mask; 519 default: 520 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 521 HWADDR_PRIx"\n", __func__, offset); 522 return 0; 523 }; 524 } 525 526 static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, 527 uint32_t size) 528 { 529 AspeedGPIOState *s = ASPEED_GPIO(opaque); 530 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 531 const GPIOSetProperties *props; 532 uint64_t idx = -1; 533 const AspeedGPIOReg *reg; 534 GPIOSets *set; 535 uint32_t cleared; 536 537 idx = offset >> 2; 538 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 539 idx -= GPIO_DEBOUNCE_TIME_1; 540 s->debounce_regs[idx] = (uint32_t) data; 541 return; 542 } 543 544 reg = &agc->reg_table[idx]; 545 if (reg->set_idx >= agc->nr_gpio_sets) { 546 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 547 HWADDR_PRIx"\n", __func__, offset); 548 return; 549 } 550 551 set = &s->sets[reg->set_idx]; 552 props = &agc->props[reg->set_idx]; 553 554 switch (reg->type) { 555 case gpio_reg_data_value: 556 data &= props->output; 557 data = update_value_control_source(set, set->data_value, data); 558 set->data_read = data; 559 aspeed_gpio_update(s, set, data); 560 return; 561 case gpio_reg_direction: 562 /* 563 * where data is the value attempted to be written to the pin: 564 * pin type | input mask | output mask | expected value 565 * ------------------------------------------------------------ 566 * bidirectional | 1 | 1 | data 567 * input only | 1 | 0 | 0 568 * output only | 0 | 1 | 1 569 * no pin / gap | 0 | 0 | 0 570 * 571 * which is captured by: 572 * data = ( data | ~input) & output; 573 */ 574 data = (data | ~props->input) & props->output; 575 set->direction = update_value_control_source(set, set->direction, data); 576 break; 577 case gpio_reg_int_enable: 578 set->int_enable = update_value_control_source(set, set->int_enable, 579 data); 580 break; 581 case gpio_reg_int_sens_0: 582 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, 583 data); 584 break; 585 case gpio_reg_int_sens_1: 586 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, 587 data); 588 break; 589 case gpio_reg_int_sens_2: 590 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, 591 data); 592 break; 593 case gpio_reg_int_status: 594 cleared = ctpop32(data & set->int_status); 595 if (s->pending && cleared) { 596 assert(s->pending >= cleared); 597 s->pending -= cleared; 598 } 599 set->int_status &= ~data; 600 break; 601 case gpio_reg_reset_tolerant: 602 set->reset_tol = update_value_control_source(set, set->reset_tol, 603 data); 604 return; 605 case gpio_reg_debounce_1: 606 set->debounce_1 = update_value_control_source(set, set->debounce_1, 607 data); 608 return; 609 case gpio_reg_debounce_2: 610 set->debounce_2 = update_value_control_source(set, set->debounce_2, 611 data); 612 return; 613 case gpio_reg_cmd_source_0: 614 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; 615 return; 616 case gpio_reg_cmd_source_1: 617 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; 618 return; 619 case gpio_reg_data_read: 620 /* Read only register */ 621 return; 622 case gpio_reg_input_mask: 623 /* 624 * feeds into interrupt generation 625 * 0: read from data value reg will be updated 626 * 1: read from data value reg will not be updated 627 */ 628 set->input_mask = data & props->input; 629 break; 630 default: 631 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 632 HWADDR_PRIx"\n", __func__, offset); 633 return; 634 } 635 aspeed_gpio_update(s, set, set->data_value); 636 return; 637 } 638 639 static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx) 640 { 641 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 642 int set_idx, g_idx = *group_idx; 643 644 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { 645 const GPIOSetProperties *set_props = &agc->props[set_idx]; 646 for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) { 647 if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) { 648 *group_idx = g_idx; 649 return set_idx; 650 } 651 } 652 } 653 return -1; 654 } 655 656 static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, 657 void *opaque, Error **errp) 658 { 659 int pin = 0xfff; 660 bool level = true; 661 char group[3]; 662 AspeedGPIOState *s = ASPEED_GPIO(obj); 663 int set_idx, group_idx = 0; 664 665 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 666 error_setg(errp, "%s: error reading %s", __func__, name); 667 return; 668 } 669 set_idx = get_set_idx(s, group, &group_idx); 670 if (set_idx == -1) { 671 error_setg(errp, "%s: invalid group %s", __func__, group); 672 return; 673 } 674 pin = pin + group_idx * GPIOS_PER_GROUP; 675 level = aspeed_gpio_get_pin_level(s, set_idx, pin); 676 visit_type_bool(v, name, &level, errp); 677 } 678 679 static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, 680 void *opaque, Error **errp) 681 { 682 Error *local_err = NULL; 683 bool level; 684 int pin = 0xfff; 685 char group[3]; 686 AspeedGPIOState *s = ASPEED_GPIO(obj); 687 int set_idx, group_idx = 0; 688 689 visit_type_bool(v, name, &level, &local_err); 690 if (local_err) { 691 error_propagate(errp, local_err); 692 return; 693 } 694 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 695 error_setg(errp, "%s: error reading %s", __func__, name); 696 return; 697 } 698 set_idx = get_set_idx(s, group, &group_idx); 699 if (set_idx == -1) { 700 error_setg(errp, "%s: invalid group %s", __func__, group); 701 return; 702 } 703 pin = pin + group_idx * GPIOS_PER_GROUP; 704 aspeed_gpio_set_pin_level(s, set_idx, pin, level); 705 } 706 707 /****************** Setup functions ******************/ 708 static const GPIOSetProperties ast2400_set_props[] = { 709 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 710 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 711 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 712 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 713 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 714 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 715 [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 716 }; 717 718 static const GPIOSetProperties ast2500_set_props[] = { 719 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 720 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 721 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 722 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 723 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 724 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 725 [6] = {0xffffff0f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 726 [7] = {0x000000ff, 0x000000ff, {"AC"} }, 727 }; 728 729 static const MemoryRegionOps aspeed_gpio_ops = { 730 .read = aspeed_gpio_read, 731 .write = aspeed_gpio_write, 732 .endianness = DEVICE_LITTLE_ENDIAN, 733 .valid.min_access_size = 4, 734 .valid.max_access_size = 4, 735 }; 736 737 static void aspeed_gpio_reset(DeviceState *dev) 738 { 739 AspeedGPIOState *s = ASPEED_GPIO(dev); 740 741 /* TODO: respect the reset tolerance registers */ 742 memset(s->sets, 0, sizeof(s->sets)); 743 } 744 745 static void aspeed_gpio_realize(DeviceState *dev, Error **errp) 746 { 747 AspeedGPIOState *s = ASPEED_GPIO(dev); 748 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 749 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 750 int pin; 751 752 /* Interrupt parent line */ 753 sysbus_init_irq(sbd, &s->irq); 754 755 /* Individual GPIOs */ 756 for (pin = 0; pin < agc->nr_gpio_pins; pin++) { 757 sysbus_init_irq(sbd, &s->gpios[pin]); 758 } 759 760 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, 761 TYPE_ASPEED_GPIO, GPIO_3_6V_MEM_SIZE); 762 763 sysbus_init_mmio(sbd, &s->iomem); 764 } 765 766 static void aspeed_gpio_init(Object *obj) 767 { 768 AspeedGPIOState *s = ASPEED_GPIO(obj); 769 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 770 int pin; 771 772 for (pin = 0; pin < agc->nr_gpio_pins; pin++) { 773 char *name; 774 int set_idx = pin / GPIOS_PER_SET; 775 int pin_idx = aspeed_adjust_pin(s, pin) - (set_idx * GPIOS_PER_SET); 776 int group_idx = pin_idx >> GPIO_GROUP_SHIFT; 777 const GPIOSetProperties *props = &agc->props[set_idx]; 778 779 name = g_strdup_printf("gpio%s%d", props->group_label[group_idx], 780 pin_idx % GPIOS_PER_GROUP); 781 object_property_add(obj, name, "bool", aspeed_gpio_get_pin, 782 aspeed_gpio_set_pin, NULL, NULL, NULL); 783 } 784 } 785 786 static const VMStateDescription vmstate_gpio_regs = { 787 .name = TYPE_ASPEED_GPIO"/regs", 788 .version_id = 1, 789 .minimum_version_id = 1, 790 .fields = (VMStateField[]) { 791 VMSTATE_UINT32(data_value, GPIOSets), 792 VMSTATE_UINT32(data_read, GPIOSets), 793 VMSTATE_UINT32(direction, GPIOSets), 794 VMSTATE_UINT32(int_enable, GPIOSets), 795 VMSTATE_UINT32(int_sens_0, GPIOSets), 796 VMSTATE_UINT32(int_sens_1, GPIOSets), 797 VMSTATE_UINT32(int_sens_2, GPIOSets), 798 VMSTATE_UINT32(int_status, GPIOSets), 799 VMSTATE_UINT32(reset_tol, GPIOSets), 800 VMSTATE_UINT32(cmd_source_0, GPIOSets), 801 VMSTATE_UINT32(cmd_source_1, GPIOSets), 802 VMSTATE_UINT32(debounce_1, GPIOSets), 803 VMSTATE_UINT32(debounce_2, GPIOSets), 804 VMSTATE_UINT32(input_mask, GPIOSets), 805 VMSTATE_END_OF_LIST(), 806 } 807 }; 808 809 static const VMStateDescription vmstate_aspeed_gpio = { 810 .name = TYPE_ASPEED_GPIO, 811 .version_id = 1, 812 .minimum_version_id = 1, 813 .fields = (VMStateField[]) { 814 VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS, 815 1, vmstate_gpio_regs, GPIOSets), 816 VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState, 817 ASPEED_GPIO_NR_DEBOUNCE_REGS), 818 VMSTATE_END_OF_LIST(), 819 } 820 }; 821 822 static void aspeed_gpio_class_init(ObjectClass *klass, void *data) 823 { 824 DeviceClass *dc = DEVICE_CLASS(klass); 825 826 dc->realize = aspeed_gpio_realize; 827 dc->reset = aspeed_gpio_reset; 828 dc->desc = "Aspeed GPIO Controller"; 829 dc->vmsd = &vmstate_aspeed_gpio; 830 } 831 832 static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) 833 { 834 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 835 836 agc->props = ast2400_set_props; 837 agc->nr_gpio_pins = 216; 838 agc->nr_gpio_sets = 7; 839 agc->gap = 196; 840 agc->reg_table = aspeed_3_6v_gpios; 841 } 842 843 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) 844 { 845 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 846 847 agc->props = ast2500_set_props; 848 agc->nr_gpio_pins = 228; 849 agc->nr_gpio_sets = 8; 850 agc->gap = 220; 851 agc->reg_table = aspeed_3_6v_gpios; 852 } 853 854 static const TypeInfo aspeed_gpio_info = { 855 .name = TYPE_ASPEED_GPIO, 856 .parent = TYPE_SYS_BUS_DEVICE, 857 .instance_size = sizeof(AspeedGPIOState), 858 .class_size = sizeof(AspeedGPIOClass), 859 .class_init = aspeed_gpio_class_init, 860 .abstract = true, 861 }; 862 863 static const TypeInfo aspeed_gpio_ast2400_info = { 864 .name = TYPE_ASPEED_GPIO "-ast2400", 865 .parent = TYPE_ASPEED_GPIO, 866 .class_init = aspeed_gpio_ast2400_class_init, 867 .instance_init = aspeed_gpio_init, 868 }; 869 870 static const TypeInfo aspeed_gpio_ast2500_info = { 871 .name = TYPE_ASPEED_GPIO "-ast2500", 872 .parent = TYPE_ASPEED_GPIO, 873 .class_init = aspeed_gpio_2500_class_init, 874 .instance_init = aspeed_gpio_init, 875 }; 876 877 static void aspeed_gpio_register_types(void) 878 { 879 type_register_static(&aspeed_gpio_info); 880 type_register_static(&aspeed_gpio_ast2400_info); 881 type_register_static(&aspeed_gpio_ast2500_info); 882 } 883 884 type_init(aspeed_gpio_register_types); 885