1 /* 2 * ASPEED GPIO Controller 3 * 4 * Copyright (C) 2017-2019 IBM Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/host-utils.h" 11 #include "qemu/log.h" 12 #include "hw/gpio/aspeed_gpio.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "qapi/error.h" 15 #include "qapi/visitor.h" 16 #include "hw/irq.h" 17 #include "migration/vmstate.h" 18 19 #define GPIOS_PER_REG 32 20 #define GPIOS_PER_SET GPIOS_PER_REG 21 #define GPIO_PIN_GAP_SIZE 4 22 #define GPIOS_PER_GROUP 8 23 #define GPIO_GROUP_SHIFT 3 24 25 /* GPIO Source Types */ 26 #define ASPEED_CMD_SRC_MASK 0x01010101 27 #define ASPEED_SOURCE_ARM 0 28 #define ASPEED_SOURCE_LPC 1 29 #define ASPEED_SOURCE_COPROCESSOR 2 30 #define ASPEED_SOURCE_RESERVED 3 31 32 /* GPIO Interrupt Triggers */ 33 /* 34 * For each set of gpios there are three sensitivity registers that control 35 * the interrupt trigger mode. 36 * 37 * | 2 | 1 | 0 | trigger mode 38 * ----------------------------- 39 * | 0 | 0 | 0 | falling-edge 40 * | 0 | 0 | 1 | rising-edge 41 * | 0 | 1 | 0 | level-low 42 * | 0 | 1 | 1 | level-high 43 * | 1 | X | X | dual-edge 44 */ 45 #define ASPEED_FALLING_EDGE 0 46 #define ASPEED_RISING_EDGE 1 47 #define ASPEED_LEVEL_LOW 2 48 #define ASPEED_LEVEL_HIGH 3 49 #define ASPEED_DUAL_EDGE 4 50 51 /* GPIO Register Address Offsets */ 52 #define GPIO_ABCD_DATA_VALUE (0x000 >> 2) 53 #define GPIO_ABCD_DIRECTION (0x004 >> 2) 54 #define GPIO_ABCD_INT_ENABLE (0x008 >> 2) 55 #define GPIO_ABCD_INT_SENS_0 (0x00C >> 2) 56 #define GPIO_ABCD_INT_SENS_1 (0x010 >> 2) 57 #define GPIO_ABCD_INT_SENS_2 (0x014 >> 2) 58 #define GPIO_ABCD_INT_STATUS (0x018 >> 2) 59 #define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2) 60 #define GPIO_EFGH_DATA_VALUE (0x020 >> 2) 61 #define GPIO_EFGH_DIRECTION (0x024 >> 2) 62 #define GPIO_EFGH_INT_ENABLE (0x028 >> 2) 63 #define GPIO_EFGH_INT_SENS_0 (0x02C >> 2) 64 #define GPIO_EFGH_INT_SENS_1 (0x030 >> 2) 65 #define GPIO_EFGH_INT_SENS_2 (0x034 >> 2) 66 #define GPIO_EFGH_INT_STATUS (0x038 >> 2) 67 #define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2) 68 #define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2) 69 #define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2) 70 #define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2) 71 #define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2) 72 #define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2) 73 #define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2) 74 #define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2) 75 #define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2) 76 #define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2) 77 #define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2) 78 #define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2) 79 #define GPIO_IJKL_DATA_VALUE (0x070 >> 2) 80 #define GPIO_IJKL_DIRECTION (0x074 >> 2) 81 #define GPIO_MNOP_DATA_VALUE (0x078 >> 2) 82 #define GPIO_MNOP_DIRECTION (0x07C >> 2) 83 #define GPIO_QRST_DATA_VALUE (0x080 >> 2) 84 #define GPIO_QRST_DIRECTION (0x084 >> 2) 85 #define GPIO_UVWX_DATA_VALUE (0x088 >> 2) 86 #define GPIO_UVWX_DIRECTION (0x08C >> 2) 87 #define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2) 88 #define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2) 89 #define GPIO_IJKL_INT_ENABLE (0x098 >> 2) 90 #define GPIO_IJKL_INT_SENS_0 (0x09C >> 2) 91 #define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2) 92 #define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2) 93 #define GPIO_IJKL_INT_STATUS (0x0A8 >> 2) 94 #define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2) 95 #define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2) 96 #define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2) 97 #define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2) 98 #define GPIO_ABCD_DATA_READ (0x0C0 >> 2) 99 #define GPIO_EFGH_DATA_READ (0x0C4 >> 2) 100 #define GPIO_IJKL_DATA_READ (0x0C8 >> 2) 101 #define GPIO_MNOP_DATA_READ (0x0CC >> 2) 102 #define GPIO_QRST_DATA_READ (0x0D0 >> 2) 103 #define GPIO_UVWX_DATA_READ (0x0D4 >> 2) 104 #define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2) 105 #define GPIO_AC_DATA_READ (0x0DC >> 2) 106 #define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2) 107 #define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2) 108 #define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2) 109 #define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2) 110 #define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2) 111 #define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2) 112 #define GPIO_MNOP_INT_STATUS (0x0F8 >> 2) 113 #define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2) 114 #define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2) 115 #define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2) 116 #define GPIO_MNOP_INPUT_MASK (0x108 >> 2) 117 #define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2) 118 #define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2) 119 #define GPIO_QRST_INT_ENABLE (0x118 >> 2) 120 #define GPIO_QRST_INT_SENS_0 (0x11C >> 2) 121 #define GPIO_QRST_INT_SENS_1 (0x120 >> 2) 122 #define GPIO_QRST_INT_SENS_2 (0x124 >> 2) 123 #define GPIO_QRST_INT_STATUS (0x128 >> 2) 124 #define GPIO_QRST_RESET_TOLERANT (0x12C >> 2) 125 #define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2) 126 #define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2) 127 #define GPIO_QRST_INPUT_MASK (0x138 >> 2) 128 #define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2) 129 #define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2) 130 #define GPIO_UVWX_INT_ENABLE (0x148 >> 2) 131 #define GPIO_UVWX_INT_SENS_0 (0x14C >> 2) 132 #define GPIO_UVWX_INT_SENS_1 (0x150 >> 2) 133 #define GPIO_UVWX_INT_SENS_2 (0x154 >> 2) 134 #define GPIO_UVWX_INT_STATUS (0x158 >> 2) 135 #define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2) 136 #define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2) 137 #define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2) 138 #define GPIO_UVWX_INPUT_MASK (0x168 >> 2) 139 #define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2) 140 #define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2) 141 #define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2) 142 #define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2) 143 #define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2) 144 #define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2) 145 #define GPIO_YZAAAB_INT_STATUS (0x188 >> 2) 146 #define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2) 147 #define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2) 148 #define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2) 149 #define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2) 150 #define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2) 151 #define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2) 152 #define GPIO_AC_INT_ENABLE (0x1A8 >> 2) 153 #define GPIO_AC_INT_SENS_0 (0x1AC >> 2) 154 #define GPIO_AC_INT_SENS_1 (0x1B0 >> 2) 155 #define GPIO_AC_INT_SENS_2 (0x1B4 >> 2) 156 #define GPIO_AC_INT_STATUS (0x1B8 >> 2) 157 #define GPIO_AC_RESET_TOLERANT (0x1BC >> 2) 158 #define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2) 159 #define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2) 160 #define GPIO_AC_INPUT_MASK (0x1C8 >> 2) 161 #define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2) 162 #define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2) 163 #define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2) 164 #define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2) 165 #define GPIO_AC_DATA_VALUE (0x1E8 >> 2) 166 #define GPIO_AC_DIRECTION (0x1EC >> 2) 167 #define GPIO_3_3V_MEM_SIZE 0x1F0 168 #define GPIO_3_3V_REG_ARRAY_SIZE (GPIO_3_3V_MEM_SIZE >> 2) 169 170 /* AST2600 only - 1.8V gpios */ 171 /* 172 * The AST2600 two copies of the GPIO controller: the same 3.3V gpios as the 173 * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios 174 * (memory offsets 0x800-0x9D4). 175 */ 176 #define GPIO_1_8V_ABCD_DATA_VALUE (0x000 >> 2) 177 #define GPIO_1_8V_ABCD_DIRECTION (0x004 >> 2) 178 #define GPIO_1_8V_ABCD_INT_ENABLE (0x008 >> 2) 179 #define GPIO_1_8V_ABCD_INT_SENS_0 (0x00C >> 2) 180 #define GPIO_1_8V_ABCD_INT_SENS_1 (0x010 >> 2) 181 #define GPIO_1_8V_ABCD_INT_SENS_2 (0x014 >> 2) 182 #define GPIO_1_8V_ABCD_INT_STATUS (0x018 >> 2) 183 #define GPIO_1_8V_ABCD_RESET_TOLERANT (0x01C >> 2) 184 #define GPIO_1_8V_E_DATA_VALUE (0x020 >> 2) 185 #define GPIO_1_8V_E_DIRECTION (0x024 >> 2) 186 #define GPIO_1_8V_E_INT_ENABLE (0x028 >> 2) 187 #define GPIO_1_8V_E_INT_SENS_0 (0x02C >> 2) 188 #define GPIO_1_8V_E_INT_SENS_1 (0x030 >> 2) 189 #define GPIO_1_8V_E_INT_SENS_2 (0x034 >> 2) 190 #define GPIO_1_8V_E_INT_STATUS (0x038 >> 2) 191 #define GPIO_1_8V_E_RESET_TOLERANT (0x03C >> 2) 192 #define GPIO_1_8V_ABCD_DEBOUNCE_1 (0x040 >> 2) 193 #define GPIO_1_8V_ABCD_DEBOUNCE_2 (0x044 >> 2) 194 #define GPIO_1_8V_E_DEBOUNCE_1 (0x048 >> 2) 195 #define GPIO_1_8V_E_DEBOUNCE_2 (0x04C >> 2) 196 #define GPIO_1_8V_DEBOUNCE_TIME_1 (0x050 >> 2) 197 #define GPIO_1_8V_DEBOUNCE_TIME_2 (0x054 >> 2) 198 #define GPIO_1_8V_DEBOUNCE_TIME_3 (0x058 >> 2) 199 #define GPIO_1_8V_ABCD_COMMAND_SRC_0 (0x060 >> 2) 200 #define GPIO_1_8V_ABCD_COMMAND_SRC_1 (0x064 >> 2) 201 #define GPIO_1_8V_E_COMMAND_SRC_0 (0x068 >> 2) 202 #define GPIO_1_8V_E_COMMAND_SRC_1 (0x06C >> 2) 203 #define GPIO_1_8V_ABCD_DATA_READ (0x0C0 >> 2) 204 #define GPIO_1_8V_E_DATA_READ (0x0C4 >> 2) 205 #define GPIO_1_8V_ABCD_INPUT_MASK (0x1D0 >> 2) 206 #define GPIO_1_8V_E_INPUT_MASK (0x1D4 >> 2) 207 #define GPIO_1_8V_MEM_SIZE 0x1D8 208 #define GPIO_1_8V_REG_ARRAY_SIZE (GPIO_1_8V_MEM_SIZE >> 2) 209 210 static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) 211 { 212 uint32_t falling_edge = 0, rising_edge = 0; 213 uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1) 214 | extract32(regs->int_sens_1, gpio, 1) << 1 215 | extract32(regs->int_sens_2, gpio, 1) << 2; 216 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); 217 uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1); 218 219 if (!gpio_int_enabled) { 220 return 0; 221 } 222 223 /* Detect edges */ 224 if (gpio_curr_high && !gpio_prev_high) { 225 rising_edge = 1; 226 } else if (!gpio_curr_high && gpio_prev_high) { 227 falling_edge = 1; 228 } 229 230 if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) || 231 ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) || 232 ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) || 233 ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) || 234 ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge))) 235 { 236 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); 237 return 1; 238 } 239 return 0; 240 } 241 242 #define nested_struct_index(ta, pa, m, tb, pb) \ 243 (pb - ((tb *)(((char *)pa) + offsetof(ta, m)))) 244 245 static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs) 246 { 247 return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs); 248 } 249 250 static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, 251 uint32_t value) 252 { 253 uint32_t input_mask = regs->input_mask; 254 uint32_t direction = regs->direction; 255 uint32_t old = regs->data_value; 256 uint32_t new = value; 257 uint32_t diff; 258 int gpio; 259 260 diff = old ^ new; 261 if (diff) { 262 for (gpio = 0; gpio < GPIOS_PER_REG; gpio++) { 263 uint32_t mask = 1 << gpio; 264 265 /* If the gpio needs to be updated... */ 266 if (!(diff & mask)) { 267 continue; 268 } 269 270 /* ...and we're output or not input-masked... */ 271 if (!(direction & mask) && (input_mask & mask)) { 272 continue; 273 } 274 275 /* ...then update the state. */ 276 if (mask & new) { 277 regs->data_value |= mask; 278 } else { 279 regs->data_value &= ~mask; 280 } 281 282 /* If the gpio is set to output... */ 283 if (direction & mask) { 284 /* ...trigger the line-state IRQ */ 285 ptrdiff_t set = aspeed_gpio_set_idx(s, regs); 286 size_t offset = set * GPIOS_PER_SET + gpio; 287 qemu_set_irq(s->gpios[offset], !!(new & mask)); 288 } else { 289 /* ...otherwise if we meet the line's current IRQ policy... */ 290 if (aspeed_evaluate_irq(regs, old & mask, gpio)) { 291 /* ...trigger the VIC IRQ */ 292 s->pending++; 293 } 294 } 295 } 296 } 297 qemu_set_irq(s->irq, !!(s->pending)); 298 } 299 300 static uint32_t aspeed_adjust_pin(AspeedGPIOState *s, uint32_t pin) 301 { 302 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 303 /* 304 * The 2500 has a 4 pin gap in group AB and the 2400 has a 4 pin 305 * gap in group Y (and only four pins in AB but this is the last group so 306 * it doesn't matter). 307 */ 308 if (agc->gap && pin >= agc->gap) { 309 pin += GPIO_PIN_GAP_SIZE; 310 } 311 312 return pin; 313 } 314 315 static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx, 316 uint32_t pin) 317 { 318 uint32_t reg_val; 319 uint32_t pin_mask = 1 << pin; 320 321 reg_val = s->sets[set_idx].data_value; 322 323 return !!(reg_val & pin_mask); 324 } 325 326 static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, 327 uint32_t pin, bool level) 328 { 329 uint32_t value = s->sets[set_idx].data_value; 330 uint32_t pin_mask = 1 << pin; 331 332 if (level) { 333 value |= pin_mask; 334 } else { 335 value &= !pin_mask; 336 } 337 338 aspeed_gpio_update(s, &s->sets[set_idx], value); 339 } 340 341 /* 342 * | src_1 | src_2 | source | 343 * |-----------------------------| 344 * | 0 | 0 | ARM | 345 * | 0 | 1 | LPC | 346 * | 1 | 0 | Coprocessor| 347 * | 1 | 1 | Reserved | 348 * 349 * Once the source of a set is programmed, corresponding bits in the 350 * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and 351 * debounce registers can only be written by the source. 352 * 353 * Source is ARM by default 354 * only bits 24, 16, 8, and 0 can be set 355 * 356 * we don't currently have a model for the LPC or Coprocessor 357 */ 358 static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value, 359 uint32_t value) 360 { 361 int i; 362 int cmd_source; 363 364 /* assume the source is always ARM for now */ 365 int source = ASPEED_SOURCE_ARM; 366 367 uint32_t new_value = 0; 368 369 /* for each group in set */ 370 for (i = 0; i < GPIOS_PER_REG; i += GPIOS_PER_GROUP) { 371 cmd_source = extract32(regs->cmd_source_0, i, 1) 372 | (extract32(regs->cmd_source_1, i, 1) << 1); 373 374 if (source == cmd_source) { 375 new_value |= (0xff << i) & value; 376 } else { 377 new_value |= (0xff << i) & old_value; 378 } 379 } 380 return new_value; 381 } 382 383 static const AspeedGPIOReg aspeed_3_3v_gpios[GPIO_3_3V_REG_ARRAY_SIZE] = { 384 /* Set ABCD */ 385 [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value }, 386 [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction }, 387 [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable }, 388 [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 }, 389 [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 }, 390 [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 }, 391 [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status }, 392 [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant }, 393 [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 }, 394 [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 }, 395 [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 }, 396 [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 }, 397 [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read }, 398 [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask }, 399 /* Set EFGH */ 400 [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value }, 401 [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction }, 402 [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable }, 403 [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 }, 404 [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 }, 405 [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 }, 406 [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status }, 407 [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant }, 408 [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 }, 409 [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 }, 410 [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 }, 411 [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 }, 412 [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read }, 413 [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask }, 414 /* Set IJKL */ 415 [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value }, 416 [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction }, 417 [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable }, 418 [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 }, 419 [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 }, 420 [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 }, 421 [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status }, 422 [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant }, 423 [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 }, 424 [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 }, 425 [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 }, 426 [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 }, 427 [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read }, 428 [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask }, 429 /* Set MNOP */ 430 [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value }, 431 [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction }, 432 [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable }, 433 [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 }, 434 [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 }, 435 [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 }, 436 [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status }, 437 [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant }, 438 [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 }, 439 [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 }, 440 [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 }, 441 [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 }, 442 [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read }, 443 [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask }, 444 /* Set QRST */ 445 [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value }, 446 [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction }, 447 [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable }, 448 [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 }, 449 [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 }, 450 [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 }, 451 [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status }, 452 [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant }, 453 [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 }, 454 [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 }, 455 [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 }, 456 [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 }, 457 [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read }, 458 [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask }, 459 /* Set UVWX */ 460 [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value }, 461 [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction }, 462 [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable }, 463 [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 }, 464 [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 }, 465 [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 }, 466 [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status }, 467 [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant }, 468 [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 }, 469 [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 }, 470 [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 }, 471 [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 }, 472 [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read }, 473 [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask }, 474 /* Set YZAAAB */ 475 [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value }, 476 [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction }, 477 [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable }, 478 [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 }, 479 [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 }, 480 [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 }, 481 [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status }, 482 [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant }, 483 [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 }, 484 [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 }, 485 [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 }, 486 [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 }, 487 [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read }, 488 [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask }, 489 /* Set AC (ast2500 only) */ 490 [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value }, 491 [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction }, 492 [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable }, 493 [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 }, 494 [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 }, 495 [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 }, 496 [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status }, 497 [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant }, 498 [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 }, 499 [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 }, 500 [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 }, 501 [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 }, 502 [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read }, 503 [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, 504 }; 505 506 static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = { 507 /* 1.8V Set ABCD */ 508 [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value}, 509 [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction}, 510 [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable}, 511 [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0}, 512 [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1}, 513 [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2}, 514 [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status}, 515 [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant}, 516 [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1}, 517 [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2}, 518 [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0}, 519 [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1}, 520 [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read}, 521 [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask}, 522 /* 1.8V Set E */ 523 [GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value}, 524 [GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction}, 525 [GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable}, 526 [GPIO_1_8V_E_INT_SENS_0] = {1, gpio_reg_int_sens_0}, 527 [GPIO_1_8V_E_INT_SENS_1] = {1, gpio_reg_int_sens_1}, 528 [GPIO_1_8V_E_INT_SENS_2] = {1, gpio_reg_int_sens_2}, 529 [GPIO_1_8V_E_INT_STATUS] = {1, gpio_reg_int_status}, 530 [GPIO_1_8V_E_RESET_TOLERANT] = {1, gpio_reg_reset_tolerant}, 531 [GPIO_1_8V_E_DEBOUNCE_1] = {1, gpio_reg_debounce_1}, 532 [GPIO_1_8V_E_DEBOUNCE_2] = {1, gpio_reg_debounce_2}, 533 [GPIO_1_8V_E_COMMAND_SRC_0] = {1, gpio_reg_cmd_source_0}, 534 [GPIO_1_8V_E_COMMAND_SRC_1] = {1, gpio_reg_cmd_source_1}, 535 [GPIO_1_8V_E_DATA_READ] = {1, gpio_reg_data_read}, 536 [GPIO_1_8V_E_INPUT_MASK] = {1, gpio_reg_input_mask}, 537 }; 538 539 static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) 540 { 541 AspeedGPIOState *s = ASPEED_GPIO(opaque); 542 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 543 uint64_t idx = -1; 544 const AspeedGPIOReg *reg; 545 GPIOSets *set; 546 547 idx = offset >> 2; 548 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 549 idx -= GPIO_DEBOUNCE_TIME_1; 550 return (uint64_t) s->debounce_regs[idx]; 551 } 552 553 reg = &agc->reg_table[idx]; 554 if (reg->set_idx >= agc->nr_gpio_sets) { 555 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 556 HWADDR_PRIx"\n", __func__, offset); 557 return 0; 558 } 559 560 set = &s->sets[reg->set_idx]; 561 switch (reg->type) { 562 case gpio_reg_data_value: 563 return set->data_value; 564 case gpio_reg_direction: 565 return set->direction; 566 case gpio_reg_int_enable: 567 return set->int_enable; 568 case gpio_reg_int_sens_0: 569 return set->int_sens_0; 570 case gpio_reg_int_sens_1: 571 return set->int_sens_1; 572 case gpio_reg_int_sens_2: 573 return set->int_sens_2; 574 case gpio_reg_int_status: 575 return set->int_status; 576 case gpio_reg_reset_tolerant: 577 return set->reset_tol; 578 case gpio_reg_debounce_1: 579 return set->debounce_1; 580 case gpio_reg_debounce_2: 581 return set->debounce_2; 582 case gpio_reg_cmd_source_0: 583 return set->cmd_source_0; 584 case gpio_reg_cmd_source_1: 585 return set->cmd_source_1; 586 case gpio_reg_data_read: 587 return set->data_read; 588 case gpio_reg_input_mask: 589 return set->input_mask; 590 default: 591 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 592 HWADDR_PRIx"\n", __func__, offset); 593 return 0; 594 }; 595 } 596 597 static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, 598 uint32_t size) 599 { 600 AspeedGPIOState *s = ASPEED_GPIO(opaque); 601 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 602 const GPIOSetProperties *props; 603 uint64_t idx = -1; 604 const AspeedGPIOReg *reg; 605 GPIOSets *set; 606 uint32_t cleared; 607 608 idx = offset >> 2; 609 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 610 idx -= GPIO_DEBOUNCE_TIME_1; 611 s->debounce_regs[idx] = (uint32_t) data; 612 return; 613 } 614 615 reg = &agc->reg_table[idx]; 616 if (reg->set_idx >= agc->nr_gpio_sets) { 617 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 618 HWADDR_PRIx"\n", __func__, offset); 619 return; 620 } 621 622 set = &s->sets[reg->set_idx]; 623 props = &agc->props[reg->set_idx]; 624 625 switch (reg->type) { 626 case gpio_reg_data_value: 627 data &= props->output; 628 data = update_value_control_source(set, set->data_value, data); 629 set->data_read = data; 630 aspeed_gpio_update(s, set, data); 631 return; 632 case gpio_reg_direction: 633 /* 634 * where data is the value attempted to be written to the pin: 635 * pin type | input mask | output mask | expected value 636 * ------------------------------------------------------------ 637 * bidirectional | 1 | 1 | data 638 * input only | 1 | 0 | 0 639 * output only | 0 | 1 | 1 640 * no pin / gap | 0 | 0 | 0 641 * 642 * which is captured by: 643 * data = ( data | ~input) & output; 644 */ 645 data = (data | ~props->input) & props->output; 646 set->direction = update_value_control_source(set, set->direction, data); 647 break; 648 case gpio_reg_int_enable: 649 set->int_enable = update_value_control_source(set, set->int_enable, 650 data); 651 break; 652 case gpio_reg_int_sens_0: 653 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, 654 data); 655 break; 656 case gpio_reg_int_sens_1: 657 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, 658 data); 659 break; 660 case gpio_reg_int_sens_2: 661 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, 662 data); 663 break; 664 case gpio_reg_int_status: 665 cleared = ctpop32(data & set->int_status); 666 if (s->pending && cleared) { 667 assert(s->pending >= cleared); 668 s->pending -= cleared; 669 } 670 set->int_status &= ~data; 671 break; 672 case gpio_reg_reset_tolerant: 673 set->reset_tol = update_value_control_source(set, set->reset_tol, 674 data); 675 return; 676 case gpio_reg_debounce_1: 677 set->debounce_1 = update_value_control_source(set, set->debounce_1, 678 data); 679 return; 680 case gpio_reg_debounce_2: 681 set->debounce_2 = update_value_control_source(set, set->debounce_2, 682 data); 683 return; 684 case gpio_reg_cmd_source_0: 685 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; 686 return; 687 case gpio_reg_cmd_source_1: 688 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; 689 return; 690 case gpio_reg_data_read: 691 /* Read only register */ 692 return; 693 case gpio_reg_input_mask: 694 /* 695 * feeds into interrupt generation 696 * 0: read from data value reg will be updated 697 * 1: read from data value reg will not be updated 698 */ 699 set->input_mask = data & props->input; 700 break; 701 default: 702 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 703 HWADDR_PRIx"\n", __func__, offset); 704 return; 705 } 706 aspeed_gpio_update(s, set, set->data_value); 707 return; 708 } 709 710 static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx) 711 { 712 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 713 int set_idx, g_idx; 714 715 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { 716 const GPIOSetProperties *set_props = &agc->props[set_idx]; 717 for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) { 718 if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) { 719 *group_idx = g_idx; 720 return set_idx; 721 } 722 } 723 } 724 return -1; 725 } 726 727 static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, 728 void *opaque, Error **errp) 729 { 730 int pin = 0xfff; 731 bool level = true; 732 char group[4]; 733 AspeedGPIOState *s = ASPEED_GPIO(obj); 734 int set_idx, group_idx = 0; 735 736 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 737 /* 1.8V gpio */ 738 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 739 error_setg(errp, "%s: error reading %s", __func__, name); 740 return; 741 } 742 } 743 set_idx = get_set_idx(s, group, &group_idx); 744 if (set_idx == -1) { 745 error_setg(errp, "%s: invalid group %s", __func__, group); 746 return; 747 } 748 pin = pin + group_idx * GPIOS_PER_GROUP; 749 level = aspeed_gpio_get_pin_level(s, set_idx, pin); 750 visit_type_bool(v, name, &level, errp); 751 } 752 753 static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, 754 void *opaque, Error **errp) 755 { 756 bool level; 757 int pin = 0xfff; 758 char group[4]; 759 AspeedGPIOState *s = ASPEED_GPIO(obj); 760 int set_idx, group_idx = 0; 761 762 if (!visit_type_bool(v, name, &level, errp)) { 763 return; 764 } 765 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 766 /* 1.8V gpio */ 767 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 768 error_setg(errp, "%s: error reading %s", __func__, name); 769 return; 770 } 771 } 772 set_idx = get_set_idx(s, group, &group_idx); 773 if (set_idx == -1) { 774 error_setg(errp, "%s: invalid group %s", __func__, group); 775 return; 776 } 777 pin = pin + group_idx * GPIOS_PER_GROUP; 778 aspeed_gpio_set_pin_level(s, set_idx, pin, level); 779 } 780 781 /****************** Setup functions ******************/ 782 static const GPIOSetProperties ast2400_set_props[] = { 783 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 784 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 785 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 786 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 787 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 788 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 789 [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 790 }; 791 792 static const GPIOSetProperties ast2500_set_props[] = { 793 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 794 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 795 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 796 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 797 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 798 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 799 [6] = {0xffffff0f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 800 [7] = {0x000000ff, 0x000000ff, {"AC"} }, 801 }; 802 803 static GPIOSetProperties ast2600_3_3v_set_props[] = { 804 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 805 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 806 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 807 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 808 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 809 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 810 [6] = {0xffff0000, 0x0fff0000, {"Y", "Z", "", ""} }, 811 }; 812 813 static GPIOSetProperties ast2600_1_8v_set_props[] = { 814 [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} }, 815 [1] = {0x0000000f, 0x0000000f, {"18E"} }, 816 }; 817 818 static const MemoryRegionOps aspeed_gpio_ops = { 819 .read = aspeed_gpio_read, 820 .write = aspeed_gpio_write, 821 .endianness = DEVICE_LITTLE_ENDIAN, 822 .valid.min_access_size = 4, 823 .valid.max_access_size = 4, 824 }; 825 826 static void aspeed_gpio_reset(DeviceState *dev) 827 { 828 AspeedGPIOState *s = ASPEED_GPIO(dev); 829 830 /* TODO: respect the reset tolerance registers */ 831 memset(s->sets, 0, sizeof(s->sets)); 832 } 833 834 static void aspeed_gpio_realize(DeviceState *dev, Error **errp) 835 { 836 AspeedGPIOState *s = ASPEED_GPIO(dev); 837 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 838 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 839 int pin; 840 841 /* Interrupt parent line */ 842 sysbus_init_irq(sbd, &s->irq); 843 844 /* Individual GPIOs */ 845 for (pin = 0; pin < agc->nr_gpio_pins; pin++) { 846 sysbus_init_irq(sbd, &s->gpios[pin]); 847 } 848 849 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, 850 TYPE_ASPEED_GPIO, 0x800); 851 852 sysbus_init_mmio(sbd, &s->iomem); 853 } 854 855 static void aspeed_gpio_init(Object *obj) 856 { 857 AspeedGPIOState *s = ASPEED_GPIO(obj); 858 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 859 int pin; 860 861 for (pin = 0; pin < agc->nr_gpio_pins; pin++) { 862 char *name; 863 int set_idx = pin / GPIOS_PER_SET; 864 int pin_idx = aspeed_adjust_pin(s, pin) - (set_idx * GPIOS_PER_SET); 865 int group_idx = pin_idx >> GPIO_GROUP_SHIFT; 866 const GPIOSetProperties *props = &agc->props[set_idx]; 867 868 name = g_strdup_printf("gpio%s%d", props->group_label[group_idx], 869 pin_idx % GPIOS_PER_GROUP); 870 object_property_add(obj, name, "bool", aspeed_gpio_get_pin, 871 aspeed_gpio_set_pin, NULL, NULL); 872 g_free(name); 873 } 874 } 875 876 static const VMStateDescription vmstate_gpio_regs = { 877 .name = TYPE_ASPEED_GPIO"/regs", 878 .version_id = 1, 879 .minimum_version_id = 1, 880 .fields = (VMStateField[]) { 881 VMSTATE_UINT32(data_value, GPIOSets), 882 VMSTATE_UINT32(data_read, GPIOSets), 883 VMSTATE_UINT32(direction, GPIOSets), 884 VMSTATE_UINT32(int_enable, GPIOSets), 885 VMSTATE_UINT32(int_sens_0, GPIOSets), 886 VMSTATE_UINT32(int_sens_1, GPIOSets), 887 VMSTATE_UINT32(int_sens_2, GPIOSets), 888 VMSTATE_UINT32(int_status, GPIOSets), 889 VMSTATE_UINT32(reset_tol, GPIOSets), 890 VMSTATE_UINT32(cmd_source_0, GPIOSets), 891 VMSTATE_UINT32(cmd_source_1, GPIOSets), 892 VMSTATE_UINT32(debounce_1, GPIOSets), 893 VMSTATE_UINT32(debounce_2, GPIOSets), 894 VMSTATE_UINT32(input_mask, GPIOSets), 895 VMSTATE_END_OF_LIST(), 896 } 897 }; 898 899 static const VMStateDescription vmstate_aspeed_gpio = { 900 .name = TYPE_ASPEED_GPIO, 901 .version_id = 1, 902 .minimum_version_id = 1, 903 .fields = (VMStateField[]) { 904 VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS, 905 1, vmstate_gpio_regs, GPIOSets), 906 VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState, 907 ASPEED_GPIO_NR_DEBOUNCE_REGS), 908 VMSTATE_END_OF_LIST(), 909 } 910 }; 911 912 static void aspeed_gpio_class_init(ObjectClass *klass, void *data) 913 { 914 DeviceClass *dc = DEVICE_CLASS(klass); 915 916 dc->realize = aspeed_gpio_realize; 917 dc->reset = aspeed_gpio_reset; 918 dc->desc = "Aspeed GPIO Controller"; 919 dc->vmsd = &vmstate_aspeed_gpio; 920 } 921 922 static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) 923 { 924 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 925 926 agc->props = ast2400_set_props; 927 agc->nr_gpio_pins = 216; 928 agc->nr_gpio_sets = 7; 929 agc->gap = 196; 930 agc->reg_table = aspeed_3_3v_gpios; 931 } 932 933 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) 934 { 935 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 936 937 agc->props = ast2500_set_props; 938 agc->nr_gpio_pins = 228; 939 agc->nr_gpio_sets = 8; 940 agc->gap = 220; 941 agc->reg_table = aspeed_3_3v_gpios; 942 } 943 944 static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) 945 { 946 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 947 948 agc->props = ast2600_3_3v_set_props; 949 agc->nr_gpio_pins = 208; 950 agc->nr_gpio_sets = 7; 951 agc->reg_table = aspeed_3_3v_gpios; 952 } 953 954 static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) 955 { 956 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 957 958 agc->props = ast2600_1_8v_set_props; 959 agc->nr_gpio_pins = 36; 960 agc->nr_gpio_sets = 2; 961 agc->reg_table = aspeed_1_8v_gpios; 962 } 963 964 static const TypeInfo aspeed_gpio_info = { 965 .name = TYPE_ASPEED_GPIO, 966 .parent = TYPE_SYS_BUS_DEVICE, 967 .instance_size = sizeof(AspeedGPIOState), 968 .class_size = sizeof(AspeedGPIOClass), 969 .class_init = aspeed_gpio_class_init, 970 .abstract = true, 971 }; 972 973 static const TypeInfo aspeed_gpio_ast2400_info = { 974 .name = TYPE_ASPEED_GPIO "-ast2400", 975 .parent = TYPE_ASPEED_GPIO, 976 .class_init = aspeed_gpio_ast2400_class_init, 977 .instance_init = aspeed_gpio_init, 978 }; 979 980 static const TypeInfo aspeed_gpio_ast2500_info = { 981 .name = TYPE_ASPEED_GPIO "-ast2500", 982 .parent = TYPE_ASPEED_GPIO, 983 .class_init = aspeed_gpio_2500_class_init, 984 .instance_init = aspeed_gpio_init, 985 }; 986 987 static const TypeInfo aspeed_gpio_ast2600_3_3v_info = { 988 .name = TYPE_ASPEED_GPIO "-ast2600", 989 .parent = TYPE_ASPEED_GPIO, 990 .class_init = aspeed_gpio_ast2600_3_3v_class_init, 991 .instance_init = aspeed_gpio_init, 992 }; 993 994 static const TypeInfo aspeed_gpio_ast2600_1_8v_info = { 995 .name = TYPE_ASPEED_GPIO "-ast2600-1_8v", 996 .parent = TYPE_ASPEED_GPIO, 997 .class_init = aspeed_gpio_ast2600_1_8v_class_init, 998 .instance_init = aspeed_gpio_init, 999 }; 1000 1001 static void aspeed_gpio_register_types(void) 1002 { 1003 type_register_static(&aspeed_gpio_info); 1004 type_register_static(&aspeed_gpio_ast2400_info); 1005 type_register_static(&aspeed_gpio_ast2500_info); 1006 type_register_static(&aspeed_gpio_ast2600_3_3v_info); 1007 type_register_static(&aspeed_gpio_ast2600_1_8v_info); 1008 } 1009 1010 type_init(aspeed_gpio_register_types); 1011