1 /* 2 * ASPEED GPIO Controller 3 * 4 * Copyright (C) 2017-2019 IBM Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/host-utils.h" 11 #include "qemu/log.h" 12 #include "hw/gpio/aspeed_gpio.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "qapi/error.h" 15 #include "qapi/visitor.h" 16 #include "hw/irq.h" 17 #include "migration/vmstate.h" 18 #include "trace.h" 19 #include "hw/registerfields.h" 20 21 #define GPIOS_PER_GROUP 8 22 23 /* GPIO Source Types */ 24 #define ASPEED_CMD_SRC_MASK 0x01010101 25 #define ASPEED_SOURCE_ARM 0 26 #define ASPEED_SOURCE_LPC 1 27 #define ASPEED_SOURCE_COPROCESSOR 2 28 #define ASPEED_SOURCE_RESERVED 3 29 30 /* GPIO Interrupt Triggers */ 31 /* 32 * For each set of gpios there are three sensitivity registers that control 33 * the interrupt trigger mode. 34 * 35 * | 2 | 1 | 0 | trigger mode 36 * ----------------------------- 37 * | 0 | 0 | 0 | falling-edge 38 * | 0 | 0 | 1 | rising-edge 39 * | 0 | 1 | 0 | level-low 40 * | 0 | 1 | 1 | level-high 41 * | 1 | X | X | dual-edge 42 */ 43 #define ASPEED_FALLING_EDGE 0 44 #define ASPEED_RISING_EDGE 1 45 #define ASPEED_LEVEL_LOW 2 46 #define ASPEED_LEVEL_HIGH 3 47 #define ASPEED_DUAL_EDGE 4 48 49 /* GPIO Register Address Offsets */ 50 #define GPIO_ABCD_DATA_VALUE (0x000 >> 2) 51 #define GPIO_ABCD_DIRECTION (0x004 >> 2) 52 #define GPIO_ABCD_INT_ENABLE (0x008 >> 2) 53 #define GPIO_ABCD_INT_SENS_0 (0x00C >> 2) 54 #define GPIO_ABCD_INT_SENS_1 (0x010 >> 2) 55 #define GPIO_ABCD_INT_SENS_2 (0x014 >> 2) 56 #define GPIO_ABCD_INT_STATUS (0x018 >> 2) 57 #define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2) 58 #define GPIO_EFGH_DATA_VALUE (0x020 >> 2) 59 #define GPIO_EFGH_DIRECTION (0x024 >> 2) 60 #define GPIO_EFGH_INT_ENABLE (0x028 >> 2) 61 #define GPIO_EFGH_INT_SENS_0 (0x02C >> 2) 62 #define GPIO_EFGH_INT_SENS_1 (0x030 >> 2) 63 #define GPIO_EFGH_INT_SENS_2 (0x034 >> 2) 64 #define GPIO_EFGH_INT_STATUS (0x038 >> 2) 65 #define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2) 66 #define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2) 67 #define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2) 68 #define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2) 69 #define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2) 70 #define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2) 71 #define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2) 72 #define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2) 73 #define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2) 74 #define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2) 75 #define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2) 76 #define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2) 77 #define GPIO_IJKL_DATA_VALUE (0x070 >> 2) 78 #define GPIO_IJKL_DIRECTION (0x074 >> 2) 79 #define GPIO_MNOP_DATA_VALUE (0x078 >> 2) 80 #define GPIO_MNOP_DIRECTION (0x07C >> 2) 81 #define GPIO_QRST_DATA_VALUE (0x080 >> 2) 82 #define GPIO_QRST_DIRECTION (0x084 >> 2) 83 #define GPIO_UVWX_DATA_VALUE (0x088 >> 2) 84 #define GPIO_UVWX_DIRECTION (0x08C >> 2) 85 #define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2) 86 #define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2) 87 #define GPIO_IJKL_INT_ENABLE (0x098 >> 2) 88 #define GPIO_IJKL_INT_SENS_0 (0x09C >> 2) 89 #define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2) 90 #define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2) 91 #define GPIO_IJKL_INT_STATUS (0x0A8 >> 2) 92 #define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2) 93 #define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2) 94 #define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2) 95 #define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2) 96 #define GPIO_ABCD_DATA_READ (0x0C0 >> 2) 97 #define GPIO_EFGH_DATA_READ (0x0C4 >> 2) 98 #define GPIO_IJKL_DATA_READ (0x0C8 >> 2) 99 #define GPIO_MNOP_DATA_READ (0x0CC >> 2) 100 #define GPIO_QRST_DATA_READ (0x0D0 >> 2) 101 #define GPIO_UVWX_DATA_READ (0x0D4 >> 2) 102 #define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2) 103 #define GPIO_AC_DATA_READ (0x0DC >> 2) 104 #define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2) 105 #define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2) 106 #define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2) 107 #define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2) 108 #define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2) 109 #define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2) 110 #define GPIO_MNOP_INT_STATUS (0x0F8 >> 2) 111 #define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2) 112 #define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2) 113 #define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2) 114 #define GPIO_MNOP_INPUT_MASK (0x108 >> 2) 115 #define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2) 116 #define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2) 117 #define GPIO_QRST_INT_ENABLE (0x118 >> 2) 118 #define GPIO_QRST_INT_SENS_0 (0x11C >> 2) 119 #define GPIO_QRST_INT_SENS_1 (0x120 >> 2) 120 #define GPIO_QRST_INT_SENS_2 (0x124 >> 2) 121 #define GPIO_QRST_INT_STATUS (0x128 >> 2) 122 #define GPIO_QRST_RESET_TOLERANT (0x12C >> 2) 123 #define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2) 124 #define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2) 125 #define GPIO_QRST_INPUT_MASK (0x138 >> 2) 126 #define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2) 127 #define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2) 128 #define GPIO_UVWX_INT_ENABLE (0x148 >> 2) 129 #define GPIO_UVWX_INT_SENS_0 (0x14C >> 2) 130 #define GPIO_UVWX_INT_SENS_1 (0x150 >> 2) 131 #define GPIO_UVWX_INT_SENS_2 (0x154 >> 2) 132 #define GPIO_UVWX_INT_STATUS (0x158 >> 2) 133 #define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2) 134 #define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2) 135 #define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2) 136 #define GPIO_UVWX_INPUT_MASK (0x168 >> 2) 137 #define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2) 138 #define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2) 139 #define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2) 140 #define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2) 141 #define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2) 142 #define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2) 143 #define GPIO_YZAAAB_INT_STATUS (0x188 >> 2) 144 #define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2) 145 #define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2) 146 #define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2) 147 #define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2) 148 #define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2) 149 #define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2) 150 #define GPIO_AC_INT_ENABLE (0x1A8 >> 2) 151 #define GPIO_AC_INT_SENS_0 (0x1AC >> 2) 152 #define GPIO_AC_INT_SENS_1 (0x1B0 >> 2) 153 #define GPIO_AC_INT_SENS_2 (0x1B4 >> 2) 154 #define GPIO_AC_INT_STATUS (0x1B8 >> 2) 155 #define GPIO_AC_RESET_TOLERANT (0x1BC >> 2) 156 #define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2) 157 #define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2) 158 #define GPIO_AC_INPUT_MASK (0x1C8 >> 2) 159 #define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2) 160 #define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2) 161 #define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2) 162 #define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2) 163 #define GPIO_AC_DATA_VALUE (0x1E8 >> 2) 164 #define GPIO_AC_DIRECTION (0x1EC >> 2) 165 #define GPIO_3_3V_MEM_SIZE 0x1F0 166 #define GPIO_3_3V_REG_ARRAY_SIZE (GPIO_3_3V_MEM_SIZE >> 2) 167 168 /* AST2600 only - 1.8V gpios */ 169 /* 170 * The AST2600 two copies of the GPIO controller: the same 3.3V gpios as the 171 * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios 172 * (memory offsets 0x800-0x9D4). 173 */ 174 #define GPIO_1_8V_ABCD_DATA_VALUE (0x000 >> 2) 175 #define GPIO_1_8V_ABCD_DIRECTION (0x004 >> 2) 176 #define GPIO_1_8V_ABCD_INT_ENABLE (0x008 >> 2) 177 #define GPIO_1_8V_ABCD_INT_SENS_0 (0x00C >> 2) 178 #define GPIO_1_8V_ABCD_INT_SENS_1 (0x010 >> 2) 179 #define GPIO_1_8V_ABCD_INT_SENS_2 (0x014 >> 2) 180 #define GPIO_1_8V_ABCD_INT_STATUS (0x018 >> 2) 181 #define GPIO_1_8V_ABCD_RESET_TOLERANT (0x01C >> 2) 182 #define GPIO_1_8V_E_DATA_VALUE (0x020 >> 2) 183 #define GPIO_1_8V_E_DIRECTION (0x024 >> 2) 184 #define GPIO_1_8V_E_INT_ENABLE (0x028 >> 2) 185 #define GPIO_1_8V_E_INT_SENS_0 (0x02C >> 2) 186 #define GPIO_1_8V_E_INT_SENS_1 (0x030 >> 2) 187 #define GPIO_1_8V_E_INT_SENS_2 (0x034 >> 2) 188 #define GPIO_1_8V_E_INT_STATUS (0x038 >> 2) 189 #define GPIO_1_8V_E_RESET_TOLERANT (0x03C >> 2) 190 #define GPIO_1_8V_ABCD_DEBOUNCE_1 (0x040 >> 2) 191 #define GPIO_1_8V_ABCD_DEBOUNCE_2 (0x044 >> 2) 192 #define GPIO_1_8V_E_DEBOUNCE_1 (0x048 >> 2) 193 #define GPIO_1_8V_E_DEBOUNCE_2 (0x04C >> 2) 194 #define GPIO_1_8V_DEBOUNCE_TIME_1 (0x050 >> 2) 195 #define GPIO_1_8V_DEBOUNCE_TIME_2 (0x054 >> 2) 196 #define GPIO_1_8V_DEBOUNCE_TIME_3 (0x058 >> 2) 197 #define GPIO_1_8V_ABCD_COMMAND_SRC_0 (0x060 >> 2) 198 #define GPIO_1_8V_ABCD_COMMAND_SRC_1 (0x064 >> 2) 199 #define GPIO_1_8V_E_COMMAND_SRC_0 (0x068 >> 2) 200 #define GPIO_1_8V_E_COMMAND_SRC_1 (0x06C >> 2) 201 #define GPIO_1_8V_ABCD_DATA_READ (0x0C0 >> 2) 202 #define GPIO_1_8V_E_DATA_READ (0x0C4 >> 2) 203 #define GPIO_1_8V_ABCD_INPUT_MASK (0x1D0 >> 2) 204 #define GPIO_1_8V_E_INPUT_MASK (0x1D4 >> 2) 205 #define GPIO_1_8V_MEM_SIZE 0x1D8 206 #define GPIO_1_8V_REG_ARRAY_SIZE (GPIO_1_8V_MEM_SIZE >> 2) 207 208 /* 209 * GPIO index mode support 210 * It only supports write operation 211 */ 212 REG32(GPIO_INDEX_REG, 0x2AC) 213 FIELD(GPIO_INDEX_REG, NUMBER, 0, 8) 214 FIELD(GPIO_INDEX_REG, COMMAND, 12, 1) 215 FIELD(GPIO_INDEX_REG, TYPE, 16, 4) 216 FIELD(GPIO_INDEX_REG, DATA_VALUE, 20, 1) 217 FIELD(GPIO_INDEX_REG, DIRECTION, 20, 1) 218 FIELD(GPIO_INDEX_REG, INT_ENABLE, 20, 1) 219 FIELD(GPIO_INDEX_REG, INT_SENS_0, 21, 1) 220 FIELD(GPIO_INDEX_REG, INT_SENS_1, 22, 1) 221 FIELD(GPIO_INDEX_REG, INT_SENS_2, 23, 1) 222 FIELD(GPIO_INDEX_REG, INT_STATUS, 24, 1) 223 FIELD(GPIO_INDEX_REG, DEBOUNCE_1, 20, 1) 224 FIELD(GPIO_INDEX_REG, DEBOUNCE_2, 21, 1) 225 FIELD(GPIO_INDEX_REG, RESET_TOLERANT, 20, 1) 226 FIELD(GPIO_INDEX_REG, COMMAND_SRC_0, 20, 1) 227 FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1) 228 FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1) 229 230 static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) 231 { 232 uint32_t falling_edge = 0, rising_edge = 0; 233 uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1) 234 | extract32(regs->int_sens_1, gpio, 1) << 1 235 | extract32(regs->int_sens_2, gpio, 1) << 2; 236 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); 237 uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1); 238 239 if (!gpio_int_enabled) { 240 return 0; 241 } 242 243 /* Detect edges */ 244 if (gpio_curr_high && !gpio_prev_high) { 245 rising_edge = 1; 246 } else if (!gpio_curr_high && gpio_prev_high) { 247 falling_edge = 1; 248 } 249 250 if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) || 251 ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) || 252 ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) || 253 ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) || 254 ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge))) 255 { 256 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); 257 return 1; 258 } 259 return 0; 260 } 261 262 #define nested_struct_index(ta, pa, m, tb, pb) \ 263 (pb - ((tb *)(((char *)pa) + offsetof(ta, m)))) 264 265 static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs) 266 { 267 return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs); 268 } 269 270 static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, 271 uint32_t value) 272 { 273 uint32_t input_mask = regs->input_mask; 274 uint32_t direction = regs->direction; 275 uint32_t old = regs->data_value; 276 uint32_t new = value; 277 uint32_t diff; 278 int gpio; 279 280 diff = old ^ new; 281 if (diff) { 282 for (gpio = 0; gpio < ASPEED_GPIOS_PER_SET; gpio++) { 283 uint32_t mask = 1 << gpio; 284 285 /* If the gpio needs to be updated... */ 286 if (!(diff & mask)) { 287 continue; 288 } 289 290 /* ...and we're output or not input-masked... */ 291 if (!(direction & mask) && (input_mask & mask)) { 292 continue; 293 } 294 295 /* ...then update the state. */ 296 if (mask & new) { 297 regs->data_value |= mask; 298 } else { 299 regs->data_value &= ~mask; 300 } 301 302 /* If the gpio is set to output... */ 303 if (direction & mask) { 304 /* ...trigger the line-state IRQ */ 305 ptrdiff_t set = aspeed_gpio_set_idx(s, regs); 306 qemu_set_irq(s->gpios[set][gpio], !!(new & mask)); 307 } else { 308 /* ...otherwise if we meet the line's current IRQ policy... */ 309 if (aspeed_evaluate_irq(regs, old & mask, gpio)) { 310 /* ...trigger the VIC IRQ */ 311 s->pending++; 312 } 313 } 314 } 315 } 316 qemu_set_irq(s->irq, !!(s->pending)); 317 } 318 319 static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx, 320 uint32_t pin) 321 { 322 uint32_t reg_val; 323 uint32_t pin_mask = 1 << pin; 324 325 reg_val = s->sets[set_idx].data_value; 326 327 return !!(reg_val & pin_mask); 328 } 329 330 static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, 331 uint32_t pin, bool level) 332 { 333 uint32_t value = s->sets[set_idx].data_value; 334 uint32_t pin_mask = 1 << pin; 335 336 if (level) { 337 value |= pin_mask; 338 } else { 339 value &= ~pin_mask; 340 } 341 342 aspeed_gpio_update(s, &s->sets[set_idx], value); 343 } 344 345 /* 346 * | src_1 | src_2 | source | 347 * |-----------------------------| 348 * | 0 | 0 | ARM | 349 * | 0 | 1 | LPC | 350 * | 1 | 0 | Coprocessor| 351 * | 1 | 1 | Reserved | 352 * 353 * Once the source of a set is programmed, corresponding bits in the 354 * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and 355 * debounce registers can only be written by the source. 356 * 357 * Source is ARM by default 358 * only bits 24, 16, 8, and 0 can be set 359 * 360 * we don't currently have a model for the LPC or Coprocessor 361 */ 362 static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value, 363 uint32_t value) 364 { 365 int i; 366 int cmd_source; 367 368 /* assume the source is always ARM for now */ 369 int source = ASPEED_SOURCE_ARM; 370 371 uint32_t new_value = 0; 372 373 /* for each group in set */ 374 for (i = 0; i < ASPEED_GPIOS_PER_SET; i += GPIOS_PER_GROUP) { 375 cmd_source = extract32(regs->cmd_source_0, i, 1) 376 | (extract32(regs->cmd_source_1, i, 1) << 1); 377 378 if (source == cmd_source) { 379 new_value |= (0xff << i) & value; 380 } else { 381 new_value |= (0xff << i) & old_value; 382 } 383 } 384 return new_value; 385 } 386 387 static const AspeedGPIOReg aspeed_3_3v_gpios[GPIO_3_3V_REG_ARRAY_SIZE] = { 388 /* Set ABCD */ 389 [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value }, 390 [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction }, 391 [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable }, 392 [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 }, 393 [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 }, 394 [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 }, 395 [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status }, 396 [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant }, 397 [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 }, 398 [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 }, 399 [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 }, 400 [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 }, 401 [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read }, 402 [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask }, 403 /* Set EFGH */ 404 [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value }, 405 [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction }, 406 [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable }, 407 [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 }, 408 [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 }, 409 [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 }, 410 [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status }, 411 [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant }, 412 [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 }, 413 [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 }, 414 [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 }, 415 [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 }, 416 [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read }, 417 [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask }, 418 /* Set IJKL */ 419 [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value }, 420 [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction }, 421 [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable }, 422 [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 }, 423 [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 }, 424 [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 }, 425 [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status }, 426 [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant }, 427 [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 }, 428 [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 }, 429 [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 }, 430 [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 }, 431 [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read }, 432 [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask }, 433 /* Set MNOP */ 434 [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value }, 435 [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction }, 436 [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable }, 437 [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 }, 438 [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 }, 439 [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 }, 440 [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status }, 441 [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant }, 442 [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 }, 443 [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 }, 444 [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 }, 445 [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 }, 446 [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read }, 447 [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask }, 448 /* Set QRST */ 449 [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value }, 450 [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction }, 451 [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable }, 452 [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 }, 453 [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 }, 454 [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 }, 455 [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status }, 456 [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant }, 457 [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 }, 458 [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 }, 459 [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 }, 460 [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 }, 461 [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read }, 462 [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask }, 463 /* Set UVWX */ 464 [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value }, 465 [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction }, 466 [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable }, 467 [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 }, 468 [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 }, 469 [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 }, 470 [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status }, 471 [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant }, 472 [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 }, 473 [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 }, 474 [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 }, 475 [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 }, 476 [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read }, 477 [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask }, 478 /* Set YZAAAB */ 479 [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value }, 480 [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction }, 481 [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable }, 482 [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 }, 483 [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 }, 484 [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 }, 485 [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status }, 486 [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant }, 487 [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 }, 488 [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 }, 489 [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 }, 490 [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 }, 491 [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read }, 492 [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask }, 493 /* Set AC (ast2500 only) */ 494 [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value }, 495 [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction }, 496 [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable }, 497 [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 }, 498 [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 }, 499 [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 }, 500 [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status }, 501 [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant }, 502 [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 }, 503 [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 }, 504 [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 }, 505 [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 }, 506 [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read }, 507 [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, 508 }; 509 510 static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = { 511 /* 1.8V Set ABCD */ 512 [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value}, 513 [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction}, 514 [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable}, 515 [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0}, 516 [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1}, 517 [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2}, 518 [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status}, 519 [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant}, 520 [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1}, 521 [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2}, 522 [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0}, 523 [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1}, 524 [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read}, 525 [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask}, 526 /* 1.8V Set E */ 527 [GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value}, 528 [GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction}, 529 [GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable}, 530 [GPIO_1_8V_E_INT_SENS_0] = {1, gpio_reg_int_sens_0}, 531 [GPIO_1_8V_E_INT_SENS_1] = {1, gpio_reg_int_sens_1}, 532 [GPIO_1_8V_E_INT_SENS_2] = {1, gpio_reg_int_sens_2}, 533 [GPIO_1_8V_E_INT_STATUS] = {1, gpio_reg_int_status}, 534 [GPIO_1_8V_E_RESET_TOLERANT] = {1, gpio_reg_reset_tolerant}, 535 [GPIO_1_8V_E_DEBOUNCE_1] = {1, gpio_reg_debounce_1}, 536 [GPIO_1_8V_E_DEBOUNCE_2] = {1, gpio_reg_debounce_2}, 537 [GPIO_1_8V_E_COMMAND_SRC_0] = {1, gpio_reg_cmd_source_0}, 538 [GPIO_1_8V_E_COMMAND_SRC_1] = {1, gpio_reg_cmd_source_1}, 539 [GPIO_1_8V_E_DATA_READ] = {1, gpio_reg_data_read}, 540 [GPIO_1_8V_E_INPUT_MASK] = {1, gpio_reg_input_mask}, 541 }; 542 543 static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) 544 { 545 AspeedGPIOState *s = ASPEED_GPIO(opaque); 546 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 547 uint64_t idx = -1; 548 const AspeedGPIOReg *reg; 549 GPIOSets *set; 550 uint32_t value = 0; 551 uint64_t debounce_value; 552 553 idx = offset >> 2; 554 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 555 idx -= GPIO_DEBOUNCE_TIME_1; 556 debounce_value = (uint64_t) s->debounce_regs[idx]; 557 trace_aspeed_gpio_read(offset, debounce_value); 558 return debounce_value; 559 } 560 561 reg = &agc->reg_table[idx]; 562 if (reg->set_idx >= agc->nr_gpio_sets) { 563 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 564 PRIx64"\n", __func__, offset); 565 return 0; 566 } 567 568 set = &s->sets[reg->set_idx]; 569 switch (reg->type) { 570 case gpio_reg_data_value: 571 value = set->data_value; 572 break; 573 case gpio_reg_direction: 574 value = set->direction; 575 break; 576 case gpio_reg_int_enable: 577 value = set->int_enable; 578 break; 579 case gpio_reg_int_sens_0: 580 value = set->int_sens_0; 581 break; 582 case gpio_reg_int_sens_1: 583 value = set->int_sens_1; 584 break; 585 case gpio_reg_int_sens_2: 586 value = set->int_sens_2; 587 break; 588 case gpio_reg_int_status: 589 value = set->int_status; 590 break; 591 case gpio_reg_reset_tolerant: 592 value = set->reset_tol; 593 break; 594 case gpio_reg_debounce_1: 595 value = set->debounce_1; 596 break; 597 case gpio_reg_debounce_2: 598 value = set->debounce_2; 599 break; 600 case gpio_reg_cmd_source_0: 601 value = set->cmd_source_0; 602 break; 603 case gpio_reg_cmd_source_1: 604 value = set->cmd_source_1; 605 break; 606 case gpio_reg_data_read: 607 value = set->data_read; 608 break; 609 case gpio_reg_input_mask: 610 value = set->input_mask; 611 break; 612 default: 613 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 614 PRIx64"\n", __func__, offset); 615 return 0; 616 } 617 618 trace_aspeed_gpio_read(offset, value); 619 return value; 620 } 621 622 static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset, 623 uint64_t data, uint32_t size) 624 { 625 626 AspeedGPIOState *s = ASPEED_GPIO(opaque); 627 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 628 const GPIOSetProperties *props; 629 GPIOSets *set; 630 uint32_t reg_idx_number = FIELD_EX32(data, GPIO_INDEX_REG, NUMBER); 631 uint32_t reg_idx_type = FIELD_EX32(data, GPIO_INDEX_REG, TYPE); 632 uint32_t reg_idx_command = FIELD_EX32(data, GPIO_INDEX_REG, COMMAND); 633 uint32_t set_idx = reg_idx_number / ASPEED_GPIOS_PER_SET; 634 uint32_t pin_idx = reg_idx_number % ASPEED_GPIOS_PER_SET; 635 uint32_t group_idx = pin_idx / GPIOS_PER_GROUP; 636 uint32_t reg_value = 0; 637 uint32_t cleared; 638 639 set = &s->sets[set_idx]; 640 props = &agc->props[set_idx]; 641 642 if (reg_idx_command) 643 qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" 644 PRIx64 "index mode wrong command 0x%x\n", 645 __func__, offset, data, reg_idx_command); 646 647 switch (reg_idx_type) { 648 case gpio_reg_idx_data: 649 reg_value = set->data_read; 650 reg_value = deposit32(reg_value, pin_idx, 1, 651 FIELD_EX32(data, GPIO_INDEX_REG, DATA_VALUE)); 652 reg_value &= props->output; 653 reg_value = update_value_control_source(set, set->data_value, 654 reg_value); 655 set->data_read = reg_value; 656 aspeed_gpio_update(s, set, reg_value); 657 return; 658 case gpio_reg_idx_direction: 659 reg_value = set->direction; 660 reg_value = deposit32(reg_value, pin_idx, 1, 661 FIELD_EX32(data, GPIO_INDEX_REG, DIRECTION)); 662 /* 663 * where data is the value attempted to be written to the pin: 664 * pin type | input mask | output mask | expected value 665 * ------------------------------------------------------------ 666 * bidirectional | 1 | 1 | data 667 * input only | 1 | 0 | 0 668 * output only | 0 | 1 | 1 669 * no pin | 0 | 0 | 0 670 * 671 * which is captured by: 672 * data = ( data | ~input) & output; 673 */ 674 reg_value = (reg_value | ~props->input) & props->output; 675 set->direction = update_value_control_source(set, set->direction, 676 reg_value); 677 break; 678 case gpio_reg_idx_interrupt: 679 reg_value = set->int_enable; 680 reg_value = deposit32(reg_value, pin_idx, 1, 681 FIELD_EX32(data, GPIO_INDEX_REG, INT_ENABLE)); 682 set->int_enable = update_value_control_source(set, set->int_enable, 683 reg_value); 684 reg_value = set->int_sens_0; 685 reg_value = deposit32(reg_value, pin_idx, 1, 686 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_0)); 687 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, 688 reg_value); 689 reg_value = set->int_sens_1; 690 reg_value = deposit32(reg_value, pin_idx, 1, 691 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_1)); 692 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, 693 reg_value); 694 reg_value = set->int_sens_2; 695 reg_value = deposit32(reg_value, pin_idx, 1, 696 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_2)); 697 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, 698 reg_value); 699 /* set interrupt status */ 700 reg_value = set->int_status; 701 reg_value = deposit32(reg_value, pin_idx, 1, 702 FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)); 703 cleared = ctpop32(reg_value & set->int_status); 704 if (s->pending && cleared) { 705 assert(s->pending >= cleared); 706 s->pending -= cleared; 707 } 708 set->int_status &= ~reg_value; 709 break; 710 case gpio_reg_idx_debounce: 711 reg_value = set->debounce_1; 712 reg_value = deposit32(reg_value, pin_idx, 1, 713 FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_1)); 714 set->debounce_1 = update_value_control_source(set, set->debounce_1, 715 reg_value); 716 reg_value = set->debounce_2; 717 reg_value = deposit32(reg_value, pin_idx, 1, 718 FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_2)); 719 set->debounce_2 = update_value_control_source(set, set->debounce_2, 720 reg_value); 721 return; 722 case gpio_reg_idx_tolerance: 723 reg_value = set->reset_tol; 724 reg_value = deposit32(reg_value, pin_idx, 1, 725 FIELD_EX32(data, GPIO_INDEX_REG, RESET_TOLERANT)); 726 set->reset_tol = update_value_control_source(set, set->reset_tol, 727 reg_value); 728 return; 729 case gpio_reg_idx_cmd_src: 730 reg_value = set->cmd_source_0; 731 reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1, 732 FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC_0)); 733 set->cmd_source_0 = reg_value & ASPEED_CMD_SRC_MASK; 734 reg_value = set->cmd_source_1; 735 reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1, 736 FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC_1)); 737 set->cmd_source_1 = reg_value & ASPEED_CMD_SRC_MASK; 738 return; 739 case gpio_reg_idx_input_mask: 740 reg_value = set->input_mask; 741 reg_value = deposit32(reg_value, pin_idx, 1, 742 FIELD_EX32(data, GPIO_INDEX_REG, INPUT_MASK)); 743 /* 744 * feeds into interrupt generation 745 * 0: read from data value reg will be updated 746 * 1: read from data value reg will not be updated 747 */ 748 set->input_mask = reg_value & props->input; 749 break; 750 default: 751 qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" 752 PRIx64 "index mode wrong type 0x%x\n", 753 __func__, offset, data, reg_idx_type); 754 return; 755 } 756 aspeed_gpio_update(s, set, set->data_value); 757 return; 758 } 759 760 static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, 761 uint32_t size) 762 { 763 AspeedGPIOState *s = ASPEED_GPIO(opaque); 764 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 765 const GPIOSetProperties *props; 766 uint64_t idx = -1; 767 const AspeedGPIOReg *reg; 768 GPIOSets *set; 769 uint32_t cleared; 770 771 trace_aspeed_gpio_write(offset, data); 772 773 idx = offset >> 2; 774 775 /* check gpio index mode */ 776 if (idx == R_GPIO_INDEX_REG) { 777 aspeed_gpio_write_index_mode(opaque, offset, data, size); 778 return; 779 } 780 781 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 782 idx -= GPIO_DEBOUNCE_TIME_1; 783 s->debounce_regs[idx] = (uint32_t) data; 784 return; 785 } 786 787 reg = &agc->reg_table[idx]; 788 if (reg->set_idx >= agc->nr_gpio_sets) { 789 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 790 PRIx64"\n", __func__, offset); 791 return; 792 } 793 794 set = &s->sets[reg->set_idx]; 795 props = &agc->props[reg->set_idx]; 796 797 switch (reg->type) { 798 case gpio_reg_data_value: 799 data &= props->output; 800 data = update_value_control_source(set, set->data_value, data); 801 set->data_read = data; 802 aspeed_gpio_update(s, set, data); 803 return; 804 case gpio_reg_direction: 805 /* 806 * where data is the value attempted to be written to the pin: 807 * pin type | input mask | output mask | expected value 808 * ------------------------------------------------------------ 809 * bidirectional | 1 | 1 | data 810 * input only | 1 | 0 | 0 811 * output only | 0 | 1 | 1 812 * no pin | 0 | 0 | 0 813 * 814 * which is captured by: 815 * data = ( data | ~input) & output; 816 */ 817 data = (data | ~props->input) & props->output; 818 set->direction = update_value_control_source(set, set->direction, data); 819 break; 820 case gpio_reg_int_enable: 821 set->int_enable = update_value_control_source(set, set->int_enable, 822 data); 823 break; 824 case gpio_reg_int_sens_0: 825 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, 826 data); 827 break; 828 case gpio_reg_int_sens_1: 829 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, 830 data); 831 break; 832 case gpio_reg_int_sens_2: 833 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, 834 data); 835 break; 836 case gpio_reg_int_status: 837 cleared = ctpop32(data & set->int_status); 838 if (s->pending && cleared) { 839 assert(s->pending >= cleared); 840 s->pending -= cleared; 841 } 842 set->int_status &= ~data; 843 break; 844 case gpio_reg_reset_tolerant: 845 set->reset_tol = update_value_control_source(set, set->reset_tol, 846 data); 847 return; 848 case gpio_reg_debounce_1: 849 set->debounce_1 = update_value_control_source(set, set->debounce_1, 850 data); 851 return; 852 case gpio_reg_debounce_2: 853 set->debounce_2 = update_value_control_source(set, set->debounce_2, 854 data); 855 return; 856 case gpio_reg_cmd_source_0: 857 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; 858 return; 859 case gpio_reg_cmd_source_1: 860 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; 861 return; 862 case gpio_reg_data_read: 863 /* Read only register */ 864 return; 865 case gpio_reg_input_mask: 866 /* 867 * feeds into interrupt generation 868 * 0: read from data value reg will be updated 869 * 1: read from data value reg will not be updated 870 */ 871 set->input_mask = data & props->input; 872 break; 873 default: 874 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 875 PRIx64"\n", __func__, offset); 876 return; 877 } 878 aspeed_gpio_update(s, set, set->data_value); 879 return; 880 } 881 882 static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx) 883 { 884 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 885 int set_idx, g_idx; 886 887 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { 888 const GPIOSetProperties *set_props = &agc->props[set_idx]; 889 for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) { 890 if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) { 891 *group_idx = g_idx; 892 return set_idx; 893 } 894 } 895 } 896 return -1; 897 } 898 899 static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, 900 void *opaque, Error **errp) 901 { 902 int pin = 0xfff; 903 bool level = true; 904 char group[4]; 905 AspeedGPIOState *s = ASPEED_GPIO(obj); 906 int set_idx, group_idx = 0; 907 908 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 909 /* 1.8V gpio */ 910 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 911 error_setg(errp, "%s: error reading %s", __func__, name); 912 return; 913 } 914 } 915 set_idx = get_set_idx(s, group, &group_idx); 916 if (set_idx == -1) { 917 error_setg(errp, "%s: invalid group %s", __func__, group); 918 return; 919 } 920 pin = pin + group_idx * GPIOS_PER_GROUP; 921 level = aspeed_gpio_get_pin_level(s, set_idx, pin); 922 visit_type_bool(v, name, &level, errp); 923 } 924 925 static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, 926 void *opaque, Error **errp) 927 { 928 bool level; 929 int pin = 0xfff; 930 char group[4]; 931 AspeedGPIOState *s = ASPEED_GPIO(obj); 932 int set_idx, group_idx = 0; 933 934 if (!visit_type_bool(v, name, &level, errp)) { 935 return; 936 } 937 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 938 /* 1.8V gpio */ 939 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 940 error_setg(errp, "%s: error reading %s", __func__, name); 941 return; 942 } 943 } 944 set_idx = get_set_idx(s, group, &group_idx); 945 if (set_idx == -1) { 946 error_setg(errp, "%s: invalid group %s", __func__, group); 947 return; 948 } 949 pin = pin + group_idx * GPIOS_PER_GROUP; 950 aspeed_gpio_set_pin_level(s, set_idx, pin, level); 951 } 952 953 /****************** Setup functions ******************/ 954 static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 955 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 956 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 957 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 958 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 959 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 960 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 961 [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 962 }; 963 964 static const GPIOSetProperties ast2500_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 965 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 966 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 967 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 968 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 969 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 970 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 971 [6] = {0x0fffffff, 0x0fffffff, {"Y", "Z", "AA", "AB"} }, 972 [7] = {0x000000ff, 0x000000ff, {"AC"} }, 973 }; 974 975 static GPIOSetProperties ast2600_3_3v_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 976 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 977 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 978 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 979 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 980 [4] = {0xffffffff, 0x00ffffff, {"Q", "R", "S", "T"} }, 981 [5] = {0xffffffff, 0xffffff00, {"U", "V", "W", "X"} }, 982 [6] = {0x0000ffff, 0x0000ffff, {"Y", "Z"} }, 983 }; 984 985 static GPIOSetProperties ast2600_1_8v_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 986 [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} }, 987 [1] = {0x0000000f, 0x0000000f, {"18E"} }, 988 }; 989 990 static GPIOSetProperties ast1030_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 991 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 992 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 993 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 994 [3] = {0xffffff3f, 0xffffff3f, {"M", "N", "O", "P"} }, 995 [4] = {0xff060c1f, 0x00060c1f, {"Q", "R", "S", "T"} }, 996 [5] = {0x000000ff, 0x00000000, {"U"} }, 997 }; 998 999 static const MemoryRegionOps aspeed_gpio_ops = { 1000 .read = aspeed_gpio_read, 1001 .write = aspeed_gpio_write, 1002 .endianness = DEVICE_LITTLE_ENDIAN, 1003 .valid.min_access_size = 4, 1004 .valid.max_access_size = 4, 1005 }; 1006 1007 static void aspeed_gpio_reset(DeviceState *dev) 1008 { 1009 AspeedGPIOState *s = ASPEED_GPIO(dev); 1010 1011 /* TODO: respect the reset tolerance registers */ 1012 memset(s->sets, 0, sizeof(s->sets)); 1013 } 1014 1015 static void aspeed_gpio_realize(DeviceState *dev, Error **errp) 1016 { 1017 AspeedGPIOState *s = ASPEED_GPIO(dev); 1018 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1019 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 1020 1021 /* Interrupt parent line */ 1022 sysbus_init_irq(sbd, &s->irq); 1023 1024 /* Individual GPIOs */ 1025 for (int i = 0; i < ASPEED_GPIO_MAX_NR_SETS; i++) { 1026 const GPIOSetProperties *props = &agc->props[i]; 1027 uint32_t skip = ~(props->input | props->output); 1028 for (int j = 0; j < ASPEED_GPIOS_PER_SET; j++) { 1029 if (skip >> j & 1) { 1030 continue; 1031 } 1032 sysbus_init_irq(sbd, &s->gpios[i][j]); 1033 } 1034 } 1035 1036 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, 1037 TYPE_ASPEED_GPIO, 0x800); 1038 1039 sysbus_init_mmio(sbd, &s->iomem); 1040 } 1041 1042 static void aspeed_gpio_init(Object *obj) 1043 { 1044 AspeedGPIOState *s = ASPEED_GPIO(obj); 1045 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 1046 1047 for (int i = 0; i < ASPEED_GPIO_MAX_NR_SETS; i++) { 1048 const GPIOSetProperties *props = &agc->props[i]; 1049 uint32_t skip = ~(props->input | props->output); 1050 for (int j = 0; j < ASPEED_GPIOS_PER_SET; j++) { 1051 if (skip >> j & 1) { 1052 continue; 1053 } 1054 int group_idx = j / GPIOS_PER_GROUP; 1055 int pin_idx = j % GPIOS_PER_GROUP; 1056 const char *group = &props->group_label[group_idx][0]; 1057 char *name = g_strdup_printf("gpio%s%d", group, pin_idx); 1058 object_property_add(obj, name, "bool", aspeed_gpio_get_pin, 1059 aspeed_gpio_set_pin, NULL, NULL); 1060 g_free(name); 1061 } 1062 } 1063 } 1064 1065 static const VMStateDescription vmstate_gpio_regs = { 1066 .name = TYPE_ASPEED_GPIO"/regs", 1067 .version_id = 1, 1068 .minimum_version_id = 1, 1069 .fields = (VMStateField[]) { 1070 VMSTATE_UINT32(data_value, GPIOSets), 1071 VMSTATE_UINT32(data_read, GPIOSets), 1072 VMSTATE_UINT32(direction, GPIOSets), 1073 VMSTATE_UINT32(int_enable, GPIOSets), 1074 VMSTATE_UINT32(int_sens_0, GPIOSets), 1075 VMSTATE_UINT32(int_sens_1, GPIOSets), 1076 VMSTATE_UINT32(int_sens_2, GPIOSets), 1077 VMSTATE_UINT32(int_status, GPIOSets), 1078 VMSTATE_UINT32(reset_tol, GPIOSets), 1079 VMSTATE_UINT32(cmd_source_0, GPIOSets), 1080 VMSTATE_UINT32(cmd_source_1, GPIOSets), 1081 VMSTATE_UINT32(debounce_1, GPIOSets), 1082 VMSTATE_UINT32(debounce_2, GPIOSets), 1083 VMSTATE_UINT32(input_mask, GPIOSets), 1084 VMSTATE_END_OF_LIST(), 1085 } 1086 }; 1087 1088 static const VMStateDescription vmstate_aspeed_gpio = { 1089 .name = TYPE_ASPEED_GPIO, 1090 .version_id = 1, 1091 .minimum_version_id = 1, 1092 .fields = (VMStateField[]) { 1093 VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS, 1094 1, vmstate_gpio_regs, GPIOSets), 1095 VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState, 1096 ASPEED_GPIO_NR_DEBOUNCE_REGS), 1097 VMSTATE_END_OF_LIST(), 1098 } 1099 }; 1100 1101 static void aspeed_gpio_class_init(ObjectClass *klass, void *data) 1102 { 1103 DeviceClass *dc = DEVICE_CLASS(klass); 1104 1105 dc->realize = aspeed_gpio_realize; 1106 dc->reset = aspeed_gpio_reset; 1107 dc->desc = "Aspeed GPIO Controller"; 1108 dc->vmsd = &vmstate_aspeed_gpio; 1109 } 1110 1111 static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) 1112 { 1113 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1114 1115 agc->props = ast2400_set_props; 1116 agc->nr_gpio_pins = 216; 1117 agc->nr_gpio_sets = 7; 1118 agc->reg_table = aspeed_3_3v_gpios; 1119 } 1120 1121 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) 1122 { 1123 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1124 1125 agc->props = ast2500_set_props; 1126 agc->nr_gpio_pins = 228; 1127 agc->nr_gpio_sets = 8; 1128 agc->reg_table = aspeed_3_3v_gpios; 1129 } 1130 1131 static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) 1132 { 1133 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1134 1135 agc->props = ast2600_3_3v_set_props; 1136 agc->nr_gpio_pins = 208; 1137 agc->nr_gpio_sets = 7; 1138 agc->reg_table = aspeed_3_3v_gpios; 1139 } 1140 1141 static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) 1142 { 1143 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1144 1145 agc->props = ast2600_1_8v_set_props; 1146 agc->nr_gpio_pins = 36; 1147 agc->nr_gpio_sets = 2; 1148 agc->reg_table = aspeed_1_8v_gpios; 1149 } 1150 1151 static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) 1152 { 1153 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1154 1155 agc->props = ast1030_set_props; 1156 agc->nr_gpio_pins = 151; 1157 agc->nr_gpio_sets = 6; 1158 agc->reg_table = aspeed_3_3v_gpios; 1159 } 1160 1161 static const TypeInfo aspeed_gpio_info = { 1162 .name = TYPE_ASPEED_GPIO, 1163 .parent = TYPE_SYS_BUS_DEVICE, 1164 .instance_size = sizeof(AspeedGPIOState), 1165 .class_size = sizeof(AspeedGPIOClass), 1166 .class_init = aspeed_gpio_class_init, 1167 .abstract = true, 1168 }; 1169 1170 static const TypeInfo aspeed_gpio_ast2400_info = { 1171 .name = TYPE_ASPEED_GPIO "-ast2400", 1172 .parent = TYPE_ASPEED_GPIO, 1173 .class_init = aspeed_gpio_ast2400_class_init, 1174 .instance_init = aspeed_gpio_init, 1175 }; 1176 1177 static const TypeInfo aspeed_gpio_ast2500_info = { 1178 .name = TYPE_ASPEED_GPIO "-ast2500", 1179 .parent = TYPE_ASPEED_GPIO, 1180 .class_init = aspeed_gpio_2500_class_init, 1181 .instance_init = aspeed_gpio_init, 1182 }; 1183 1184 static const TypeInfo aspeed_gpio_ast2600_3_3v_info = { 1185 .name = TYPE_ASPEED_GPIO "-ast2600", 1186 .parent = TYPE_ASPEED_GPIO, 1187 .class_init = aspeed_gpio_ast2600_3_3v_class_init, 1188 .instance_init = aspeed_gpio_init, 1189 }; 1190 1191 static const TypeInfo aspeed_gpio_ast2600_1_8v_info = { 1192 .name = TYPE_ASPEED_GPIO "-ast2600-1_8v", 1193 .parent = TYPE_ASPEED_GPIO, 1194 .class_init = aspeed_gpio_ast2600_1_8v_class_init, 1195 .instance_init = aspeed_gpio_init, 1196 }; 1197 1198 static const TypeInfo aspeed_gpio_ast1030_info = { 1199 .name = TYPE_ASPEED_GPIO "-ast1030", 1200 .parent = TYPE_ASPEED_GPIO, 1201 .class_init = aspeed_gpio_1030_class_init, 1202 .instance_init = aspeed_gpio_init, 1203 }; 1204 1205 static void aspeed_gpio_register_types(void) 1206 { 1207 type_register_static(&aspeed_gpio_info); 1208 type_register_static(&aspeed_gpio_ast2400_info); 1209 type_register_static(&aspeed_gpio_ast2500_info); 1210 type_register_static(&aspeed_gpio_ast2600_3_3v_info); 1211 type_register_static(&aspeed_gpio_ast2600_1_8v_info); 1212 type_register_static(&aspeed_gpio_ast1030_info); 1213 } 1214 1215 type_init(aspeed_gpio_register_types); 1216