1 /* 2 * SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright (C) 2019 IBM Corp. 4 * 5 * IBM On-chip Peripheral Bus 6 */ 7 8 #include "qemu/osdep.h" 9 10 #include "qapi/error.h" 11 12 #include "qemu/log.h" 13 14 #include "hw/fsi/bits.h" 15 #include "hw/fsi/fsi-master.h" 16 #include "hw/fsi/opb.h" 17 18 #define TO_REG(x) ((x) >> 2) 19 20 #define FSI_MMODE TO_REG(0x000) 21 #define FSI_MMODE_IPOLL_DMA_EN BE_BIT(0) 22 #define FSI_MMODE_HW_ERROR_RECOVERY_EN BE_BIT(1) 23 #define FSI_MMODE_RELATIVE_ADDRESS_EN BE_BIT(2) 24 #define FSI_MMODE_PARITY_CHECK_EN BE_BIT(3) 25 #define FSI_MMODE_CLOCK_DIVIDER_0 BE_GENMASK(4, 13) 26 #define FSI_MMODE_CLOCK_DIVIDER_1 BE_GENMASK(14, 23) 27 #define FSI_MMODE_DEBUG_EN BE_BIT(24) 28 29 #define FSI_MDELAY TO_REG(0x004) 30 #define FSI_MDELAY_ECHO_0 BE_GENMASK(0, 3) 31 #define FSI_MDELAY_SEND_0 BE_GENMASK(4, 7) 32 #define FSI_MDELAY_ECHO_1 BE_GENMASK(8, 11) 33 #define FSI_MDELAY_SEND_1 BE_GENMASK(12, 15) 34 35 #define FSI_MENP0 TO_REG(0x010) 36 #define FSI_MENP32 TO_REG(0x014) 37 #define FSI_MSENP0 TO_REG(0x018) 38 #define FSI_MLEVP0 TO_REG(0x018) 39 #define FSI_MSENP32 TO_REG(0x01c) 40 #define FSI_MLEVP32 TO_REG(0x01c) 41 #define FSI_MCENP0 TO_REG(0x020) 42 #define FSI_MREFP0 TO_REG(0x020) 43 #define FSI_MCENP32 TO_REG(0x024) 44 #define FSI_MREFP32 TO_REG(0x024) 45 46 #define FSI_MAEB TO_REG(0x070) 47 #define FSI_MAEB_ANY_CPU_ERROR BE_BIT(0) 48 #define FSI_MAEB_ANY_DMA_ERROR BE_GENMASK(1, 16) 49 #define FSI_MAEB_ANY_PARITY_ERROR BE_BIT(17) 50 51 #define FSI_MVER TO_REG(0x074) 52 #define FSI_MVER_VERSION BE_GENMASK(0, 7) 53 #define FSI_MVER_BRIDGES BE_GENMASK(8, 15) 54 #define FSI_MVER_PORTS BE_GENMASK(16, 23) 55 56 #define FSI_MRESP0 TO_REG(0x0d0) 57 #define FSI_MRESP0_RESET_PORT_GENERAL BE_BIT(0) 58 #define FSI_MRESP0_RESET_PORT_ERROR BE_BIT(1) 59 #define FSI_MRESP0_RESET_ALL_BRIDGES_GENERAL BE_BIT(2) 60 #define FSI_MRESP0_RESET_ALL_PORTS_GENERAL BE_BIT(3) 61 #define FSI_MRESP0_RESET_MASTER BE_BIT(4) 62 #define FSI_MRESP0_RESET_PARITY_ERROR_LATCH BE_BIT(5) 63 64 #define FSI_MRESB0 TO_REG(0x1d0) 65 #define FSI_MRESB0_RESET_GENERAL BE_BIT(0) 66 #define FSI_MRESB0_RESET_ERROR BE_BIT(1) 67 #define FSI_MRESB0_SET_DMA_SUSPEND BE_BIT(5) 68 #define FSI_MRESB0_CLEAR_DMA_SUSPEND BE_BIT(6) 69 #define FSI_MRESB0_SET_DELAY_MEASURE BE_BIT(7) 70 71 #define FSI_MECTRL TO_REG(0x2e0) 72 #define FSI_MECTRL_TEST_PULSE BE_GENMASK(0, 7) 73 #define FSI_MECTRL_INHIBIT_PARITY_ERROR BE_GENMASK(8, 15) 74 #define FSI_MECTRL_ENABLE_OPB_ERR_ACK BE_BIT(16) 75 #define FSI_MECTRL_AUTO_TERMINATE BE_BIT(17) 76 #define FSI_MECTRL_PORT_ERROR_FREEZE BE_BIT(18) 77 78 static uint64_t fsi_master_read(void *opaque, hwaddr addr, unsigned size) 79 { 80 FSIMasterState *s = FSI_MASTER(opaque); 81 82 qemu_log_mask(LOG_UNIMP, "%s: read @0x%" HWADDR_PRIx " size=%d\n", 83 __func__, addr, size); 84 85 if (addr + size > sizeof(s->regs)) { 86 qemu_log_mask(LOG_GUEST_ERROR, "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n", 87 __func__, addr, size); 88 return 0; 89 } 90 91 return s->regs[TO_REG(addr)]; 92 } 93 94 static void fsi_master_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) 95 { 96 FSIMasterState *s = FSI_MASTER(opaque); 97 98 qemu_log_mask(LOG_UNIMP, "%s: write @0x%" HWADDR_PRIx " size=%d " 99 "value=%"PRIx64"\n", __func__, addr, size, data); 100 101 if (addr + size > sizeof(s->regs)) { 102 qemu_log_mask(LOG_GUEST_ERROR, "%s: Out of bounds write: %"HWADDR_PRIx" for %u\n", 103 __func__, addr, size); 104 return; 105 } 106 107 switch (TO_REG(addr)) { 108 case FSI_MENP0: 109 s->regs[FSI_MENP0] = data; 110 break; 111 case FSI_MENP32: 112 s->regs[FSI_MENP32] = data; 113 break; 114 case FSI_MSENP0: 115 s->regs[FSI_MENP0] |= data; 116 break; 117 case FSI_MSENP32: 118 s->regs[FSI_MENP32] |= data; 119 break; 120 case FSI_MCENP0: 121 s->regs[FSI_MENP0] &= ~data; 122 break; 123 case FSI_MCENP32: 124 s->regs[FSI_MENP32] &= ~data; 125 break; 126 case FSI_MRESP0: 127 /* Perform necessary resets leave register 0 to indicate no errors */ 128 break; 129 case FSI_MRESB0: 130 if (data & FSI_MRESB0_RESET_GENERAL) { 131 qdev_reset_all(DEVICE(opaque)); 132 } 133 if (data & FSI_MRESB0_RESET_ERROR) { 134 /* FIXME: this seems dubious */ 135 qdev_reset_all(DEVICE(opaque)); 136 } 137 break; 138 default: 139 s->regs[TO_REG(addr)] = data; 140 } 141 } 142 143 static const struct MemoryRegionOps fsi_master_ops = { 144 .read = fsi_master_read, 145 .write = fsi_master_write, 146 .endianness = DEVICE_BIG_ENDIAN, 147 }; 148 149 static void fsi_master_realize(DeviceState *dev, Error **errp) 150 { 151 FSIMasterState *s = FSI_MASTER(dev); 152 Error *err = NULL; 153 154 qbus_create_inplace(&s->bus, sizeof(s->bus), TYPE_FSI_BUS, DEVICE(s), NULL); 155 156 memory_region_init_io(&s->iomem, OBJECT(s), &fsi_master_ops, s, 157 TYPE_FSI_MASTER, 0x10000000); 158 memory_region_init(&s->opb2fsi, OBJECT(s), "fsi.opb2fsi", 0x10000000); 159 160 object_property_set_bool(OBJECT(&s->bus), "realized", true, &err); 161 if (err) { 162 error_propagate(errp, err); 163 return; 164 } 165 166 memory_region_add_subregion(&s->opb2fsi, 0, &s->bus.slave.mr); 167 } 168 169 static void fsi_master_reset(DeviceState *dev) 170 { 171 FSIMasterState *s = FSI_MASTER(dev); 172 173 /* ASPEED default */ 174 s->regs[FSI_MVER] = 0xe0050101; 175 } 176 177 static void fsi_master_class_init(ObjectClass *klass, void *data) 178 { 179 DeviceClass *dc = DEVICE_CLASS(klass); 180 181 dc->bus_type = TYPE_OP_BUS; 182 dc->desc = "FSI Master"; 183 dc->realize = fsi_master_realize; 184 dc->reset = fsi_master_reset; 185 } 186 187 static const TypeInfo fsi_master_info = { 188 .name = TYPE_FSI_MASTER, 189 .parent = TYPE_DEVICE, 190 .instance_size = sizeof(FSIMasterState), 191 .class_init = fsi_master_class_init, 192 }; 193 194 static void fsi_register_types(void) 195 { 196 type_register_static(&fsi_master_info); 197 } 198 199 type_init(fsi_register_types); 200