xref: /openbmc/qemu/hw/fsi/fsi-master.c (revision 6a02465f)
1 /*
2  * SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright (C) 2024 IBM Corp.
4  *
5  * IBM Flexible Service Interface master
6  */
7 
8 #include "qemu/osdep.h"
9 #include "qapi/error.h"
10 #include "qemu/log.h"
11 #include "trace.h"
12 
13 #include "hw/fsi/fsi-master.h"
14 
15 #define TYPE_OP_BUS "opb"
16 
17 #define TO_REG(x)                               ((x) >> 2)
18 
19 #define FSI_MENP0                               TO_REG(0x010)
20 #define FSI_MENP32                              TO_REG(0x014)
21 #define FSI_MSENP0                              TO_REG(0x018)
22 #define FSI_MLEVP0                              TO_REG(0x018)
23 #define FSI_MSENP32                             TO_REG(0x01c)
24 #define FSI_MLEVP32                             TO_REG(0x01c)
25 #define FSI_MCENP0                              TO_REG(0x020)
26 #define FSI_MREFP0                              TO_REG(0x020)
27 #define FSI_MCENP32                             TO_REG(0x024)
28 #define FSI_MREFP32                             TO_REG(0x024)
29 
30 #define FSI_MVER                                TO_REG(0x074)
31 #define FSI_MRESP0                              TO_REG(0x0d0)
32 
33 #define FSI_MRESB0                              TO_REG(0x1d0)
34 #define   FSI_MRESB0_RESET_GENERAL              BIT(31)
35 #define   FSI_MRESB0_RESET_ERROR                BIT(30)
36 
37 static uint64_t fsi_master_read(void *opaque, hwaddr addr, unsigned size)
38 {
39     FSIMasterState *s = FSI_MASTER(opaque);
40     int reg = TO_REG(addr);
41 
42     trace_fsi_master_read(addr, size);
43 
44     if (reg >= FSI_MASTER_NR_REGS) {
45         qemu_log_mask(LOG_GUEST_ERROR,
46                       "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
47                       __func__, addr, size);
48         return 0;
49     }
50 
51     return s->regs[reg];
52 }
53 
54 static void fsi_master_write(void *opaque, hwaddr addr, uint64_t data,
55                              unsigned size)
56 {
57     FSIMasterState *s = FSI_MASTER(opaque);
58     int reg = TO_REG(addr);
59 
60     trace_fsi_master_write(addr, size, data);
61 
62     if (reg >= FSI_MASTER_NR_REGS) {
63         qemu_log_mask(LOG_GUEST_ERROR,
64                       "%s: Out of bounds write: %"HWADDR_PRIx" for %u\n",
65                       __func__, addr, size);
66         return;
67     }
68 
69     switch (reg) {
70     case FSI_MENP0:
71         s->regs[FSI_MENP0] = data;
72         break;
73     case FSI_MENP32:
74         s->regs[FSI_MENP32] = data;
75         break;
76     case FSI_MSENP0:
77         s->regs[FSI_MENP0] |= data;
78         break;
79     case FSI_MSENP32:
80         s->regs[FSI_MENP32] |= data;
81         break;
82     case FSI_MCENP0:
83         s->regs[FSI_MENP0] &= ~data;
84         break;
85     case FSI_MCENP32:
86         s->regs[FSI_MENP32] &= ~data;
87         break;
88     case FSI_MRESP0:
89         /* Perform necessary resets leave register 0 to indicate no errors */
90         break;
91     case FSI_MRESB0:
92         if (data & FSI_MRESB0_RESET_GENERAL) {
93             device_cold_reset(DEVICE(opaque));
94         }
95         if (data & FSI_MRESB0_RESET_ERROR) {
96             /* FIXME: this seems dubious */
97             device_cold_reset(DEVICE(opaque));
98         }
99         break;
100     default:
101         s->regs[reg] = data;
102     }
103 }
104 
105 static const struct MemoryRegionOps fsi_master_ops = {
106     .read = fsi_master_read,
107     .write = fsi_master_write,
108     .endianness = DEVICE_BIG_ENDIAN,
109 };
110 
111 static void fsi_master_init(Object *o)
112 {
113     FSIMasterState *s = FSI_MASTER(o);
114 
115     object_initialize_child(o, "cfam", &s->cfam, TYPE_FSI_CFAM);
116 
117     qbus_init(&s->bus, sizeof(s->bus), TYPE_FSI_BUS, DEVICE(s), NULL);
118 
119     memory_region_init_io(&s->iomem, OBJECT(s), &fsi_master_ops, s,
120                           TYPE_FSI_MASTER, 0x10000000);
121     memory_region_init(&s->opb2fsi, OBJECT(s), "fsi.opb2fsi", 0x10000000);
122 }
123 
124 static void fsi_master_realize(DeviceState *dev, Error **errp)
125 {
126     FSIMasterState *s = FSI_MASTER(dev);
127 
128     if (!qdev_realize(DEVICE(&s->cfam), BUS(&s->bus), errp)) {
129         return;
130     }
131 
132     /* address ? */
133     memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.mr);
134 }
135 
136 static void fsi_master_reset(DeviceState *dev)
137 {
138     FSIMasterState *s = FSI_MASTER(dev);
139 
140     /* Initialize registers */
141     memset(s->regs, 0, sizeof(s->regs));
142 
143     /* ASPEED default */
144     s->regs[FSI_MVER] = 0xe0050101;
145 }
146 
147 static void fsi_master_class_init(ObjectClass *klass, void *data)
148 {
149     DeviceClass *dc = DEVICE_CLASS(klass);
150 
151     dc->bus_type = TYPE_OP_BUS;
152     dc->desc = "FSI Master";
153     dc->realize = fsi_master_realize;
154     dc->reset = fsi_master_reset;
155 }
156 
157 static const TypeInfo fsi_master_info = {
158     .name = TYPE_FSI_MASTER,
159     .parent = TYPE_DEVICE,
160     .instance_init = fsi_master_init,
161     .instance_size = sizeof(FSIMasterState),
162     .class_init = fsi_master_class_init,
163 };
164 
165 static void fsi_register_types(void)
166 {
167     type_register_static(&fsi_master_info);
168 }
169 
170 type_init(fsi_register_types);
171