1 /* 2 * QEMU Sparc32 DMA controller emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Modifications: 7 * 2010-Feb-14 Artyom Tarasenko : reworked irq generation 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/hw.h" 30 #include "hw/irq.h" 31 #include "hw/sparc/sparc32_dma.h" 32 #include "hw/sparc/sun4m_iommu.h" 33 #include "hw/sysbus.h" 34 #include "sysemu/dma.h" 35 #include "qapi/error.h" 36 #include "qemu/module.h" 37 #include "trace.h" 38 39 /* 40 * This is the DMA controller part of chip STP2000 (Master I/O), also 41 * produced as NCR89C100. See 42 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 43 * and 44 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt 45 */ 46 47 #define DMA_SIZE (4 * sizeof(uint32_t)) 48 /* We need the mask, because one instance of the device is not page 49 aligned (ledma, start address 0x0010) */ 50 #define DMA_MASK (DMA_SIZE - 1) 51 /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */ 52 #define DMA_ETH_SIZE (8 * sizeof(uint32_t)) 53 #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1) 54 55 #define DMA_VER 0xa0000000 56 #define DMA_INTR 1 57 #define DMA_INTREN 0x10 58 #define DMA_WRITE_MEM 0x100 59 #define DMA_EN 0x200 60 #define DMA_LOADED 0x04000000 61 #define DMA_DRAIN_FIFO 0x40 62 #define DMA_RESET 0x80 63 64 /* XXX SCSI and ethernet should have different read-only bit masks */ 65 #define DMA_CSR_RO_MASK 0xfe000007 66 67 enum { 68 GPIO_RESET = 0, 69 GPIO_DMA, 70 }; 71 72 /* Note: on sparc, the lance 16 bit bus is swapped */ 73 void ledma_memory_read(void *opaque, hwaddr addr, 74 uint8_t *buf, int len, int do_bswap) 75 { 76 DMADeviceState *s = opaque; 77 IOMMUState *is = (IOMMUState *)s->iommu; 78 int i; 79 80 addr |= s->dmaregs[3]; 81 trace_ledma_memory_read(addr, len); 82 if (do_bswap) { 83 dma_memory_read(&is->iommu_as, addr, buf, len); 84 } else { 85 addr &= ~1; 86 len &= ~1; 87 dma_memory_read(&is->iommu_as, addr, buf, len); 88 for(i = 0; i < len; i += 2) { 89 bswap16s((uint16_t *)(buf + i)); 90 } 91 } 92 } 93 94 void ledma_memory_write(void *opaque, hwaddr addr, 95 uint8_t *buf, int len, int do_bswap) 96 { 97 DMADeviceState *s = opaque; 98 IOMMUState *is = (IOMMUState *)s->iommu; 99 int l, i; 100 uint16_t tmp_buf[32]; 101 102 addr |= s->dmaregs[3]; 103 trace_ledma_memory_write(addr, len); 104 if (do_bswap) { 105 dma_memory_write(&is->iommu_as, addr, buf, len); 106 } else { 107 addr &= ~1; 108 len &= ~1; 109 while (len > 0) { 110 l = len; 111 if (l > sizeof(tmp_buf)) 112 l = sizeof(tmp_buf); 113 for(i = 0; i < l; i += 2) { 114 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i)); 115 } 116 dma_memory_write(&is->iommu_as, addr, tmp_buf, l); 117 len -= l; 118 buf += l; 119 addr += l; 120 } 121 } 122 } 123 124 static void dma_set_irq(void *opaque, int irq, int level) 125 { 126 DMADeviceState *s = opaque; 127 if (level) { 128 s->dmaregs[0] |= DMA_INTR; 129 if (s->dmaregs[0] & DMA_INTREN) { 130 trace_sparc32_dma_set_irq_raise(); 131 qemu_irq_raise(s->irq); 132 } 133 } else { 134 if (s->dmaregs[0] & DMA_INTR) { 135 s->dmaregs[0] &= ~DMA_INTR; 136 if (s->dmaregs[0] & DMA_INTREN) { 137 trace_sparc32_dma_set_irq_lower(); 138 qemu_irq_lower(s->irq); 139 } 140 } 141 } 142 } 143 144 void espdma_memory_read(void *opaque, uint8_t *buf, int len) 145 { 146 DMADeviceState *s = opaque; 147 IOMMUState *is = (IOMMUState *)s->iommu; 148 149 trace_espdma_memory_read(s->dmaregs[1], len); 150 dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len); 151 s->dmaregs[1] += len; 152 } 153 154 void espdma_memory_write(void *opaque, uint8_t *buf, int len) 155 { 156 DMADeviceState *s = opaque; 157 IOMMUState *is = (IOMMUState *)s->iommu; 158 159 trace_espdma_memory_write(s->dmaregs[1], len); 160 dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len); 161 s->dmaregs[1] += len; 162 } 163 164 static uint64_t dma_mem_read(void *opaque, hwaddr addr, 165 unsigned size) 166 { 167 DMADeviceState *s = opaque; 168 uint32_t saddr; 169 170 saddr = (addr & DMA_MASK) >> 2; 171 trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]); 172 return s->dmaregs[saddr]; 173 } 174 175 static void dma_mem_write(void *opaque, hwaddr addr, 176 uint64_t val, unsigned size) 177 { 178 DMADeviceState *s = opaque; 179 uint32_t saddr; 180 181 saddr = (addr & DMA_MASK) >> 2; 182 trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val); 183 switch (saddr) { 184 case 0: 185 if (val & DMA_INTREN) { 186 if (s->dmaregs[0] & DMA_INTR) { 187 trace_sparc32_dma_set_irq_raise(); 188 qemu_irq_raise(s->irq); 189 } 190 } else { 191 if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) { 192 trace_sparc32_dma_set_irq_lower(); 193 qemu_irq_lower(s->irq); 194 } 195 } 196 if (val & DMA_RESET) { 197 qemu_irq_raise(s->gpio[GPIO_RESET]); 198 qemu_irq_lower(s->gpio[GPIO_RESET]); 199 } else if (val & DMA_DRAIN_FIFO) { 200 val &= ~DMA_DRAIN_FIFO; 201 } else if (val == 0) 202 val = DMA_DRAIN_FIFO; 203 204 if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) { 205 trace_sparc32_dma_enable_raise(); 206 qemu_irq_raise(s->gpio[GPIO_DMA]); 207 } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) { 208 trace_sparc32_dma_enable_lower(); 209 qemu_irq_lower(s->gpio[GPIO_DMA]); 210 } 211 212 val &= ~DMA_CSR_RO_MASK; 213 val |= DMA_VER; 214 s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val; 215 break; 216 case 1: 217 s->dmaregs[0] |= DMA_LOADED; 218 /* fall through */ 219 default: 220 s->dmaregs[saddr] = val; 221 break; 222 } 223 } 224 225 static const MemoryRegionOps dma_mem_ops = { 226 .read = dma_mem_read, 227 .write = dma_mem_write, 228 .endianness = DEVICE_NATIVE_ENDIAN, 229 .valid = { 230 .min_access_size = 4, 231 .max_access_size = 4, 232 }, 233 }; 234 235 static void sparc32_dma_device_reset(DeviceState *d) 236 { 237 DMADeviceState *s = SPARC32_DMA_DEVICE(d); 238 239 memset(s->dmaregs, 0, DMA_SIZE); 240 s->dmaregs[0] = DMA_VER; 241 } 242 243 static const VMStateDescription vmstate_sparc32_dma_device = { 244 .name ="sparc32_dma", 245 .version_id = 2, 246 .minimum_version_id = 2, 247 .fields = (VMStateField[]) { 248 VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS), 249 VMSTATE_END_OF_LIST() 250 } 251 }; 252 253 static void sparc32_dma_device_init(Object *obj) 254 { 255 DeviceState *dev = DEVICE(obj); 256 DMADeviceState *s = SPARC32_DMA_DEVICE(obj); 257 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 258 259 sysbus_init_irq(sbd, &s->irq); 260 261 sysbus_init_mmio(sbd, &s->iomem); 262 263 object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU, 264 (Object **) &s->iommu, 265 qdev_prop_allow_set_link_before_realize, 266 0, NULL); 267 268 qdev_init_gpio_in(dev, dma_set_irq, 1); 269 qdev_init_gpio_out(dev, s->gpio, 2); 270 } 271 272 static void sparc32_dma_device_class_init(ObjectClass *klass, void *data) 273 { 274 DeviceClass *dc = DEVICE_CLASS(klass); 275 276 dc->reset = sparc32_dma_device_reset; 277 dc->vmsd = &vmstate_sparc32_dma_device; 278 } 279 280 static const TypeInfo sparc32_dma_device_info = { 281 .name = TYPE_SPARC32_DMA_DEVICE, 282 .parent = TYPE_SYS_BUS_DEVICE, 283 .abstract = true, 284 .instance_size = sizeof(DMADeviceState), 285 .instance_init = sparc32_dma_device_init, 286 .class_init = sparc32_dma_device_class_init, 287 }; 288 289 static void sparc32_espdma_device_init(Object *obj) 290 { 291 DMADeviceState *s = SPARC32_DMA_DEVICE(obj); 292 293 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s, 294 "espdma-mmio", DMA_SIZE); 295 } 296 297 static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp) 298 { 299 DeviceState *d; 300 SysBusESPState *sysbus; 301 ESPState *esp; 302 303 d = qdev_create(NULL, TYPE_ESP); 304 object_property_add_child(OBJECT(dev), "esp", OBJECT(d), errp); 305 sysbus = ESP_STATE(d); 306 esp = &sysbus->esp; 307 esp->dma_memory_read = espdma_memory_read; 308 esp->dma_memory_write = espdma_memory_write; 309 esp->dma_opaque = SPARC32_DMA_DEVICE(dev); 310 sysbus->it_shift = 2; 311 esp->dma_enabled = 1; 312 qdev_init_nofail(d); 313 } 314 315 static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data) 316 { 317 DeviceClass *dc = DEVICE_CLASS(klass); 318 319 dc->realize = sparc32_espdma_device_realize; 320 } 321 322 static const TypeInfo sparc32_espdma_device_info = { 323 .name = TYPE_SPARC32_ESPDMA_DEVICE, 324 .parent = TYPE_SPARC32_DMA_DEVICE, 325 .instance_size = sizeof(ESPDMADeviceState), 326 .instance_init = sparc32_espdma_device_init, 327 .class_init = sparc32_espdma_device_class_init, 328 }; 329 330 static void sparc32_ledma_device_init(Object *obj) 331 { 332 DMADeviceState *s = SPARC32_DMA_DEVICE(obj); 333 334 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s, 335 "ledma-mmio", DMA_SIZE); 336 } 337 338 static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp) 339 { 340 DeviceState *d; 341 NICInfo *nd = &nd_table[0]; 342 343 qemu_check_nic_model(nd, TYPE_LANCE); 344 345 d = qdev_create(NULL, TYPE_LANCE); 346 object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp); 347 qdev_set_nic_properties(d, nd); 348 qdev_prop_set_ptr(d, "dma", dev); 349 qdev_init_nofail(d); 350 } 351 352 static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data) 353 { 354 DeviceClass *dc = DEVICE_CLASS(klass); 355 356 dc->realize = sparc32_ledma_device_realize; 357 } 358 359 static const TypeInfo sparc32_ledma_device_info = { 360 .name = TYPE_SPARC32_LEDMA_DEVICE, 361 .parent = TYPE_SPARC32_DMA_DEVICE, 362 .instance_size = sizeof(LEDMADeviceState), 363 .instance_init = sparc32_ledma_device_init, 364 .class_init = sparc32_ledma_device_class_init, 365 }; 366 367 static void sparc32_dma_realize(DeviceState *dev, Error **errp) 368 { 369 SPARC32DMAState *s = SPARC32_DMA(dev); 370 DeviceState *espdma, *esp, *ledma, *lance; 371 SysBusDevice *sbd; 372 Object *iommu; 373 374 iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL); 375 if (!iommu) { 376 error_setg(errp, "unable to locate sun4m IOMMU device"); 377 return; 378 } 379 380 espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE); 381 object_property_set_link(OBJECT(espdma), iommu, "iommu", errp); 382 object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma), errp); 383 qdev_init_nofail(espdma); 384 385 esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp")); 386 sbd = SYS_BUS_DEVICE(esp); 387 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0)); 388 qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0)); 389 qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1)); 390 391 sbd = SYS_BUS_DEVICE(espdma); 392 memory_region_add_subregion(&s->dmamem, 0x0, 393 sysbus_mmio_get_region(sbd, 0)); 394 395 ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE); 396 object_property_set_link(OBJECT(ledma), iommu, "iommu", errp); 397 object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma), errp); 398 qdev_init_nofail(ledma); 399 400 lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance")); 401 sbd = SYS_BUS_DEVICE(lance); 402 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0)); 403 qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0)); 404 405 sbd = SYS_BUS_DEVICE(ledma); 406 memory_region_add_subregion(&s->dmamem, 0x10, 407 sysbus_mmio_get_region(sbd, 0)); 408 409 /* Add ledma alias to handle SunOS 5.7 - Solaris 9 invalid access bug */ 410 memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias", 411 sysbus_mmio_get_region(sbd, 0), 0x4, 0x4); 412 memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias); 413 } 414 415 static void sparc32_dma_init(Object *obj) 416 { 417 SPARC32DMAState *s = SPARC32_DMA(obj); 418 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 419 420 memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE); 421 sysbus_init_mmio(sbd, &s->dmamem); 422 } 423 424 static void sparc32_dma_class_init(ObjectClass *klass, void *data) 425 { 426 DeviceClass *dc = DEVICE_CLASS(klass); 427 428 dc->realize = sparc32_dma_realize; 429 } 430 431 static const TypeInfo sparc32_dma_info = { 432 .name = TYPE_SPARC32_DMA, 433 .parent = TYPE_SYS_BUS_DEVICE, 434 .instance_size = sizeof(SPARC32DMAState), 435 .instance_init = sparc32_dma_init, 436 .class_init = sparc32_dma_class_init, 437 }; 438 439 440 static void sparc32_dma_register_types(void) 441 { 442 type_register_static(&sparc32_dma_device_info); 443 type_register_static(&sparc32_espdma_device_info); 444 type_register_static(&sparc32_ledma_device_info); 445 type_register_static(&sparc32_dma_info); 446 } 447 448 type_init(sparc32_dma_register_types) 449