1 /* 2 * QEMU JAZZ RC4030 chipset 3 * 4 * Copyright (c) 2007-2013 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/hw.h" 26 #include "hw/mips/mips.h" 27 #include "hw/sysbus.h" 28 #include "qemu/timer.h" 29 #include "exec/address-spaces.h" 30 #include "trace.h" 31 32 /********************************************************/ 33 /* rc4030 emulation */ 34 35 #define MAX_TL_ENTRIES 512 36 37 typedef struct dma_pagetable_entry { 38 int32_t frame; 39 int32_t owner; 40 } QEMU_PACKED dma_pagetable_entry; 41 42 #define DMA_PAGESIZE 4096 43 #define DMA_REG_ENABLE 1 44 #define DMA_REG_COUNT 2 45 #define DMA_REG_ADDRESS 3 46 47 #define DMA_FLAG_ENABLE 0x0001 48 #define DMA_FLAG_MEM_TO_DEV 0x0002 49 #define DMA_FLAG_TC_INTR 0x0100 50 #define DMA_FLAG_MEM_INTR 0x0200 51 #define DMA_FLAG_ADDR_INTR 0x0400 52 53 #define TYPE_RC4030 "rc4030" 54 #define RC4030(obj) \ 55 OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030) 56 57 typedef struct rc4030State 58 { 59 SysBusDevice parent; 60 61 uint32_t config; /* 0x0000: RC4030 config register */ 62 uint32_t revision; /* 0x0008: RC4030 Revision register */ 63 uint32_t invalid_address_register; /* 0x0010: Invalid Address register */ 64 65 /* DMA */ 66 uint32_t dma_regs[8][4]; 67 uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */ 68 uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */ 69 70 /* cache */ 71 uint32_t cache_maint; /* 0x0030: Cache Maintenance */ 72 uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */ 73 uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */ 74 uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */ 75 uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */ 76 uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */ 77 78 uint32_t nmi_interrupt; /* 0x0200: interrupt source */ 79 uint32_t memory_refresh_rate; /* 0x0210: memory refresh rate */ 80 uint32_t nvram_protect; /* 0x0220: NV ram protect register */ 81 uint32_t rem_speed[16]; 82 uint32_t imr_jazz; /* Local bus int enable mask */ 83 uint32_t isr_jazz; /* Local bus int source */ 84 85 /* timer */ 86 QEMUTimer *periodic_timer; 87 uint32_t itr; /* Interval timer reload */ 88 89 qemu_irq timer_irq; 90 qemu_irq jazz_bus_irq; 91 92 /* biggest translation table */ 93 MemoryRegion dma_tt; 94 /* translation table memory region alias, added to system RAM */ 95 MemoryRegion dma_tt_alias; 96 /* whole DMA memory region, root of DMA address space */ 97 MemoryRegion dma_mr; 98 /* translation table entry aliases, added to DMA memory region */ 99 MemoryRegion dma_mrs[MAX_TL_ENTRIES]; 100 AddressSpace dma_as; 101 102 MemoryRegion iomem_chipset; 103 MemoryRegion iomem_jazzio; 104 } rc4030State; 105 106 static void set_next_tick(rc4030State *s) 107 { 108 qemu_irq_lower(s->timer_irq); 109 uint32_t tm_hz; 110 111 tm_hz = 1000 / (s->itr + 1); 112 113 timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 114 get_ticks_per_sec() / tm_hz); 115 } 116 117 /* called for accesses to rc4030 */ 118 static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size) 119 { 120 rc4030State *s = opaque; 121 uint32_t val; 122 123 addr &= 0x3fff; 124 switch (addr & ~0x3) { 125 /* Global config register */ 126 case 0x0000: 127 val = s->config; 128 break; 129 /* Revision register */ 130 case 0x0008: 131 val = s->revision; 132 break; 133 /* Invalid Address register */ 134 case 0x0010: 135 val = s->invalid_address_register; 136 break; 137 /* DMA transl. table base */ 138 case 0x0018: 139 val = s->dma_tl_base; 140 break; 141 /* DMA transl. table limit */ 142 case 0x0020: 143 val = s->dma_tl_limit; 144 break; 145 /* Remote Failed Address */ 146 case 0x0038: 147 val = s->remote_failed_address; 148 break; 149 /* Memory Failed Address */ 150 case 0x0040: 151 val = s->memory_failed_address; 152 break; 153 /* I/O Cache Byte Mask */ 154 case 0x0058: 155 val = s->cache_bmask; 156 /* HACK */ 157 if (s->cache_bmask == (uint32_t)-1) 158 s->cache_bmask = 0; 159 break; 160 /* Remote Speed Registers */ 161 case 0x0070: 162 case 0x0078: 163 case 0x0080: 164 case 0x0088: 165 case 0x0090: 166 case 0x0098: 167 case 0x00a0: 168 case 0x00a8: 169 case 0x00b0: 170 case 0x00b8: 171 case 0x00c0: 172 case 0x00c8: 173 case 0x00d0: 174 case 0x00d8: 175 case 0x00e0: 176 case 0x00e8: 177 val = s->rem_speed[(addr - 0x0070) >> 3]; 178 break; 179 /* DMA channel base address */ 180 case 0x0100: 181 case 0x0108: 182 case 0x0110: 183 case 0x0118: 184 case 0x0120: 185 case 0x0128: 186 case 0x0130: 187 case 0x0138: 188 case 0x0140: 189 case 0x0148: 190 case 0x0150: 191 case 0x0158: 192 case 0x0160: 193 case 0x0168: 194 case 0x0170: 195 case 0x0178: 196 case 0x0180: 197 case 0x0188: 198 case 0x0190: 199 case 0x0198: 200 case 0x01a0: 201 case 0x01a8: 202 case 0x01b0: 203 case 0x01b8: 204 case 0x01c0: 205 case 0x01c8: 206 case 0x01d0: 207 case 0x01d8: 208 case 0x01e0: 209 case 0x01e8: 210 case 0x01f0: 211 case 0x01f8: 212 { 213 int entry = (addr - 0x0100) >> 5; 214 int idx = (addr & 0x1f) >> 3; 215 val = s->dma_regs[entry][idx]; 216 } 217 break; 218 /* Interrupt source */ 219 case 0x0200: 220 val = s->nmi_interrupt; 221 break; 222 /* Error type */ 223 case 0x0208: 224 val = 0; 225 break; 226 /* Memory refresh rate */ 227 case 0x0210: 228 val = s->memory_refresh_rate; 229 break; 230 /* NV ram protect register */ 231 case 0x0220: 232 val = s->nvram_protect; 233 break; 234 /* Interval timer count */ 235 case 0x0230: 236 val = 0; 237 qemu_irq_lower(s->timer_irq); 238 break; 239 /* EISA interrupt */ 240 case 0x0238: 241 val = 7; /* FIXME: should be read from EISA controller */ 242 break; 243 default: 244 qemu_log_mask(LOG_GUEST_ERROR, 245 "rc4030: invalid read at 0x%x", (int)addr); 246 val = 0; 247 break; 248 } 249 250 if ((addr & ~3) != 0x230) { 251 trace_rc4030_read(addr, val); 252 } 253 254 return val; 255 } 256 257 static void rc4030_dma_as_update_one(rc4030State *s, int index, uint32_t frame) 258 { 259 if (index < MAX_TL_ENTRIES) { 260 memory_region_set_enabled(&s->dma_mrs[index], false); 261 } 262 263 if (!frame) { 264 return; 265 } 266 267 if (index >= MAX_TL_ENTRIES) { 268 qemu_log_mask(LOG_UNIMP, 269 "rc4030: trying to use too high " 270 "translation table entry %d (max allowed=%d)", 271 index, MAX_TL_ENTRIES); 272 return; 273 } 274 memory_region_set_alias_offset(&s->dma_mrs[index], frame); 275 memory_region_set_enabled(&s->dma_mrs[index], true); 276 } 277 278 static void rc4030_dma_tt_write(void *opaque, hwaddr addr, uint64_t data, 279 unsigned int size) 280 { 281 rc4030State *s = opaque; 282 283 /* write memory */ 284 memcpy(memory_region_get_ram_ptr(&s->dma_tt) + addr, &data, size); 285 286 /* update dma address space (only if frame field has been written) */ 287 if (addr % sizeof(dma_pagetable_entry) == 0) { 288 int index = addr / sizeof(dma_pagetable_entry); 289 memory_region_transaction_begin(); 290 rc4030_dma_as_update_one(s, index, (uint32_t)data); 291 memory_region_transaction_commit(); 292 } 293 } 294 295 static const MemoryRegionOps rc4030_dma_tt_ops = { 296 .write = rc4030_dma_tt_write, 297 .impl.min_access_size = 4, 298 .impl.max_access_size = 4, 299 }; 300 301 static void rc4030_dma_tt_update(rc4030State *s, uint32_t new_tl_base, 302 uint32_t new_tl_limit) 303 { 304 int entries, i; 305 dma_pagetable_entry *dma_tl_contents; 306 307 if (s->dma_tl_limit) { 308 /* write old dma tl table to physical memory */ 309 memory_region_del_subregion(get_system_memory(), &s->dma_tt_alias); 310 cpu_physical_memory_write(s->dma_tl_limit & 0x7fffffff, 311 memory_region_get_ram_ptr(&s->dma_tt), 312 memory_region_size(&s->dma_tt_alias)); 313 } 314 object_unparent(OBJECT(&s->dma_tt_alias)); 315 316 s->dma_tl_base = new_tl_base; 317 s->dma_tl_limit = new_tl_limit; 318 new_tl_base &= 0x7fffffff; 319 320 if (s->dma_tl_limit) { 321 uint64_t dma_tt_size; 322 if (s->dma_tl_limit <= memory_region_size(&s->dma_tt)) { 323 dma_tt_size = s->dma_tl_limit; 324 } else { 325 dma_tt_size = memory_region_size(&s->dma_tt); 326 } 327 memory_region_init_alias(&s->dma_tt_alias, OBJECT(s), 328 "dma-table-alias", 329 &s->dma_tt, 0, dma_tt_size); 330 dma_tl_contents = memory_region_get_ram_ptr(&s->dma_tt); 331 cpu_physical_memory_read(new_tl_base, dma_tl_contents, dma_tt_size); 332 333 memory_region_transaction_begin(); 334 entries = dma_tt_size / sizeof(dma_pagetable_entry); 335 for (i = 0; i < entries; i++) { 336 rc4030_dma_as_update_one(s, i, dma_tl_contents[i].frame); 337 } 338 memory_region_add_subregion(get_system_memory(), new_tl_base, 339 &s->dma_tt_alias); 340 memory_region_transaction_commit(); 341 } else { 342 memory_region_init(&s->dma_tt_alias, OBJECT(s), 343 "dma-table-alias", 0); 344 } 345 } 346 347 static void rc4030_write(void *opaque, hwaddr addr, uint64_t data, 348 unsigned int size) 349 { 350 rc4030State *s = opaque; 351 uint32_t val = data; 352 addr &= 0x3fff; 353 354 trace_rc4030_write(addr, val); 355 356 switch (addr & ~0x3) { 357 /* Global config register */ 358 case 0x0000: 359 s->config = val; 360 break; 361 /* DMA transl. table base */ 362 case 0x0018: 363 rc4030_dma_tt_update(s, val, s->dma_tl_limit); 364 break; 365 /* DMA transl. table limit */ 366 case 0x0020: 367 rc4030_dma_tt_update(s, s->dma_tl_base, val); 368 break; 369 /* DMA transl. table invalidated */ 370 case 0x0028: 371 break; 372 /* Cache Maintenance */ 373 case 0x0030: 374 s->cache_maint = val; 375 break; 376 /* I/O Cache Physical Tag */ 377 case 0x0048: 378 s->cache_ptag = val; 379 break; 380 /* I/O Cache Logical Tag */ 381 case 0x0050: 382 s->cache_ltag = val; 383 break; 384 /* I/O Cache Byte Mask */ 385 case 0x0058: 386 s->cache_bmask |= val; /* HACK */ 387 break; 388 /* I/O Cache Buffer Window */ 389 case 0x0060: 390 /* HACK */ 391 if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { 392 hwaddr dest = s->cache_ptag & ~0x1; 393 dest += (s->cache_maint & 0x3) << 3; 394 cpu_physical_memory_write(dest, &val, 4); 395 } 396 break; 397 /* Remote Speed Registers */ 398 case 0x0070: 399 case 0x0078: 400 case 0x0080: 401 case 0x0088: 402 case 0x0090: 403 case 0x0098: 404 case 0x00a0: 405 case 0x00a8: 406 case 0x00b0: 407 case 0x00b8: 408 case 0x00c0: 409 case 0x00c8: 410 case 0x00d0: 411 case 0x00d8: 412 case 0x00e0: 413 case 0x00e8: 414 s->rem_speed[(addr - 0x0070) >> 3] = val; 415 break; 416 /* DMA channel base address */ 417 case 0x0100: 418 case 0x0108: 419 case 0x0110: 420 case 0x0118: 421 case 0x0120: 422 case 0x0128: 423 case 0x0130: 424 case 0x0138: 425 case 0x0140: 426 case 0x0148: 427 case 0x0150: 428 case 0x0158: 429 case 0x0160: 430 case 0x0168: 431 case 0x0170: 432 case 0x0178: 433 case 0x0180: 434 case 0x0188: 435 case 0x0190: 436 case 0x0198: 437 case 0x01a0: 438 case 0x01a8: 439 case 0x01b0: 440 case 0x01b8: 441 case 0x01c0: 442 case 0x01c8: 443 case 0x01d0: 444 case 0x01d8: 445 case 0x01e0: 446 case 0x01e8: 447 case 0x01f0: 448 case 0x01f8: 449 { 450 int entry = (addr - 0x0100) >> 5; 451 int idx = (addr & 0x1f) >> 3; 452 s->dma_regs[entry][idx] = val; 453 } 454 break; 455 /* Memory refresh rate */ 456 case 0x0210: 457 s->memory_refresh_rate = val; 458 break; 459 /* Interval timer reload */ 460 case 0x0228: 461 s->itr = val; 462 qemu_irq_lower(s->timer_irq); 463 set_next_tick(s); 464 break; 465 /* EISA interrupt */ 466 case 0x0238: 467 break; 468 default: 469 qemu_log_mask(LOG_GUEST_ERROR, 470 "rc4030: invalid write of 0x%02x at 0x%x", 471 val, (int)addr); 472 break; 473 } 474 } 475 476 static const MemoryRegionOps rc4030_ops = { 477 .read = rc4030_read, 478 .write = rc4030_write, 479 .impl.min_access_size = 4, 480 .impl.max_access_size = 4, 481 .endianness = DEVICE_NATIVE_ENDIAN, 482 }; 483 484 static void update_jazz_irq(rc4030State *s) 485 { 486 uint16_t pending; 487 488 pending = s->isr_jazz & s->imr_jazz; 489 490 if (pending != 0) 491 qemu_irq_raise(s->jazz_bus_irq); 492 else 493 qemu_irq_lower(s->jazz_bus_irq); 494 } 495 496 static void rc4030_irq_jazz_request(void *opaque, int irq, int level) 497 { 498 rc4030State *s = opaque; 499 500 if (level) { 501 s->isr_jazz |= 1 << irq; 502 } else { 503 s->isr_jazz &= ~(1 << irq); 504 } 505 506 update_jazz_irq(s); 507 } 508 509 static void rc4030_periodic_timer(void *opaque) 510 { 511 rc4030State *s = opaque; 512 513 set_next_tick(s); 514 qemu_irq_raise(s->timer_irq); 515 } 516 517 static uint64_t jazzio_read(void *opaque, hwaddr addr, unsigned int size) 518 { 519 rc4030State *s = opaque; 520 uint32_t val; 521 uint32_t irq; 522 addr &= 0xfff; 523 524 switch (addr) { 525 /* Local bus int source */ 526 case 0x00: { 527 uint32_t pending = s->isr_jazz & s->imr_jazz; 528 val = 0; 529 irq = 0; 530 while (pending) { 531 if (pending & 1) { 532 val = (irq + 1) << 2; 533 break; 534 } 535 irq++; 536 pending >>= 1; 537 } 538 break; 539 } 540 /* Local bus int enable mask */ 541 case 0x02: 542 val = s->imr_jazz; 543 break; 544 default: 545 qemu_log_mask(LOG_GUEST_ERROR, 546 "rc4030/jazzio: invalid read at 0x%x", (int)addr); 547 val = 0; 548 break; 549 } 550 551 trace_jazzio_read(addr, val); 552 553 return val; 554 } 555 556 static void jazzio_write(void *opaque, hwaddr addr, uint64_t data, 557 unsigned int size) 558 { 559 rc4030State *s = opaque; 560 uint32_t val = data; 561 addr &= 0xfff; 562 563 trace_jazzio_write(addr, val); 564 565 switch (addr) { 566 /* Local bus int enable mask */ 567 case 0x02: 568 s->imr_jazz = val; 569 update_jazz_irq(s); 570 break; 571 default: 572 qemu_log_mask(LOG_GUEST_ERROR, 573 "rc4030/jazzio: invalid write of 0x%02x at 0x%x", 574 val, (int)addr); 575 break; 576 } 577 } 578 579 static const MemoryRegionOps jazzio_ops = { 580 .read = jazzio_read, 581 .write = jazzio_write, 582 .impl.min_access_size = 2, 583 .impl.max_access_size = 2, 584 .endianness = DEVICE_NATIVE_ENDIAN, 585 }; 586 587 static void rc4030_reset(DeviceState *dev) 588 { 589 rc4030State *s = RC4030(dev); 590 int i; 591 592 s->config = 0x410; /* some boards seem to accept 0x104 too */ 593 s->revision = 1; 594 s->invalid_address_register = 0; 595 596 memset(s->dma_regs, 0, sizeof(s->dma_regs)); 597 rc4030_dma_tt_update(s, 0, 0); 598 599 s->remote_failed_address = s->memory_failed_address = 0; 600 s->cache_maint = 0; 601 s->cache_ptag = s->cache_ltag = 0; 602 s->cache_bmask = 0; 603 604 s->memory_refresh_rate = 0x18186; 605 s->nvram_protect = 7; 606 for (i = 0; i < 15; i++) 607 s->rem_speed[i] = 7; 608 s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ 609 s->isr_jazz = 0; 610 611 s->itr = 0; 612 613 qemu_irq_lower(s->timer_irq); 614 qemu_irq_lower(s->jazz_bus_irq); 615 } 616 617 static int rc4030_load(QEMUFile *f, void *opaque, int version_id) 618 { 619 rc4030State* s = opaque; 620 int i, j; 621 622 if (version_id != 2) 623 return -EINVAL; 624 625 s->config = qemu_get_be32(f); 626 s->invalid_address_register = qemu_get_be32(f); 627 for (i = 0; i < 8; i++) 628 for (j = 0; j < 4; j++) 629 s->dma_regs[i][j] = qemu_get_be32(f); 630 s->dma_tl_base = qemu_get_be32(f); 631 s->dma_tl_limit = qemu_get_be32(f); 632 s->cache_maint = qemu_get_be32(f); 633 s->remote_failed_address = qemu_get_be32(f); 634 s->memory_failed_address = qemu_get_be32(f); 635 s->cache_ptag = qemu_get_be32(f); 636 s->cache_ltag = qemu_get_be32(f); 637 s->cache_bmask = qemu_get_be32(f); 638 s->memory_refresh_rate = qemu_get_be32(f); 639 s->nvram_protect = qemu_get_be32(f); 640 for (i = 0; i < 15; i++) 641 s->rem_speed[i] = qemu_get_be32(f); 642 s->imr_jazz = qemu_get_be32(f); 643 s->isr_jazz = qemu_get_be32(f); 644 s->itr = qemu_get_be32(f); 645 646 set_next_tick(s); 647 update_jazz_irq(s); 648 649 return 0; 650 } 651 652 static void rc4030_save(QEMUFile *f, void *opaque) 653 { 654 rc4030State* s = opaque; 655 int i, j; 656 657 qemu_put_be32(f, s->config); 658 qemu_put_be32(f, s->invalid_address_register); 659 for (i = 0; i < 8; i++) 660 for (j = 0; j < 4; j++) 661 qemu_put_be32(f, s->dma_regs[i][j]); 662 qemu_put_be32(f, s->dma_tl_base); 663 qemu_put_be32(f, s->dma_tl_limit); 664 qemu_put_be32(f, s->cache_maint); 665 qemu_put_be32(f, s->remote_failed_address); 666 qemu_put_be32(f, s->memory_failed_address); 667 qemu_put_be32(f, s->cache_ptag); 668 qemu_put_be32(f, s->cache_ltag); 669 qemu_put_be32(f, s->cache_bmask); 670 qemu_put_be32(f, s->memory_refresh_rate); 671 qemu_put_be32(f, s->nvram_protect); 672 for (i = 0; i < 15; i++) 673 qemu_put_be32(f, s->rem_speed[i]); 674 qemu_put_be32(f, s->imr_jazz); 675 qemu_put_be32(f, s->isr_jazz); 676 qemu_put_be32(f, s->itr); 677 } 678 679 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) 680 { 681 rc4030State *s = opaque; 682 hwaddr dma_addr; 683 int dev_to_mem; 684 685 s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); 686 687 /* Check DMA channel consistency */ 688 dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; 689 if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) || 690 (is_write != dev_to_mem)) { 691 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; 692 s->nmi_interrupt |= 1 << n; 693 return; 694 } 695 696 /* Get start address and len */ 697 if (len > s->dma_regs[n][DMA_REG_COUNT]) 698 len = s->dma_regs[n][DMA_REG_COUNT]; 699 dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; 700 701 /* Read/write data at right place */ 702 address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED, 703 buf, len, is_write); 704 705 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; 706 s->dma_regs[n][DMA_REG_COUNT] -= len; 707 } 708 709 struct rc4030DMAState { 710 void *opaque; 711 int n; 712 }; 713 714 void rc4030_dma_read(void *dma, uint8_t *buf, int len) 715 { 716 rc4030_dma s = dma; 717 rc4030_do_dma(s->opaque, s->n, buf, len, 0); 718 } 719 720 void rc4030_dma_write(void *dma, uint8_t *buf, int len) 721 { 722 rc4030_dma s = dma; 723 rc4030_do_dma(s->opaque, s->n, buf, len, 1); 724 } 725 726 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) 727 { 728 rc4030_dma *s; 729 struct rc4030DMAState *p; 730 int i; 731 732 s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n); 733 p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n); 734 for (i = 0; i < n; i++) { 735 p->opaque = opaque; 736 p->n = i; 737 s[i] = p; 738 p++; 739 } 740 return s; 741 } 742 743 static void rc4030_initfn(Object *obj) 744 { 745 DeviceState *dev = DEVICE(obj); 746 rc4030State *s = RC4030(obj); 747 SysBusDevice *sysbus = SYS_BUS_DEVICE(obj); 748 749 qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16); 750 751 sysbus_init_irq(sysbus, &s->timer_irq); 752 sysbus_init_irq(sysbus, &s->jazz_bus_irq); 753 754 register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s); 755 756 sysbus_init_mmio(sysbus, &s->iomem_chipset); 757 sysbus_init_mmio(sysbus, &s->iomem_jazzio); 758 } 759 760 static void rc4030_realize(DeviceState *dev, Error **errp) 761 { 762 rc4030State *s = RC4030(dev); 763 Object *o = OBJECT(dev); 764 int i; 765 766 s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 767 rc4030_periodic_timer, s); 768 769 memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s, 770 "rc4030.chipset", 0x300); 771 memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s, 772 "rc4030.jazzio", 0x00001000); 773 774 memory_region_init_rom_device(&s->dma_tt, o, 775 &rc4030_dma_tt_ops, s, "dma-table", 776 MAX_TL_ENTRIES * sizeof(dma_pagetable_entry), 777 NULL); 778 memory_region_init(&s->dma_tt_alias, o, "dma-table-alias", 0); 779 memory_region_init(&s->dma_mr, o, "dma", INT32_MAX); 780 for (i = 0; i < MAX_TL_ENTRIES; ++i) { 781 memory_region_init_alias(&s->dma_mrs[i], o, "dma-alias", 782 get_system_memory(), 0, DMA_PAGESIZE); 783 memory_region_set_enabled(&s->dma_mrs[i], false); 784 memory_region_add_subregion(&s->dma_mr, i * DMA_PAGESIZE, 785 &s->dma_mrs[i]); 786 } 787 address_space_init(&s->dma_as, &s->dma_mr, "rc4030-dma"); 788 } 789 790 static void rc4030_unrealize(DeviceState *dev, Error **errp) 791 { 792 rc4030State *s = RC4030(dev); 793 int i; 794 795 timer_free(s->periodic_timer); 796 797 address_space_destroy(&s->dma_as); 798 object_unparent(OBJECT(&s->dma_tt)); 799 object_unparent(OBJECT(&s->dma_tt_alias)); 800 object_unparent(OBJECT(&s->dma_mr)); 801 for (i = 0; i < MAX_TL_ENTRIES; ++i) { 802 memory_region_del_subregion(&s->dma_mr, &s->dma_mrs[i]); 803 object_unparent(OBJECT(&s->dma_mrs[i])); 804 } 805 } 806 807 static void rc4030_class_init(ObjectClass *klass, void *class_data) 808 { 809 DeviceClass *dc = DEVICE_CLASS(klass); 810 811 dc->realize = rc4030_realize; 812 dc->unrealize = rc4030_unrealize; 813 dc->reset = rc4030_reset; 814 } 815 816 static const TypeInfo rc4030_info = { 817 .name = TYPE_RC4030, 818 .parent = TYPE_SYS_BUS_DEVICE, 819 .instance_size = sizeof(rc4030State), 820 .instance_init = rc4030_initfn, 821 .class_init = rc4030_class_init, 822 }; 823 824 static void rc4030_register_types(void) 825 { 826 type_register_static(&rc4030_info); 827 } 828 829 type_init(rc4030_register_types) 830 831 DeviceState *rc4030_init(rc4030_dma **dmas, MemoryRegion **dma_mr) 832 { 833 DeviceState *dev; 834 835 dev = qdev_create(NULL, TYPE_RC4030); 836 qdev_init_nofail(dev); 837 838 *dmas = rc4030_allocate_dmas(dev, 4); 839 *dma_mr = &RC4030(dev)->dma_mr; 840 return dev; 841 } 842