1 /* 2 * QEMU JAZZ RC4030 chipset 3 * 4 * Copyright (c) 2007-2013 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/mips/mips.h" 28 #include "hw/sysbus.h" 29 #include "qemu/timer.h" 30 #include "qemu/log.h" 31 #include "qemu/module.h" 32 #include "exec/address-spaces.h" 33 #include "trace.h" 34 35 /********************************************************/ 36 /* rc4030 emulation */ 37 38 typedef struct dma_pagetable_entry { 39 int32_t frame; 40 int32_t owner; 41 } QEMU_PACKED dma_pagetable_entry; 42 43 #define DMA_PAGESIZE 4096 44 #define DMA_REG_ENABLE 1 45 #define DMA_REG_COUNT 2 46 #define DMA_REG_ADDRESS 3 47 48 #define DMA_FLAG_ENABLE 0x0001 49 #define DMA_FLAG_MEM_TO_DEV 0x0002 50 #define DMA_FLAG_TC_INTR 0x0100 51 #define DMA_FLAG_MEM_INTR 0x0200 52 #define DMA_FLAG_ADDR_INTR 0x0400 53 54 #define TYPE_RC4030 "rc4030" 55 #define RC4030(obj) \ 56 OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030) 57 58 #define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region" 59 60 typedef struct rc4030State 61 { 62 SysBusDevice parent; 63 64 uint32_t config; /* 0x0000: RC4030 config register */ 65 uint32_t revision; /* 0x0008: RC4030 Revision register */ 66 uint32_t invalid_address_register; /* 0x0010: Invalid Address register */ 67 68 /* DMA */ 69 uint32_t dma_regs[8][4]; 70 uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */ 71 uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */ 72 73 /* cache */ 74 uint32_t cache_maint; /* 0x0030: Cache Maintenance */ 75 uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */ 76 uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */ 77 uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */ 78 uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */ 79 uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */ 80 81 uint32_t nmi_interrupt; /* 0x0200: interrupt source */ 82 uint32_t memory_refresh_rate; /* 0x0210: memory refresh rate */ 83 uint32_t nvram_protect; /* 0x0220: NV ram protect register */ 84 uint32_t rem_speed[16]; 85 uint32_t imr_jazz; /* Local bus int enable mask */ 86 uint32_t isr_jazz; /* Local bus int source */ 87 88 /* timer */ 89 QEMUTimer *periodic_timer; 90 uint32_t itr; /* Interval timer reload */ 91 92 qemu_irq timer_irq; 93 qemu_irq jazz_bus_irq; 94 95 /* whole DMA memory region, root of DMA address space */ 96 IOMMUMemoryRegion dma_mr; 97 AddressSpace dma_as; 98 99 MemoryRegion iomem_chipset; 100 MemoryRegion iomem_jazzio; 101 } rc4030State; 102 103 static void set_next_tick(rc4030State *s) 104 { 105 uint32_t tm_hz; 106 qemu_irq_lower(s->timer_irq); 107 108 tm_hz = 1000 / (s->itr + 1); 109 110 timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 111 NANOSECONDS_PER_SECOND / tm_hz); 112 } 113 114 /* called for accesses to rc4030 */ 115 static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size) 116 { 117 rc4030State *s = opaque; 118 uint32_t val; 119 120 addr &= 0x3fff; 121 switch (addr & ~0x3) { 122 /* Global config register */ 123 case 0x0000: 124 val = s->config; 125 break; 126 /* Revision register */ 127 case 0x0008: 128 val = s->revision; 129 break; 130 /* Invalid Address register */ 131 case 0x0010: 132 val = s->invalid_address_register; 133 break; 134 /* DMA transl. table base */ 135 case 0x0018: 136 val = s->dma_tl_base; 137 break; 138 /* DMA transl. table limit */ 139 case 0x0020: 140 val = s->dma_tl_limit; 141 break; 142 /* Remote Failed Address */ 143 case 0x0038: 144 val = s->remote_failed_address; 145 break; 146 /* Memory Failed Address */ 147 case 0x0040: 148 val = s->memory_failed_address; 149 break; 150 /* I/O Cache Byte Mask */ 151 case 0x0058: 152 val = s->cache_bmask; 153 /* HACK */ 154 if (s->cache_bmask == (uint32_t)-1) 155 s->cache_bmask = 0; 156 break; 157 /* Remote Speed Registers */ 158 case 0x0070: 159 case 0x0078: 160 case 0x0080: 161 case 0x0088: 162 case 0x0090: 163 case 0x0098: 164 case 0x00a0: 165 case 0x00a8: 166 case 0x00b0: 167 case 0x00b8: 168 case 0x00c0: 169 case 0x00c8: 170 case 0x00d0: 171 case 0x00d8: 172 case 0x00e0: 173 case 0x00e8: 174 val = s->rem_speed[(addr - 0x0070) >> 3]; 175 break; 176 /* DMA channel base address */ 177 case 0x0100: 178 case 0x0108: 179 case 0x0110: 180 case 0x0118: 181 case 0x0120: 182 case 0x0128: 183 case 0x0130: 184 case 0x0138: 185 case 0x0140: 186 case 0x0148: 187 case 0x0150: 188 case 0x0158: 189 case 0x0160: 190 case 0x0168: 191 case 0x0170: 192 case 0x0178: 193 case 0x0180: 194 case 0x0188: 195 case 0x0190: 196 case 0x0198: 197 case 0x01a0: 198 case 0x01a8: 199 case 0x01b0: 200 case 0x01b8: 201 case 0x01c0: 202 case 0x01c8: 203 case 0x01d0: 204 case 0x01d8: 205 case 0x01e0: 206 case 0x01e8: 207 case 0x01f0: 208 case 0x01f8: 209 { 210 int entry = (addr - 0x0100) >> 5; 211 int idx = (addr & 0x1f) >> 3; 212 val = s->dma_regs[entry][idx]; 213 } 214 break; 215 /* Interrupt source */ 216 case 0x0200: 217 val = s->nmi_interrupt; 218 break; 219 /* Error type */ 220 case 0x0208: 221 val = 0; 222 break; 223 /* Memory refresh rate */ 224 case 0x0210: 225 val = s->memory_refresh_rate; 226 break; 227 /* NV ram protect register */ 228 case 0x0220: 229 val = s->nvram_protect; 230 break; 231 /* Interval timer count */ 232 case 0x0230: 233 val = 0; 234 qemu_irq_lower(s->timer_irq); 235 break; 236 /* EISA interrupt */ 237 case 0x0238: 238 val = 7; /* FIXME: should be read from EISA controller */ 239 break; 240 default: 241 qemu_log_mask(LOG_GUEST_ERROR, 242 "rc4030: invalid read at 0x%x", (int)addr); 243 val = 0; 244 break; 245 } 246 247 if ((addr & ~3) != 0x230) { 248 trace_rc4030_read(addr, val); 249 } 250 251 return val; 252 } 253 254 static void rc4030_write(void *opaque, hwaddr addr, uint64_t data, 255 unsigned int size) 256 { 257 rc4030State *s = opaque; 258 uint32_t val = data; 259 addr &= 0x3fff; 260 261 trace_rc4030_write(addr, val); 262 263 switch (addr & ~0x3) { 264 /* Global config register */ 265 case 0x0000: 266 s->config = val; 267 break; 268 /* DMA transl. table base */ 269 case 0x0018: 270 s->dma_tl_base = val; 271 break; 272 /* DMA transl. table limit */ 273 case 0x0020: 274 s->dma_tl_limit = val; 275 break; 276 /* DMA transl. table invalidated */ 277 case 0x0028: 278 break; 279 /* Cache Maintenance */ 280 case 0x0030: 281 s->cache_maint = val; 282 break; 283 /* I/O Cache Physical Tag */ 284 case 0x0048: 285 s->cache_ptag = val; 286 break; 287 /* I/O Cache Logical Tag */ 288 case 0x0050: 289 s->cache_ltag = val; 290 break; 291 /* I/O Cache Byte Mask */ 292 case 0x0058: 293 s->cache_bmask |= val; /* HACK */ 294 break; 295 /* I/O Cache Buffer Window */ 296 case 0x0060: 297 /* HACK */ 298 if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { 299 hwaddr dest = s->cache_ptag & ~0x1; 300 dest += (s->cache_maint & 0x3) << 3; 301 cpu_physical_memory_write(dest, &val, 4); 302 } 303 break; 304 /* Remote Speed Registers */ 305 case 0x0070: 306 case 0x0078: 307 case 0x0080: 308 case 0x0088: 309 case 0x0090: 310 case 0x0098: 311 case 0x00a0: 312 case 0x00a8: 313 case 0x00b0: 314 case 0x00b8: 315 case 0x00c0: 316 case 0x00c8: 317 case 0x00d0: 318 case 0x00d8: 319 case 0x00e0: 320 case 0x00e8: 321 s->rem_speed[(addr - 0x0070) >> 3] = val; 322 break; 323 /* DMA channel base address */ 324 case 0x0100: 325 case 0x0108: 326 case 0x0110: 327 case 0x0118: 328 case 0x0120: 329 case 0x0128: 330 case 0x0130: 331 case 0x0138: 332 case 0x0140: 333 case 0x0148: 334 case 0x0150: 335 case 0x0158: 336 case 0x0160: 337 case 0x0168: 338 case 0x0170: 339 case 0x0178: 340 case 0x0180: 341 case 0x0188: 342 case 0x0190: 343 case 0x0198: 344 case 0x01a0: 345 case 0x01a8: 346 case 0x01b0: 347 case 0x01b8: 348 case 0x01c0: 349 case 0x01c8: 350 case 0x01d0: 351 case 0x01d8: 352 case 0x01e0: 353 case 0x01e8: 354 case 0x01f0: 355 case 0x01f8: 356 { 357 int entry = (addr - 0x0100) >> 5; 358 int idx = (addr & 0x1f) >> 3; 359 s->dma_regs[entry][idx] = val; 360 } 361 break; 362 /* Memory refresh rate */ 363 case 0x0210: 364 s->memory_refresh_rate = val; 365 break; 366 /* Interval timer reload */ 367 case 0x0228: 368 s->itr = val & 0x01FF; 369 qemu_irq_lower(s->timer_irq); 370 set_next_tick(s); 371 break; 372 /* EISA interrupt */ 373 case 0x0238: 374 break; 375 default: 376 qemu_log_mask(LOG_GUEST_ERROR, 377 "rc4030: invalid write of 0x%02x at 0x%x", 378 val, (int)addr); 379 break; 380 } 381 } 382 383 static const MemoryRegionOps rc4030_ops = { 384 .read = rc4030_read, 385 .write = rc4030_write, 386 .impl.min_access_size = 4, 387 .impl.max_access_size = 4, 388 .endianness = DEVICE_NATIVE_ENDIAN, 389 }; 390 391 static void update_jazz_irq(rc4030State *s) 392 { 393 uint16_t pending; 394 395 pending = s->isr_jazz & s->imr_jazz; 396 397 if (pending != 0) 398 qemu_irq_raise(s->jazz_bus_irq); 399 else 400 qemu_irq_lower(s->jazz_bus_irq); 401 } 402 403 static void rc4030_irq_jazz_request(void *opaque, int irq, int level) 404 { 405 rc4030State *s = opaque; 406 407 if (level) { 408 s->isr_jazz |= 1 << irq; 409 } else { 410 s->isr_jazz &= ~(1 << irq); 411 } 412 413 update_jazz_irq(s); 414 } 415 416 static void rc4030_periodic_timer(void *opaque) 417 { 418 rc4030State *s = opaque; 419 420 set_next_tick(s); 421 qemu_irq_raise(s->timer_irq); 422 } 423 424 static uint64_t jazzio_read(void *opaque, hwaddr addr, unsigned int size) 425 { 426 rc4030State *s = opaque; 427 uint32_t val; 428 uint32_t irq; 429 addr &= 0xfff; 430 431 switch (addr) { 432 /* Local bus int source */ 433 case 0x00: { 434 uint32_t pending = s->isr_jazz & s->imr_jazz; 435 val = 0; 436 irq = 0; 437 while (pending) { 438 if (pending & 1) { 439 val = (irq + 1) << 2; 440 break; 441 } 442 irq++; 443 pending >>= 1; 444 } 445 break; 446 } 447 /* Local bus int enable mask */ 448 case 0x02: 449 val = s->imr_jazz; 450 break; 451 default: 452 qemu_log_mask(LOG_GUEST_ERROR, 453 "rc4030/jazzio: invalid read at 0x%x", (int)addr); 454 val = 0; 455 break; 456 } 457 458 trace_jazzio_read(addr, val); 459 460 return val; 461 } 462 463 static void jazzio_write(void *opaque, hwaddr addr, uint64_t data, 464 unsigned int size) 465 { 466 rc4030State *s = opaque; 467 uint32_t val = data; 468 addr &= 0xfff; 469 470 trace_jazzio_write(addr, val); 471 472 switch (addr) { 473 /* Local bus int enable mask */ 474 case 0x02: 475 s->imr_jazz = val; 476 update_jazz_irq(s); 477 break; 478 default: 479 qemu_log_mask(LOG_GUEST_ERROR, 480 "rc4030/jazzio: invalid write of 0x%02x at 0x%x", 481 val, (int)addr); 482 break; 483 } 484 } 485 486 static const MemoryRegionOps jazzio_ops = { 487 .read = jazzio_read, 488 .write = jazzio_write, 489 .impl.min_access_size = 2, 490 .impl.max_access_size = 2, 491 .endianness = DEVICE_NATIVE_ENDIAN, 492 }; 493 494 static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr, 495 IOMMUAccessFlags flag, int iommu_idx) 496 { 497 rc4030State *s = container_of(iommu, rc4030State, dma_mr); 498 IOMMUTLBEntry ret = { 499 .target_as = &address_space_memory, 500 .iova = addr & ~(DMA_PAGESIZE - 1), 501 .translated_addr = 0, 502 .addr_mask = DMA_PAGESIZE - 1, 503 .perm = IOMMU_NONE, 504 }; 505 uint64_t i, entry_address; 506 dma_pagetable_entry entry; 507 508 i = addr / DMA_PAGESIZE; 509 if (i < s->dma_tl_limit / sizeof(entry)) { 510 entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry); 511 if (address_space_read(ret.target_as, entry_address, 512 MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry, 513 sizeof(entry)) == MEMTX_OK) { 514 ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1); 515 ret.perm = IOMMU_RW; 516 } 517 } 518 519 return ret; 520 } 521 522 static void rc4030_reset(DeviceState *dev) 523 { 524 rc4030State *s = RC4030(dev); 525 int i; 526 527 s->config = 0x410; /* some boards seem to accept 0x104 too */ 528 s->revision = 1; 529 s->invalid_address_register = 0; 530 531 memset(s->dma_regs, 0, sizeof(s->dma_regs)); 532 533 s->remote_failed_address = s->memory_failed_address = 0; 534 s->cache_maint = 0; 535 s->cache_ptag = s->cache_ltag = 0; 536 s->cache_bmask = 0; 537 538 s->memory_refresh_rate = 0x18186; 539 s->nvram_protect = 7; 540 for (i = 0; i < 15; i++) 541 s->rem_speed[i] = 7; 542 s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ 543 s->isr_jazz = 0; 544 545 s->itr = 0; 546 547 qemu_irq_lower(s->timer_irq); 548 qemu_irq_lower(s->jazz_bus_irq); 549 } 550 551 static int rc4030_post_load(void *opaque, int version_id) 552 { 553 rc4030State* s = opaque; 554 555 set_next_tick(s); 556 update_jazz_irq(s); 557 558 return 0; 559 } 560 561 static const VMStateDescription vmstate_rc4030 = { 562 .name = "rc4030", 563 .version_id = 3, 564 .post_load = rc4030_post_load, 565 .fields = (VMStateField []) { 566 VMSTATE_UINT32(config, rc4030State), 567 VMSTATE_UINT32(invalid_address_register, rc4030State), 568 VMSTATE_UINT32_2DARRAY(dma_regs, rc4030State, 8, 4), 569 VMSTATE_UINT32(dma_tl_base, rc4030State), 570 VMSTATE_UINT32(dma_tl_limit, rc4030State), 571 VMSTATE_UINT32(cache_maint, rc4030State), 572 VMSTATE_UINT32(remote_failed_address, rc4030State), 573 VMSTATE_UINT32(memory_failed_address, rc4030State), 574 VMSTATE_UINT32(cache_ptag, rc4030State), 575 VMSTATE_UINT32(cache_ltag, rc4030State), 576 VMSTATE_UINT32(cache_bmask, rc4030State), 577 VMSTATE_UINT32(memory_refresh_rate, rc4030State), 578 VMSTATE_UINT32(nvram_protect, rc4030State), 579 VMSTATE_UINT32_ARRAY(rem_speed, rc4030State, 16), 580 VMSTATE_UINT32(imr_jazz, rc4030State), 581 VMSTATE_UINT32(isr_jazz, rc4030State), 582 VMSTATE_UINT32(itr, rc4030State), 583 VMSTATE_END_OF_LIST() 584 } 585 }; 586 587 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) 588 { 589 rc4030State *s = opaque; 590 hwaddr dma_addr; 591 int dev_to_mem; 592 593 s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); 594 595 /* Check DMA channel consistency */ 596 dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; 597 if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) || 598 (is_write != dev_to_mem)) { 599 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; 600 s->nmi_interrupt |= 1 << n; 601 return; 602 } 603 604 /* Get start address and len */ 605 if (len > s->dma_regs[n][DMA_REG_COUNT]) 606 len = s->dma_regs[n][DMA_REG_COUNT]; 607 dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; 608 609 /* Read/write data at right place */ 610 address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED, 611 buf, len, is_write); 612 613 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; 614 s->dma_regs[n][DMA_REG_COUNT] -= len; 615 } 616 617 struct rc4030DMAState { 618 void *opaque; 619 int n; 620 }; 621 622 void rc4030_dma_read(void *dma, uint8_t *buf, int len) 623 { 624 rc4030_dma s = dma; 625 rc4030_do_dma(s->opaque, s->n, buf, len, 0); 626 } 627 628 void rc4030_dma_write(void *dma, uint8_t *buf, int len) 629 { 630 rc4030_dma s = dma; 631 rc4030_do_dma(s->opaque, s->n, buf, len, 1); 632 } 633 634 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) 635 { 636 rc4030_dma *s; 637 struct rc4030DMAState *p; 638 int i; 639 640 s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n); 641 p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n); 642 for (i = 0; i < n; i++) { 643 p->opaque = opaque; 644 p->n = i; 645 s[i] = p; 646 p++; 647 } 648 return s; 649 } 650 651 static void rc4030_initfn(Object *obj) 652 { 653 DeviceState *dev = DEVICE(obj); 654 rc4030State *s = RC4030(obj); 655 SysBusDevice *sysbus = SYS_BUS_DEVICE(obj); 656 657 qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16); 658 659 sysbus_init_irq(sysbus, &s->timer_irq); 660 sysbus_init_irq(sysbus, &s->jazz_bus_irq); 661 662 sysbus_init_mmio(sysbus, &s->iomem_chipset); 663 sysbus_init_mmio(sysbus, &s->iomem_jazzio); 664 } 665 666 static void rc4030_realize(DeviceState *dev, Error **errp) 667 { 668 rc4030State *s = RC4030(dev); 669 Object *o = OBJECT(dev); 670 671 s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 672 rc4030_periodic_timer, s); 673 674 memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s, 675 "rc4030.chipset", 0x300); 676 memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s, 677 "rc4030.jazzio", 0x00001000); 678 679 memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr), 680 TYPE_RC4030_IOMMU_MEMORY_REGION, 681 o, "rc4030.dma", UINT32_MAX); 682 address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma"); 683 } 684 685 static void rc4030_unrealize(DeviceState *dev, Error **errp) 686 { 687 rc4030State *s = RC4030(dev); 688 689 timer_free(s->periodic_timer); 690 691 address_space_destroy(&s->dma_as); 692 object_unparent(OBJECT(&s->dma_mr)); 693 } 694 695 static void rc4030_class_init(ObjectClass *klass, void *class_data) 696 { 697 DeviceClass *dc = DEVICE_CLASS(klass); 698 699 dc->realize = rc4030_realize; 700 dc->unrealize = rc4030_unrealize; 701 dc->reset = rc4030_reset; 702 dc->vmsd = &vmstate_rc4030; 703 } 704 705 static const TypeInfo rc4030_info = { 706 .name = TYPE_RC4030, 707 .parent = TYPE_SYS_BUS_DEVICE, 708 .instance_size = sizeof(rc4030State), 709 .instance_init = rc4030_initfn, 710 .class_init = rc4030_class_init, 711 }; 712 713 static void rc4030_iommu_memory_region_class_init(ObjectClass *klass, 714 void *data) 715 { 716 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 717 718 imrc->translate = rc4030_dma_translate; 719 } 720 721 static const TypeInfo rc4030_iommu_memory_region_info = { 722 .parent = TYPE_IOMMU_MEMORY_REGION, 723 .name = TYPE_RC4030_IOMMU_MEMORY_REGION, 724 .class_init = rc4030_iommu_memory_region_class_init, 725 }; 726 727 static void rc4030_register_types(void) 728 { 729 type_register_static(&rc4030_info); 730 type_register_static(&rc4030_iommu_memory_region_info); 731 } 732 733 type_init(rc4030_register_types) 734 735 DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr) 736 { 737 DeviceState *dev; 738 739 dev = qdev_create(NULL, TYPE_RC4030); 740 qdev_init_nofail(dev); 741 742 *dmas = rc4030_allocate_dmas(dev, 4); 743 *dma_mr = &RC4030(dev)->dma_mr; 744 return dev; 745 } 746