1 /* 2 * ARM PrimeCell PL330 DMA Controller 3 * 4 * Copyright (c) 2009 Samsung Electronics. 5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru> 6 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 7 * Copyright (c) 2012 PetaLogix Pty Ltd. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; version 2 or later. 12 * 13 * You should have received a copy of the GNU General Public License along 14 * with this program; if not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "hw/irq.h" 20 #include "hw/qdev-properties.h" 21 #include "hw/sysbus.h" 22 #include "migration/vmstate.h" 23 #include "qapi/error.h" 24 #include "qemu/timer.h" 25 #include "sysemu/dma.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "trace.h" 29 30 #ifndef PL330_ERR_DEBUG 31 #define PL330_ERR_DEBUG 0 32 #endif 33 34 #define PL330_PERIPH_NUM 32 35 #define PL330_MAX_BURST_LEN 128 36 #define PL330_INSN_MAXSIZE 6 37 38 #define PL330_FIFO_OK 0 39 #define PL330_FIFO_STALL 1 40 #define PL330_FIFO_ERR (-1) 41 42 #define PL330_FAULT_UNDEF_INSTR (1 << 0) 43 #define PL330_FAULT_OPERAND_INVALID (1 << 1) 44 #define PL330_FAULT_DMAGO_ERR (1 << 4) 45 #define PL330_FAULT_EVENT_ERR (1 << 5) 46 #define PL330_FAULT_CH_PERIPH_ERR (1 << 6) 47 #define PL330_FAULT_CH_RDWR_ERR (1 << 7) 48 #define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12) 49 #define PL330_FAULT_FIFOEMPTY_ERR (1 << 13) 50 #define PL330_FAULT_INSTR_FETCH_ERR (1 << 16) 51 #define PL330_FAULT_DATA_WRITE_ERR (1 << 17) 52 #define PL330_FAULT_DATA_READ_ERR (1 << 18) 53 #define PL330_FAULT_DBG_INSTR (1 << 30) 54 #define PL330_FAULT_LOCKUP_ERR (1 << 31) 55 56 #define PL330_UNTAGGED 0xff 57 58 #define PL330_SINGLE 0x0 59 #define PL330_BURST 0x1 60 61 #define PL330_WATCHDOG_LIMIT 1024 62 63 /* IOMEM mapped registers */ 64 #define PL330_REG_DSR 0x000 65 #define PL330_REG_DPC 0x004 66 #define PL330_REG_INTEN 0x020 67 #define PL330_REG_INT_EVENT_RIS 0x024 68 #define PL330_REG_INTMIS 0x028 69 #define PL330_REG_INTCLR 0x02C 70 #define PL330_REG_FSRD 0x030 71 #define PL330_REG_FSRC 0x034 72 #define PL330_REG_FTRD 0x038 73 #define PL330_REG_FTR_BASE 0x040 74 #define PL330_REG_CSR_BASE 0x100 75 #define PL330_REG_CPC_BASE 0x104 76 #define PL330_REG_CHANCTRL 0x400 77 #define PL330_REG_DBGSTATUS 0xD00 78 #define PL330_REG_DBGCMD 0xD04 79 #define PL330_REG_DBGINST0 0xD08 80 #define PL330_REG_DBGINST1 0xD0C 81 #define PL330_REG_CR0_BASE 0xE00 82 #define PL330_REG_PERIPH_ID 0xFE0 83 84 #define PL330_IOMEM_SIZE 0x1000 85 86 #define CFG_BOOT_ADDR 2 87 #define CFG_INS 3 88 #define CFG_PNS 4 89 #define CFG_CRD 5 90 91 static const uint32_t pl330_id[] = { 92 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1 93 }; 94 95 /* DMA channel states as they are described in PL330 Technical Reference Manual 96 * Most of them will not be used in emulation. 97 */ 98 typedef enum { 99 pl330_chan_stopped = 0, 100 pl330_chan_executing = 1, 101 pl330_chan_cache_miss = 2, 102 pl330_chan_updating_pc = 3, 103 pl330_chan_waiting_event = 4, 104 pl330_chan_at_barrier = 5, 105 pl330_chan_queue_busy = 6, 106 pl330_chan_waiting_periph = 7, 107 pl330_chan_killing = 8, 108 pl330_chan_completing = 9, 109 pl330_chan_fault_completing = 14, 110 pl330_chan_fault = 15, 111 } PL330ChanState; 112 113 typedef struct PL330State PL330State; 114 115 typedef struct PL330Chan { 116 uint32_t src; 117 uint32_t dst; 118 uint32_t pc; 119 uint32_t control; 120 uint32_t status; 121 uint32_t lc[2]; 122 uint32_t fault_type; 123 uint32_t watchdog_timer; 124 125 bool ns; 126 uint8_t request_flag; 127 uint8_t wakeup; 128 uint8_t wfp_sbp; 129 130 uint8_t state; 131 uint8_t stall; 132 133 bool is_manager; 134 PL330State *parent; 135 uint8_t tag; 136 } PL330Chan; 137 138 static const VMStateDescription vmstate_pl330_chan = { 139 .name = "pl330_chan", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .fields = (VMStateField[]) { 143 VMSTATE_UINT32(src, PL330Chan), 144 VMSTATE_UINT32(dst, PL330Chan), 145 VMSTATE_UINT32(pc, PL330Chan), 146 VMSTATE_UINT32(control, PL330Chan), 147 VMSTATE_UINT32(status, PL330Chan), 148 VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2), 149 VMSTATE_UINT32(fault_type, PL330Chan), 150 VMSTATE_UINT32(watchdog_timer, PL330Chan), 151 VMSTATE_BOOL(ns, PL330Chan), 152 VMSTATE_UINT8(request_flag, PL330Chan), 153 VMSTATE_UINT8(wakeup, PL330Chan), 154 VMSTATE_UINT8(wfp_sbp, PL330Chan), 155 VMSTATE_UINT8(state, PL330Chan), 156 VMSTATE_UINT8(stall, PL330Chan), 157 VMSTATE_END_OF_LIST() 158 } 159 }; 160 161 typedef struct PL330Fifo { 162 uint8_t *buf; 163 uint8_t *tag; 164 uint32_t head; 165 uint32_t num; 166 uint32_t buf_size; 167 } PL330Fifo; 168 169 static const VMStateDescription vmstate_pl330_fifo = { 170 .name = "pl330_chan", 171 .version_id = 1, 172 .minimum_version_id = 1, 173 .fields = (VMStateField[]) { 174 VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, buf_size), 175 VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, buf_size), 176 VMSTATE_UINT32(head, PL330Fifo), 177 VMSTATE_UINT32(num, PL330Fifo), 178 VMSTATE_UINT32(buf_size, PL330Fifo), 179 VMSTATE_END_OF_LIST() 180 } 181 }; 182 183 typedef struct PL330QueueEntry { 184 uint32_t addr; 185 uint32_t len; 186 uint8_t n; 187 bool inc; 188 bool z; 189 uint8_t tag; 190 uint8_t seqn; 191 } PL330QueueEntry; 192 193 static const VMStateDescription vmstate_pl330_queue_entry = { 194 .name = "pl330_queue_entry", 195 .version_id = 1, 196 .minimum_version_id = 1, 197 .fields = (VMStateField[]) { 198 VMSTATE_UINT32(addr, PL330QueueEntry), 199 VMSTATE_UINT32(len, PL330QueueEntry), 200 VMSTATE_UINT8(n, PL330QueueEntry), 201 VMSTATE_BOOL(inc, PL330QueueEntry), 202 VMSTATE_BOOL(z, PL330QueueEntry), 203 VMSTATE_UINT8(tag, PL330QueueEntry), 204 VMSTATE_UINT8(seqn, PL330QueueEntry), 205 VMSTATE_END_OF_LIST() 206 } 207 }; 208 209 typedef struct PL330Queue { 210 PL330State *parent; 211 PL330QueueEntry *queue; 212 uint32_t queue_size; 213 } PL330Queue; 214 215 static const VMStateDescription vmstate_pl330_queue = { 216 .name = "pl330_queue", 217 .version_id = 2, 218 .minimum_version_id = 2, 219 .fields = (VMStateField[]) { 220 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size, 221 vmstate_pl330_queue_entry, 222 PL330QueueEntry), 223 VMSTATE_END_OF_LIST() 224 } 225 }; 226 227 struct PL330State { 228 SysBusDevice parent_obj; 229 230 MemoryRegion iomem; 231 qemu_irq irq_abort; 232 qemu_irq *irq; 233 234 /* Config registers. cfg[5] = CfgDn. */ 235 uint32_t cfg[6]; 236 #define EVENT_SEC_STATE 3 237 #define PERIPH_SEC_STATE 4 238 /* cfg 0 bits and pieces */ 239 uint32_t num_chnls; 240 uint8_t num_periph_req; 241 uint8_t num_events; 242 uint8_t mgr_ns_at_rst; 243 /* cfg 1 bits and pieces */ 244 uint8_t i_cache_len; 245 uint8_t num_i_cache_lines; 246 /* CRD bits and pieces */ 247 uint8_t data_width; 248 uint8_t wr_cap; 249 uint8_t wr_q_dep; 250 uint8_t rd_cap; 251 uint8_t rd_q_dep; 252 uint16_t data_buffer_dep; 253 254 PL330Chan manager; 255 PL330Chan *chan; 256 PL330Fifo fifo; 257 PL330Queue read_queue; 258 PL330Queue write_queue; 259 uint8_t *lo_seqn; 260 uint8_t *hi_seqn; 261 QEMUTimer *timer; /* is used for restore dma. */ 262 263 uint32_t inten; 264 uint32_t int_status; 265 uint32_t ev_status; 266 uint32_t dbg[2]; 267 uint8_t debug_status; 268 uint8_t num_faulting; 269 uint8_t periph_busy[PL330_PERIPH_NUM]; 270 271 }; 272 273 #define TYPE_PL330 "pl330" 274 #define PL330(obj) OBJECT_CHECK(PL330State, (obj), TYPE_PL330) 275 276 static const VMStateDescription vmstate_pl330 = { 277 .name = "pl330", 278 .version_id = 2, 279 .minimum_version_id = 2, 280 .fields = (VMStateField[]) { 281 VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan), 282 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls, 283 vmstate_pl330_chan, PL330Chan), 284 VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls), 285 VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls), 286 VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo), 287 VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue, 288 PL330Queue), 289 VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue, 290 PL330Queue), 291 VMSTATE_TIMER_PTR(timer, PL330State), 292 VMSTATE_UINT32(inten, PL330State), 293 VMSTATE_UINT32(int_status, PL330State), 294 VMSTATE_UINT32(ev_status, PL330State), 295 VMSTATE_UINT32_ARRAY(dbg, PL330State, 2), 296 VMSTATE_UINT8(debug_status, PL330State), 297 VMSTATE_UINT8(num_faulting, PL330State), 298 VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM), 299 VMSTATE_END_OF_LIST() 300 } 301 }; 302 303 typedef struct PL330InsnDesc { 304 /* OPCODE of the instruction */ 305 uint8_t opcode; 306 /* Mask so we can select several sibling instructions, such as 307 DMALD, DMALDS and DMALDB */ 308 uint8_t opmask; 309 /* Size of instruction in bytes */ 310 uint8_t size; 311 /* Interpreter */ 312 void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len); 313 } PL330InsnDesc; 314 315 static void pl330_hexdump(uint8_t *buf, size_t size) 316 { 317 unsigned int b, i, len; 318 char tmpbuf[80]; 319 320 for (b = 0; b < size; b += 16) { 321 len = size - b; 322 if (len > 16) { 323 len = 16; 324 } 325 tmpbuf[0] = '\0'; 326 for (i = 0; i < len; i++) { 327 if ((i % 4) == 0) { 328 strcat(tmpbuf, " "); 329 } 330 sprintf(tmpbuf + strlen(tmpbuf), " %02x", buf[b + i]); 331 } 332 trace_pl330_hexdump(b, tmpbuf); 333 } 334 } 335 336 /* MFIFO Implementation 337 * 338 * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are 339 * stored in this buffer. Data is stored in BUF field, tags - in the 340 * corresponding array elements of TAG field. 341 */ 342 343 /* Initialize queue. */ 344 345 static void pl330_fifo_init(PL330Fifo *s, uint32_t size) 346 { 347 s->buf = g_malloc0(size); 348 s->tag = g_malloc0(size); 349 s->buf_size = size; 350 } 351 352 /* Cyclic increment */ 353 354 static inline int pl330_fifo_inc(PL330Fifo *s, int x) 355 { 356 return (x + 1) % s->buf_size; 357 } 358 359 /* Number of empty bytes in MFIFO */ 360 361 static inline int pl330_fifo_num_free(PL330Fifo *s) 362 { 363 return s->buf_size - s->num; 364 } 365 366 /* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG. 367 * Zero returned on success, PL330_FIFO_STALL if there is no enough free 368 * space in MFIFO to store requested amount of data. If push was unsuccessful 369 * no data is stored to MFIFO. 370 */ 371 372 static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) 373 { 374 int i; 375 376 if (s->buf_size - s->num < len) { 377 return PL330_FIFO_STALL; 378 } 379 for (i = 0; i < len; i++) { 380 int push_idx = (s->head + s->num + i) % s->buf_size; 381 s->buf[push_idx] = buf[i]; 382 s->tag[push_idx] = tag; 383 } 384 s->num += len; 385 return PL330_FIFO_OK; 386 } 387 388 /* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each 389 * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch 390 * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was 391 * unsuccessful no data is removed from MFIFO. 392 */ 393 394 static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) 395 { 396 int i; 397 398 if (s->num < len) { 399 return PL330_FIFO_STALL; 400 } 401 for (i = 0; i < len; i++) { 402 if (s->tag[s->head] == tag) { 403 int get_idx = (s->head + i) % s->buf_size; 404 buf[i] = s->buf[get_idx]; 405 } else { /* Tag mismatch - Rollback transaction */ 406 return PL330_FIFO_ERR; 407 } 408 } 409 s->head = (s->head + len) % s->buf_size; 410 s->num -= len; 411 return PL330_FIFO_OK; 412 } 413 414 /* Reset MFIFO. This completely erases all data in it. */ 415 416 static inline void pl330_fifo_reset(PL330Fifo *s) 417 { 418 s->head = 0; 419 s->num = 0; 420 } 421 422 /* Return tag of the first byte stored in MFIFO. If MFIFO is empty 423 * PL330_UNTAGGED is returned. 424 */ 425 426 static inline uint8_t pl330_fifo_tag(PL330Fifo *s) 427 { 428 return (!s->num) ? PL330_UNTAGGED : s->tag[s->head]; 429 } 430 431 /* Returns non-zero if tag TAG is present in fifo or zero otherwise */ 432 433 static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag) 434 { 435 int i, n; 436 437 i = s->head; 438 for (n = 0; n < s->num; n++) { 439 if (s->tag[i] == tag) { 440 return 1; 441 } 442 i = pl330_fifo_inc(s, i); 443 } 444 return 0; 445 } 446 447 /* Remove all entry tagged with TAG from MFIFO */ 448 449 static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag) 450 { 451 int i, t, n; 452 453 t = i = s->head; 454 for (n = 0; n < s->num; n++) { 455 if (s->tag[i] != tag) { 456 s->buf[t] = s->buf[i]; 457 s->tag[t] = s->tag[i]; 458 t = pl330_fifo_inc(s, t); 459 } else { 460 s->num = s->num - 1; 461 } 462 i = pl330_fifo_inc(s, i); 463 } 464 } 465 466 /* Read-Write Queue implementation 467 * 468 * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores). 469 * Each instruction is described by source (for loads) or destination (for 470 * stores) address ADDR, width of data to be loaded/stored LEN, number of 471 * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel 472 * this instruction belongs to. Queue does not store any information about 473 * nature of the instruction: is it load or store. PL330 has different queues 474 * for loads and stores so this is already known at the top level where it 475 * matters. 476 * 477 * Queue works as FIFO for instructions with equivalent tags, but can issue 478 * instructions with different tags in arbitrary order. SEQN field attached to 479 * each instruction helps to achieve this. For each TAG queue contains 480 * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to 481 * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is 482 * followed by SEQN=0. 483 * 484 * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed 485 * in this case. 486 */ 487 488 static void pl330_queue_reset(PL330Queue *s) 489 { 490 int i; 491 492 for (i = 0; i < s->queue_size; i++) { 493 s->queue[i].tag = PL330_UNTAGGED; 494 } 495 } 496 497 /* Initialize queue */ 498 static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent) 499 { 500 s->parent = parent; 501 s->queue = g_new0(PL330QueueEntry, size); 502 s->queue_size = size; 503 } 504 505 /* Returns pointer to an empty slot or NULL if queue is full */ 506 static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s) 507 { 508 int i; 509 510 for (i = 0; i < s->queue_size; i++) { 511 if (s->queue[i].tag == PL330_UNTAGGED) { 512 return &s->queue[i]; 513 } 514 } 515 return NULL; 516 } 517 518 /* Put instruction in queue. 519 * Return value: 520 * - zero - OK 521 * - non-zero - queue is full 522 */ 523 524 static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr, 525 int len, int n, bool inc, bool z, uint8_t tag) 526 { 527 PL330QueueEntry *entry = pl330_queue_find_empty(s); 528 529 if (!entry) { 530 return 1; 531 } 532 entry->tag = tag; 533 entry->addr = addr; 534 entry->len = len; 535 entry->n = n; 536 entry->z = z; 537 entry->inc = inc; 538 entry->seqn = s->parent->hi_seqn[tag]; 539 s->parent->hi_seqn[tag]++; 540 return 0; 541 } 542 543 /* Returns a pointer to queue slot containing instruction which satisfies 544 * following conditions: 545 * - it has valid tag value (not PL330_UNTAGGED) 546 * - if enforce_seq is set it has to be issuable without violating queue 547 * logic (see above) 548 * - if TAG argument is not PL330_UNTAGGED this instruction has tag value 549 * equivalent to the argument TAG value. 550 * If such instruction cannot be found NULL is returned. 551 */ 552 553 static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag, 554 bool enforce_seq) 555 { 556 int i; 557 558 for (i = 0; i < s->queue_size; i++) { 559 if (s->queue[i].tag != PL330_UNTAGGED) { 560 if ((!enforce_seq || 561 s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) && 562 (s->queue[i].tag == tag || tag == PL330_UNTAGGED || 563 s->queue[i].z)) { 564 return &s->queue[i]; 565 } 566 } 567 } 568 return NULL; 569 } 570 571 /* Removes instruction from queue. */ 572 573 static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e) 574 { 575 s->parent->lo_seqn[e->tag]++; 576 e->tag = PL330_UNTAGGED; 577 } 578 579 /* Removes all instructions tagged with TAG from queue. */ 580 581 static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag) 582 { 583 int i; 584 585 for (i = 0; i < s->queue_size; i++) { 586 if (s->queue[i].tag == tag) { 587 s->queue[i].tag = PL330_UNTAGGED; 588 } 589 } 590 } 591 592 /* DMA instruction execution engine */ 593 594 /* Moves DMA channel to the FAULT state and updates it's status. */ 595 596 static inline void pl330_fault(PL330Chan *ch, uint32_t flags) 597 { 598 trace_pl330_fault(ch, flags); 599 ch->fault_type |= flags; 600 if (ch->state == pl330_chan_fault) { 601 return; 602 } 603 ch->state = pl330_chan_fault; 604 ch->parent->num_faulting++; 605 if (ch->parent->num_faulting == 1) { 606 trace_pl330_fault_abort(); 607 qemu_irq_raise(ch->parent->irq_abort); 608 } 609 } 610 611 /* 612 * For information about instructions see PL330 Technical Reference Manual. 613 * 614 * Arguments: 615 * CH - channel executing the instruction 616 * OPCODE - opcode 617 * ARGS - array of 8-bit arguments 618 * LEN - number of elements in ARGS array 619 */ 620 621 static void pl330_dmaadxh(PL330Chan *ch, uint8_t *args, bool ra, bool neg) 622 { 623 uint32_t im = (args[1] << 8) | args[0]; 624 if (neg) { 625 im |= 0xffffu << 16; 626 } 627 628 if (ch->is_manager) { 629 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 630 return; 631 } 632 if (ra) { 633 ch->dst += im; 634 } else { 635 ch->src += im; 636 } 637 } 638 639 static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 640 { 641 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), false); 642 } 643 644 static void pl330_dmaadnh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 645 { 646 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), true); 647 } 648 649 static void pl330_dmaend(PL330Chan *ch, uint8_t opcode, 650 uint8_t *args, int len) 651 { 652 PL330State *s = ch->parent; 653 654 if (ch->state == pl330_chan_executing && !ch->is_manager) { 655 /* Wait for all transfers to complete */ 656 if (pl330_fifo_has_tag(&s->fifo, ch->tag) || 657 pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL || 658 pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) { 659 660 ch->stall = 1; 661 return; 662 } 663 } 664 trace_pl330_dmaend(); 665 pl330_fifo_tagged_remove(&s->fifo, ch->tag); 666 pl330_queue_remove_tagged(&s->read_queue, ch->tag); 667 pl330_queue_remove_tagged(&s->write_queue, ch->tag); 668 ch->state = pl330_chan_stopped; 669 } 670 671 static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode, 672 uint8_t *args, int len) 673 { 674 uint8_t periph_id; 675 676 if (args[0] & 7) { 677 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 678 return; 679 } 680 periph_id = (args[0] >> 3) & 0x1f; 681 if (periph_id >= ch->parent->num_periph_req) { 682 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 683 return; 684 } 685 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 686 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 687 return; 688 } 689 /* Do nothing */ 690 } 691 692 static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 693 { 694 uint8_t chan_id; 695 uint8_t ns; 696 uint32_t pc; 697 PL330Chan *s; 698 699 trace_pl330_dmago(); 700 701 if (!ch->is_manager) { 702 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 703 return; 704 } 705 ns = !!(opcode & 2); 706 chan_id = args[0] & 7; 707 if ((args[0] >> 3)) { 708 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 709 return; 710 } 711 if (chan_id >= ch->parent->num_chnls) { 712 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 713 return; 714 } 715 pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | 716 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); 717 if (ch->parent->chan[chan_id].state != pl330_chan_stopped) { 718 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 719 return; 720 } 721 if (ch->ns && !ns) { 722 pl330_fault(ch, PL330_FAULT_DMAGO_ERR); 723 return; 724 } 725 s = &ch->parent->chan[chan_id]; 726 s->ns = ns; 727 s->pc = pc; 728 s->state = pl330_chan_executing; 729 } 730 731 static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 732 { 733 uint8_t bs = opcode & 3; 734 uint32_t size, num; 735 bool inc; 736 737 if (bs == 2) { 738 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 739 return; 740 } 741 if ((bs == 1 && ch->request_flag == PL330_BURST) || 742 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 743 /* Perform NOP */ 744 return; 745 } 746 if (bs == 1 && ch->request_flag == PL330_SINGLE) { 747 num = 1; 748 } else { 749 num = ((ch->control >> 4) & 0xf) + 1; 750 } 751 size = (uint32_t)1 << ((ch->control >> 1) & 0x7); 752 inc = !!(ch->control & 1); 753 ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src, 754 size, num, inc, 0, ch->tag); 755 if (!ch->stall) { 756 trace_pl330_dmald(ch->tag, ch->src, size, num, inc ? 'Y' : 'N'); 757 ch->src += inc ? size * num - (ch->src & (size - 1)) : 0; 758 } 759 } 760 761 static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 762 { 763 uint8_t periph_id; 764 765 if (args[0] & 7) { 766 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 767 return; 768 } 769 periph_id = (args[0] >> 3) & 0x1f; 770 if (periph_id >= ch->parent->num_periph_req) { 771 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 772 return; 773 } 774 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 775 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 776 return; 777 } 778 pl330_dmald(ch, opcode, args, len); 779 } 780 781 static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 782 { 783 uint8_t lc = (opcode & 2) >> 1; 784 785 ch->lc[lc] = args[0]; 786 } 787 788 static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 789 { 790 if (ch->state == pl330_chan_fault || 791 ch->state == pl330_chan_fault_completing) { 792 /* This is the only way for a channel to leave the faulting state */ 793 ch->fault_type = 0; 794 ch->parent->num_faulting--; 795 if (ch->parent->num_faulting == 0) { 796 trace_pl330_dmakill(); 797 qemu_irq_lower(ch->parent->irq_abort); 798 } 799 } 800 ch->state = pl330_chan_killing; 801 pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag); 802 pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag); 803 pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag); 804 ch->state = pl330_chan_stopped; 805 } 806 807 static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode, 808 uint8_t *args, int len) 809 { 810 uint8_t nf = (opcode & 0x10) >> 4; 811 uint8_t bs = opcode & 3; 812 uint8_t lc = (opcode & 4) >> 2; 813 814 trace_pl330_dmalpend(nf, bs, lc, ch->lc[lc], ch->request_flag); 815 816 if (bs == 2) { 817 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 818 return; 819 } 820 if ((bs == 1 && ch->request_flag == PL330_BURST) || 821 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 822 /* Perform NOP */ 823 return; 824 } 825 if (!nf || ch->lc[lc]) { 826 if (nf) { 827 ch->lc[lc]--; 828 } 829 trace_pl330_dmalpiter(); 830 ch->pc -= args[0]; 831 ch->pc -= len + 1; 832 /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */ 833 } else { 834 trace_pl330_dmalpfallthrough(); 835 } 836 } 837 838 839 static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 840 { 841 uint8_t rd = args[0] & 7; 842 uint32_t im; 843 844 if ((args[0] >> 3)) { 845 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 846 return; 847 } 848 im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | 849 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); 850 switch (rd) { 851 case 0: 852 ch->src = im; 853 break; 854 case 1: 855 ch->control = im; 856 break; 857 case 2: 858 ch->dst = im; 859 break; 860 default: 861 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 862 return; 863 } 864 } 865 866 static void pl330_dmanop(PL330Chan *ch, uint8_t opcode, 867 uint8_t *args, int len) 868 { 869 /* NOP is NOP. */ 870 } 871 872 static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 873 { 874 if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) { 875 ch->state = pl330_chan_at_barrier; 876 ch->stall = 1; 877 return; 878 } else { 879 ch->state = pl330_chan_executing; 880 } 881 } 882 883 static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 884 { 885 uint8_t ev_id; 886 887 if (args[0] & 7) { 888 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 889 return; 890 } 891 ev_id = (args[0] >> 3) & 0x1f; 892 if (ev_id >= ch->parent->num_events) { 893 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 894 return; 895 } 896 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { 897 pl330_fault(ch, PL330_FAULT_EVENT_ERR); 898 return; 899 } 900 if (ch->parent->inten & (1 << ev_id)) { 901 ch->parent->int_status |= (1 << ev_id); 902 trace_pl330_dmasev_evirq(ev_id); 903 qemu_irq_raise(ch->parent->irq[ev_id]); 904 } 905 trace_pl330_dmasev_event(ev_id); 906 ch->parent->ev_status |= (1 << ev_id); 907 } 908 909 static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 910 { 911 uint8_t bs = opcode & 3; 912 uint32_t size, num; 913 bool inc; 914 915 if (bs == 2) { 916 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 917 return; 918 } 919 if ((bs == 1 && ch->request_flag == PL330_BURST) || 920 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 921 /* Perform NOP */ 922 return; 923 } 924 num = ((ch->control >> 18) & 0xf) + 1; 925 size = (uint32_t)1 << ((ch->control >> 15) & 0x7); 926 inc = !!((ch->control >> 14) & 1); 927 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, 928 size, num, inc, 0, ch->tag); 929 if (!ch->stall) { 930 trace_pl330_dmast(ch->tag, ch->dst, size, num, inc ? 'Y' : 'N'); 931 ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0; 932 } 933 } 934 935 static void pl330_dmastp(PL330Chan *ch, uint8_t opcode, 936 uint8_t *args, int len) 937 { 938 uint8_t periph_id; 939 940 if (args[0] & 7) { 941 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 942 return; 943 } 944 periph_id = (args[0] >> 3) & 0x1f; 945 if (periph_id >= ch->parent->num_periph_req) { 946 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 947 return; 948 } 949 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 950 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 951 return; 952 } 953 pl330_dmast(ch, opcode, args, len); 954 } 955 956 static void pl330_dmastz(PL330Chan *ch, uint8_t opcode, 957 uint8_t *args, int len) 958 { 959 uint32_t size, num; 960 bool inc; 961 962 num = ((ch->control >> 18) & 0xf) + 1; 963 size = (uint32_t)1 << ((ch->control >> 15) & 0x7); 964 inc = !!((ch->control >> 14) & 1); 965 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, 966 size, num, inc, 1, ch->tag); 967 if (inc) { 968 ch->dst += size * num; 969 } 970 } 971 972 static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode, 973 uint8_t *args, int len) 974 { 975 uint8_t ev_id; 976 int i; 977 978 if (args[0] & 5) { 979 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 980 return; 981 } 982 ev_id = (args[0] >> 3) & 0x1f; 983 if (ev_id >= ch->parent->num_events) { 984 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 985 return; 986 } 987 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { 988 pl330_fault(ch, PL330_FAULT_EVENT_ERR); 989 return; 990 } 991 ch->wakeup = ev_id; 992 ch->state = pl330_chan_waiting_event; 993 if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) { 994 ch->state = pl330_chan_executing; 995 /* If anyone else is currently waiting on the same event, let them 996 * clear the ev_status so they pick up event as well 997 */ 998 for (i = 0; i < ch->parent->num_chnls; ++i) { 999 PL330Chan *peer = &ch->parent->chan[i]; 1000 if (peer->state == pl330_chan_waiting_event && 1001 peer->wakeup == ev_id) { 1002 return; 1003 } 1004 } 1005 ch->parent->ev_status &= ~(1 << ev_id); 1006 trace_pl330_dmawfe(ev_id); 1007 } else { 1008 ch->stall = 1; 1009 } 1010 } 1011 1012 static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode, 1013 uint8_t *args, int len) 1014 { 1015 uint8_t bs = opcode & 3; 1016 uint8_t periph_id; 1017 1018 if (args[0] & 7) { 1019 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1020 return; 1021 } 1022 periph_id = (args[0] >> 3) & 0x1f; 1023 if (periph_id >= ch->parent->num_periph_req) { 1024 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1025 return; 1026 } 1027 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 1028 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 1029 return; 1030 } 1031 switch (bs) { 1032 case 0: /* S */ 1033 ch->request_flag = PL330_SINGLE; 1034 ch->wfp_sbp = 0; 1035 break; 1036 case 1: /* P */ 1037 ch->request_flag = PL330_BURST; 1038 ch->wfp_sbp = 2; 1039 break; 1040 case 2: /* B */ 1041 ch->request_flag = PL330_BURST; 1042 ch->wfp_sbp = 1; 1043 break; 1044 default: 1045 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1046 return; 1047 } 1048 1049 if (ch->parent->periph_busy[periph_id]) { 1050 ch->state = pl330_chan_waiting_periph; 1051 ch->stall = 1; 1052 } else if (ch->state == pl330_chan_waiting_periph) { 1053 ch->state = pl330_chan_executing; 1054 } 1055 } 1056 1057 static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode, 1058 uint8_t *args, int len) 1059 { 1060 if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) { 1061 ch->state = pl330_chan_at_barrier; 1062 ch->stall = 1; 1063 return; 1064 } else { 1065 ch->state = pl330_chan_executing; 1066 } 1067 } 1068 1069 /* NULL terminated array of the instruction descriptions. */ 1070 static const PL330InsnDesc insn_desc[] = { 1071 { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, }, 1072 { .opcode = 0x5c, .opmask = 0xFD, .size = 3, .exec = pl330_dmaadnh, }, 1073 { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, }, 1074 { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, }, 1075 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, 1076 { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, }, 1077 { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, }, 1078 { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, }, 1079 /* dmastp must be before dmalpend in this list, because their maps 1080 * are overlapping 1081 */ 1082 { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, }, 1083 { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, }, 1084 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, 1085 { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, }, 1086 { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, }, 1087 { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, }, 1088 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, 1089 { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, }, 1090 { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, }, 1091 { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, }, 1092 { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, }, 1093 { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, }, 1094 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } 1095 }; 1096 1097 /* Instructions which can be issued via debug registers. */ 1098 static const PL330InsnDesc debug_insn_desc[] = { 1099 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, 1100 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, 1101 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, 1102 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } 1103 }; 1104 1105 static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch) 1106 { 1107 uint8_t opcode; 1108 int i; 1109 1110 dma_memory_read(&address_space_memory, ch->pc, &opcode, 1); 1111 for (i = 0; insn_desc[i].size; i++) { 1112 if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) { 1113 return &insn_desc[i]; 1114 } 1115 } 1116 return NULL; 1117 } 1118 1119 static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn) 1120 { 1121 uint8_t buf[PL330_INSN_MAXSIZE]; 1122 1123 assert(insn->size <= PL330_INSN_MAXSIZE); 1124 dma_memory_read(&address_space_memory, ch->pc, buf, insn->size); 1125 insn->exec(ch, buf[0], &buf[1], insn->size - 1); 1126 } 1127 1128 static inline void pl330_update_pc(PL330Chan *ch, 1129 const PL330InsnDesc *insn) 1130 { 1131 ch->pc += insn->size; 1132 } 1133 1134 /* Try to execute current instruction in channel CH. Number of executed 1135 instructions is returned (0 or 1). */ 1136 static int pl330_chan_exec(PL330Chan *ch) 1137 { 1138 const PL330InsnDesc *insn; 1139 1140 if (ch->state != pl330_chan_executing && 1141 ch->state != pl330_chan_waiting_periph && 1142 ch->state != pl330_chan_at_barrier && 1143 ch->state != pl330_chan_waiting_event) { 1144 return 0; 1145 } 1146 ch->stall = 0; 1147 insn = pl330_fetch_insn(ch); 1148 if (!insn) { 1149 trace_pl330_chan_exec_undef(); 1150 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 1151 return 0; 1152 } 1153 pl330_exec_insn(ch, insn); 1154 if (!ch->stall) { 1155 pl330_update_pc(ch, insn); 1156 ch->watchdog_timer = 0; 1157 return 1; 1158 /* WDT only active in exec state */ 1159 } else if (ch->state == pl330_chan_executing) { 1160 ch->watchdog_timer++; 1161 if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) { 1162 pl330_fault(ch, PL330_FAULT_LOCKUP_ERR); 1163 } 1164 } 1165 return 0; 1166 } 1167 1168 /* Try to execute 1 instruction in each channel, one instruction from read 1169 queue and one instruction from write queue. Number of successfully executed 1170 instructions is returned. */ 1171 static int pl330_exec_cycle(PL330Chan *channel) 1172 { 1173 PL330State *s = channel->parent; 1174 PL330QueueEntry *q; 1175 int i; 1176 int num_exec = 0; 1177 int fifo_res = 0; 1178 uint8_t buf[PL330_MAX_BURST_LEN]; 1179 1180 /* Execute one instruction in each channel */ 1181 num_exec += pl330_chan_exec(channel); 1182 1183 /* Execute one instruction from read queue */ 1184 q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true); 1185 if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) { 1186 int len = q->len - (q->addr & (q->len - 1)); 1187 1188 dma_memory_read(&address_space_memory, q->addr, buf, len); 1189 trace_pl330_exec_cycle(q->addr, len); 1190 if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { 1191 pl330_hexdump(buf, len); 1192 } 1193 fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag); 1194 if (fifo_res == PL330_FIFO_OK) { 1195 if (q->inc) { 1196 q->addr += len; 1197 } 1198 q->n--; 1199 if (!q->n) { 1200 pl330_queue_remove_insn(&s->read_queue, q); 1201 } 1202 num_exec++; 1203 } 1204 } 1205 1206 /* Execute one instruction from write queue. */ 1207 q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true); 1208 if (q != NULL) { 1209 int len = q->len - (q->addr & (q->len - 1)); 1210 1211 if (q->z) { 1212 for (i = 0; i < len; i++) { 1213 buf[i] = 0; 1214 } 1215 } else { 1216 fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag); 1217 } 1218 if (fifo_res == PL330_FIFO_OK || q->z) { 1219 dma_memory_write(&address_space_memory, q->addr, buf, len); 1220 trace_pl330_exec_cycle(q->addr, len); 1221 if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { 1222 pl330_hexdump(buf, len); 1223 } 1224 if (q->inc) { 1225 q->addr += len; 1226 } 1227 num_exec++; 1228 } else if (fifo_res == PL330_FIFO_STALL) { 1229 pl330_fault(&channel->parent->chan[q->tag], 1230 PL330_FAULT_FIFOEMPTY_ERR); 1231 } 1232 q->n--; 1233 if (!q->n) { 1234 pl330_queue_remove_insn(&s->write_queue, q); 1235 } 1236 } 1237 1238 return num_exec; 1239 } 1240 1241 static int pl330_exec_channel(PL330Chan *channel) 1242 { 1243 int insr_exec = 0; 1244 1245 /* TODO: Is it all right to execute everything or should we do per-cycle 1246 simulation? */ 1247 while (pl330_exec_cycle(channel)) { 1248 insr_exec++; 1249 } 1250 1251 /* Detect deadlock */ 1252 if (channel->state == pl330_chan_executing) { 1253 pl330_fault(channel, PL330_FAULT_LOCKUP_ERR); 1254 } 1255 /* Situation when one of the queues has deadlocked but all channels 1256 * have finished their programs should be impossible. 1257 */ 1258 1259 return insr_exec; 1260 } 1261 1262 static inline void pl330_exec(PL330State *s) 1263 { 1264 int i, insr_exec; 1265 trace_pl330_exec(); 1266 do { 1267 insr_exec = pl330_exec_channel(&s->manager); 1268 1269 for (i = 0; i < s->num_chnls; i++) { 1270 insr_exec += pl330_exec_channel(&s->chan[i]); 1271 } 1272 } while (insr_exec); 1273 } 1274 1275 static void pl330_exec_cycle_timer(void *opaque) 1276 { 1277 PL330State *s = (PL330State *)opaque; 1278 pl330_exec(s); 1279 } 1280 1281 /* Stop or restore dma operations */ 1282 1283 static void pl330_dma_stop_irq(void *opaque, int irq, int level) 1284 { 1285 PL330State *s = (PL330State *)opaque; 1286 1287 if (s->periph_busy[irq] != level) { 1288 s->periph_busy[irq] = level; 1289 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 1290 } 1291 } 1292 1293 static void pl330_debug_exec(PL330State *s) 1294 { 1295 uint8_t args[5]; 1296 uint8_t opcode; 1297 uint8_t chan_id; 1298 int i; 1299 PL330Chan *ch; 1300 const PL330InsnDesc *insn; 1301 1302 s->debug_status = 1; 1303 chan_id = (s->dbg[0] >> 8) & 0x07; 1304 opcode = (s->dbg[0] >> 16) & 0xff; 1305 args[0] = (s->dbg[0] >> 24) & 0xff; 1306 args[1] = (s->dbg[1] >> 0) & 0xff; 1307 args[2] = (s->dbg[1] >> 8) & 0xff; 1308 args[3] = (s->dbg[1] >> 16) & 0xff; 1309 args[4] = (s->dbg[1] >> 24) & 0xff; 1310 trace_pl330_debug_exec(chan_id); 1311 if (s->dbg[0] & 1) { 1312 ch = &s->chan[chan_id]; 1313 } else { 1314 ch = &s->manager; 1315 } 1316 insn = NULL; 1317 for (i = 0; debug_insn_desc[i].size; i++) { 1318 if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) { 1319 insn = &debug_insn_desc[i]; 1320 } 1321 } 1322 if (!insn) { 1323 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR); 1324 return ; 1325 } 1326 ch->stall = 0; 1327 insn->exec(ch, opcode, args, insn->size - 1); 1328 if (ch->fault_type) { 1329 ch->fault_type |= PL330_FAULT_DBG_INSTR; 1330 } 1331 if (ch->stall) { 1332 trace_pl330_debug_exec_stall(); 1333 qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not " 1334 "implemented\n"); 1335 } 1336 s->debug_status = 0; 1337 } 1338 1339 /* IOMEM mapped registers */ 1340 1341 static void pl330_iomem_write(void *opaque, hwaddr offset, 1342 uint64_t value, unsigned size) 1343 { 1344 PL330State *s = (PL330State *) opaque; 1345 int i; 1346 1347 trace_pl330_iomem_write((unsigned)offset, (unsigned)value); 1348 1349 switch (offset) { 1350 case PL330_REG_INTEN: 1351 s->inten = value; 1352 break; 1353 case PL330_REG_INTCLR: 1354 for (i = 0; i < s->num_events; i++) { 1355 if (s->int_status & s->inten & value & (1 << i)) { 1356 trace_pl330_iomem_write_clr(i); 1357 qemu_irq_lower(s->irq[i]); 1358 } 1359 } 1360 s->ev_status &= ~(value & s->inten); 1361 s->int_status &= ~(value & s->inten); 1362 break; 1363 case PL330_REG_DBGCMD: 1364 if ((value & 3) == 0) { 1365 pl330_debug_exec(s); 1366 pl330_exec(s); 1367 } else { 1368 qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u " 1369 "for offset " TARGET_FMT_plx "\n", (unsigned)value, 1370 offset); 1371 } 1372 break; 1373 case PL330_REG_DBGINST0: 1374 s->dbg[0] = value; 1375 break; 1376 case PL330_REG_DBGINST1: 1377 s->dbg[1] = value; 1378 break; 1379 default: 1380 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx 1381 "\n", offset); 1382 break; 1383 } 1384 } 1385 1386 static inline uint32_t pl330_iomem_read_imp(void *opaque, 1387 hwaddr offset) 1388 { 1389 PL330State *s = (PL330State *)opaque; 1390 int chan_id; 1391 int i; 1392 uint32_t res; 1393 1394 if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) { 1395 return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2]; 1396 } 1397 if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) { 1398 return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2]; 1399 } 1400 if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) { 1401 offset -= PL330_REG_CHANCTRL; 1402 chan_id = offset >> 5; 1403 if (chan_id >= s->num_chnls) { 1404 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1405 TARGET_FMT_plx "\n", offset); 1406 return 0; 1407 } 1408 switch (offset & 0x1f) { 1409 case 0x00: 1410 return s->chan[chan_id].src; 1411 case 0x04: 1412 return s->chan[chan_id].dst; 1413 case 0x08: 1414 return s->chan[chan_id].control; 1415 case 0x0C: 1416 return s->chan[chan_id].lc[0]; 1417 case 0x10: 1418 return s->chan[chan_id].lc[1]; 1419 default: 1420 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1421 TARGET_FMT_plx "\n", offset); 1422 return 0; 1423 } 1424 } 1425 if (offset >= PL330_REG_CSR_BASE && offset < 0x400) { 1426 offset -= PL330_REG_CSR_BASE; 1427 chan_id = offset >> 3; 1428 if (chan_id >= s->num_chnls) { 1429 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1430 TARGET_FMT_plx "\n", offset); 1431 return 0; 1432 } 1433 switch ((offset >> 2) & 1) { 1434 case 0x0: 1435 res = (s->chan[chan_id].ns << 21) | 1436 (s->chan[chan_id].wakeup << 4) | 1437 (s->chan[chan_id].state) | 1438 (s->chan[chan_id].wfp_sbp << 14); 1439 return res; 1440 case 0x1: 1441 return s->chan[chan_id].pc; 1442 default: 1443 qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n"); 1444 return 0; 1445 } 1446 } 1447 if (offset >= PL330_REG_FTR_BASE && offset < 0x100) { 1448 offset -= PL330_REG_FTR_BASE; 1449 chan_id = offset >> 2; 1450 if (chan_id >= s->num_chnls) { 1451 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1452 TARGET_FMT_plx "\n", offset); 1453 return 0; 1454 } 1455 return s->chan[chan_id].fault_type; 1456 } 1457 switch (offset) { 1458 case PL330_REG_DSR: 1459 return (s->manager.ns << 9) | (s->manager.wakeup << 4) | 1460 (s->manager.state & 0xf); 1461 case PL330_REG_DPC: 1462 return s->manager.pc; 1463 case PL330_REG_INTEN: 1464 return s->inten; 1465 case PL330_REG_INT_EVENT_RIS: 1466 return s->ev_status; 1467 case PL330_REG_INTMIS: 1468 return s->int_status; 1469 case PL330_REG_INTCLR: 1470 /* Documentation says that we can't read this register 1471 * but linux kernel does it 1472 */ 1473 return 0; 1474 case PL330_REG_FSRD: 1475 return s->manager.state ? 1 : 0; 1476 case PL330_REG_FSRC: 1477 res = 0; 1478 for (i = 0; i < s->num_chnls; i++) { 1479 if (s->chan[i].state == pl330_chan_fault || 1480 s->chan[i].state == pl330_chan_fault_completing) { 1481 res |= 1 << i; 1482 } 1483 } 1484 return res; 1485 case PL330_REG_FTRD: 1486 return s->manager.fault_type; 1487 case PL330_REG_DBGSTATUS: 1488 return s->debug_status; 1489 default: 1490 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1491 TARGET_FMT_plx "\n", offset); 1492 } 1493 return 0; 1494 } 1495 1496 static uint64_t pl330_iomem_read(void *opaque, hwaddr offset, 1497 unsigned size) 1498 { 1499 uint32_t ret = pl330_iomem_read_imp(opaque, offset); 1500 trace_pl330_iomem_read((uint32_t)offset, ret); 1501 return ret; 1502 } 1503 1504 static const MemoryRegionOps pl330_ops = { 1505 .read = pl330_iomem_read, 1506 .write = pl330_iomem_write, 1507 .endianness = DEVICE_NATIVE_ENDIAN, 1508 .impl = { 1509 .min_access_size = 4, 1510 .max_access_size = 4, 1511 } 1512 }; 1513 1514 /* Controller logic and initialization */ 1515 1516 static void pl330_chan_reset(PL330Chan *ch) 1517 { 1518 ch->src = 0; 1519 ch->dst = 0; 1520 ch->pc = 0; 1521 ch->state = pl330_chan_stopped; 1522 ch->watchdog_timer = 0; 1523 ch->stall = 0; 1524 ch->control = 0; 1525 ch->status = 0; 1526 ch->fault_type = 0; 1527 } 1528 1529 static void pl330_reset(DeviceState *d) 1530 { 1531 int i; 1532 PL330State *s = PL330(d); 1533 1534 s->inten = 0; 1535 s->int_status = 0; 1536 s->ev_status = 0; 1537 s->debug_status = 0; 1538 s->num_faulting = 0; 1539 s->manager.ns = s->mgr_ns_at_rst; 1540 pl330_fifo_reset(&s->fifo); 1541 pl330_queue_reset(&s->read_queue); 1542 pl330_queue_reset(&s->write_queue); 1543 1544 for (i = 0; i < s->num_chnls; i++) { 1545 pl330_chan_reset(&s->chan[i]); 1546 } 1547 for (i = 0; i < s->num_periph_req; i++) { 1548 s->periph_busy[i] = 0; 1549 } 1550 1551 timer_del(s->timer); 1552 } 1553 1554 static void pl330_realize(DeviceState *dev, Error **errp) 1555 { 1556 int i; 1557 PL330State *s = PL330(dev); 1558 1559 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort); 1560 memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s, 1561 "dma", PL330_IOMEM_SIZE); 1562 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1563 1564 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s); 1565 1566 s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) | 1567 (s->num_periph_req > 0 ? 1 : 0) | 1568 ((s->num_chnls - 1) & 0x7) << 4 | 1569 ((s->num_periph_req - 1) & 0x1f) << 12 | 1570 ((s->num_events - 1) & 0x1f) << 17; 1571 1572 switch (s->i_cache_len) { 1573 case (4): 1574 s->cfg[1] |= 2; 1575 break; 1576 case (8): 1577 s->cfg[1] |= 3; 1578 break; 1579 case (16): 1580 s->cfg[1] |= 4; 1581 break; 1582 case (32): 1583 s->cfg[1] |= 5; 1584 break; 1585 default: 1586 error_setg(errp, "Bad value for i-cache_len property: %" PRIx8, 1587 s->i_cache_len); 1588 return; 1589 } 1590 s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4; 1591 1592 s->chan = g_new0(PL330Chan, s->num_chnls); 1593 s->hi_seqn = g_new0(uint8_t, s->num_chnls); 1594 s->lo_seqn = g_new0(uint8_t, s->num_chnls); 1595 for (i = 0; i < s->num_chnls; i++) { 1596 s->chan[i].parent = s; 1597 s->chan[i].tag = (uint8_t)i; 1598 } 1599 s->manager.parent = s; 1600 s->manager.tag = s->num_chnls; 1601 s->manager.is_manager = true; 1602 1603 s->irq = g_new0(qemu_irq, s->num_events); 1604 for (i = 0; i < s->num_events; i++) { 1605 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1606 } 1607 1608 qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM); 1609 1610 switch (s->data_width) { 1611 case (32): 1612 s->cfg[CFG_CRD] |= 0x2; 1613 break; 1614 case (64): 1615 s->cfg[CFG_CRD] |= 0x3; 1616 break; 1617 case (128): 1618 s->cfg[CFG_CRD] |= 0x4; 1619 break; 1620 default: 1621 error_setg(errp, "Bad value for data_width property: %" PRIx8, 1622 s->data_width); 1623 return; 1624 } 1625 1626 s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 | 1627 ((s->wr_q_dep - 1) & 0xf) << 8 | 1628 ((s->rd_cap - 1) & 0x7) << 12 | 1629 ((s->rd_q_dep - 1) & 0xf) << 16 | 1630 ((s->data_buffer_dep - 1) & 0x1ff) << 20; 1631 1632 pl330_queue_init(&s->read_queue, s->rd_q_dep, s); 1633 pl330_queue_init(&s->write_queue, s->wr_q_dep, s); 1634 pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep); 1635 } 1636 1637 static Property pl330_properties[] = { 1638 /* CR0 */ 1639 DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8), 1640 DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4), 1641 DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16), 1642 DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0), 1643 /* CR1 */ 1644 DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4), 1645 DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8), 1646 /* CR2-4 */ 1647 DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0), 1648 DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0), 1649 DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0), 1650 /* CRD */ 1651 DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64), 1652 DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8), 1653 DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16), 1654 DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8), 1655 DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16), 1656 DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256), 1657 1658 DEFINE_PROP_END_OF_LIST(), 1659 }; 1660 1661 static void pl330_class_init(ObjectClass *klass, void *data) 1662 { 1663 DeviceClass *dc = DEVICE_CLASS(klass); 1664 1665 dc->realize = pl330_realize; 1666 dc->reset = pl330_reset; 1667 device_class_set_props(dc, pl330_properties); 1668 dc->vmsd = &vmstate_pl330; 1669 } 1670 1671 static const TypeInfo pl330_type_info = { 1672 .name = TYPE_PL330, 1673 .parent = TYPE_SYS_BUS_DEVICE, 1674 .instance_size = sizeof(PL330State), 1675 .class_init = pl330_class_init, 1676 }; 1677 1678 static void pl330_register_types(void) 1679 { 1680 type_register_static(&pl330_type_info); 1681 } 1682 1683 type_init(pl330_register_types) 1684