1 /* 2 * ARM PrimeCell PL330 DMA Controller 3 * 4 * Copyright (c) 2009 Samsung Electronics. 5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru> 6 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 7 * Copyright (c) 2012 PetaLogix Pty Ltd. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; version 2 or later. 12 * 13 * You should have received a copy of the GNU General Public License along 14 * with this program; if not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "hw/irq.h" 20 #include "hw/qdev-properties.h" 21 #include "hw/sysbus.h" 22 #include "migration/vmstate.h" 23 #include "qapi/error.h" 24 #include "qemu/timer.h" 25 #include "sysemu/dma.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "trace.h" 29 #include "qom/object.h" 30 31 #ifndef PL330_ERR_DEBUG 32 #define PL330_ERR_DEBUG 0 33 #endif 34 35 #define PL330_PERIPH_NUM 32 36 #define PL330_MAX_BURST_LEN 128 37 #define PL330_INSN_MAXSIZE 6 38 39 #define PL330_FIFO_OK 0 40 #define PL330_FIFO_STALL 1 41 #define PL330_FIFO_ERR (-1) 42 43 #define PL330_FAULT_UNDEF_INSTR (1 << 0) 44 #define PL330_FAULT_OPERAND_INVALID (1 << 1) 45 #define PL330_FAULT_DMAGO_ERR (1 << 4) 46 #define PL330_FAULT_EVENT_ERR (1 << 5) 47 #define PL330_FAULT_CH_PERIPH_ERR (1 << 6) 48 #define PL330_FAULT_CH_RDWR_ERR (1 << 7) 49 #define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12) 50 #define PL330_FAULT_FIFOEMPTY_ERR (1 << 13) 51 #define PL330_FAULT_INSTR_FETCH_ERR (1 << 16) 52 #define PL330_FAULT_DATA_WRITE_ERR (1 << 17) 53 #define PL330_FAULT_DATA_READ_ERR (1 << 18) 54 #define PL330_FAULT_DBG_INSTR (1 << 30) 55 #define PL330_FAULT_LOCKUP_ERR (1 << 31) 56 57 #define PL330_UNTAGGED 0xff 58 59 #define PL330_SINGLE 0x0 60 #define PL330_BURST 0x1 61 62 #define PL330_WATCHDOG_LIMIT 1024 63 64 /* IOMEM mapped registers */ 65 #define PL330_REG_DSR 0x000 66 #define PL330_REG_DPC 0x004 67 #define PL330_REG_INTEN 0x020 68 #define PL330_REG_INT_EVENT_RIS 0x024 69 #define PL330_REG_INTMIS 0x028 70 #define PL330_REG_INTCLR 0x02C 71 #define PL330_REG_FSRD 0x030 72 #define PL330_REG_FSRC 0x034 73 #define PL330_REG_FTRD 0x038 74 #define PL330_REG_FTR_BASE 0x040 75 #define PL330_REG_CSR_BASE 0x100 76 #define PL330_REG_CPC_BASE 0x104 77 #define PL330_REG_CHANCTRL 0x400 78 #define PL330_REG_DBGSTATUS 0xD00 79 #define PL330_REG_DBGCMD 0xD04 80 #define PL330_REG_DBGINST0 0xD08 81 #define PL330_REG_DBGINST1 0xD0C 82 #define PL330_REG_CR0_BASE 0xE00 83 #define PL330_REG_PERIPH_ID 0xFE0 84 85 #define PL330_IOMEM_SIZE 0x1000 86 87 #define CFG_BOOT_ADDR 2 88 #define CFG_INS 3 89 #define CFG_PNS 4 90 #define CFG_CRD 5 91 92 static const uint32_t pl330_id[] = { 93 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1 94 }; 95 96 /* DMA channel states as they are described in PL330 Technical Reference Manual 97 * Most of them will not be used in emulation. 98 */ 99 typedef enum { 100 pl330_chan_stopped = 0, 101 pl330_chan_executing = 1, 102 pl330_chan_cache_miss = 2, 103 pl330_chan_updating_pc = 3, 104 pl330_chan_waiting_event = 4, 105 pl330_chan_at_barrier = 5, 106 pl330_chan_queue_busy = 6, 107 pl330_chan_waiting_periph = 7, 108 pl330_chan_killing = 8, 109 pl330_chan_completing = 9, 110 pl330_chan_fault_completing = 14, 111 pl330_chan_fault = 15, 112 } PL330ChanState; 113 114 typedef struct PL330State PL330State; 115 116 typedef struct PL330Chan { 117 uint32_t src; 118 uint32_t dst; 119 uint32_t pc; 120 uint32_t control; 121 uint32_t status; 122 uint32_t lc[2]; 123 uint32_t fault_type; 124 uint32_t watchdog_timer; 125 126 bool ns; 127 uint8_t request_flag; 128 uint8_t wakeup; 129 uint8_t wfp_sbp; 130 131 uint8_t state; 132 uint8_t stall; 133 134 bool is_manager; 135 PL330State *parent; 136 uint8_t tag; 137 } PL330Chan; 138 139 static const VMStateDescription vmstate_pl330_chan = { 140 .name = "pl330_chan", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .fields = (VMStateField[]) { 144 VMSTATE_UINT32(src, PL330Chan), 145 VMSTATE_UINT32(dst, PL330Chan), 146 VMSTATE_UINT32(pc, PL330Chan), 147 VMSTATE_UINT32(control, PL330Chan), 148 VMSTATE_UINT32(status, PL330Chan), 149 VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2), 150 VMSTATE_UINT32(fault_type, PL330Chan), 151 VMSTATE_UINT32(watchdog_timer, PL330Chan), 152 VMSTATE_BOOL(ns, PL330Chan), 153 VMSTATE_UINT8(request_flag, PL330Chan), 154 VMSTATE_UINT8(wakeup, PL330Chan), 155 VMSTATE_UINT8(wfp_sbp, PL330Chan), 156 VMSTATE_UINT8(state, PL330Chan), 157 VMSTATE_UINT8(stall, PL330Chan), 158 VMSTATE_END_OF_LIST() 159 } 160 }; 161 162 typedef struct PL330Fifo { 163 uint8_t *buf; 164 uint8_t *tag; 165 uint32_t head; 166 uint32_t num; 167 uint32_t buf_size; 168 } PL330Fifo; 169 170 static const VMStateDescription vmstate_pl330_fifo = { 171 .name = "pl330_chan", 172 .version_id = 1, 173 .minimum_version_id = 1, 174 .fields = (VMStateField[]) { 175 VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, buf_size), 176 VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, buf_size), 177 VMSTATE_UINT32(head, PL330Fifo), 178 VMSTATE_UINT32(num, PL330Fifo), 179 VMSTATE_UINT32(buf_size, PL330Fifo), 180 VMSTATE_END_OF_LIST() 181 } 182 }; 183 184 typedef struct PL330QueueEntry { 185 uint32_t addr; 186 uint32_t len; 187 uint8_t n; 188 bool inc; 189 bool z; 190 uint8_t tag; 191 uint8_t seqn; 192 } PL330QueueEntry; 193 194 static const VMStateDescription vmstate_pl330_queue_entry = { 195 .name = "pl330_queue_entry", 196 .version_id = 1, 197 .minimum_version_id = 1, 198 .fields = (VMStateField[]) { 199 VMSTATE_UINT32(addr, PL330QueueEntry), 200 VMSTATE_UINT32(len, PL330QueueEntry), 201 VMSTATE_UINT8(n, PL330QueueEntry), 202 VMSTATE_BOOL(inc, PL330QueueEntry), 203 VMSTATE_BOOL(z, PL330QueueEntry), 204 VMSTATE_UINT8(tag, PL330QueueEntry), 205 VMSTATE_UINT8(seqn, PL330QueueEntry), 206 VMSTATE_END_OF_LIST() 207 } 208 }; 209 210 typedef struct PL330Queue { 211 PL330State *parent; 212 PL330QueueEntry *queue; 213 uint32_t queue_size; 214 } PL330Queue; 215 216 static const VMStateDescription vmstate_pl330_queue = { 217 .name = "pl330_queue", 218 .version_id = 2, 219 .minimum_version_id = 2, 220 .fields = (VMStateField[]) { 221 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size, 222 vmstate_pl330_queue_entry, 223 PL330QueueEntry), 224 VMSTATE_END_OF_LIST() 225 } 226 }; 227 228 struct PL330State { 229 SysBusDevice parent_obj; 230 231 MemoryRegion iomem; 232 qemu_irq irq_abort; 233 qemu_irq *irq; 234 235 /* Config registers. cfg[5] = CfgDn. */ 236 uint32_t cfg[6]; 237 #define EVENT_SEC_STATE 3 238 #define PERIPH_SEC_STATE 4 239 /* cfg 0 bits and pieces */ 240 uint32_t num_chnls; 241 uint8_t num_periph_req; 242 uint8_t num_events; 243 uint8_t mgr_ns_at_rst; 244 /* cfg 1 bits and pieces */ 245 uint8_t i_cache_len; 246 uint8_t num_i_cache_lines; 247 /* CRD bits and pieces */ 248 uint8_t data_width; 249 uint8_t wr_cap; 250 uint8_t wr_q_dep; 251 uint8_t rd_cap; 252 uint8_t rd_q_dep; 253 uint16_t data_buffer_dep; 254 255 PL330Chan manager; 256 PL330Chan *chan; 257 PL330Fifo fifo; 258 PL330Queue read_queue; 259 PL330Queue write_queue; 260 uint8_t *lo_seqn; 261 uint8_t *hi_seqn; 262 QEMUTimer *timer; /* is used for restore dma. */ 263 264 uint32_t inten; 265 uint32_t int_status; 266 uint32_t ev_status; 267 uint32_t dbg[2]; 268 uint8_t debug_status; 269 uint8_t num_faulting; 270 uint8_t periph_busy[PL330_PERIPH_NUM]; 271 272 }; 273 274 #define TYPE_PL330 "pl330" 275 DECLARE_INSTANCE_CHECKER(PL330State, PL330, 276 TYPE_PL330) 277 278 static const VMStateDescription vmstate_pl330 = { 279 .name = "pl330", 280 .version_id = 2, 281 .minimum_version_id = 2, 282 .fields = (VMStateField[]) { 283 VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan), 284 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls, 285 vmstate_pl330_chan, PL330Chan), 286 VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls), 287 VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls), 288 VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo), 289 VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue, 290 PL330Queue), 291 VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue, 292 PL330Queue), 293 VMSTATE_TIMER_PTR(timer, PL330State), 294 VMSTATE_UINT32(inten, PL330State), 295 VMSTATE_UINT32(int_status, PL330State), 296 VMSTATE_UINT32(ev_status, PL330State), 297 VMSTATE_UINT32_ARRAY(dbg, PL330State, 2), 298 VMSTATE_UINT8(debug_status, PL330State), 299 VMSTATE_UINT8(num_faulting, PL330State), 300 VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM), 301 VMSTATE_END_OF_LIST() 302 } 303 }; 304 305 typedef struct PL330InsnDesc { 306 /* OPCODE of the instruction */ 307 uint8_t opcode; 308 /* Mask so we can select several sibling instructions, such as 309 DMALD, DMALDS and DMALDB */ 310 uint8_t opmask; 311 /* Size of instruction in bytes */ 312 uint8_t size; 313 /* Interpreter */ 314 void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len); 315 } PL330InsnDesc; 316 317 static void pl330_hexdump(uint8_t *buf, size_t size) 318 { 319 unsigned int b, i, len; 320 char tmpbuf[80]; 321 322 for (b = 0; b < size; b += 16) { 323 len = size - b; 324 if (len > 16) { 325 len = 16; 326 } 327 tmpbuf[0] = '\0'; 328 for (i = 0; i < len; i++) { 329 if ((i % 4) == 0) { 330 strcat(tmpbuf, " "); 331 } 332 sprintf(tmpbuf + strlen(tmpbuf), " %02x", buf[b + i]); 333 } 334 trace_pl330_hexdump(b, tmpbuf); 335 } 336 } 337 338 /* MFIFO Implementation 339 * 340 * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are 341 * stored in this buffer. Data is stored in BUF field, tags - in the 342 * corresponding array elements of TAG field. 343 */ 344 345 /* Initialize queue. */ 346 347 static void pl330_fifo_init(PL330Fifo *s, uint32_t size) 348 { 349 s->buf = g_malloc0(size); 350 s->tag = g_malloc0(size); 351 s->buf_size = size; 352 } 353 354 /* Cyclic increment */ 355 356 static inline int pl330_fifo_inc(PL330Fifo *s, int x) 357 { 358 return (x + 1) % s->buf_size; 359 } 360 361 /* Number of empty bytes in MFIFO */ 362 363 static inline int pl330_fifo_num_free(PL330Fifo *s) 364 { 365 return s->buf_size - s->num; 366 } 367 368 /* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG. 369 * Zero returned on success, PL330_FIFO_STALL if there is no enough free 370 * space in MFIFO to store requested amount of data. If push was unsuccessful 371 * no data is stored to MFIFO. 372 */ 373 374 static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) 375 { 376 int i; 377 378 if (s->buf_size - s->num < len) { 379 return PL330_FIFO_STALL; 380 } 381 for (i = 0; i < len; i++) { 382 int push_idx = (s->head + s->num + i) % s->buf_size; 383 s->buf[push_idx] = buf[i]; 384 s->tag[push_idx] = tag; 385 } 386 s->num += len; 387 return PL330_FIFO_OK; 388 } 389 390 /* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each 391 * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch 392 * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was 393 * unsuccessful no data is removed from MFIFO. 394 */ 395 396 static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) 397 { 398 int i; 399 400 if (s->num < len) { 401 return PL330_FIFO_STALL; 402 } 403 for (i = 0; i < len; i++) { 404 if (s->tag[s->head] == tag) { 405 int get_idx = (s->head + i) % s->buf_size; 406 buf[i] = s->buf[get_idx]; 407 } else { /* Tag mismatch - Rollback transaction */ 408 return PL330_FIFO_ERR; 409 } 410 } 411 s->head = (s->head + len) % s->buf_size; 412 s->num -= len; 413 return PL330_FIFO_OK; 414 } 415 416 /* Reset MFIFO. This completely erases all data in it. */ 417 418 static inline void pl330_fifo_reset(PL330Fifo *s) 419 { 420 s->head = 0; 421 s->num = 0; 422 } 423 424 /* Return tag of the first byte stored in MFIFO. If MFIFO is empty 425 * PL330_UNTAGGED is returned. 426 */ 427 428 static inline uint8_t pl330_fifo_tag(PL330Fifo *s) 429 { 430 return (!s->num) ? PL330_UNTAGGED : s->tag[s->head]; 431 } 432 433 /* Returns non-zero if tag TAG is present in fifo or zero otherwise */ 434 435 static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag) 436 { 437 int i, n; 438 439 i = s->head; 440 for (n = 0; n < s->num; n++) { 441 if (s->tag[i] == tag) { 442 return 1; 443 } 444 i = pl330_fifo_inc(s, i); 445 } 446 return 0; 447 } 448 449 /* Remove all entry tagged with TAG from MFIFO */ 450 451 static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag) 452 { 453 int i, t, n; 454 455 t = i = s->head; 456 for (n = 0; n < s->num; n++) { 457 if (s->tag[i] != tag) { 458 s->buf[t] = s->buf[i]; 459 s->tag[t] = s->tag[i]; 460 t = pl330_fifo_inc(s, t); 461 } else { 462 s->num = s->num - 1; 463 } 464 i = pl330_fifo_inc(s, i); 465 } 466 } 467 468 /* Read-Write Queue implementation 469 * 470 * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores). 471 * Each instruction is described by source (for loads) or destination (for 472 * stores) address ADDR, width of data to be loaded/stored LEN, number of 473 * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel 474 * this instruction belongs to. Queue does not store any information about 475 * nature of the instruction: is it load or store. PL330 has different queues 476 * for loads and stores so this is already known at the top level where it 477 * matters. 478 * 479 * Queue works as FIFO for instructions with equivalent tags, but can issue 480 * instructions with different tags in arbitrary order. SEQN field attached to 481 * each instruction helps to achieve this. For each TAG queue contains 482 * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to 483 * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is 484 * followed by SEQN=0. 485 * 486 * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed 487 * in this case. 488 */ 489 490 static void pl330_queue_reset(PL330Queue *s) 491 { 492 int i; 493 494 for (i = 0; i < s->queue_size; i++) { 495 s->queue[i].tag = PL330_UNTAGGED; 496 } 497 } 498 499 /* Initialize queue */ 500 static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent) 501 { 502 s->parent = parent; 503 s->queue = g_new0(PL330QueueEntry, size); 504 s->queue_size = size; 505 } 506 507 /* Returns pointer to an empty slot or NULL if queue is full */ 508 static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s) 509 { 510 int i; 511 512 for (i = 0; i < s->queue_size; i++) { 513 if (s->queue[i].tag == PL330_UNTAGGED) { 514 return &s->queue[i]; 515 } 516 } 517 return NULL; 518 } 519 520 /* Put instruction in queue. 521 * Return value: 522 * - zero - OK 523 * - non-zero - queue is full 524 */ 525 526 static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr, 527 int len, int n, bool inc, bool z, uint8_t tag) 528 { 529 PL330QueueEntry *entry = pl330_queue_find_empty(s); 530 531 if (!entry) { 532 return 1; 533 } 534 entry->tag = tag; 535 entry->addr = addr; 536 entry->len = len; 537 entry->n = n; 538 entry->z = z; 539 entry->inc = inc; 540 entry->seqn = s->parent->hi_seqn[tag]; 541 s->parent->hi_seqn[tag]++; 542 return 0; 543 } 544 545 /* Returns a pointer to queue slot containing instruction which satisfies 546 * following conditions: 547 * - it has valid tag value (not PL330_UNTAGGED) 548 * - if enforce_seq is set it has to be issuable without violating queue 549 * logic (see above) 550 * - if TAG argument is not PL330_UNTAGGED this instruction has tag value 551 * equivalent to the argument TAG value. 552 * If such instruction cannot be found NULL is returned. 553 */ 554 555 static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag, 556 bool enforce_seq) 557 { 558 int i; 559 560 for (i = 0; i < s->queue_size; i++) { 561 if (s->queue[i].tag != PL330_UNTAGGED) { 562 if ((!enforce_seq || 563 s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) && 564 (s->queue[i].tag == tag || tag == PL330_UNTAGGED || 565 s->queue[i].z)) { 566 return &s->queue[i]; 567 } 568 } 569 } 570 return NULL; 571 } 572 573 /* Removes instruction from queue. */ 574 575 static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e) 576 { 577 s->parent->lo_seqn[e->tag]++; 578 e->tag = PL330_UNTAGGED; 579 } 580 581 /* Removes all instructions tagged with TAG from queue. */ 582 583 static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag) 584 { 585 int i; 586 587 for (i = 0; i < s->queue_size; i++) { 588 if (s->queue[i].tag == tag) { 589 s->queue[i].tag = PL330_UNTAGGED; 590 } 591 } 592 } 593 594 /* DMA instruction execution engine */ 595 596 /* Moves DMA channel to the FAULT state and updates it's status. */ 597 598 static inline void pl330_fault(PL330Chan *ch, uint32_t flags) 599 { 600 trace_pl330_fault(ch, flags); 601 ch->fault_type |= flags; 602 if (ch->state == pl330_chan_fault) { 603 return; 604 } 605 ch->state = pl330_chan_fault; 606 ch->parent->num_faulting++; 607 if (ch->parent->num_faulting == 1) { 608 trace_pl330_fault_abort(); 609 qemu_irq_raise(ch->parent->irq_abort); 610 } 611 } 612 613 /* 614 * For information about instructions see PL330 Technical Reference Manual. 615 * 616 * Arguments: 617 * CH - channel executing the instruction 618 * OPCODE - opcode 619 * ARGS - array of 8-bit arguments 620 * LEN - number of elements in ARGS array 621 */ 622 623 static void pl330_dmaadxh(PL330Chan *ch, uint8_t *args, bool ra, bool neg) 624 { 625 uint32_t im = (args[1] << 8) | args[0]; 626 if (neg) { 627 im |= 0xffffu << 16; 628 } 629 630 if (ch->is_manager) { 631 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 632 return; 633 } 634 if (ra) { 635 ch->dst += im; 636 } else { 637 ch->src += im; 638 } 639 } 640 641 static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 642 { 643 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), false); 644 } 645 646 static void pl330_dmaadnh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 647 { 648 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), true); 649 } 650 651 static void pl330_dmaend(PL330Chan *ch, uint8_t opcode, 652 uint8_t *args, int len) 653 { 654 PL330State *s = ch->parent; 655 656 if (ch->state == pl330_chan_executing && !ch->is_manager) { 657 /* Wait for all transfers to complete */ 658 if (pl330_fifo_has_tag(&s->fifo, ch->tag) || 659 pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL || 660 pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) { 661 662 ch->stall = 1; 663 return; 664 } 665 } 666 trace_pl330_dmaend(); 667 pl330_fifo_tagged_remove(&s->fifo, ch->tag); 668 pl330_queue_remove_tagged(&s->read_queue, ch->tag); 669 pl330_queue_remove_tagged(&s->write_queue, ch->tag); 670 ch->state = pl330_chan_stopped; 671 } 672 673 static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode, 674 uint8_t *args, int len) 675 { 676 uint8_t periph_id; 677 678 if (args[0] & 7) { 679 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 680 return; 681 } 682 periph_id = (args[0] >> 3) & 0x1f; 683 if (periph_id >= ch->parent->num_periph_req) { 684 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 685 return; 686 } 687 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 688 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 689 return; 690 } 691 /* Do nothing */ 692 } 693 694 static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 695 { 696 uint8_t chan_id; 697 uint8_t ns; 698 uint32_t pc; 699 PL330Chan *s; 700 701 trace_pl330_dmago(); 702 703 if (!ch->is_manager) { 704 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 705 return; 706 } 707 ns = !!(opcode & 2); 708 chan_id = args[0] & 7; 709 if ((args[0] >> 3)) { 710 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 711 return; 712 } 713 if (chan_id >= ch->parent->num_chnls) { 714 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 715 return; 716 } 717 pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | 718 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); 719 if (ch->parent->chan[chan_id].state != pl330_chan_stopped) { 720 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 721 return; 722 } 723 if (ch->ns && !ns) { 724 pl330_fault(ch, PL330_FAULT_DMAGO_ERR); 725 return; 726 } 727 s = &ch->parent->chan[chan_id]; 728 s->ns = ns; 729 s->pc = pc; 730 s->state = pl330_chan_executing; 731 } 732 733 static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 734 { 735 uint8_t bs = opcode & 3; 736 uint32_t size, num; 737 bool inc; 738 739 if (bs == 2) { 740 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 741 return; 742 } 743 if ((bs == 1 && ch->request_flag == PL330_BURST) || 744 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 745 /* Perform NOP */ 746 return; 747 } 748 if (bs == 1 && ch->request_flag == PL330_SINGLE) { 749 num = 1; 750 } else { 751 num = ((ch->control >> 4) & 0xf) + 1; 752 } 753 size = (uint32_t)1 << ((ch->control >> 1) & 0x7); 754 inc = !!(ch->control & 1); 755 ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src, 756 size, num, inc, 0, ch->tag); 757 if (!ch->stall) { 758 trace_pl330_dmald(ch->tag, ch->src, size, num, inc ? 'Y' : 'N'); 759 ch->src += inc ? size * num - (ch->src & (size - 1)) : 0; 760 } 761 } 762 763 static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 764 { 765 uint8_t periph_id; 766 767 if (args[0] & 7) { 768 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 769 return; 770 } 771 periph_id = (args[0] >> 3) & 0x1f; 772 if (periph_id >= ch->parent->num_periph_req) { 773 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 774 return; 775 } 776 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 777 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 778 return; 779 } 780 pl330_dmald(ch, opcode, args, len); 781 } 782 783 static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 784 { 785 uint8_t lc = (opcode & 2) >> 1; 786 787 ch->lc[lc] = args[0]; 788 } 789 790 static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 791 { 792 if (ch->state == pl330_chan_fault || 793 ch->state == pl330_chan_fault_completing) { 794 /* This is the only way for a channel to leave the faulting state */ 795 ch->fault_type = 0; 796 ch->parent->num_faulting--; 797 if (ch->parent->num_faulting == 0) { 798 trace_pl330_dmakill(); 799 qemu_irq_lower(ch->parent->irq_abort); 800 } 801 } 802 ch->state = pl330_chan_killing; 803 pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag); 804 pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag); 805 pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag); 806 ch->state = pl330_chan_stopped; 807 } 808 809 static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode, 810 uint8_t *args, int len) 811 { 812 uint8_t nf = (opcode & 0x10) >> 4; 813 uint8_t bs = opcode & 3; 814 uint8_t lc = (opcode & 4) >> 2; 815 816 trace_pl330_dmalpend(nf, bs, lc, ch->lc[lc], ch->request_flag); 817 818 if (bs == 2) { 819 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 820 return; 821 } 822 if ((bs == 1 && ch->request_flag == PL330_BURST) || 823 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 824 /* Perform NOP */ 825 return; 826 } 827 if (!nf || ch->lc[lc]) { 828 if (nf) { 829 ch->lc[lc]--; 830 } 831 trace_pl330_dmalpiter(); 832 ch->pc -= args[0]; 833 ch->pc -= len + 1; 834 /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */ 835 } else { 836 trace_pl330_dmalpfallthrough(); 837 } 838 } 839 840 841 static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 842 { 843 uint8_t rd = args[0] & 7; 844 uint32_t im; 845 846 if ((args[0] >> 3)) { 847 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 848 return; 849 } 850 im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | 851 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); 852 switch (rd) { 853 case 0: 854 ch->src = im; 855 break; 856 case 1: 857 ch->control = im; 858 break; 859 case 2: 860 ch->dst = im; 861 break; 862 default: 863 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 864 return; 865 } 866 } 867 868 static void pl330_dmanop(PL330Chan *ch, uint8_t opcode, 869 uint8_t *args, int len) 870 { 871 /* NOP is NOP. */ 872 } 873 874 static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 875 { 876 if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) { 877 ch->state = pl330_chan_at_barrier; 878 ch->stall = 1; 879 return; 880 } else { 881 ch->state = pl330_chan_executing; 882 } 883 } 884 885 static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 886 { 887 uint8_t ev_id; 888 889 if (args[0] & 7) { 890 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 891 return; 892 } 893 ev_id = (args[0] >> 3) & 0x1f; 894 if (ev_id >= ch->parent->num_events) { 895 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 896 return; 897 } 898 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { 899 pl330_fault(ch, PL330_FAULT_EVENT_ERR); 900 return; 901 } 902 if (ch->parent->inten & (1 << ev_id)) { 903 ch->parent->int_status |= (1 << ev_id); 904 trace_pl330_dmasev_evirq(ev_id); 905 qemu_irq_raise(ch->parent->irq[ev_id]); 906 } 907 trace_pl330_dmasev_event(ev_id); 908 ch->parent->ev_status |= (1 << ev_id); 909 } 910 911 static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 912 { 913 uint8_t bs = opcode & 3; 914 uint32_t size, num; 915 bool inc; 916 917 if (bs == 2) { 918 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 919 return; 920 } 921 if ((bs == 1 && ch->request_flag == PL330_BURST) || 922 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 923 /* Perform NOP */ 924 return; 925 } 926 num = ((ch->control >> 18) & 0xf) + 1; 927 size = (uint32_t)1 << ((ch->control >> 15) & 0x7); 928 inc = !!((ch->control >> 14) & 1); 929 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, 930 size, num, inc, 0, ch->tag); 931 if (!ch->stall) { 932 trace_pl330_dmast(ch->tag, ch->dst, size, num, inc ? 'Y' : 'N'); 933 ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0; 934 } 935 } 936 937 static void pl330_dmastp(PL330Chan *ch, uint8_t opcode, 938 uint8_t *args, int len) 939 { 940 uint8_t periph_id; 941 942 if (args[0] & 7) { 943 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 944 return; 945 } 946 periph_id = (args[0] >> 3) & 0x1f; 947 if (periph_id >= ch->parent->num_periph_req) { 948 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 949 return; 950 } 951 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 952 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 953 return; 954 } 955 pl330_dmast(ch, opcode, args, len); 956 } 957 958 static void pl330_dmastz(PL330Chan *ch, uint8_t opcode, 959 uint8_t *args, int len) 960 { 961 uint32_t size, num; 962 bool inc; 963 964 num = ((ch->control >> 18) & 0xf) + 1; 965 size = (uint32_t)1 << ((ch->control >> 15) & 0x7); 966 inc = !!((ch->control >> 14) & 1); 967 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, 968 size, num, inc, 1, ch->tag); 969 if (inc) { 970 ch->dst += size * num; 971 } 972 } 973 974 static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode, 975 uint8_t *args, int len) 976 { 977 uint8_t ev_id; 978 int i; 979 980 if (args[0] & 5) { 981 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 982 return; 983 } 984 ev_id = (args[0] >> 3) & 0x1f; 985 if (ev_id >= ch->parent->num_events) { 986 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 987 return; 988 } 989 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { 990 pl330_fault(ch, PL330_FAULT_EVENT_ERR); 991 return; 992 } 993 ch->wakeup = ev_id; 994 ch->state = pl330_chan_waiting_event; 995 if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) { 996 ch->state = pl330_chan_executing; 997 /* If anyone else is currently waiting on the same event, let them 998 * clear the ev_status so they pick up event as well 999 */ 1000 for (i = 0; i < ch->parent->num_chnls; ++i) { 1001 PL330Chan *peer = &ch->parent->chan[i]; 1002 if (peer->state == pl330_chan_waiting_event && 1003 peer->wakeup == ev_id) { 1004 return; 1005 } 1006 } 1007 ch->parent->ev_status &= ~(1 << ev_id); 1008 trace_pl330_dmawfe(ev_id); 1009 } else { 1010 ch->stall = 1; 1011 } 1012 } 1013 1014 static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode, 1015 uint8_t *args, int len) 1016 { 1017 uint8_t bs = opcode & 3; 1018 uint8_t periph_id; 1019 1020 if (args[0] & 7) { 1021 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1022 return; 1023 } 1024 periph_id = (args[0] >> 3) & 0x1f; 1025 if (periph_id >= ch->parent->num_periph_req) { 1026 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1027 return; 1028 } 1029 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 1030 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 1031 return; 1032 } 1033 switch (bs) { 1034 case 0: /* S */ 1035 ch->request_flag = PL330_SINGLE; 1036 ch->wfp_sbp = 0; 1037 break; 1038 case 1: /* P */ 1039 ch->request_flag = PL330_BURST; 1040 ch->wfp_sbp = 2; 1041 break; 1042 case 2: /* B */ 1043 ch->request_flag = PL330_BURST; 1044 ch->wfp_sbp = 1; 1045 break; 1046 default: 1047 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1048 return; 1049 } 1050 1051 if (ch->parent->periph_busy[periph_id]) { 1052 ch->state = pl330_chan_waiting_periph; 1053 ch->stall = 1; 1054 } else if (ch->state == pl330_chan_waiting_periph) { 1055 ch->state = pl330_chan_executing; 1056 } 1057 } 1058 1059 static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode, 1060 uint8_t *args, int len) 1061 { 1062 if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) { 1063 ch->state = pl330_chan_at_barrier; 1064 ch->stall = 1; 1065 return; 1066 } else { 1067 ch->state = pl330_chan_executing; 1068 } 1069 } 1070 1071 /* NULL terminated array of the instruction descriptions. */ 1072 static const PL330InsnDesc insn_desc[] = { 1073 { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, }, 1074 { .opcode = 0x5c, .opmask = 0xFD, .size = 3, .exec = pl330_dmaadnh, }, 1075 { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, }, 1076 { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, }, 1077 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, 1078 { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, }, 1079 { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, }, 1080 { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, }, 1081 /* dmastp must be before dmalpend in this list, because their maps 1082 * are overlapping 1083 */ 1084 { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, }, 1085 { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, }, 1086 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, 1087 { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, }, 1088 { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, }, 1089 { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, }, 1090 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, 1091 { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, }, 1092 { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, }, 1093 { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, }, 1094 { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, }, 1095 { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, }, 1096 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } 1097 }; 1098 1099 /* Instructions which can be issued via debug registers. */ 1100 static const PL330InsnDesc debug_insn_desc[] = { 1101 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, 1102 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, 1103 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, 1104 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } 1105 }; 1106 1107 static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch) 1108 { 1109 uint8_t opcode; 1110 int i; 1111 1112 dma_memory_read(&address_space_memory, ch->pc, &opcode, 1); 1113 for (i = 0; insn_desc[i].size; i++) { 1114 if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) { 1115 return &insn_desc[i]; 1116 } 1117 } 1118 return NULL; 1119 } 1120 1121 static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn) 1122 { 1123 uint8_t buf[PL330_INSN_MAXSIZE]; 1124 1125 assert(insn->size <= PL330_INSN_MAXSIZE); 1126 dma_memory_read(&address_space_memory, ch->pc, buf, insn->size); 1127 insn->exec(ch, buf[0], &buf[1], insn->size - 1); 1128 } 1129 1130 static inline void pl330_update_pc(PL330Chan *ch, 1131 const PL330InsnDesc *insn) 1132 { 1133 ch->pc += insn->size; 1134 } 1135 1136 /* Try to execute current instruction in channel CH. Number of executed 1137 instructions is returned (0 or 1). */ 1138 static int pl330_chan_exec(PL330Chan *ch) 1139 { 1140 const PL330InsnDesc *insn; 1141 1142 if (ch->state != pl330_chan_executing && 1143 ch->state != pl330_chan_waiting_periph && 1144 ch->state != pl330_chan_at_barrier && 1145 ch->state != pl330_chan_waiting_event) { 1146 return 0; 1147 } 1148 ch->stall = 0; 1149 insn = pl330_fetch_insn(ch); 1150 if (!insn) { 1151 trace_pl330_chan_exec_undef(); 1152 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 1153 return 0; 1154 } 1155 pl330_exec_insn(ch, insn); 1156 if (!ch->stall) { 1157 pl330_update_pc(ch, insn); 1158 ch->watchdog_timer = 0; 1159 return 1; 1160 /* WDT only active in exec state */ 1161 } else if (ch->state == pl330_chan_executing) { 1162 ch->watchdog_timer++; 1163 if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) { 1164 pl330_fault(ch, PL330_FAULT_LOCKUP_ERR); 1165 } 1166 } 1167 return 0; 1168 } 1169 1170 /* Try to execute 1 instruction in each channel, one instruction from read 1171 queue and one instruction from write queue. Number of successfully executed 1172 instructions is returned. */ 1173 static int pl330_exec_cycle(PL330Chan *channel) 1174 { 1175 PL330State *s = channel->parent; 1176 PL330QueueEntry *q; 1177 int i; 1178 int num_exec = 0; 1179 int fifo_res = 0; 1180 uint8_t buf[PL330_MAX_BURST_LEN]; 1181 1182 /* Execute one instruction in each channel */ 1183 num_exec += pl330_chan_exec(channel); 1184 1185 /* Execute one instruction from read queue */ 1186 q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true); 1187 if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) { 1188 int len = q->len - (q->addr & (q->len - 1)); 1189 1190 dma_memory_read(&address_space_memory, q->addr, buf, len); 1191 trace_pl330_exec_cycle(q->addr, len); 1192 if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { 1193 pl330_hexdump(buf, len); 1194 } 1195 fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag); 1196 if (fifo_res == PL330_FIFO_OK) { 1197 if (q->inc) { 1198 q->addr += len; 1199 } 1200 q->n--; 1201 if (!q->n) { 1202 pl330_queue_remove_insn(&s->read_queue, q); 1203 } 1204 num_exec++; 1205 } 1206 } 1207 1208 /* Execute one instruction from write queue. */ 1209 q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true); 1210 if (q != NULL) { 1211 int len = q->len - (q->addr & (q->len - 1)); 1212 1213 if (q->z) { 1214 for (i = 0; i < len; i++) { 1215 buf[i] = 0; 1216 } 1217 } else { 1218 fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag); 1219 } 1220 if (fifo_res == PL330_FIFO_OK || q->z) { 1221 dma_memory_write(&address_space_memory, q->addr, buf, len); 1222 trace_pl330_exec_cycle(q->addr, len); 1223 if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { 1224 pl330_hexdump(buf, len); 1225 } 1226 if (q->inc) { 1227 q->addr += len; 1228 } 1229 num_exec++; 1230 } else if (fifo_res == PL330_FIFO_STALL) { 1231 pl330_fault(&channel->parent->chan[q->tag], 1232 PL330_FAULT_FIFOEMPTY_ERR); 1233 } 1234 q->n--; 1235 if (!q->n) { 1236 pl330_queue_remove_insn(&s->write_queue, q); 1237 } 1238 } 1239 1240 return num_exec; 1241 } 1242 1243 static int pl330_exec_channel(PL330Chan *channel) 1244 { 1245 int insr_exec = 0; 1246 1247 /* TODO: Is it all right to execute everything or should we do per-cycle 1248 simulation? */ 1249 while (pl330_exec_cycle(channel)) { 1250 insr_exec++; 1251 } 1252 1253 /* Detect deadlock */ 1254 if (channel->state == pl330_chan_executing) { 1255 pl330_fault(channel, PL330_FAULT_LOCKUP_ERR); 1256 } 1257 /* Situation when one of the queues has deadlocked but all channels 1258 * have finished their programs should be impossible. 1259 */ 1260 1261 return insr_exec; 1262 } 1263 1264 static inline void pl330_exec(PL330State *s) 1265 { 1266 int i, insr_exec; 1267 trace_pl330_exec(); 1268 do { 1269 insr_exec = pl330_exec_channel(&s->manager); 1270 1271 for (i = 0; i < s->num_chnls; i++) { 1272 insr_exec += pl330_exec_channel(&s->chan[i]); 1273 } 1274 } while (insr_exec); 1275 } 1276 1277 static void pl330_exec_cycle_timer(void *opaque) 1278 { 1279 PL330State *s = (PL330State *)opaque; 1280 pl330_exec(s); 1281 } 1282 1283 /* Stop or restore dma operations */ 1284 1285 static void pl330_dma_stop_irq(void *opaque, int irq, int level) 1286 { 1287 PL330State *s = (PL330State *)opaque; 1288 1289 if (s->periph_busy[irq] != level) { 1290 s->periph_busy[irq] = level; 1291 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 1292 } 1293 } 1294 1295 static void pl330_debug_exec(PL330State *s) 1296 { 1297 uint8_t args[5]; 1298 uint8_t opcode; 1299 uint8_t chan_id; 1300 int i; 1301 PL330Chan *ch; 1302 const PL330InsnDesc *insn; 1303 1304 s->debug_status = 1; 1305 chan_id = (s->dbg[0] >> 8) & 0x07; 1306 opcode = (s->dbg[0] >> 16) & 0xff; 1307 args[0] = (s->dbg[0] >> 24) & 0xff; 1308 args[1] = (s->dbg[1] >> 0) & 0xff; 1309 args[2] = (s->dbg[1] >> 8) & 0xff; 1310 args[3] = (s->dbg[1] >> 16) & 0xff; 1311 args[4] = (s->dbg[1] >> 24) & 0xff; 1312 trace_pl330_debug_exec(chan_id); 1313 if (s->dbg[0] & 1) { 1314 ch = &s->chan[chan_id]; 1315 } else { 1316 ch = &s->manager; 1317 } 1318 insn = NULL; 1319 for (i = 0; debug_insn_desc[i].size; i++) { 1320 if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) { 1321 insn = &debug_insn_desc[i]; 1322 } 1323 } 1324 if (!insn) { 1325 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR); 1326 return ; 1327 } 1328 ch->stall = 0; 1329 insn->exec(ch, opcode, args, insn->size - 1); 1330 if (ch->fault_type) { 1331 ch->fault_type |= PL330_FAULT_DBG_INSTR; 1332 } 1333 if (ch->stall) { 1334 trace_pl330_debug_exec_stall(); 1335 qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not " 1336 "implemented\n"); 1337 } 1338 s->debug_status = 0; 1339 } 1340 1341 /* IOMEM mapped registers */ 1342 1343 static void pl330_iomem_write(void *opaque, hwaddr offset, 1344 uint64_t value, unsigned size) 1345 { 1346 PL330State *s = (PL330State *) opaque; 1347 int i; 1348 1349 trace_pl330_iomem_write((unsigned)offset, (unsigned)value); 1350 1351 switch (offset) { 1352 case PL330_REG_INTEN: 1353 s->inten = value; 1354 break; 1355 case PL330_REG_INTCLR: 1356 for (i = 0; i < s->num_events; i++) { 1357 if (s->int_status & s->inten & value & (1 << i)) { 1358 trace_pl330_iomem_write_clr(i); 1359 qemu_irq_lower(s->irq[i]); 1360 } 1361 } 1362 s->ev_status &= ~(value & s->inten); 1363 s->int_status &= ~(value & s->inten); 1364 break; 1365 case PL330_REG_DBGCMD: 1366 if ((value & 3) == 0) { 1367 pl330_debug_exec(s); 1368 pl330_exec(s); 1369 } else { 1370 qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u " 1371 "for offset " TARGET_FMT_plx "\n", (unsigned)value, 1372 offset); 1373 } 1374 break; 1375 case PL330_REG_DBGINST0: 1376 s->dbg[0] = value; 1377 break; 1378 case PL330_REG_DBGINST1: 1379 s->dbg[1] = value; 1380 break; 1381 default: 1382 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx 1383 "\n", offset); 1384 break; 1385 } 1386 } 1387 1388 static inline uint32_t pl330_iomem_read_imp(void *opaque, 1389 hwaddr offset) 1390 { 1391 PL330State *s = (PL330State *)opaque; 1392 int chan_id; 1393 int i; 1394 uint32_t res; 1395 1396 if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) { 1397 return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2]; 1398 } 1399 if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) { 1400 return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2]; 1401 } 1402 if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) { 1403 offset -= PL330_REG_CHANCTRL; 1404 chan_id = offset >> 5; 1405 if (chan_id >= s->num_chnls) { 1406 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1407 TARGET_FMT_plx "\n", offset); 1408 return 0; 1409 } 1410 switch (offset & 0x1f) { 1411 case 0x00: 1412 return s->chan[chan_id].src; 1413 case 0x04: 1414 return s->chan[chan_id].dst; 1415 case 0x08: 1416 return s->chan[chan_id].control; 1417 case 0x0C: 1418 return s->chan[chan_id].lc[0]; 1419 case 0x10: 1420 return s->chan[chan_id].lc[1]; 1421 default: 1422 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1423 TARGET_FMT_plx "\n", offset); 1424 return 0; 1425 } 1426 } 1427 if (offset >= PL330_REG_CSR_BASE && offset < 0x400) { 1428 offset -= PL330_REG_CSR_BASE; 1429 chan_id = offset >> 3; 1430 if (chan_id >= s->num_chnls) { 1431 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1432 TARGET_FMT_plx "\n", offset); 1433 return 0; 1434 } 1435 switch ((offset >> 2) & 1) { 1436 case 0x0: 1437 res = (s->chan[chan_id].ns << 21) | 1438 (s->chan[chan_id].wakeup << 4) | 1439 (s->chan[chan_id].state) | 1440 (s->chan[chan_id].wfp_sbp << 14); 1441 return res; 1442 case 0x1: 1443 return s->chan[chan_id].pc; 1444 default: 1445 qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n"); 1446 return 0; 1447 } 1448 } 1449 if (offset >= PL330_REG_FTR_BASE && offset < 0x100) { 1450 offset -= PL330_REG_FTR_BASE; 1451 chan_id = offset >> 2; 1452 if (chan_id >= s->num_chnls) { 1453 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1454 TARGET_FMT_plx "\n", offset); 1455 return 0; 1456 } 1457 return s->chan[chan_id].fault_type; 1458 } 1459 switch (offset) { 1460 case PL330_REG_DSR: 1461 return (s->manager.ns << 9) | (s->manager.wakeup << 4) | 1462 (s->manager.state & 0xf); 1463 case PL330_REG_DPC: 1464 return s->manager.pc; 1465 case PL330_REG_INTEN: 1466 return s->inten; 1467 case PL330_REG_INT_EVENT_RIS: 1468 return s->ev_status; 1469 case PL330_REG_INTMIS: 1470 return s->int_status; 1471 case PL330_REG_INTCLR: 1472 /* Documentation says that we can't read this register 1473 * but linux kernel does it 1474 */ 1475 return 0; 1476 case PL330_REG_FSRD: 1477 return s->manager.state ? 1 : 0; 1478 case PL330_REG_FSRC: 1479 res = 0; 1480 for (i = 0; i < s->num_chnls; i++) { 1481 if (s->chan[i].state == pl330_chan_fault || 1482 s->chan[i].state == pl330_chan_fault_completing) { 1483 res |= 1 << i; 1484 } 1485 } 1486 return res; 1487 case PL330_REG_FTRD: 1488 return s->manager.fault_type; 1489 case PL330_REG_DBGSTATUS: 1490 return s->debug_status; 1491 default: 1492 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1493 TARGET_FMT_plx "\n", offset); 1494 } 1495 return 0; 1496 } 1497 1498 static uint64_t pl330_iomem_read(void *opaque, hwaddr offset, 1499 unsigned size) 1500 { 1501 uint32_t ret = pl330_iomem_read_imp(opaque, offset); 1502 trace_pl330_iomem_read((uint32_t)offset, ret); 1503 return ret; 1504 } 1505 1506 static const MemoryRegionOps pl330_ops = { 1507 .read = pl330_iomem_read, 1508 .write = pl330_iomem_write, 1509 .endianness = DEVICE_NATIVE_ENDIAN, 1510 .impl = { 1511 .min_access_size = 4, 1512 .max_access_size = 4, 1513 } 1514 }; 1515 1516 /* Controller logic and initialization */ 1517 1518 static void pl330_chan_reset(PL330Chan *ch) 1519 { 1520 ch->src = 0; 1521 ch->dst = 0; 1522 ch->pc = 0; 1523 ch->state = pl330_chan_stopped; 1524 ch->watchdog_timer = 0; 1525 ch->stall = 0; 1526 ch->control = 0; 1527 ch->status = 0; 1528 ch->fault_type = 0; 1529 } 1530 1531 static void pl330_reset(DeviceState *d) 1532 { 1533 int i; 1534 PL330State *s = PL330(d); 1535 1536 s->inten = 0; 1537 s->int_status = 0; 1538 s->ev_status = 0; 1539 s->debug_status = 0; 1540 s->num_faulting = 0; 1541 s->manager.ns = s->mgr_ns_at_rst; 1542 pl330_fifo_reset(&s->fifo); 1543 pl330_queue_reset(&s->read_queue); 1544 pl330_queue_reset(&s->write_queue); 1545 1546 for (i = 0; i < s->num_chnls; i++) { 1547 pl330_chan_reset(&s->chan[i]); 1548 } 1549 for (i = 0; i < s->num_periph_req; i++) { 1550 s->periph_busy[i] = 0; 1551 } 1552 1553 timer_del(s->timer); 1554 } 1555 1556 static void pl330_realize(DeviceState *dev, Error **errp) 1557 { 1558 int i; 1559 PL330State *s = PL330(dev); 1560 1561 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort); 1562 memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s, 1563 "dma", PL330_IOMEM_SIZE); 1564 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1565 1566 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s); 1567 1568 s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) | 1569 (s->num_periph_req > 0 ? 1 : 0) | 1570 ((s->num_chnls - 1) & 0x7) << 4 | 1571 ((s->num_periph_req - 1) & 0x1f) << 12 | 1572 ((s->num_events - 1) & 0x1f) << 17; 1573 1574 switch (s->i_cache_len) { 1575 case (4): 1576 s->cfg[1] |= 2; 1577 break; 1578 case (8): 1579 s->cfg[1] |= 3; 1580 break; 1581 case (16): 1582 s->cfg[1] |= 4; 1583 break; 1584 case (32): 1585 s->cfg[1] |= 5; 1586 break; 1587 default: 1588 error_setg(errp, "Bad value for i-cache_len property: %" PRIx8, 1589 s->i_cache_len); 1590 return; 1591 } 1592 s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4; 1593 1594 s->chan = g_new0(PL330Chan, s->num_chnls); 1595 s->hi_seqn = g_new0(uint8_t, s->num_chnls); 1596 s->lo_seqn = g_new0(uint8_t, s->num_chnls); 1597 for (i = 0; i < s->num_chnls; i++) { 1598 s->chan[i].parent = s; 1599 s->chan[i].tag = (uint8_t)i; 1600 } 1601 s->manager.parent = s; 1602 s->manager.tag = s->num_chnls; 1603 s->manager.is_manager = true; 1604 1605 s->irq = g_new0(qemu_irq, s->num_events); 1606 for (i = 0; i < s->num_events; i++) { 1607 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1608 } 1609 1610 qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM); 1611 1612 switch (s->data_width) { 1613 case (32): 1614 s->cfg[CFG_CRD] |= 0x2; 1615 break; 1616 case (64): 1617 s->cfg[CFG_CRD] |= 0x3; 1618 break; 1619 case (128): 1620 s->cfg[CFG_CRD] |= 0x4; 1621 break; 1622 default: 1623 error_setg(errp, "Bad value for data_width property: %" PRIx8, 1624 s->data_width); 1625 return; 1626 } 1627 1628 s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 | 1629 ((s->wr_q_dep - 1) & 0xf) << 8 | 1630 ((s->rd_cap - 1) & 0x7) << 12 | 1631 ((s->rd_q_dep - 1) & 0xf) << 16 | 1632 ((s->data_buffer_dep - 1) & 0x1ff) << 20; 1633 1634 pl330_queue_init(&s->read_queue, s->rd_q_dep, s); 1635 pl330_queue_init(&s->write_queue, s->wr_q_dep, s); 1636 pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep); 1637 } 1638 1639 static Property pl330_properties[] = { 1640 /* CR0 */ 1641 DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8), 1642 DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4), 1643 DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16), 1644 DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0), 1645 /* CR1 */ 1646 DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4), 1647 DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8), 1648 /* CR2-4 */ 1649 DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0), 1650 DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0), 1651 DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0), 1652 /* CRD */ 1653 DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64), 1654 DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8), 1655 DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16), 1656 DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8), 1657 DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16), 1658 DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256), 1659 1660 DEFINE_PROP_END_OF_LIST(), 1661 }; 1662 1663 static void pl330_class_init(ObjectClass *klass, void *data) 1664 { 1665 DeviceClass *dc = DEVICE_CLASS(klass); 1666 1667 dc->realize = pl330_realize; 1668 dc->reset = pl330_reset; 1669 device_class_set_props(dc, pl330_properties); 1670 dc->vmsd = &vmstate_pl330; 1671 } 1672 1673 static const TypeInfo pl330_type_info = { 1674 .name = TYPE_PL330, 1675 .parent = TYPE_SYS_BUS_DEVICE, 1676 .instance_size = sizeof(PL330State), 1677 .class_init = pl330_class_init, 1678 }; 1679 1680 static void pl330_register_types(void) 1681 { 1682 type_register_static(&pl330_type_info); 1683 } 1684 1685 type_init(pl330_register_types) 1686