1 /* 2 * ARM PrimeCell PL330 DMA Controller 3 * 4 * Copyright (c) 2009 Samsung Electronics. 5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru> 6 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 7 * Copyright (c) 2012 PetaLogix Pty Ltd. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; version 2 or later. 12 * 13 * You should have received a copy of the GNU General Public License along 14 * with this program; if not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "hw/sysbus.h" 19 #include "qemu/timer.h" 20 #include "sysemu/dma.h" 21 22 #ifndef PL330_ERR_DEBUG 23 #define PL330_ERR_DEBUG 0 24 #endif 25 26 #define DB_PRINT_L(lvl, fmt, args...) do {\ 27 if (PL330_ERR_DEBUG >= lvl) {\ 28 fprintf(stderr, "PL330: %s:" fmt, __func__, ## args);\ 29 } \ 30 } while (0); 31 32 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 33 34 #define PL330_PERIPH_NUM 32 35 #define PL330_MAX_BURST_LEN 128 36 #define PL330_INSN_MAXSIZE 6 37 38 #define PL330_FIFO_OK 0 39 #define PL330_FIFO_STALL 1 40 #define PL330_FIFO_ERR (-1) 41 42 #define PL330_FAULT_UNDEF_INSTR (1 << 0) 43 #define PL330_FAULT_OPERAND_INVALID (1 << 1) 44 #define PL330_FAULT_DMAGO_ERR (1 << 4) 45 #define PL330_FAULT_EVENT_ERR (1 << 5) 46 #define PL330_FAULT_CH_PERIPH_ERR (1 << 6) 47 #define PL330_FAULT_CH_RDWR_ERR (1 << 7) 48 #define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12) 49 #define PL330_FAULT_FIFOEMPTY_ERR (1 << 13) 50 #define PL330_FAULT_INSTR_FETCH_ERR (1 << 16) 51 #define PL330_FAULT_DATA_WRITE_ERR (1 << 17) 52 #define PL330_FAULT_DATA_READ_ERR (1 << 18) 53 #define PL330_FAULT_DBG_INSTR (1 << 30) 54 #define PL330_FAULT_LOCKUP_ERR (1 << 31) 55 56 #define PL330_UNTAGGED 0xff 57 58 #define PL330_SINGLE 0x0 59 #define PL330_BURST 0x1 60 61 #define PL330_WATCHDOG_LIMIT 1024 62 63 /* IOMEM mapped registers */ 64 #define PL330_REG_DSR 0x000 65 #define PL330_REG_DPC 0x004 66 #define PL330_REG_INTEN 0x020 67 #define PL330_REG_INT_EVENT_RIS 0x024 68 #define PL330_REG_INTMIS 0x028 69 #define PL330_REG_INTCLR 0x02C 70 #define PL330_REG_FSRD 0x030 71 #define PL330_REG_FSRC 0x034 72 #define PL330_REG_FTRD 0x038 73 #define PL330_REG_FTR_BASE 0x040 74 #define PL330_REG_CSR_BASE 0x100 75 #define PL330_REG_CPC_BASE 0x104 76 #define PL330_REG_CHANCTRL 0x400 77 #define PL330_REG_DBGSTATUS 0xD00 78 #define PL330_REG_DBGCMD 0xD04 79 #define PL330_REG_DBGINST0 0xD08 80 #define PL330_REG_DBGINST1 0xD0C 81 #define PL330_REG_CR0_BASE 0xE00 82 #define PL330_REG_PERIPH_ID 0xFE0 83 84 #define PL330_IOMEM_SIZE 0x1000 85 86 #define CFG_BOOT_ADDR 2 87 #define CFG_INS 3 88 #define CFG_PNS 4 89 #define CFG_CRD 5 90 91 static const uint32_t pl330_id[] = { 92 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1 93 }; 94 95 /* DMA channel states as they are described in PL330 Technical Reference Manual 96 * Most of them will not be used in emulation. 97 */ 98 typedef enum { 99 pl330_chan_stopped = 0, 100 pl330_chan_executing = 1, 101 pl330_chan_cache_miss = 2, 102 pl330_chan_updating_pc = 3, 103 pl330_chan_waiting_event = 4, 104 pl330_chan_at_barrier = 5, 105 pl330_chan_queue_busy = 6, 106 pl330_chan_waiting_periph = 7, 107 pl330_chan_killing = 8, 108 pl330_chan_completing = 9, 109 pl330_chan_fault_completing = 14, 110 pl330_chan_fault = 15, 111 } PL330ChanState; 112 113 typedef struct PL330State PL330State; 114 115 typedef struct PL330Chan { 116 uint32_t src; 117 uint32_t dst; 118 uint32_t pc; 119 uint32_t control; 120 uint32_t status; 121 uint32_t lc[2]; 122 uint32_t fault_type; 123 uint32_t watchdog_timer; 124 125 bool ns; 126 uint8_t request_flag; 127 uint8_t wakeup; 128 uint8_t wfp_sbp; 129 130 uint8_t state; 131 uint8_t stall; 132 133 bool is_manager; 134 PL330State *parent; 135 uint8_t tag; 136 } PL330Chan; 137 138 static const VMStateDescription vmstate_pl330_chan = { 139 .name = "pl330_chan", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .fields = (VMStateField[]) { 143 VMSTATE_UINT32(src, PL330Chan), 144 VMSTATE_UINT32(dst, PL330Chan), 145 VMSTATE_UINT32(pc, PL330Chan), 146 VMSTATE_UINT32(control, PL330Chan), 147 VMSTATE_UINT32(status, PL330Chan), 148 VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2), 149 VMSTATE_UINT32(fault_type, PL330Chan), 150 VMSTATE_UINT32(watchdog_timer, PL330Chan), 151 VMSTATE_BOOL(ns, PL330Chan), 152 VMSTATE_UINT8(request_flag, PL330Chan), 153 VMSTATE_UINT8(wakeup, PL330Chan), 154 VMSTATE_UINT8(wfp_sbp, PL330Chan), 155 VMSTATE_UINT8(state, PL330Chan), 156 VMSTATE_UINT8(stall, PL330Chan), 157 VMSTATE_END_OF_LIST() 158 } 159 }; 160 161 typedef struct PL330Fifo { 162 uint8_t *buf; 163 uint8_t *tag; 164 uint32_t head; 165 uint32_t num; 166 uint32_t buf_size; 167 } PL330Fifo; 168 169 static const VMStateDescription vmstate_pl330_fifo = { 170 .name = "pl330_chan", 171 .version_id = 1, 172 .minimum_version_id = 1, 173 .fields = (VMStateField[]) { 174 VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, 0, buf_size), 175 VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, 0, buf_size), 176 VMSTATE_UINT32(head, PL330Fifo), 177 VMSTATE_UINT32(num, PL330Fifo), 178 VMSTATE_UINT32(buf_size, PL330Fifo), 179 VMSTATE_END_OF_LIST() 180 } 181 }; 182 183 typedef struct PL330QueueEntry { 184 uint32_t addr; 185 uint32_t len; 186 uint8_t n; 187 bool inc; 188 bool z; 189 uint8_t tag; 190 uint8_t seqn; 191 } PL330QueueEntry; 192 193 static const VMStateDescription vmstate_pl330_queue_entry = { 194 .name = "pl330_queue_entry", 195 .version_id = 1, 196 .minimum_version_id = 1, 197 .fields = (VMStateField[]) { 198 VMSTATE_UINT32(addr, PL330QueueEntry), 199 VMSTATE_UINT32(len, PL330QueueEntry), 200 VMSTATE_UINT8(n, PL330QueueEntry), 201 VMSTATE_BOOL(inc, PL330QueueEntry), 202 VMSTATE_BOOL(z, PL330QueueEntry), 203 VMSTATE_UINT8(tag, PL330QueueEntry), 204 VMSTATE_UINT8(seqn, PL330QueueEntry), 205 VMSTATE_END_OF_LIST() 206 } 207 }; 208 209 typedef struct PL330Queue { 210 PL330State *parent; 211 PL330QueueEntry *queue; 212 uint32_t queue_size; 213 } PL330Queue; 214 215 static const VMStateDescription vmstate_pl330_queue = { 216 .name = "pl330_queue", 217 .version_id = 1, 218 .minimum_version_id = 1, 219 .fields = (VMStateField[]) { 220 VMSTATE_STRUCT_VARRAY_UINT32(queue, PL330Queue, queue_size, 1, 221 vmstate_pl330_queue_entry, PL330QueueEntry), 222 VMSTATE_END_OF_LIST() 223 } 224 }; 225 226 struct PL330State { 227 SysBusDevice parent_obj; 228 229 MemoryRegion iomem; 230 qemu_irq irq_abort; 231 qemu_irq *irq; 232 233 /* Config registers. cfg[5] = CfgDn. */ 234 uint32_t cfg[6]; 235 #define EVENT_SEC_STATE 3 236 #define PERIPH_SEC_STATE 4 237 /* cfg 0 bits and pieces */ 238 uint32_t num_chnls; 239 uint8_t num_periph_req; 240 uint8_t num_events; 241 uint8_t mgr_ns_at_rst; 242 /* cfg 1 bits and pieces */ 243 uint8_t i_cache_len; 244 uint8_t num_i_cache_lines; 245 /* CRD bits and pieces */ 246 uint8_t data_width; 247 uint8_t wr_cap; 248 uint8_t wr_q_dep; 249 uint8_t rd_cap; 250 uint8_t rd_q_dep; 251 uint16_t data_buffer_dep; 252 253 PL330Chan manager; 254 PL330Chan *chan; 255 PL330Fifo fifo; 256 PL330Queue read_queue; 257 PL330Queue write_queue; 258 uint8_t *lo_seqn; 259 uint8_t *hi_seqn; 260 QEMUTimer *timer; /* is used for restore dma. */ 261 262 uint32_t inten; 263 uint32_t int_status; 264 uint32_t ev_status; 265 uint32_t dbg[2]; 266 uint8_t debug_status; 267 uint8_t num_faulting; 268 uint8_t periph_busy[PL330_PERIPH_NUM]; 269 270 }; 271 272 #define TYPE_PL330 "pl330" 273 #define PL330(obj) OBJECT_CHECK(PL330State, (obj), TYPE_PL330) 274 275 static const VMStateDescription vmstate_pl330 = { 276 .name = "pl330", 277 .version_id = 1, 278 .minimum_version_id = 1, 279 .fields = (VMStateField[]) { 280 VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan), 281 VMSTATE_STRUCT_VARRAY_UINT32(chan, PL330State, num_chnls, 0, 282 vmstate_pl330_chan, PL330Chan), 283 VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, 0, num_chnls), 284 VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, 0, num_chnls), 285 VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo), 286 VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue, 287 PL330Queue), 288 VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue, 289 PL330Queue), 290 VMSTATE_TIMER_PTR(timer, PL330State), 291 VMSTATE_UINT32(inten, PL330State), 292 VMSTATE_UINT32(int_status, PL330State), 293 VMSTATE_UINT32(ev_status, PL330State), 294 VMSTATE_UINT32_ARRAY(dbg, PL330State, 2), 295 VMSTATE_UINT8(debug_status, PL330State), 296 VMSTATE_UINT8(num_faulting, PL330State), 297 VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM), 298 VMSTATE_END_OF_LIST() 299 } 300 }; 301 302 typedef struct PL330InsnDesc { 303 /* OPCODE of the instruction */ 304 uint8_t opcode; 305 /* Mask so we can select several sibling instructions, such as 306 DMALD, DMALDS and DMALDB */ 307 uint8_t opmask; 308 /* Size of instruction in bytes */ 309 uint8_t size; 310 /* Interpreter */ 311 void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len); 312 } PL330InsnDesc; 313 314 315 /* MFIFO Implementation 316 * 317 * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are 318 * stored in this buffer. Data is stored in BUF field, tags - in the 319 * corresponding array elements of TAG field. 320 */ 321 322 /* Initialize queue. */ 323 324 static void pl330_fifo_init(PL330Fifo *s, uint32_t size) 325 { 326 s->buf = g_malloc0(size); 327 s->tag = g_malloc0(size); 328 s->buf_size = size; 329 } 330 331 /* Cyclic increment */ 332 333 static inline int pl330_fifo_inc(PL330Fifo *s, int x) 334 { 335 return (x + 1) % s->buf_size; 336 } 337 338 /* Number of empty bytes in MFIFO */ 339 340 static inline int pl330_fifo_num_free(PL330Fifo *s) 341 { 342 return s->buf_size - s->num; 343 } 344 345 /* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG. 346 * Zero returned on success, PL330_FIFO_STALL if there is no enough free 347 * space in MFIFO to store requested amount of data. If push was unsuccessful 348 * no data is stored to MFIFO. 349 */ 350 351 static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) 352 { 353 int i; 354 355 if (s->buf_size - s->num < len) { 356 return PL330_FIFO_STALL; 357 } 358 for (i = 0; i < len; i++) { 359 int push_idx = (s->head + s->num + i) % s->buf_size; 360 s->buf[push_idx] = buf[i]; 361 s->tag[push_idx] = tag; 362 } 363 s->num += len; 364 return PL330_FIFO_OK; 365 } 366 367 /* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each 368 * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch 369 * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was 370 * unsuccessful no data is removed from MFIFO. 371 */ 372 373 static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) 374 { 375 int i; 376 377 if (s->num < len) { 378 return PL330_FIFO_STALL; 379 } 380 for (i = 0; i < len; i++) { 381 if (s->tag[s->head] == tag) { 382 int get_idx = (s->head + i) % s->buf_size; 383 buf[i] = s->buf[get_idx]; 384 } else { /* Tag mismatch - Rollback transaction */ 385 return PL330_FIFO_ERR; 386 } 387 } 388 s->head = (s->head + len) % s->buf_size; 389 s->num -= len; 390 return PL330_FIFO_OK; 391 } 392 393 /* Reset MFIFO. This completely erases all data in it. */ 394 395 static inline void pl330_fifo_reset(PL330Fifo *s) 396 { 397 s->head = 0; 398 s->num = 0; 399 } 400 401 /* Return tag of the first byte stored in MFIFO. If MFIFO is empty 402 * PL330_UNTAGGED is returned. 403 */ 404 405 static inline uint8_t pl330_fifo_tag(PL330Fifo *s) 406 { 407 return (!s->num) ? PL330_UNTAGGED : s->tag[s->head]; 408 } 409 410 /* Returns non-zero if tag TAG is present in fifo or zero otherwise */ 411 412 static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag) 413 { 414 int i, n; 415 416 i = s->head; 417 for (n = 0; n < s->num; n++) { 418 if (s->tag[i] == tag) { 419 return 1; 420 } 421 i = pl330_fifo_inc(s, i); 422 } 423 return 0; 424 } 425 426 /* Remove all entry tagged with TAG from MFIFO */ 427 428 static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag) 429 { 430 int i, t, n; 431 432 t = i = s->head; 433 for (n = 0; n < s->num; n++) { 434 if (s->tag[i] != tag) { 435 s->buf[t] = s->buf[i]; 436 s->tag[t] = s->tag[i]; 437 t = pl330_fifo_inc(s, t); 438 } else { 439 s->num = s->num - 1; 440 } 441 i = pl330_fifo_inc(s, i); 442 } 443 } 444 445 /* Read-Write Queue implementation 446 * 447 * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores). 448 * Each instruction is described by source (for loads) or destination (for 449 * stores) address ADDR, width of data to be loaded/stored LEN, number of 450 * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel 451 * this instruction belongs to. Queue does not store any information about 452 * nature of the instruction: is it load or store. PL330 has different queues 453 * for loads and stores so this is already known at the top level where it 454 * matters. 455 * 456 * Queue works as FIFO for instructions with equivalent tags, but can issue 457 * instructions with different tags in arbitrary order. SEQN field attached to 458 * each instruction helps to achieve this. For each TAG queue contains 459 * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to 460 * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is 461 * followed by SEQN=0. 462 * 463 * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed 464 * in this case. 465 */ 466 467 static void pl330_queue_reset(PL330Queue *s) 468 { 469 int i; 470 471 for (i = 0; i < s->queue_size; i++) { 472 s->queue[i].tag = PL330_UNTAGGED; 473 } 474 } 475 476 /* Initialize queue */ 477 static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent) 478 { 479 s->parent = parent; 480 s->queue = g_new0(PL330QueueEntry, size); 481 s->queue_size = size; 482 } 483 484 /* Returns pointer to an empty slot or NULL if queue is full */ 485 static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s) 486 { 487 int i; 488 489 for (i = 0; i < s->queue_size; i++) { 490 if (s->queue[i].tag == PL330_UNTAGGED) { 491 return &s->queue[i]; 492 } 493 } 494 return NULL; 495 } 496 497 /* Put instruction in queue. 498 * Return value: 499 * - zero - OK 500 * - non-zero - queue is full 501 */ 502 503 static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr, 504 int len, int n, bool inc, bool z, uint8_t tag) 505 { 506 PL330QueueEntry *entry = pl330_queue_find_empty(s); 507 508 if (!entry) { 509 return 1; 510 } 511 entry->tag = tag; 512 entry->addr = addr; 513 entry->len = len; 514 entry->n = n; 515 entry->z = z; 516 entry->inc = inc; 517 entry->seqn = s->parent->hi_seqn[tag]; 518 s->parent->hi_seqn[tag]++; 519 return 0; 520 } 521 522 /* Returns a pointer to queue slot containing instruction which satisfies 523 * following conditions: 524 * - it has valid tag value (not PL330_UNTAGGED) 525 * - if enforce_seq is set it has to be issuable without violating queue 526 * logic (see above) 527 * - if TAG argument is not PL330_UNTAGGED this instruction has tag value 528 * equivalent to the argument TAG value. 529 * If such instruction cannot be found NULL is returned. 530 */ 531 532 static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag, 533 bool enforce_seq) 534 { 535 int i; 536 537 for (i = 0; i < s->queue_size; i++) { 538 if (s->queue[i].tag != PL330_UNTAGGED) { 539 if ((!enforce_seq || 540 s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) && 541 (s->queue[i].tag == tag || tag == PL330_UNTAGGED || 542 s->queue[i].z)) { 543 return &s->queue[i]; 544 } 545 } 546 } 547 return NULL; 548 } 549 550 /* Removes instruction from queue. */ 551 552 static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e) 553 { 554 s->parent->lo_seqn[e->tag]++; 555 e->tag = PL330_UNTAGGED; 556 } 557 558 /* Removes all instructions tagged with TAG from queue. */ 559 560 static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag) 561 { 562 int i; 563 564 for (i = 0; i < s->queue_size; i++) { 565 if (s->queue[i].tag == tag) { 566 s->queue[i].tag = PL330_UNTAGGED; 567 } 568 } 569 } 570 571 /* DMA instruction execution engine */ 572 573 /* Moves DMA channel to the FAULT state and updates it's status. */ 574 575 static inline void pl330_fault(PL330Chan *ch, uint32_t flags) 576 { 577 DB_PRINT("ch: %p, flags: %" PRIx32 "\n", ch, flags); 578 ch->fault_type |= flags; 579 if (ch->state == pl330_chan_fault) { 580 return; 581 } 582 ch->state = pl330_chan_fault; 583 ch->parent->num_faulting++; 584 if (ch->parent->num_faulting == 1) { 585 DB_PRINT("abort interrupt raised\n"); 586 qemu_irq_raise(ch->parent->irq_abort); 587 } 588 } 589 590 /* 591 * For information about instructions see PL330 Technical Reference Manual. 592 * 593 * Arguments: 594 * CH - channel executing the instruction 595 * OPCODE - opcode 596 * ARGS - array of 8-bit arguments 597 * LEN - number of elements in ARGS array 598 */ 599 600 static void pl330_dmaadxh(PL330Chan *ch, uint8_t *args, bool ra, bool neg) 601 { 602 uint32_t im = (args[1] << 8) | args[0]; 603 if (neg) { 604 im |= 0xffffu << 16; 605 } 606 607 if (ch->is_manager) { 608 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 609 return; 610 } 611 if (ra) { 612 ch->dst += im; 613 } else { 614 ch->src += im; 615 } 616 } 617 618 static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 619 { 620 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), false); 621 } 622 623 static void pl330_dmaadnh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 624 { 625 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), true); 626 } 627 628 static void pl330_dmaend(PL330Chan *ch, uint8_t opcode, 629 uint8_t *args, int len) 630 { 631 PL330State *s = ch->parent; 632 633 if (ch->state == pl330_chan_executing && !ch->is_manager) { 634 /* Wait for all transfers to complete */ 635 if (pl330_fifo_has_tag(&s->fifo, ch->tag) || 636 pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL || 637 pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) { 638 639 ch->stall = 1; 640 return; 641 } 642 } 643 DB_PRINT("DMA ending!\n"); 644 pl330_fifo_tagged_remove(&s->fifo, ch->tag); 645 pl330_queue_remove_tagged(&s->read_queue, ch->tag); 646 pl330_queue_remove_tagged(&s->write_queue, ch->tag); 647 ch->state = pl330_chan_stopped; 648 } 649 650 static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode, 651 uint8_t *args, int len) 652 { 653 uint8_t periph_id; 654 655 if (args[0] & 7) { 656 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 657 return; 658 } 659 periph_id = (args[0] >> 3) & 0x1f; 660 if (periph_id >= ch->parent->num_periph_req) { 661 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 662 return; 663 } 664 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 665 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 666 return; 667 } 668 /* Do nothing */ 669 } 670 671 static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 672 { 673 uint8_t chan_id; 674 uint8_t ns; 675 uint32_t pc; 676 PL330Chan *s; 677 678 DB_PRINT("\n"); 679 680 if (!ch->is_manager) { 681 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 682 return; 683 } 684 ns = !!(opcode & 2); 685 chan_id = args[0] & 7; 686 if ((args[0] >> 3)) { 687 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 688 return; 689 } 690 if (chan_id >= ch->parent->num_chnls) { 691 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 692 return; 693 } 694 pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | 695 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); 696 if (ch->parent->chan[chan_id].state != pl330_chan_stopped) { 697 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 698 return; 699 } 700 if (ch->ns && !ns) { 701 pl330_fault(ch, PL330_FAULT_DMAGO_ERR); 702 return; 703 } 704 s = &ch->parent->chan[chan_id]; 705 s->ns = ns; 706 s->pc = pc; 707 s->state = pl330_chan_executing; 708 } 709 710 static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 711 { 712 uint8_t bs = opcode & 3; 713 uint32_t size, num; 714 bool inc; 715 716 if (bs == 2) { 717 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 718 return; 719 } 720 if ((bs == 1 && ch->request_flag == PL330_BURST) || 721 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 722 /* Perform NOP */ 723 return; 724 } 725 if (bs == 1 && ch->request_flag == PL330_SINGLE) { 726 num = 1; 727 } else { 728 num = ((ch->control >> 4) & 0xf) + 1; 729 } 730 size = (uint32_t)1 << ((ch->control >> 1) & 0x7); 731 inc = !!(ch->control & 1); 732 ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src, 733 size, num, inc, 0, ch->tag); 734 if (!ch->stall) { 735 DB_PRINT("channel:%" PRId8 " address:%08" PRIx32 " size:%" PRIx32 736 " num:%" PRId32 " %c\n", 737 ch->tag, ch->src, size, num, inc ? 'Y' : 'N'); 738 ch->src += inc ? size * num - (ch->src & (size - 1)) : 0; 739 } 740 } 741 742 static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 743 { 744 uint8_t periph_id; 745 746 if (args[0] & 7) { 747 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 748 return; 749 } 750 periph_id = (args[0] >> 3) & 0x1f; 751 if (periph_id >= ch->parent->num_periph_req) { 752 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 753 return; 754 } 755 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 756 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 757 return; 758 } 759 pl330_dmald(ch, opcode, args, len); 760 } 761 762 static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 763 { 764 uint8_t lc = (opcode & 2) >> 1; 765 766 ch->lc[lc] = args[0]; 767 } 768 769 static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 770 { 771 if (ch->state == pl330_chan_fault || 772 ch->state == pl330_chan_fault_completing) { 773 /* This is the only way for a channel to leave the faulting state */ 774 ch->fault_type = 0; 775 ch->parent->num_faulting--; 776 if (ch->parent->num_faulting == 0) { 777 DB_PRINT("abort interrupt lowered\n"); 778 qemu_irq_lower(ch->parent->irq_abort); 779 } 780 } 781 ch->state = pl330_chan_killing; 782 pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag); 783 pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag); 784 pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag); 785 ch->state = pl330_chan_stopped; 786 } 787 788 static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode, 789 uint8_t *args, int len) 790 { 791 uint8_t nf = (opcode & 0x10) >> 4; 792 uint8_t bs = opcode & 3; 793 uint8_t lc = (opcode & 4) >> 2; 794 795 if (bs == 2) { 796 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 797 return; 798 } 799 if ((bs == 1 && ch->request_flag == PL330_BURST) || 800 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 801 /* Perform NOP */ 802 return; 803 } 804 if (!nf || ch->lc[lc]) { 805 if (nf) { 806 ch->lc[lc]--; 807 } 808 DB_PRINT("loop reiteration\n"); 809 ch->pc -= args[0]; 810 ch->pc -= len + 1; 811 /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */ 812 } else { 813 DB_PRINT("loop fallthrough\n"); 814 } 815 } 816 817 818 static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 819 { 820 uint8_t rd = args[0] & 7; 821 uint32_t im; 822 823 if ((args[0] >> 3)) { 824 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 825 return; 826 } 827 im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | 828 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); 829 switch (rd) { 830 case 0: 831 ch->src = im; 832 break; 833 case 1: 834 ch->control = im; 835 break; 836 case 2: 837 ch->dst = im; 838 break; 839 default: 840 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 841 return; 842 } 843 } 844 845 static void pl330_dmanop(PL330Chan *ch, uint8_t opcode, 846 uint8_t *args, int len) 847 { 848 /* NOP is NOP. */ 849 } 850 851 static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 852 { 853 if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) { 854 ch->state = pl330_chan_at_barrier; 855 ch->stall = 1; 856 return; 857 } else { 858 ch->state = pl330_chan_executing; 859 } 860 } 861 862 static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 863 { 864 uint8_t ev_id; 865 866 if (args[0] & 7) { 867 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 868 return; 869 } 870 ev_id = (args[0] >> 3) & 0x1f; 871 if (ev_id >= ch->parent->num_events) { 872 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 873 return; 874 } 875 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { 876 pl330_fault(ch, PL330_FAULT_EVENT_ERR); 877 return; 878 } 879 if (ch->parent->inten & (1 << ev_id)) { 880 ch->parent->int_status |= (1 << ev_id); 881 DB_PRINT("event interrupt raised %" PRId8 "\n", ev_id); 882 qemu_irq_raise(ch->parent->irq[ev_id]); 883 } 884 DB_PRINT("event raised %" PRId8 "\n", ev_id); 885 ch->parent->ev_status |= (1 << ev_id); 886 } 887 888 static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 889 { 890 uint8_t bs = opcode & 3; 891 uint32_t size, num; 892 bool inc; 893 894 if (bs == 2) { 895 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 896 return; 897 } 898 if ((bs == 1 && ch->request_flag == PL330_BURST) || 899 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 900 /* Perform NOP */ 901 return; 902 } 903 num = ((ch->control >> 18) & 0xf) + 1; 904 size = (uint32_t)1 << ((ch->control >> 15) & 0x7); 905 inc = !!((ch->control >> 14) & 1); 906 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, 907 size, num, inc, 0, ch->tag); 908 if (!ch->stall) { 909 DB_PRINT("channel:%" PRId8 " address:%08" PRIx32 " size:%" PRIx32 910 " num:%" PRId32 " %c\n", 911 ch->tag, ch->dst, size, num, inc ? 'Y' : 'N'); 912 ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0; 913 } 914 } 915 916 static void pl330_dmastp(PL330Chan *ch, uint8_t opcode, 917 uint8_t *args, int len) 918 { 919 uint8_t periph_id; 920 921 if (args[0] & 7) { 922 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 923 return; 924 } 925 periph_id = (args[0] >> 3) & 0x1f; 926 if (periph_id >= ch->parent->num_periph_req) { 927 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 928 return; 929 } 930 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 931 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 932 return; 933 } 934 pl330_dmast(ch, opcode, args, len); 935 } 936 937 static void pl330_dmastz(PL330Chan *ch, uint8_t opcode, 938 uint8_t *args, int len) 939 { 940 uint32_t size, num; 941 bool inc; 942 943 num = ((ch->control >> 18) & 0xf) + 1; 944 size = (uint32_t)1 << ((ch->control >> 15) & 0x7); 945 inc = !!((ch->control >> 14) & 1); 946 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, 947 size, num, inc, 1, ch->tag); 948 if (inc) { 949 ch->dst += size * num; 950 } 951 } 952 953 static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode, 954 uint8_t *args, int len) 955 { 956 uint8_t ev_id; 957 int i; 958 959 if (args[0] & 5) { 960 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 961 return; 962 } 963 ev_id = (args[0] >> 3) & 0x1f; 964 if (ev_id >= ch->parent->num_events) { 965 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 966 return; 967 } 968 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { 969 pl330_fault(ch, PL330_FAULT_EVENT_ERR); 970 return; 971 } 972 ch->wakeup = ev_id; 973 ch->state = pl330_chan_waiting_event; 974 if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) { 975 ch->state = pl330_chan_executing; 976 /* If anyone else is currently waiting on the same event, let them 977 * clear the ev_status so they pick up event as well 978 */ 979 for (i = 0; i < ch->parent->num_chnls; ++i) { 980 PL330Chan *peer = &ch->parent->chan[i]; 981 if (peer->state == pl330_chan_waiting_event && 982 peer->wakeup == ev_id) { 983 return; 984 } 985 } 986 ch->parent->ev_status &= ~(1 << ev_id); 987 DB_PRINT("event lowered %" PRIx8 "\n", ev_id); 988 } else { 989 ch->stall = 1; 990 } 991 } 992 993 static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode, 994 uint8_t *args, int len) 995 { 996 uint8_t bs = opcode & 3; 997 uint8_t periph_id; 998 999 if (args[0] & 7) { 1000 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1001 return; 1002 } 1003 periph_id = (args[0] >> 3) & 0x1f; 1004 if (periph_id >= ch->parent->num_periph_req) { 1005 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1006 return; 1007 } 1008 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 1009 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 1010 return; 1011 } 1012 switch (bs) { 1013 case 0: /* S */ 1014 ch->request_flag = PL330_SINGLE; 1015 ch->wfp_sbp = 0; 1016 break; 1017 case 1: /* P */ 1018 ch->request_flag = PL330_BURST; 1019 ch->wfp_sbp = 2; 1020 break; 1021 case 2: /* B */ 1022 ch->request_flag = PL330_BURST; 1023 ch->wfp_sbp = 1; 1024 break; 1025 default: 1026 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1027 return; 1028 } 1029 1030 if (ch->parent->periph_busy[periph_id]) { 1031 ch->state = pl330_chan_waiting_periph; 1032 ch->stall = 1; 1033 } else if (ch->state == pl330_chan_waiting_periph) { 1034 ch->state = pl330_chan_executing; 1035 } 1036 } 1037 1038 static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode, 1039 uint8_t *args, int len) 1040 { 1041 if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) { 1042 ch->state = pl330_chan_at_barrier; 1043 ch->stall = 1; 1044 return; 1045 } else { 1046 ch->state = pl330_chan_executing; 1047 } 1048 } 1049 1050 /* NULL terminated array of the instruction descriptions. */ 1051 static const PL330InsnDesc insn_desc[] = { 1052 { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, }, 1053 { .opcode = 0x5c, .opmask = 0xFD, .size = 3, .exec = pl330_dmaadnh, }, 1054 { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, }, 1055 { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, }, 1056 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, 1057 { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, }, 1058 { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, }, 1059 { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, }, 1060 /* dmastp must be before dmalpend in this list, because their maps 1061 * are overlapping 1062 */ 1063 { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, }, 1064 { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, }, 1065 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, 1066 { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, }, 1067 { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, }, 1068 { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, }, 1069 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, 1070 { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, }, 1071 { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, }, 1072 { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, }, 1073 { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, }, 1074 { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, }, 1075 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } 1076 }; 1077 1078 /* Instructions which can be issued via debug registers. */ 1079 static const PL330InsnDesc debug_insn_desc[] = { 1080 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, 1081 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, 1082 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, 1083 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } 1084 }; 1085 1086 static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch) 1087 { 1088 uint8_t opcode; 1089 int i; 1090 1091 dma_memory_read(&address_space_memory, ch->pc, &opcode, 1); 1092 for (i = 0; insn_desc[i].size; i++) { 1093 if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) { 1094 return &insn_desc[i]; 1095 } 1096 } 1097 return NULL; 1098 } 1099 1100 static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn) 1101 { 1102 uint8_t buf[PL330_INSN_MAXSIZE]; 1103 1104 assert(insn->size <= PL330_INSN_MAXSIZE); 1105 dma_memory_read(&address_space_memory, ch->pc, buf, insn->size); 1106 insn->exec(ch, buf[0], &buf[1], insn->size - 1); 1107 } 1108 1109 static inline void pl330_update_pc(PL330Chan *ch, 1110 const PL330InsnDesc *insn) 1111 { 1112 ch->pc += insn->size; 1113 } 1114 1115 /* Try to execute current instruction in channel CH. Number of executed 1116 instructions is returned (0 or 1). */ 1117 static int pl330_chan_exec(PL330Chan *ch) 1118 { 1119 const PL330InsnDesc *insn; 1120 1121 if (ch->state != pl330_chan_executing && 1122 ch->state != pl330_chan_waiting_periph && 1123 ch->state != pl330_chan_at_barrier && 1124 ch->state != pl330_chan_waiting_event) { 1125 return 0; 1126 } 1127 ch->stall = 0; 1128 insn = pl330_fetch_insn(ch); 1129 if (!insn) { 1130 DB_PRINT("pl330 undefined instruction\n"); 1131 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 1132 return 0; 1133 } 1134 pl330_exec_insn(ch, insn); 1135 if (!ch->stall) { 1136 pl330_update_pc(ch, insn); 1137 ch->watchdog_timer = 0; 1138 return 1; 1139 /* WDT only active in exec state */ 1140 } else if (ch->state == pl330_chan_executing) { 1141 ch->watchdog_timer++; 1142 if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) { 1143 pl330_fault(ch, PL330_FAULT_LOCKUP_ERR); 1144 } 1145 } 1146 return 0; 1147 } 1148 1149 /* Try to execute 1 instruction in each channel, one instruction from read 1150 queue and one instruction from write queue. Number of successfully executed 1151 instructions is returned. */ 1152 static int pl330_exec_cycle(PL330Chan *channel) 1153 { 1154 PL330State *s = channel->parent; 1155 PL330QueueEntry *q; 1156 int i; 1157 int num_exec = 0; 1158 int fifo_res = 0; 1159 uint8_t buf[PL330_MAX_BURST_LEN]; 1160 1161 /* Execute one instruction in each channel */ 1162 num_exec += pl330_chan_exec(channel); 1163 1164 /* Execute one instruction from read queue */ 1165 q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true); 1166 if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) { 1167 int len = q->len - (q->addr & (q->len - 1)); 1168 1169 dma_memory_read(&address_space_memory, q->addr, buf, len); 1170 if (PL330_ERR_DEBUG > 1) { 1171 DB_PRINT("PL330 read from memory @%08" PRIx32 " (size = %08x):\n", 1172 q->addr, len); 1173 qemu_hexdump((char *)buf, stderr, "", len); 1174 } 1175 fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag); 1176 if (fifo_res == PL330_FIFO_OK) { 1177 if (q->inc) { 1178 q->addr += len; 1179 } 1180 q->n--; 1181 if (!q->n) { 1182 pl330_queue_remove_insn(&s->read_queue, q); 1183 } 1184 num_exec++; 1185 } 1186 } 1187 1188 /* Execute one instruction from write queue. */ 1189 q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true); 1190 if (q != NULL) { 1191 int len = q->len - (q->addr & (q->len - 1)); 1192 1193 if (q->z) { 1194 for (i = 0; i < len; i++) { 1195 buf[i] = 0; 1196 } 1197 } else { 1198 fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag); 1199 } 1200 if (fifo_res == PL330_FIFO_OK || q->z) { 1201 dma_memory_write(&address_space_memory, q->addr, buf, len); 1202 if (PL330_ERR_DEBUG > 1) { 1203 DB_PRINT("PL330 read from memory @%08" PRIx32 1204 " (size = %08x):\n", q->addr, len); 1205 qemu_hexdump((char *)buf, stderr, "", len); 1206 } 1207 if (q->inc) { 1208 q->addr += len; 1209 } 1210 num_exec++; 1211 } else if (fifo_res == PL330_FIFO_STALL) { 1212 pl330_fault(&channel->parent->chan[q->tag], 1213 PL330_FAULT_FIFOEMPTY_ERR); 1214 } 1215 q->n--; 1216 if (!q->n) { 1217 pl330_queue_remove_insn(&s->write_queue, q); 1218 } 1219 } 1220 1221 return num_exec; 1222 } 1223 1224 static int pl330_exec_channel(PL330Chan *channel) 1225 { 1226 int insr_exec = 0; 1227 1228 /* TODO: Is it all right to execute everything or should we do per-cycle 1229 simulation? */ 1230 while (pl330_exec_cycle(channel)) { 1231 insr_exec++; 1232 } 1233 1234 /* Detect deadlock */ 1235 if (channel->state == pl330_chan_executing) { 1236 pl330_fault(channel, PL330_FAULT_LOCKUP_ERR); 1237 } 1238 /* Situation when one of the queues has deadlocked but all channels 1239 * have finished their programs should be impossible. 1240 */ 1241 1242 return insr_exec; 1243 } 1244 1245 static inline void pl330_exec(PL330State *s) 1246 { 1247 DB_PRINT("\n"); 1248 int i, insr_exec; 1249 do { 1250 insr_exec = pl330_exec_channel(&s->manager); 1251 1252 for (i = 0; i < s->num_chnls; i++) { 1253 insr_exec += pl330_exec_channel(&s->chan[i]); 1254 } 1255 } while (insr_exec); 1256 } 1257 1258 static void pl330_exec_cycle_timer(void *opaque) 1259 { 1260 PL330State *s = (PL330State *)opaque; 1261 pl330_exec(s); 1262 } 1263 1264 /* Stop or restore dma operations */ 1265 1266 static void pl330_dma_stop_irq(void *opaque, int irq, int level) 1267 { 1268 PL330State *s = (PL330State *)opaque; 1269 1270 if (s->periph_busy[irq] != level) { 1271 s->periph_busy[irq] = level; 1272 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 1273 } 1274 } 1275 1276 static void pl330_debug_exec(PL330State *s) 1277 { 1278 uint8_t args[5]; 1279 uint8_t opcode; 1280 uint8_t chan_id; 1281 int i; 1282 PL330Chan *ch; 1283 const PL330InsnDesc *insn; 1284 1285 s->debug_status = 1; 1286 chan_id = (s->dbg[0] >> 8) & 0x07; 1287 opcode = (s->dbg[0] >> 16) & 0xff; 1288 args[0] = (s->dbg[0] >> 24) & 0xff; 1289 args[1] = (s->dbg[1] >> 0) & 0xff; 1290 args[2] = (s->dbg[1] >> 8) & 0xff; 1291 args[3] = (s->dbg[1] >> 16) & 0xff; 1292 args[4] = (s->dbg[1] >> 24) & 0xff; 1293 DB_PRINT("chan id: %" PRIx8 "\n", chan_id); 1294 if (s->dbg[0] & 1) { 1295 ch = &s->chan[chan_id]; 1296 } else { 1297 ch = &s->manager; 1298 } 1299 insn = NULL; 1300 for (i = 0; debug_insn_desc[i].size; i++) { 1301 if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) { 1302 insn = &debug_insn_desc[i]; 1303 } 1304 } 1305 if (!insn) { 1306 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR); 1307 return ; 1308 } 1309 ch->stall = 0; 1310 insn->exec(ch, opcode, args, insn->size - 1); 1311 if (ch->fault_type) { 1312 ch->fault_type |= PL330_FAULT_DBG_INSTR; 1313 } 1314 if (ch->stall) { 1315 qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not " 1316 "implemented\n"); 1317 } 1318 s->debug_status = 0; 1319 } 1320 1321 /* IOMEM mapped registers */ 1322 1323 static void pl330_iomem_write(void *opaque, hwaddr offset, 1324 uint64_t value, unsigned size) 1325 { 1326 PL330State *s = (PL330State *) opaque; 1327 int i; 1328 1329 DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)value); 1330 1331 switch (offset) { 1332 case PL330_REG_INTEN: 1333 s->inten = value; 1334 break; 1335 case PL330_REG_INTCLR: 1336 for (i = 0; i < s->num_events; i++) { 1337 if (s->int_status & s->inten & value & (1 << i)) { 1338 DB_PRINT("event interrupt lowered %d\n", i); 1339 qemu_irq_lower(s->irq[i]); 1340 } 1341 } 1342 s->ev_status &= ~(value & s->inten); 1343 s->int_status &= ~(value & s->inten); 1344 break; 1345 case PL330_REG_DBGCMD: 1346 if ((value & 3) == 0) { 1347 pl330_debug_exec(s); 1348 pl330_exec(s); 1349 } else { 1350 qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u " 1351 "for offset " TARGET_FMT_plx "\n", (unsigned)value, 1352 offset); 1353 } 1354 break; 1355 case PL330_REG_DBGINST0: 1356 DB_PRINT("s->dbg[0] = %08x\n", (unsigned)value); 1357 s->dbg[0] = value; 1358 break; 1359 case PL330_REG_DBGINST1: 1360 DB_PRINT("s->dbg[1] = %08x\n", (unsigned)value); 1361 s->dbg[1] = value; 1362 break; 1363 default: 1364 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx 1365 "\n", offset); 1366 break; 1367 } 1368 } 1369 1370 static inline uint32_t pl330_iomem_read_imp(void *opaque, 1371 hwaddr offset) 1372 { 1373 PL330State *s = (PL330State *)opaque; 1374 int chan_id; 1375 int i; 1376 uint32_t res; 1377 1378 if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) { 1379 return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2]; 1380 } 1381 if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) { 1382 return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2]; 1383 } 1384 if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) { 1385 offset -= PL330_REG_CHANCTRL; 1386 chan_id = offset >> 5; 1387 if (chan_id >= s->num_chnls) { 1388 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1389 TARGET_FMT_plx "\n", offset); 1390 return 0; 1391 } 1392 switch (offset & 0x1f) { 1393 case 0x00: 1394 return s->chan[chan_id].src; 1395 case 0x04: 1396 return s->chan[chan_id].dst; 1397 case 0x08: 1398 return s->chan[chan_id].control; 1399 case 0x0C: 1400 return s->chan[chan_id].lc[0]; 1401 case 0x10: 1402 return s->chan[chan_id].lc[1]; 1403 default: 1404 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1405 TARGET_FMT_plx "\n", offset); 1406 return 0; 1407 } 1408 } 1409 if (offset >= PL330_REG_CSR_BASE && offset < 0x400) { 1410 offset -= PL330_REG_CSR_BASE; 1411 chan_id = offset >> 3; 1412 if (chan_id >= s->num_chnls) { 1413 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1414 TARGET_FMT_plx "\n", offset); 1415 return 0; 1416 } 1417 switch ((offset >> 2) & 1) { 1418 case 0x0: 1419 res = (s->chan[chan_id].ns << 21) | 1420 (s->chan[chan_id].wakeup << 4) | 1421 (s->chan[chan_id].state) | 1422 (s->chan[chan_id].wfp_sbp << 14); 1423 return res; 1424 case 0x1: 1425 return s->chan[chan_id].pc; 1426 default: 1427 qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n"); 1428 return 0; 1429 } 1430 } 1431 if (offset >= PL330_REG_FTR_BASE && offset < 0x100) { 1432 offset -= PL330_REG_FTR_BASE; 1433 chan_id = offset >> 2; 1434 if (chan_id >= s->num_chnls) { 1435 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1436 TARGET_FMT_plx "\n", offset); 1437 return 0; 1438 } 1439 return s->chan[chan_id].fault_type; 1440 } 1441 switch (offset) { 1442 case PL330_REG_DSR: 1443 return (s->manager.ns << 9) | (s->manager.wakeup << 4) | 1444 (s->manager.state & 0xf); 1445 case PL330_REG_DPC: 1446 return s->manager.pc; 1447 case PL330_REG_INTEN: 1448 return s->inten; 1449 case PL330_REG_INT_EVENT_RIS: 1450 return s->ev_status; 1451 case PL330_REG_INTMIS: 1452 return s->int_status; 1453 case PL330_REG_INTCLR: 1454 /* Documentation says that we can't read this register 1455 * but linux kernel does it 1456 */ 1457 return 0; 1458 case PL330_REG_FSRD: 1459 return s->manager.state ? 1 : 0; 1460 case PL330_REG_FSRC: 1461 res = 0; 1462 for (i = 0; i < s->num_chnls; i++) { 1463 if (s->chan[i].state == pl330_chan_fault || 1464 s->chan[i].state == pl330_chan_fault_completing) { 1465 res |= 1 << i; 1466 } 1467 } 1468 return res; 1469 case PL330_REG_FTRD: 1470 return s->manager.fault_type; 1471 case PL330_REG_DBGSTATUS: 1472 return s->debug_status; 1473 default: 1474 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1475 TARGET_FMT_plx "\n", offset); 1476 } 1477 return 0; 1478 } 1479 1480 static uint64_t pl330_iomem_read(void *opaque, hwaddr offset, 1481 unsigned size) 1482 { 1483 uint32_t ret = pl330_iomem_read_imp(opaque, offset); 1484 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset, ret); 1485 return ret; 1486 } 1487 1488 static const MemoryRegionOps pl330_ops = { 1489 .read = pl330_iomem_read, 1490 .write = pl330_iomem_write, 1491 .endianness = DEVICE_NATIVE_ENDIAN, 1492 .impl = { 1493 .min_access_size = 4, 1494 .max_access_size = 4, 1495 } 1496 }; 1497 1498 /* Controller logic and initialization */ 1499 1500 static void pl330_chan_reset(PL330Chan *ch) 1501 { 1502 ch->src = 0; 1503 ch->dst = 0; 1504 ch->pc = 0; 1505 ch->state = pl330_chan_stopped; 1506 ch->watchdog_timer = 0; 1507 ch->stall = 0; 1508 ch->control = 0; 1509 ch->status = 0; 1510 ch->fault_type = 0; 1511 } 1512 1513 static void pl330_reset(DeviceState *d) 1514 { 1515 int i; 1516 PL330State *s = PL330(d); 1517 1518 s->inten = 0; 1519 s->int_status = 0; 1520 s->ev_status = 0; 1521 s->debug_status = 0; 1522 s->num_faulting = 0; 1523 s->manager.ns = s->mgr_ns_at_rst; 1524 pl330_fifo_reset(&s->fifo); 1525 pl330_queue_reset(&s->read_queue); 1526 pl330_queue_reset(&s->write_queue); 1527 1528 for (i = 0; i < s->num_chnls; i++) { 1529 pl330_chan_reset(&s->chan[i]); 1530 } 1531 for (i = 0; i < s->num_periph_req; i++) { 1532 s->periph_busy[i] = 0; 1533 } 1534 1535 timer_del(s->timer); 1536 } 1537 1538 static void pl330_realize(DeviceState *dev, Error **errp) 1539 { 1540 int i; 1541 PL330State *s = PL330(dev); 1542 1543 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort); 1544 memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s, 1545 "dma", PL330_IOMEM_SIZE); 1546 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1547 1548 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s); 1549 1550 s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) | 1551 (s->num_periph_req > 0 ? 1 : 0) | 1552 ((s->num_chnls - 1) & 0x7) << 4 | 1553 ((s->num_periph_req - 1) & 0x1f) << 12 | 1554 ((s->num_events - 1) & 0x1f) << 17; 1555 1556 switch (s->i_cache_len) { 1557 case (4): 1558 s->cfg[1] |= 2; 1559 break; 1560 case (8): 1561 s->cfg[1] |= 3; 1562 break; 1563 case (16): 1564 s->cfg[1] |= 4; 1565 break; 1566 case (32): 1567 s->cfg[1] |= 5; 1568 break; 1569 default: 1570 error_setg(errp, "Bad value for i-cache_len property: %" PRIx8, 1571 s->i_cache_len); 1572 return; 1573 } 1574 s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4; 1575 1576 s->chan = g_new0(PL330Chan, s->num_chnls); 1577 s->hi_seqn = g_new0(uint8_t, s->num_chnls); 1578 s->lo_seqn = g_new0(uint8_t, s->num_chnls); 1579 for (i = 0; i < s->num_chnls; i++) { 1580 s->chan[i].parent = s; 1581 s->chan[i].tag = (uint8_t)i; 1582 } 1583 s->manager.parent = s; 1584 s->manager.tag = s->num_chnls; 1585 s->manager.is_manager = true; 1586 1587 s->irq = g_new0(qemu_irq, s->num_events); 1588 for (i = 0; i < s->num_events; i++) { 1589 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1590 } 1591 1592 qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM); 1593 1594 switch (s->data_width) { 1595 case (32): 1596 s->cfg[CFG_CRD] |= 0x2; 1597 break; 1598 case (64): 1599 s->cfg[CFG_CRD] |= 0x3; 1600 break; 1601 case (128): 1602 s->cfg[CFG_CRD] |= 0x4; 1603 break; 1604 default: 1605 error_setg(errp, "Bad value for data_width property: %" PRIx8, 1606 s->data_width); 1607 return; 1608 } 1609 1610 s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 | 1611 ((s->wr_q_dep - 1) & 0xf) << 8 | 1612 ((s->rd_cap - 1) & 0x7) << 12 | 1613 ((s->rd_q_dep - 1) & 0xf) << 16 | 1614 ((s->data_buffer_dep - 1) & 0x1ff) << 20; 1615 1616 pl330_queue_init(&s->read_queue, s->rd_q_dep, s); 1617 pl330_queue_init(&s->write_queue, s->wr_q_dep, s); 1618 pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep); 1619 } 1620 1621 static Property pl330_properties[] = { 1622 /* CR0 */ 1623 DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8), 1624 DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4), 1625 DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16), 1626 DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0), 1627 /* CR1 */ 1628 DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4), 1629 DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8), 1630 /* CR2-4 */ 1631 DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0), 1632 DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0), 1633 DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0), 1634 /* CRD */ 1635 DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64), 1636 DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8), 1637 DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16), 1638 DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8), 1639 DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16), 1640 DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256), 1641 1642 DEFINE_PROP_END_OF_LIST(), 1643 }; 1644 1645 static void pl330_class_init(ObjectClass *klass, void *data) 1646 { 1647 DeviceClass *dc = DEVICE_CLASS(klass); 1648 1649 dc->realize = pl330_realize; 1650 dc->reset = pl330_reset; 1651 dc->props = pl330_properties; 1652 dc->vmsd = &vmstate_pl330; 1653 } 1654 1655 static const TypeInfo pl330_type_info = { 1656 .name = TYPE_PL330, 1657 .parent = TYPE_SYS_BUS_DEVICE, 1658 .instance_size = sizeof(PL330State), 1659 .class_init = pl330_class_init, 1660 }; 1661 1662 static void pl330_register_types(void) 1663 { 1664 type_register_static(&pl330_type_info); 1665 } 1666 1667 type_init(pl330_register_types) 1668