1 /* 2 * ARM PrimeCell PL330 DMA Controller 3 * 4 * Copyright (c) 2009 Samsung Electronics. 5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru> 6 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 7 * Copyright (c) 2012 PetaLogix Pty Ltd. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; version 2 or later. 12 * 13 * You should have received a copy of the GNU General Public License along 14 * with this program; if not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "hw/sysbus.h" 20 #include "qapi/error.h" 21 #include "qemu/timer.h" 22 #include "sysemu/dma.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 26 #ifndef PL330_ERR_DEBUG 27 #define PL330_ERR_DEBUG 0 28 #endif 29 30 #define DB_PRINT_L(lvl, fmt, args...) do {\ 31 if (PL330_ERR_DEBUG >= lvl) {\ 32 fprintf(stderr, "PL330: %s:" fmt, __func__, ## args);\ 33 } \ 34 } while (0) 35 36 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 37 38 #define PL330_PERIPH_NUM 32 39 #define PL330_MAX_BURST_LEN 128 40 #define PL330_INSN_MAXSIZE 6 41 42 #define PL330_FIFO_OK 0 43 #define PL330_FIFO_STALL 1 44 #define PL330_FIFO_ERR (-1) 45 46 #define PL330_FAULT_UNDEF_INSTR (1 << 0) 47 #define PL330_FAULT_OPERAND_INVALID (1 << 1) 48 #define PL330_FAULT_DMAGO_ERR (1 << 4) 49 #define PL330_FAULT_EVENT_ERR (1 << 5) 50 #define PL330_FAULT_CH_PERIPH_ERR (1 << 6) 51 #define PL330_FAULT_CH_RDWR_ERR (1 << 7) 52 #define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12) 53 #define PL330_FAULT_FIFOEMPTY_ERR (1 << 13) 54 #define PL330_FAULT_INSTR_FETCH_ERR (1 << 16) 55 #define PL330_FAULT_DATA_WRITE_ERR (1 << 17) 56 #define PL330_FAULT_DATA_READ_ERR (1 << 18) 57 #define PL330_FAULT_DBG_INSTR (1 << 30) 58 #define PL330_FAULT_LOCKUP_ERR (1 << 31) 59 60 #define PL330_UNTAGGED 0xff 61 62 #define PL330_SINGLE 0x0 63 #define PL330_BURST 0x1 64 65 #define PL330_WATCHDOG_LIMIT 1024 66 67 /* IOMEM mapped registers */ 68 #define PL330_REG_DSR 0x000 69 #define PL330_REG_DPC 0x004 70 #define PL330_REG_INTEN 0x020 71 #define PL330_REG_INT_EVENT_RIS 0x024 72 #define PL330_REG_INTMIS 0x028 73 #define PL330_REG_INTCLR 0x02C 74 #define PL330_REG_FSRD 0x030 75 #define PL330_REG_FSRC 0x034 76 #define PL330_REG_FTRD 0x038 77 #define PL330_REG_FTR_BASE 0x040 78 #define PL330_REG_CSR_BASE 0x100 79 #define PL330_REG_CPC_BASE 0x104 80 #define PL330_REG_CHANCTRL 0x400 81 #define PL330_REG_DBGSTATUS 0xD00 82 #define PL330_REG_DBGCMD 0xD04 83 #define PL330_REG_DBGINST0 0xD08 84 #define PL330_REG_DBGINST1 0xD0C 85 #define PL330_REG_CR0_BASE 0xE00 86 #define PL330_REG_PERIPH_ID 0xFE0 87 88 #define PL330_IOMEM_SIZE 0x1000 89 90 #define CFG_BOOT_ADDR 2 91 #define CFG_INS 3 92 #define CFG_PNS 4 93 #define CFG_CRD 5 94 95 static const uint32_t pl330_id[] = { 96 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1 97 }; 98 99 /* DMA channel states as they are described in PL330 Technical Reference Manual 100 * Most of them will not be used in emulation. 101 */ 102 typedef enum { 103 pl330_chan_stopped = 0, 104 pl330_chan_executing = 1, 105 pl330_chan_cache_miss = 2, 106 pl330_chan_updating_pc = 3, 107 pl330_chan_waiting_event = 4, 108 pl330_chan_at_barrier = 5, 109 pl330_chan_queue_busy = 6, 110 pl330_chan_waiting_periph = 7, 111 pl330_chan_killing = 8, 112 pl330_chan_completing = 9, 113 pl330_chan_fault_completing = 14, 114 pl330_chan_fault = 15, 115 } PL330ChanState; 116 117 typedef struct PL330State PL330State; 118 119 typedef struct PL330Chan { 120 uint32_t src; 121 uint32_t dst; 122 uint32_t pc; 123 uint32_t control; 124 uint32_t status; 125 uint32_t lc[2]; 126 uint32_t fault_type; 127 uint32_t watchdog_timer; 128 129 bool ns; 130 uint8_t request_flag; 131 uint8_t wakeup; 132 uint8_t wfp_sbp; 133 134 uint8_t state; 135 uint8_t stall; 136 137 bool is_manager; 138 PL330State *parent; 139 uint8_t tag; 140 } PL330Chan; 141 142 static const VMStateDescription vmstate_pl330_chan = { 143 .name = "pl330_chan", 144 .version_id = 1, 145 .minimum_version_id = 1, 146 .fields = (VMStateField[]) { 147 VMSTATE_UINT32(src, PL330Chan), 148 VMSTATE_UINT32(dst, PL330Chan), 149 VMSTATE_UINT32(pc, PL330Chan), 150 VMSTATE_UINT32(control, PL330Chan), 151 VMSTATE_UINT32(status, PL330Chan), 152 VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2), 153 VMSTATE_UINT32(fault_type, PL330Chan), 154 VMSTATE_UINT32(watchdog_timer, PL330Chan), 155 VMSTATE_BOOL(ns, PL330Chan), 156 VMSTATE_UINT8(request_flag, PL330Chan), 157 VMSTATE_UINT8(wakeup, PL330Chan), 158 VMSTATE_UINT8(wfp_sbp, PL330Chan), 159 VMSTATE_UINT8(state, PL330Chan), 160 VMSTATE_UINT8(stall, PL330Chan), 161 VMSTATE_END_OF_LIST() 162 } 163 }; 164 165 typedef struct PL330Fifo { 166 uint8_t *buf; 167 uint8_t *tag; 168 uint32_t head; 169 uint32_t num; 170 uint32_t buf_size; 171 } PL330Fifo; 172 173 static const VMStateDescription vmstate_pl330_fifo = { 174 .name = "pl330_chan", 175 .version_id = 1, 176 .minimum_version_id = 1, 177 .fields = (VMStateField[]) { 178 VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, buf_size), 179 VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, buf_size), 180 VMSTATE_UINT32(head, PL330Fifo), 181 VMSTATE_UINT32(num, PL330Fifo), 182 VMSTATE_UINT32(buf_size, PL330Fifo), 183 VMSTATE_END_OF_LIST() 184 } 185 }; 186 187 typedef struct PL330QueueEntry { 188 uint32_t addr; 189 uint32_t len; 190 uint8_t n; 191 bool inc; 192 bool z; 193 uint8_t tag; 194 uint8_t seqn; 195 } PL330QueueEntry; 196 197 static const VMStateDescription vmstate_pl330_queue_entry = { 198 .name = "pl330_queue_entry", 199 .version_id = 1, 200 .minimum_version_id = 1, 201 .fields = (VMStateField[]) { 202 VMSTATE_UINT32(addr, PL330QueueEntry), 203 VMSTATE_UINT32(len, PL330QueueEntry), 204 VMSTATE_UINT8(n, PL330QueueEntry), 205 VMSTATE_BOOL(inc, PL330QueueEntry), 206 VMSTATE_BOOL(z, PL330QueueEntry), 207 VMSTATE_UINT8(tag, PL330QueueEntry), 208 VMSTATE_UINT8(seqn, PL330QueueEntry), 209 VMSTATE_END_OF_LIST() 210 } 211 }; 212 213 typedef struct PL330Queue { 214 PL330State *parent; 215 PL330QueueEntry *queue; 216 uint32_t queue_size; 217 } PL330Queue; 218 219 static const VMStateDescription vmstate_pl330_queue = { 220 .name = "pl330_queue", 221 .version_id = 2, 222 .minimum_version_id = 2, 223 .fields = (VMStateField[]) { 224 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size, 225 vmstate_pl330_queue_entry, 226 PL330QueueEntry), 227 VMSTATE_END_OF_LIST() 228 } 229 }; 230 231 struct PL330State { 232 SysBusDevice parent_obj; 233 234 MemoryRegion iomem; 235 qemu_irq irq_abort; 236 qemu_irq *irq; 237 238 /* Config registers. cfg[5] = CfgDn. */ 239 uint32_t cfg[6]; 240 #define EVENT_SEC_STATE 3 241 #define PERIPH_SEC_STATE 4 242 /* cfg 0 bits and pieces */ 243 uint32_t num_chnls; 244 uint8_t num_periph_req; 245 uint8_t num_events; 246 uint8_t mgr_ns_at_rst; 247 /* cfg 1 bits and pieces */ 248 uint8_t i_cache_len; 249 uint8_t num_i_cache_lines; 250 /* CRD bits and pieces */ 251 uint8_t data_width; 252 uint8_t wr_cap; 253 uint8_t wr_q_dep; 254 uint8_t rd_cap; 255 uint8_t rd_q_dep; 256 uint16_t data_buffer_dep; 257 258 PL330Chan manager; 259 PL330Chan *chan; 260 PL330Fifo fifo; 261 PL330Queue read_queue; 262 PL330Queue write_queue; 263 uint8_t *lo_seqn; 264 uint8_t *hi_seqn; 265 QEMUTimer *timer; /* is used for restore dma. */ 266 267 uint32_t inten; 268 uint32_t int_status; 269 uint32_t ev_status; 270 uint32_t dbg[2]; 271 uint8_t debug_status; 272 uint8_t num_faulting; 273 uint8_t periph_busy[PL330_PERIPH_NUM]; 274 275 }; 276 277 #define TYPE_PL330 "pl330" 278 #define PL330(obj) OBJECT_CHECK(PL330State, (obj), TYPE_PL330) 279 280 static const VMStateDescription vmstate_pl330 = { 281 .name = "pl330", 282 .version_id = 2, 283 .minimum_version_id = 2, 284 .fields = (VMStateField[]) { 285 VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan), 286 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls, 287 vmstate_pl330_chan, PL330Chan), 288 VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls), 289 VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls), 290 VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo), 291 VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue, 292 PL330Queue), 293 VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue, 294 PL330Queue), 295 VMSTATE_TIMER_PTR(timer, PL330State), 296 VMSTATE_UINT32(inten, PL330State), 297 VMSTATE_UINT32(int_status, PL330State), 298 VMSTATE_UINT32(ev_status, PL330State), 299 VMSTATE_UINT32_ARRAY(dbg, PL330State, 2), 300 VMSTATE_UINT8(debug_status, PL330State), 301 VMSTATE_UINT8(num_faulting, PL330State), 302 VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM), 303 VMSTATE_END_OF_LIST() 304 } 305 }; 306 307 typedef struct PL330InsnDesc { 308 /* OPCODE of the instruction */ 309 uint8_t opcode; 310 /* Mask so we can select several sibling instructions, such as 311 DMALD, DMALDS and DMALDB */ 312 uint8_t opmask; 313 /* Size of instruction in bytes */ 314 uint8_t size; 315 /* Interpreter */ 316 void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len); 317 } PL330InsnDesc; 318 319 320 /* MFIFO Implementation 321 * 322 * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are 323 * stored in this buffer. Data is stored in BUF field, tags - in the 324 * corresponding array elements of TAG field. 325 */ 326 327 /* Initialize queue. */ 328 329 static void pl330_fifo_init(PL330Fifo *s, uint32_t size) 330 { 331 s->buf = g_malloc0(size); 332 s->tag = g_malloc0(size); 333 s->buf_size = size; 334 } 335 336 /* Cyclic increment */ 337 338 static inline int pl330_fifo_inc(PL330Fifo *s, int x) 339 { 340 return (x + 1) % s->buf_size; 341 } 342 343 /* Number of empty bytes in MFIFO */ 344 345 static inline int pl330_fifo_num_free(PL330Fifo *s) 346 { 347 return s->buf_size - s->num; 348 } 349 350 /* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG. 351 * Zero returned on success, PL330_FIFO_STALL if there is no enough free 352 * space in MFIFO to store requested amount of data. If push was unsuccessful 353 * no data is stored to MFIFO. 354 */ 355 356 static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) 357 { 358 int i; 359 360 if (s->buf_size - s->num < len) { 361 return PL330_FIFO_STALL; 362 } 363 for (i = 0; i < len; i++) { 364 int push_idx = (s->head + s->num + i) % s->buf_size; 365 s->buf[push_idx] = buf[i]; 366 s->tag[push_idx] = tag; 367 } 368 s->num += len; 369 return PL330_FIFO_OK; 370 } 371 372 /* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each 373 * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch 374 * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was 375 * unsuccessful no data is removed from MFIFO. 376 */ 377 378 static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) 379 { 380 int i; 381 382 if (s->num < len) { 383 return PL330_FIFO_STALL; 384 } 385 for (i = 0; i < len; i++) { 386 if (s->tag[s->head] == tag) { 387 int get_idx = (s->head + i) % s->buf_size; 388 buf[i] = s->buf[get_idx]; 389 } else { /* Tag mismatch - Rollback transaction */ 390 return PL330_FIFO_ERR; 391 } 392 } 393 s->head = (s->head + len) % s->buf_size; 394 s->num -= len; 395 return PL330_FIFO_OK; 396 } 397 398 /* Reset MFIFO. This completely erases all data in it. */ 399 400 static inline void pl330_fifo_reset(PL330Fifo *s) 401 { 402 s->head = 0; 403 s->num = 0; 404 } 405 406 /* Return tag of the first byte stored in MFIFO. If MFIFO is empty 407 * PL330_UNTAGGED is returned. 408 */ 409 410 static inline uint8_t pl330_fifo_tag(PL330Fifo *s) 411 { 412 return (!s->num) ? PL330_UNTAGGED : s->tag[s->head]; 413 } 414 415 /* Returns non-zero if tag TAG is present in fifo or zero otherwise */ 416 417 static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag) 418 { 419 int i, n; 420 421 i = s->head; 422 for (n = 0; n < s->num; n++) { 423 if (s->tag[i] == tag) { 424 return 1; 425 } 426 i = pl330_fifo_inc(s, i); 427 } 428 return 0; 429 } 430 431 /* Remove all entry tagged with TAG from MFIFO */ 432 433 static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag) 434 { 435 int i, t, n; 436 437 t = i = s->head; 438 for (n = 0; n < s->num; n++) { 439 if (s->tag[i] != tag) { 440 s->buf[t] = s->buf[i]; 441 s->tag[t] = s->tag[i]; 442 t = pl330_fifo_inc(s, t); 443 } else { 444 s->num = s->num - 1; 445 } 446 i = pl330_fifo_inc(s, i); 447 } 448 } 449 450 /* Read-Write Queue implementation 451 * 452 * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores). 453 * Each instruction is described by source (for loads) or destination (for 454 * stores) address ADDR, width of data to be loaded/stored LEN, number of 455 * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel 456 * this instruction belongs to. Queue does not store any information about 457 * nature of the instruction: is it load or store. PL330 has different queues 458 * for loads and stores so this is already known at the top level where it 459 * matters. 460 * 461 * Queue works as FIFO for instructions with equivalent tags, but can issue 462 * instructions with different tags in arbitrary order. SEQN field attached to 463 * each instruction helps to achieve this. For each TAG queue contains 464 * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to 465 * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is 466 * followed by SEQN=0. 467 * 468 * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed 469 * in this case. 470 */ 471 472 static void pl330_queue_reset(PL330Queue *s) 473 { 474 int i; 475 476 for (i = 0; i < s->queue_size; i++) { 477 s->queue[i].tag = PL330_UNTAGGED; 478 } 479 } 480 481 /* Initialize queue */ 482 static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent) 483 { 484 s->parent = parent; 485 s->queue = g_new0(PL330QueueEntry, size); 486 s->queue_size = size; 487 } 488 489 /* Returns pointer to an empty slot or NULL if queue is full */ 490 static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s) 491 { 492 int i; 493 494 for (i = 0; i < s->queue_size; i++) { 495 if (s->queue[i].tag == PL330_UNTAGGED) { 496 return &s->queue[i]; 497 } 498 } 499 return NULL; 500 } 501 502 /* Put instruction in queue. 503 * Return value: 504 * - zero - OK 505 * - non-zero - queue is full 506 */ 507 508 static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr, 509 int len, int n, bool inc, bool z, uint8_t tag) 510 { 511 PL330QueueEntry *entry = pl330_queue_find_empty(s); 512 513 if (!entry) { 514 return 1; 515 } 516 entry->tag = tag; 517 entry->addr = addr; 518 entry->len = len; 519 entry->n = n; 520 entry->z = z; 521 entry->inc = inc; 522 entry->seqn = s->parent->hi_seqn[tag]; 523 s->parent->hi_seqn[tag]++; 524 return 0; 525 } 526 527 /* Returns a pointer to queue slot containing instruction which satisfies 528 * following conditions: 529 * - it has valid tag value (not PL330_UNTAGGED) 530 * - if enforce_seq is set it has to be issuable without violating queue 531 * logic (see above) 532 * - if TAG argument is not PL330_UNTAGGED this instruction has tag value 533 * equivalent to the argument TAG value. 534 * If such instruction cannot be found NULL is returned. 535 */ 536 537 static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag, 538 bool enforce_seq) 539 { 540 int i; 541 542 for (i = 0; i < s->queue_size; i++) { 543 if (s->queue[i].tag != PL330_UNTAGGED) { 544 if ((!enforce_seq || 545 s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) && 546 (s->queue[i].tag == tag || tag == PL330_UNTAGGED || 547 s->queue[i].z)) { 548 return &s->queue[i]; 549 } 550 } 551 } 552 return NULL; 553 } 554 555 /* Removes instruction from queue. */ 556 557 static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e) 558 { 559 s->parent->lo_seqn[e->tag]++; 560 e->tag = PL330_UNTAGGED; 561 } 562 563 /* Removes all instructions tagged with TAG from queue. */ 564 565 static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag) 566 { 567 int i; 568 569 for (i = 0; i < s->queue_size; i++) { 570 if (s->queue[i].tag == tag) { 571 s->queue[i].tag = PL330_UNTAGGED; 572 } 573 } 574 } 575 576 /* DMA instruction execution engine */ 577 578 /* Moves DMA channel to the FAULT state and updates it's status. */ 579 580 static inline void pl330_fault(PL330Chan *ch, uint32_t flags) 581 { 582 DB_PRINT("ch: %p, flags: %" PRIx32 "\n", ch, flags); 583 ch->fault_type |= flags; 584 if (ch->state == pl330_chan_fault) { 585 return; 586 } 587 ch->state = pl330_chan_fault; 588 ch->parent->num_faulting++; 589 if (ch->parent->num_faulting == 1) { 590 DB_PRINT("abort interrupt raised\n"); 591 qemu_irq_raise(ch->parent->irq_abort); 592 } 593 } 594 595 /* 596 * For information about instructions see PL330 Technical Reference Manual. 597 * 598 * Arguments: 599 * CH - channel executing the instruction 600 * OPCODE - opcode 601 * ARGS - array of 8-bit arguments 602 * LEN - number of elements in ARGS array 603 */ 604 605 static void pl330_dmaadxh(PL330Chan *ch, uint8_t *args, bool ra, bool neg) 606 { 607 uint32_t im = (args[1] << 8) | args[0]; 608 if (neg) { 609 im |= 0xffffu << 16; 610 } 611 612 if (ch->is_manager) { 613 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 614 return; 615 } 616 if (ra) { 617 ch->dst += im; 618 } else { 619 ch->src += im; 620 } 621 } 622 623 static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 624 { 625 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), false); 626 } 627 628 static void pl330_dmaadnh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 629 { 630 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), true); 631 } 632 633 static void pl330_dmaend(PL330Chan *ch, uint8_t opcode, 634 uint8_t *args, int len) 635 { 636 PL330State *s = ch->parent; 637 638 if (ch->state == pl330_chan_executing && !ch->is_manager) { 639 /* Wait for all transfers to complete */ 640 if (pl330_fifo_has_tag(&s->fifo, ch->tag) || 641 pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL || 642 pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) { 643 644 ch->stall = 1; 645 return; 646 } 647 } 648 DB_PRINT("DMA ending!\n"); 649 pl330_fifo_tagged_remove(&s->fifo, ch->tag); 650 pl330_queue_remove_tagged(&s->read_queue, ch->tag); 651 pl330_queue_remove_tagged(&s->write_queue, ch->tag); 652 ch->state = pl330_chan_stopped; 653 } 654 655 static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode, 656 uint8_t *args, int len) 657 { 658 uint8_t periph_id; 659 660 if (args[0] & 7) { 661 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 662 return; 663 } 664 periph_id = (args[0] >> 3) & 0x1f; 665 if (periph_id >= ch->parent->num_periph_req) { 666 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 667 return; 668 } 669 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 670 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 671 return; 672 } 673 /* Do nothing */ 674 } 675 676 static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 677 { 678 uint8_t chan_id; 679 uint8_t ns; 680 uint32_t pc; 681 PL330Chan *s; 682 683 DB_PRINT("\n"); 684 685 if (!ch->is_manager) { 686 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 687 return; 688 } 689 ns = !!(opcode & 2); 690 chan_id = args[0] & 7; 691 if ((args[0] >> 3)) { 692 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 693 return; 694 } 695 if (chan_id >= ch->parent->num_chnls) { 696 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 697 return; 698 } 699 pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | 700 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); 701 if (ch->parent->chan[chan_id].state != pl330_chan_stopped) { 702 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 703 return; 704 } 705 if (ch->ns && !ns) { 706 pl330_fault(ch, PL330_FAULT_DMAGO_ERR); 707 return; 708 } 709 s = &ch->parent->chan[chan_id]; 710 s->ns = ns; 711 s->pc = pc; 712 s->state = pl330_chan_executing; 713 } 714 715 static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 716 { 717 uint8_t bs = opcode & 3; 718 uint32_t size, num; 719 bool inc; 720 721 if (bs == 2) { 722 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 723 return; 724 } 725 if ((bs == 1 && ch->request_flag == PL330_BURST) || 726 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 727 /* Perform NOP */ 728 return; 729 } 730 if (bs == 1 && ch->request_flag == PL330_SINGLE) { 731 num = 1; 732 } else { 733 num = ((ch->control >> 4) & 0xf) + 1; 734 } 735 size = (uint32_t)1 << ((ch->control >> 1) & 0x7); 736 inc = !!(ch->control & 1); 737 ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src, 738 size, num, inc, 0, ch->tag); 739 if (!ch->stall) { 740 DB_PRINT("channel:%" PRId8 " address:%08" PRIx32 " size:%" PRIx32 741 " num:%" PRId32 " %c\n", 742 ch->tag, ch->src, size, num, inc ? 'Y' : 'N'); 743 ch->src += inc ? size * num - (ch->src & (size - 1)) : 0; 744 } 745 } 746 747 static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 748 { 749 uint8_t periph_id; 750 751 if (args[0] & 7) { 752 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 753 return; 754 } 755 periph_id = (args[0] >> 3) & 0x1f; 756 if (periph_id >= ch->parent->num_periph_req) { 757 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 758 return; 759 } 760 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 761 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 762 return; 763 } 764 pl330_dmald(ch, opcode, args, len); 765 } 766 767 static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 768 { 769 uint8_t lc = (opcode & 2) >> 1; 770 771 ch->lc[lc] = args[0]; 772 } 773 774 static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 775 { 776 if (ch->state == pl330_chan_fault || 777 ch->state == pl330_chan_fault_completing) { 778 /* This is the only way for a channel to leave the faulting state */ 779 ch->fault_type = 0; 780 ch->parent->num_faulting--; 781 if (ch->parent->num_faulting == 0) { 782 DB_PRINT("abort interrupt lowered\n"); 783 qemu_irq_lower(ch->parent->irq_abort); 784 } 785 } 786 ch->state = pl330_chan_killing; 787 pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag); 788 pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag); 789 pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag); 790 ch->state = pl330_chan_stopped; 791 } 792 793 static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode, 794 uint8_t *args, int len) 795 { 796 uint8_t nf = (opcode & 0x10) >> 4; 797 uint8_t bs = opcode & 3; 798 uint8_t lc = (opcode & 4) >> 2; 799 800 if (bs == 2) { 801 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 802 return; 803 } 804 if ((bs == 1 && ch->request_flag == PL330_BURST) || 805 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 806 /* Perform NOP */ 807 return; 808 } 809 if (!nf || ch->lc[lc]) { 810 if (nf) { 811 ch->lc[lc]--; 812 } 813 DB_PRINT("loop reiteration\n"); 814 ch->pc -= args[0]; 815 ch->pc -= len + 1; 816 /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */ 817 } else { 818 DB_PRINT("loop fallthrough\n"); 819 } 820 } 821 822 823 static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 824 { 825 uint8_t rd = args[0] & 7; 826 uint32_t im; 827 828 if ((args[0] >> 3)) { 829 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 830 return; 831 } 832 im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | 833 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); 834 switch (rd) { 835 case 0: 836 ch->src = im; 837 break; 838 case 1: 839 ch->control = im; 840 break; 841 case 2: 842 ch->dst = im; 843 break; 844 default: 845 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 846 return; 847 } 848 } 849 850 static void pl330_dmanop(PL330Chan *ch, uint8_t opcode, 851 uint8_t *args, int len) 852 { 853 /* NOP is NOP. */ 854 } 855 856 static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 857 { 858 if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) { 859 ch->state = pl330_chan_at_barrier; 860 ch->stall = 1; 861 return; 862 } else { 863 ch->state = pl330_chan_executing; 864 } 865 } 866 867 static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 868 { 869 uint8_t ev_id; 870 871 if (args[0] & 7) { 872 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 873 return; 874 } 875 ev_id = (args[0] >> 3) & 0x1f; 876 if (ev_id >= ch->parent->num_events) { 877 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 878 return; 879 } 880 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { 881 pl330_fault(ch, PL330_FAULT_EVENT_ERR); 882 return; 883 } 884 if (ch->parent->inten & (1 << ev_id)) { 885 ch->parent->int_status |= (1 << ev_id); 886 DB_PRINT("event interrupt raised %" PRId8 "\n", ev_id); 887 qemu_irq_raise(ch->parent->irq[ev_id]); 888 } 889 DB_PRINT("event raised %" PRId8 "\n", ev_id); 890 ch->parent->ev_status |= (1 << ev_id); 891 } 892 893 static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) 894 { 895 uint8_t bs = opcode & 3; 896 uint32_t size, num; 897 bool inc; 898 899 if (bs == 2) { 900 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 901 return; 902 } 903 if ((bs == 1 && ch->request_flag == PL330_BURST) || 904 (bs == 3 && ch->request_flag == PL330_SINGLE)) { 905 /* Perform NOP */ 906 return; 907 } 908 num = ((ch->control >> 18) & 0xf) + 1; 909 size = (uint32_t)1 << ((ch->control >> 15) & 0x7); 910 inc = !!((ch->control >> 14) & 1); 911 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, 912 size, num, inc, 0, ch->tag); 913 if (!ch->stall) { 914 DB_PRINT("channel:%" PRId8 " address:%08" PRIx32 " size:%" PRIx32 915 " num:%" PRId32 " %c\n", 916 ch->tag, ch->dst, size, num, inc ? 'Y' : 'N'); 917 ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0; 918 } 919 } 920 921 static void pl330_dmastp(PL330Chan *ch, uint8_t opcode, 922 uint8_t *args, int len) 923 { 924 uint8_t periph_id; 925 926 if (args[0] & 7) { 927 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 928 return; 929 } 930 periph_id = (args[0] >> 3) & 0x1f; 931 if (periph_id >= ch->parent->num_periph_req) { 932 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 933 return; 934 } 935 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 936 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 937 return; 938 } 939 pl330_dmast(ch, opcode, args, len); 940 } 941 942 static void pl330_dmastz(PL330Chan *ch, uint8_t opcode, 943 uint8_t *args, int len) 944 { 945 uint32_t size, num; 946 bool inc; 947 948 num = ((ch->control >> 18) & 0xf) + 1; 949 size = (uint32_t)1 << ((ch->control >> 15) & 0x7); 950 inc = !!((ch->control >> 14) & 1); 951 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, 952 size, num, inc, 1, ch->tag); 953 if (inc) { 954 ch->dst += size * num; 955 } 956 } 957 958 static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode, 959 uint8_t *args, int len) 960 { 961 uint8_t ev_id; 962 int i; 963 964 if (args[0] & 5) { 965 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 966 return; 967 } 968 ev_id = (args[0] >> 3) & 0x1f; 969 if (ev_id >= ch->parent->num_events) { 970 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 971 return; 972 } 973 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { 974 pl330_fault(ch, PL330_FAULT_EVENT_ERR); 975 return; 976 } 977 ch->wakeup = ev_id; 978 ch->state = pl330_chan_waiting_event; 979 if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) { 980 ch->state = pl330_chan_executing; 981 /* If anyone else is currently waiting on the same event, let them 982 * clear the ev_status so they pick up event as well 983 */ 984 for (i = 0; i < ch->parent->num_chnls; ++i) { 985 PL330Chan *peer = &ch->parent->chan[i]; 986 if (peer->state == pl330_chan_waiting_event && 987 peer->wakeup == ev_id) { 988 return; 989 } 990 } 991 ch->parent->ev_status &= ~(1 << ev_id); 992 DB_PRINT("event lowered %" PRIx8 "\n", ev_id); 993 } else { 994 ch->stall = 1; 995 } 996 } 997 998 static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode, 999 uint8_t *args, int len) 1000 { 1001 uint8_t bs = opcode & 3; 1002 uint8_t periph_id; 1003 1004 if (args[0] & 7) { 1005 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1006 return; 1007 } 1008 periph_id = (args[0] >> 3) & 0x1f; 1009 if (periph_id >= ch->parent->num_periph_req) { 1010 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1011 return; 1012 } 1013 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { 1014 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); 1015 return; 1016 } 1017 switch (bs) { 1018 case 0: /* S */ 1019 ch->request_flag = PL330_SINGLE; 1020 ch->wfp_sbp = 0; 1021 break; 1022 case 1: /* P */ 1023 ch->request_flag = PL330_BURST; 1024 ch->wfp_sbp = 2; 1025 break; 1026 case 2: /* B */ 1027 ch->request_flag = PL330_BURST; 1028 ch->wfp_sbp = 1; 1029 break; 1030 default: 1031 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); 1032 return; 1033 } 1034 1035 if (ch->parent->periph_busy[periph_id]) { 1036 ch->state = pl330_chan_waiting_periph; 1037 ch->stall = 1; 1038 } else if (ch->state == pl330_chan_waiting_periph) { 1039 ch->state = pl330_chan_executing; 1040 } 1041 } 1042 1043 static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode, 1044 uint8_t *args, int len) 1045 { 1046 if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) { 1047 ch->state = pl330_chan_at_barrier; 1048 ch->stall = 1; 1049 return; 1050 } else { 1051 ch->state = pl330_chan_executing; 1052 } 1053 } 1054 1055 /* NULL terminated array of the instruction descriptions. */ 1056 static const PL330InsnDesc insn_desc[] = { 1057 { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, }, 1058 { .opcode = 0x5c, .opmask = 0xFD, .size = 3, .exec = pl330_dmaadnh, }, 1059 { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, }, 1060 { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, }, 1061 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, 1062 { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, }, 1063 { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, }, 1064 { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, }, 1065 /* dmastp must be before dmalpend in this list, because their maps 1066 * are overlapping 1067 */ 1068 { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, }, 1069 { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, }, 1070 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, 1071 { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, }, 1072 { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, }, 1073 { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, }, 1074 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, 1075 { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, }, 1076 { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, }, 1077 { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, }, 1078 { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, }, 1079 { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, }, 1080 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } 1081 }; 1082 1083 /* Instructions which can be issued via debug registers. */ 1084 static const PL330InsnDesc debug_insn_desc[] = { 1085 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, 1086 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, 1087 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, 1088 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } 1089 }; 1090 1091 static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch) 1092 { 1093 uint8_t opcode; 1094 int i; 1095 1096 dma_memory_read(&address_space_memory, ch->pc, &opcode, 1); 1097 for (i = 0; insn_desc[i].size; i++) { 1098 if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) { 1099 return &insn_desc[i]; 1100 } 1101 } 1102 return NULL; 1103 } 1104 1105 static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn) 1106 { 1107 uint8_t buf[PL330_INSN_MAXSIZE]; 1108 1109 assert(insn->size <= PL330_INSN_MAXSIZE); 1110 dma_memory_read(&address_space_memory, ch->pc, buf, insn->size); 1111 insn->exec(ch, buf[0], &buf[1], insn->size - 1); 1112 } 1113 1114 static inline void pl330_update_pc(PL330Chan *ch, 1115 const PL330InsnDesc *insn) 1116 { 1117 ch->pc += insn->size; 1118 } 1119 1120 /* Try to execute current instruction in channel CH. Number of executed 1121 instructions is returned (0 or 1). */ 1122 static int pl330_chan_exec(PL330Chan *ch) 1123 { 1124 const PL330InsnDesc *insn; 1125 1126 if (ch->state != pl330_chan_executing && 1127 ch->state != pl330_chan_waiting_periph && 1128 ch->state != pl330_chan_at_barrier && 1129 ch->state != pl330_chan_waiting_event) { 1130 return 0; 1131 } 1132 ch->stall = 0; 1133 insn = pl330_fetch_insn(ch); 1134 if (!insn) { 1135 DB_PRINT("pl330 undefined instruction\n"); 1136 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); 1137 return 0; 1138 } 1139 pl330_exec_insn(ch, insn); 1140 if (!ch->stall) { 1141 pl330_update_pc(ch, insn); 1142 ch->watchdog_timer = 0; 1143 return 1; 1144 /* WDT only active in exec state */ 1145 } else if (ch->state == pl330_chan_executing) { 1146 ch->watchdog_timer++; 1147 if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) { 1148 pl330_fault(ch, PL330_FAULT_LOCKUP_ERR); 1149 } 1150 } 1151 return 0; 1152 } 1153 1154 /* Try to execute 1 instruction in each channel, one instruction from read 1155 queue and one instruction from write queue. Number of successfully executed 1156 instructions is returned. */ 1157 static int pl330_exec_cycle(PL330Chan *channel) 1158 { 1159 PL330State *s = channel->parent; 1160 PL330QueueEntry *q; 1161 int i; 1162 int num_exec = 0; 1163 int fifo_res = 0; 1164 uint8_t buf[PL330_MAX_BURST_LEN]; 1165 1166 /* Execute one instruction in each channel */ 1167 num_exec += pl330_chan_exec(channel); 1168 1169 /* Execute one instruction from read queue */ 1170 q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true); 1171 if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) { 1172 int len = q->len - (q->addr & (q->len - 1)); 1173 1174 dma_memory_read(&address_space_memory, q->addr, buf, len); 1175 if (PL330_ERR_DEBUG > 1) { 1176 DB_PRINT("PL330 read from memory @%08" PRIx32 " (size = %08x):\n", 1177 q->addr, len); 1178 qemu_hexdump((char *)buf, stderr, "", len); 1179 } 1180 fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag); 1181 if (fifo_res == PL330_FIFO_OK) { 1182 if (q->inc) { 1183 q->addr += len; 1184 } 1185 q->n--; 1186 if (!q->n) { 1187 pl330_queue_remove_insn(&s->read_queue, q); 1188 } 1189 num_exec++; 1190 } 1191 } 1192 1193 /* Execute one instruction from write queue. */ 1194 q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true); 1195 if (q != NULL) { 1196 int len = q->len - (q->addr & (q->len - 1)); 1197 1198 if (q->z) { 1199 for (i = 0; i < len; i++) { 1200 buf[i] = 0; 1201 } 1202 } else { 1203 fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag); 1204 } 1205 if (fifo_res == PL330_FIFO_OK || q->z) { 1206 dma_memory_write(&address_space_memory, q->addr, buf, len); 1207 if (PL330_ERR_DEBUG > 1) { 1208 DB_PRINT("PL330 read from memory @%08" PRIx32 1209 " (size = %08x):\n", q->addr, len); 1210 qemu_hexdump((char *)buf, stderr, "", len); 1211 } 1212 if (q->inc) { 1213 q->addr += len; 1214 } 1215 num_exec++; 1216 } else if (fifo_res == PL330_FIFO_STALL) { 1217 pl330_fault(&channel->parent->chan[q->tag], 1218 PL330_FAULT_FIFOEMPTY_ERR); 1219 } 1220 q->n--; 1221 if (!q->n) { 1222 pl330_queue_remove_insn(&s->write_queue, q); 1223 } 1224 } 1225 1226 return num_exec; 1227 } 1228 1229 static int pl330_exec_channel(PL330Chan *channel) 1230 { 1231 int insr_exec = 0; 1232 1233 /* TODO: Is it all right to execute everything or should we do per-cycle 1234 simulation? */ 1235 while (pl330_exec_cycle(channel)) { 1236 insr_exec++; 1237 } 1238 1239 /* Detect deadlock */ 1240 if (channel->state == pl330_chan_executing) { 1241 pl330_fault(channel, PL330_FAULT_LOCKUP_ERR); 1242 } 1243 /* Situation when one of the queues has deadlocked but all channels 1244 * have finished their programs should be impossible. 1245 */ 1246 1247 return insr_exec; 1248 } 1249 1250 static inline void pl330_exec(PL330State *s) 1251 { 1252 DB_PRINT("\n"); 1253 int i, insr_exec; 1254 do { 1255 insr_exec = pl330_exec_channel(&s->manager); 1256 1257 for (i = 0; i < s->num_chnls; i++) { 1258 insr_exec += pl330_exec_channel(&s->chan[i]); 1259 } 1260 } while (insr_exec); 1261 } 1262 1263 static void pl330_exec_cycle_timer(void *opaque) 1264 { 1265 PL330State *s = (PL330State *)opaque; 1266 pl330_exec(s); 1267 } 1268 1269 /* Stop or restore dma operations */ 1270 1271 static void pl330_dma_stop_irq(void *opaque, int irq, int level) 1272 { 1273 PL330State *s = (PL330State *)opaque; 1274 1275 if (s->periph_busy[irq] != level) { 1276 s->periph_busy[irq] = level; 1277 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 1278 } 1279 } 1280 1281 static void pl330_debug_exec(PL330State *s) 1282 { 1283 uint8_t args[5]; 1284 uint8_t opcode; 1285 uint8_t chan_id; 1286 int i; 1287 PL330Chan *ch; 1288 const PL330InsnDesc *insn; 1289 1290 s->debug_status = 1; 1291 chan_id = (s->dbg[0] >> 8) & 0x07; 1292 opcode = (s->dbg[0] >> 16) & 0xff; 1293 args[0] = (s->dbg[0] >> 24) & 0xff; 1294 args[1] = (s->dbg[1] >> 0) & 0xff; 1295 args[2] = (s->dbg[1] >> 8) & 0xff; 1296 args[3] = (s->dbg[1] >> 16) & 0xff; 1297 args[4] = (s->dbg[1] >> 24) & 0xff; 1298 DB_PRINT("chan id: %" PRIx8 "\n", chan_id); 1299 if (s->dbg[0] & 1) { 1300 ch = &s->chan[chan_id]; 1301 } else { 1302 ch = &s->manager; 1303 } 1304 insn = NULL; 1305 for (i = 0; debug_insn_desc[i].size; i++) { 1306 if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) { 1307 insn = &debug_insn_desc[i]; 1308 } 1309 } 1310 if (!insn) { 1311 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR); 1312 return ; 1313 } 1314 ch->stall = 0; 1315 insn->exec(ch, opcode, args, insn->size - 1); 1316 if (ch->fault_type) { 1317 ch->fault_type |= PL330_FAULT_DBG_INSTR; 1318 } 1319 if (ch->stall) { 1320 qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not " 1321 "implemented\n"); 1322 } 1323 s->debug_status = 0; 1324 } 1325 1326 /* IOMEM mapped registers */ 1327 1328 static void pl330_iomem_write(void *opaque, hwaddr offset, 1329 uint64_t value, unsigned size) 1330 { 1331 PL330State *s = (PL330State *) opaque; 1332 int i; 1333 1334 DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)value); 1335 1336 switch (offset) { 1337 case PL330_REG_INTEN: 1338 s->inten = value; 1339 break; 1340 case PL330_REG_INTCLR: 1341 for (i = 0; i < s->num_events; i++) { 1342 if (s->int_status & s->inten & value & (1 << i)) { 1343 DB_PRINT("event interrupt lowered %d\n", i); 1344 qemu_irq_lower(s->irq[i]); 1345 } 1346 } 1347 s->ev_status &= ~(value & s->inten); 1348 s->int_status &= ~(value & s->inten); 1349 break; 1350 case PL330_REG_DBGCMD: 1351 if ((value & 3) == 0) { 1352 pl330_debug_exec(s); 1353 pl330_exec(s); 1354 } else { 1355 qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u " 1356 "for offset " TARGET_FMT_plx "\n", (unsigned)value, 1357 offset); 1358 } 1359 break; 1360 case PL330_REG_DBGINST0: 1361 DB_PRINT("s->dbg[0] = %08x\n", (unsigned)value); 1362 s->dbg[0] = value; 1363 break; 1364 case PL330_REG_DBGINST1: 1365 DB_PRINT("s->dbg[1] = %08x\n", (unsigned)value); 1366 s->dbg[1] = value; 1367 break; 1368 default: 1369 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx 1370 "\n", offset); 1371 break; 1372 } 1373 } 1374 1375 static inline uint32_t pl330_iomem_read_imp(void *opaque, 1376 hwaddr offset) 1377 { 1378 PL330State *s = (PL330State *)opaque; 1379 int chan_id; 1380 int i; 1381 uint32_t res; 1382 1383 if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) { 1384 return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2]; 1385 } 1386 if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) { 1387 return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2]; 1388 } 1389 if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) { 1390 offset -= PL330_REG_CHANCTRL; 1391 chan_id = offset >> 5; 1392 if (chan_id >= s->num_chnls) { 1393 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1394 TARGET_FMT_plx "\n", offset); 1395 return 0; 1396 } 1397 switch (offset & 0x1f) { 1398 case 0x00: 1399 return s->chan[chan_id].src; 1400 case 0x04: 1401 return s->chan[chan_id].dst; 1402 case 0x08: 1403 return s->chan[chan_id].control; 1404 case 0x0C: 1405 return s->chan[chan_id].lc[0]; 1406 case 0x10: 1407 return s->chan[chan_id].lc[1]; 1408 default: 1409 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1410 TARGET_FMT_plx "\n", offset); 1411 return 0; 1412 } 1413 } 1414 if (offset >= PL330_REG_CSR_BASE && offset < 0x400) { 1415 offset -= PL330_REG_CSR_BASE; 1416 chan_id = offset >> 3; 1417 if (chan_id >= s->num_chnls) { 1418 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1419 TARGET_FMT_plx "\n", offset); 1420 return 0; 1421 } 1422 switch ((offset >> 2) & 1) { 1423 case 0x0: 1424 res = (s->chan[chan_id].ns << 21) | 1425 (s->chan[chan_id].wakeup << 4) | 1426 (s->chan[chan_id].state) | 1427 (s->chan[chan_id].wfp_sbp << 14); 1428 return res; 1429 case 0x1: 1430 return s->chan[chan_id].pc; 1431 default: 1432 qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n"); 1433 return 0; 1434 } 1435 } 1436 if (offset >= PL330_REG_FTR_BASE && offset < 0x100) { 1437 offset -= PL330_REG_FTR_BASE; 1438 chan_id = offset >> 2; 1439 if (chan_id >= s->num_chnls) { 1440 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1441 TARGET_FMT_plx "\n", offset); 1442 return 0; 1443 } 1444 return s->chan[chan_id].fault_type; 1445 } 1446 switch (offset) { 1447 case PL330_REG_DSR: 1448 return (s->manager.ns << 9) | (s->manager.wakeup << 4) | 1449 (s->manager.state & 0xf); 1450 case PL330_REG_DPC: 1451 return s->manager.pc; 1452 case PL330_REG_INTEN: 1453 return s->inten; 1454 case PL330_REG_INT_EVENT_RIS: 1455 return s->ev_status; 1456 case PL330_REG_INTMIS: 1457 return s->int_status; 1458 case PL330_REG_INTCLR: 1459 /* Documentation says that we can't read this register 1460 * but linux kernel does it 1461 */ 1462 return 0; 1463 case PL330_REG_FSRD: 1464 return s->manager.state ? 1 : 0; 1465 case PL330_REG_FSRC: 1466 res = 0; 1467 for (i = 0; i < s->num_chnls; i++) { 1468 if (s->chan[i].state == pl330_chan_fault || 1469 s->chan[i].state == pl330_chan_fault_completing) { 1470 res |= 1 << i; 1471 } 1472 } 1473 return res; 1474 case PL330_REG_FTRD: 1475 return s->manager.fault_type; 1476 case PL330_REG_DBGSTATUS: 1477 return s->debug_status; 1478 default: 1479 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " 1480 TARGET_FMT_plx "\n", offset); 1481 } 1482 return 0; 1483 } 1484 1485 static uint64_t pl330_iomem_read(void *opaque, hwaddr offset, 1486 unsigned size) 1487 { 1488 uint32_t ret = pl330_iomem_read_imp(opaque, offset); 1489 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset, ret); 1490 return ret; 1491 } 1492 1493 static const MemoryRegionOps pl330_ops = { 1494 .read = pl330_iomem_read, 1495 .write = pl330_iomem_write, 1496 .endianness = DEVICE_NATIVE_ENDIAN, 1497 .impl = { 1498 .min_access_size = 4, 1499 .max_access_size = 4, 1500 } 1501 }; 1502 1503 /* Controller logic and initialization */ 1504 1505 static void pl330_chan_reset(PL330Chan *ch) 1506 { 1507 ch->src = 0; 1508 ch->dst = 0; 1509 ch->pc = 0; 1510 ch->state = pl330_chan_stopped; 1511 ch->watchdog_timer = 0; 1512 ch->stall = 0; 1513 ch->control = 0; 1514 ch->status = 0; 1515 ch->fault_type = 0; 1516 } 1517 1518 static void pl330_reset(DeviceState *d) 1519 { 1520 int i; 1521 PL330State *s = PL330(d); 1522 1523 s->inten = 0; 1524 s->int_status = 0; 1525 s->ev_status = 0; 1526 s->debug_status = 0; 1527 s->num_faulting = 0; 1528 s->manager.ns = s->mgr_ns_at_rst; 1529 pl330_fifo_reset(&s->fifo); 1530 pl330_queue_reset(&s->read_queue); 1531 pl330_queue_reset(&s->write_queue); 1532 1533 for (i = 0; i < s->num_chnls; i++) { 1534 pl330_chan_reset(&s->chan[i]); 1535 } 1536 for (i = 0; i < s->num_periph_req; i++) { 1537 s->periph_busy[i] = 0; 1538 } 1539 1540 timer_del(s->timer); 1541 } 1542 1543 static void pl330_realize(DeviceState *dev, Error **errp) 1544 { 1545 int i; 1546 PL330State *s = PL330(dev); 1547 1548 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort); 1549 memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s, 1550 "dma", PL330_IOMEM_SIZE); 1551 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1552 1553 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s); 1554 1555 s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) | 1556 (s->num_periph_req > 0 ? 1 : 0) | 1557 ((s->num_chnls - 1) & 0x7) << 4 | 1558 ((s->num_periph_req - 1) & 0x1f) << 12 | 1559 ((s->num_events - 1) & 0x1f) << 17; 1560 1561 switch (s->i_cache_len) { 1562 case (4): 1563 s->cfg[1] |= 2; 1564 break; 1565 case (8): 1566 s->cfg[1] |= 3; 1567 break; 1568 case (16): 1569 s->cfg[1] |= 4; 1570 break; 1571 case (32): 1572 s->cfg[1] |= 5; 1573 break; 1574 default: 1575 error_setg(errp, "Bad value for i-cache_len property: %" PRIx8, 1576 s->i_cache_len); 1577 return; 1578 } 1579 s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4; 1580 1581 s->chan = g_new0(PL330Chan, s->num_chnls); 1582 s->hi_seqn = g_new0(uint8_t, s->num_chnls); 1583 s->lo_seqn = g_new0(uint8_t, s->num_chnls); 1584 for (i = 0; i < s->num_chnls; i++) { 1585 s->chan[i].parent = s; 1586 s->chan[i].tag = (uint8_t)i; 1587 } 1588 s->manager.parent = s; 1589 s->manager.tag = s->num_chnls; 1590 s->manager.is_manager = true; 1591 1592 s->irq = g_new0(qemu_irq, s->num_events); 1593 for (i = 0; i < s->num_events; i++) { 1594 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1595 } 1596 1597 qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM); 1598 1599 switch (s->data_width) { 1600 case (32): 1601 s->cfg[CFG_CRD] |= 0x2; 1602 break; 1603 case (64): 1604 s->cfg[CFG_CRD] |= 0x3; 1605 break; 1606 case (128): 1607 s->cfg[CFG_CRD] |= 0x4; 1608 break; 1609 default: 1610 error_setg(errp, "Bad value for data_width property: %" PRIx8, 1611 s->data_width); 1612 return; 1613 } 1614 1615 s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 | 1616 ((s->wr_q_dep - 1) & 0xf) << 8 | 1617 ((s->rd_cap - 1) & 0x7) << 12 | 1618 ((s->rd_q_dep - 1) & 0xf) << 16 | 1619 ((s->data_buffer_dep - 1) & 0x1ff) << 20; 1620 1621 pl330_queue_init(&s->read_queue, s->rd_q_dep, s); 1622 pl330_queue_init(&s->write_queue, s->wr_q_dep, s); 1623 pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep); 1624 } 1625 1626 static Property pl330_properties[] = { 1627 /* CR0 */ 1628 DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8), 1629 DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4), 1630 DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16), 1631 DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0), 1632 /* CR1 */ 1633 DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4), 1634 DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8), 1635 /* CR2-4 */ 1636 DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0), 1637 DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0), 1638 DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0), 1639 /* CRD */ 1640 DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64), 1641 DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8), 1642 DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16), 1643 DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8), 1644 DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16), 1645 DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256), 1646 1647 DEFINE_PROP_END_OF_LIST(), 1648 }; 1649 1650 static void pl330_class_init(ObjectClass *klass, void *data) 1651 { 1652 DeviceClass *dc = DEVICE_CLASS(klass); 1653 1654 dc->realize = pl330_realize; 1655 dc->reset = pl330_reset; 1656 dc->props = pl330_properties; 1657 dc->vmsd = &vmstate_pl330; 1658 } 1659 1660 static const TypeInfo pl330_type_info = { 1661 .name = TYPE_PL330, 1662 .parent = TYPE_SYS_BUS_DEVICE, 1663 .instance_size = sizeof(PL330State), 1664 .class_init = pl330_class_init, 1665 }; 1666 1667 static void pl330_register_types(void) 1668 { 1669 type_register_static(&pl330_type_info); 1670 } 1671 1672 type_init(pl330_register_types) 1673