1 /* 2 * Arm PrimeCell PL080/PL081 DMA controller 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "exec/address-spaces.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "hw/dma/pl080.h" 16 #include "hw/irq.h" 17 #include "qapi/error.h" 18 19 #define PL080_CONF_E 0x1 20 #define PL080_CONF_M1 0x2 21 #define PL080_CONF_M2 0x4 22 23 #define PL080_CCONF_H 0x40000 24 #define PL080_CCONF_A 0x20000 25 #define PL080_CCONF_L 0x10000 26 #define PL080_CCONF_ITC 0x08000 27 #define PL080_CCONF_IE 0x04000 28 #define PL080_CCONF_E 0x00001 29 30 #define PL080_CCTRL_I 0x80000000 31 #define PL080_CCTRL_DI 0x08000000 32 #define PL080_CCTRL_SI 0x04000000 33 #define PL080_CCTRL_D 0x02000000 34 #define PL080_CCTRL_S 0x01000000 35 36 static const VMStateDescription vmstate_pl080_channel = { 37 .name = "pl080_channel", 38 .version_id = 1, 39 .minimum_version_id = 1, 40 .fields = (VMStateField[]) { 41 VMSTATE_UINT32(src, pl080_channel), 42 VMSTATE_UINT32(dest, pl080_channel), 43 VMSTATE_UINT32(lli, pl080_channel), 44 VMSTATE_UINT32(ctrl, pl080_channel), 45 VMSTATE_UINT32(conf, pl080_channel), 46 VMSTATE_END_OF_LIST() 47 } 48 }; 49 50 static const VMStateDescription vmstate_pl080 = { 51 .name = "pl080", 52 .version_id = 1, 53 .minimum_version_id = 1, 54 .fields = (VMStateField[]) { 55 VMSTATE_UINT8(tc_int, PL080State), 56 VMSTATE_UINT8(tc_mask, PL080State), 57 VMSTATE_UINT8(err_int, PL080State), 58 VMSTATE_UINT8(err_mask, PL080State), 59 VMSTATE_UINT32(conf, PL080State), 60 VMSTATE_UINT32(sync, PL080State), 61 VMSTATE_UINT32(req_single, PL080State), 62 VMSTATE_UINT32(req_burst, PL080State), 63 VMSTATE_UINT8(tc_int, PL080State), 64 VMSTATE_UINT8(tc_int, PL080State), 65 VMSTATE_UINT8(tc_int, PL080State), 66 VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS, 67 1, vmstate_pl080_channel, pl080_channel), 68 VMSTATE_INT32(running, PL080State), 69 VMSTATE_END_OF_LIST() 70 } 71 }; 72 73 static const unsigned char pl080_id[] = 74 { 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; 75 76 static const unsigned char pl081_id[] = 77 { 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; 78 79 static void pl080_update(PL080State *s) 80 { 81 bool tclevel = (s->tc_int & s->tc_mask); 82 bool errlevel = (s->err_int & s->err_mask); 83 84 qemu_set_irq(s->interr, errlevel); 85 qemu_set_irq(s->inttc, tclevel); 86 qemu_set_irq(s->irq, errlevel || tclevel); 87 } 88 89 static void pl080_run(PL080State *s) 90 { 91 int c; 92 int flow; 93 pl080_channel *ch; 94 int swidth; 95 int dwidth; 96 int xsize; 97 int n; 98 int src_id; 99 int dest_id; 100 int size; 101 uint8_t buff[4]; 102 uint32_t req; 103 104 s->tc_mask = 0; 105 for (c = 0; c < s->nchannels; c++) { 106 if (s->chan[c].conf & PL080_CCONF_ITC) 107 s->tc_mask |= 1 << c; 108 if (s->chan[c].conf & PL080_CCONF_IE) 109 s->err_mask |= 1 << c; 110 } 111 112 if ((s->conf & PL080_CONF_E) == 0) 113 return; 114 115 /* If we are already in the middle of a DMA operation then indicate that 116 there may be new DMA requests and return immediately. */ 117 if (s->running) { 118 s->running++; 119 return; 120 } 121 s->running = 1; 122 while (s->running) { 123 for (c = 0; c < s->nchannels; c++) { 124 ch = &s->chan[c]; 125 again: 126 /* Test if thiws channel has any pending DMA requests. */ 127 if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E)) 128 != PL080_CCONF_E) 129 continue; 130 flow = (ch->conf >> 11) & 7; 131 if (flow >= 4) { 132 hw_error( 133 "pl080_run: Peripheral flow control not implemented\n"); 134 } 135 src_id = (ch->conf >> 1) & 0x1f; 136 dest_id = (ch->conf >> 6) & 0x1f; 137 size = ch->ctrl & 0xfff; 138 req = s->req_single | s->req_burst; 139 switch (flow) { 140 case 0: 141 break; 142 case 1: 143 if ((req & (1u << dest_id)) == 0) 144 size = 0; 145 break; 146 case 2: 147 if ((req & (1u << src_id)) == 0) 148 size = 0; 149 break; 150 case 3: 151 if ((req & (1u << src_id)) == 0 152 || (req & (1u << dest_id)) == 0) 153 size = 0; 154 break; 155 } 156 if (!size) 157 continue; 158 159 /* Transfer one element. */ 160 /* ??? Should transfer multiple elements for a burst request. */ 161 /* ??? Unclear what the proper behavior is when source and 162 destination widths are different. */ 163 swidth = 1 << ((ch->ctrl >> 18) & 7); 164 dwidth = 1 << ((ch->ctrl >> 21) & 7); 165 for (n = 0; n < dwidth; n+= swidth) { 166 address_space_read(&s->downstream_as, ch->src, 167 MEMTXATTRS_UNSPECIFIED, buff + n, swidth); 168 if (ch->ctrl & PL080_CCTRL_SI) 169 ch->src += swidth; 170 } 171 xsize = (dwidth < swidth) ? swidth : dwidth; 172 /* ??? This may pad the value incorrectly for dwidth < 32. */ 173 for (n = 0; n < xsize; n += dwidth) { 174 address_space_write(&s->downstream_as, ch->dest + n, 175 MEMTXATTRS_UNSPECIFIED, buff + n, dwidth); 176 if (ch->ctrl & PL080_CCTRL_DI) 177 ch->dest += swidth; 178 } 179 180 size--; 181 ch->ctrl = (ch->ctrl & 0xfffff000) | size; 182 if (size == 0) { 183 /* Transfer complete. */ 184 if (ch->lli) { 185 ch->src = address_space_ldl_le(&s->downstream_as, 186 ch->lli, 187 MEMTXATTRS_UNSPECIFIED, 188 NULL); 189 ch->dest = address_space_ldl_le(&s->downstream_as, 190 ch->lli + 4, 191 MEMTXATTRS_UNSPECIFIED, 192 NULL); 193 ch->ctrl = address_space_ldl_le(&s->downstream_as, 194 ch->lli + 12, 195 MEMTXATTRS_UNSPECIFIED, 196 NULL); 197 ch->lli = address_space_ldl_le(&s->downstream_as, 198 ch->lli + 8, 199 MEMTXATTRS_UNSPECIFIED, 200 NULL); 201 } else { 202 ch->conf &= ~PL080_CCONF_E; 203 } 204 if (ch->ctrl & PL080_CCTRL_I) { 205 s->tc_int |= 1 << c; 206 } 207 } 208 goto again; 209 } 210 if (--s->running) 211 s->running = 1; 212 } 213 } 214 215 static uint64_t pl080_read(void *opaque, hwaddr offset, 216 unsigned size) 217 { 218 PL080State *s = (PL080State *)opaque; 219 uint32_t i; 220 uint32_t mask; 221 222 if (offset >= 0xfe0 && offset < 0x1000) { 223 if (s->nchannels == 8) { 224 return pl080_id[(offset - 0xfe0) >> 2]; 225 } else { 226 return pl081_id[(offset - 0xfe0) >> 2]; 227 } 228 } 229 if (offset >= 0x100 && offset < 0x200) { 230 i = (offset & 0xe0) >> 5; 231 if (i >= s->nchannels) 232 goto bad_offset; 233 switch ((offset >> 2) & 7) { 234 case 0: /* SrcAddr */ 235 return s->chan[i].src; 236 case 1: /* DestAddr */ 237 return s->chan[i].dest; 238 case 2: /* LLI */ 239 return s->chan[i].lli; 240 case 3: /* Control */ 241 return s->chan[i].ctrl; 242 case 4: /* Configuration */ 243 return s->chan[i].conf; 244 default: 245 goto bad_offset; 246 } 247 } 248 switch (offset >> 2) { 249 case 0: /* IntStatus */ 250 return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask); 251 case 1: /* IntTCStatus */ 252 return (s->tc_int & s->tc_mask); 253 case 3: /* IntErrorStatus */ 254 return (s->err_int & s->err_mask); 255 case 5: /* RawIntTCStatus */ 256 return s->tc_int; 257 case 6: /* RawIntErrorStatus */ 258 return s->err_int; 259 case 7: /* EnbldChns */ 260 mask = 0; 261 for (i = 0; i < s->nchannels; i++) { 262 if (s->chan[i].conf & PL080_CCONF_E) 263 mask |= 1 << i; 264 } 265 return mask; 266 case 8: /* SoftBReq */ 267 case 9: /* SoftSReq */ 268 case 10: /* SoftLBReq */ 269 case 11: /* SoftLSReq */ 270 /* ??? Implement these. */ 271 return 0; 272 case 12: /* Configuration */ 273 return s->conf; 274 case 13: /* Sync */ 275 return s->sync; 276 default: 277 bad_offset: 278 qemu_log_mask(LOG_GUEST_ERROR, 279 "pl080_read: Bad offset %x\n", (int)offset); 280 return 0; 281 } 282 } 283 284 static void pl080_write(void *opaque, hwaddr offset, 285 uint64_t value, unsigned size) 286 { 287 PL080State *s = (PL080State *)opaque; 288 int i; 289 290 if (offset >= 0x100 && offset < 0x200) { 291 i = (offset & 0xe0) >> 5; 292 if (i >= s->nchannels) 293 goto bad_offset; 294 switch ((offset >> 2) & 7) { 295 case 0: /* SrcAddr */ 296 s->chan[i].src = value; 297 break; 298 case 1: /* DestAddr */ 299 s->chan[i].dest = value; 300 break; 301 case 2: /* LLI */ 302 s->chan[i].lli = value; 303 break; 304 case 3: /* Control */ 305 s->chan[i].ctrl = value; 306 break; 307 case 4: /* Configuration */ 308 s->chan[i].conf = value; 309 pl080_run(s); 310 break; 311 } 312 return; 313 } 314 switch (offset >> 2) { 315 case 2: /* IntTCClear */ 316 s->tc_int &= ~value; 317 break; 318 case 4: /* IntErrorClear */ 319 s->err_int &= ~value; 320 break; 321 case 8: /* SoftBReq */ 322 case 9: /* SoftSReq */ 323 case 10: /* SoftLBReq */ 324 case 11: /* SoftLSReq */ 325 /* ??? Implement these. */ 326 qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n"); 327 break; 328 case 12: /* Configuration */ 329 s->conf = value; 330 if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) { 331 qemu_log_mask(LOG_UNIMP, 332 "pl080_write: Big-endian DMA not implemented\n"); 333 } 334 pl080_run(s); 335 break; 336 case 13: /* Sync */ 337 s->sync = value; 338 break; 339 default: 340 bad_offset: 341 qemu_log_mask(LOG_GUEST_ERROR, 342 "pl080_write: Bad offset %x\n", (int)offset); 343 } 344 pl080_update(s); 345 } 346 347 static const MemoryRegionOps pl080_ops = { 348 .read = pl080_read, 349 .write = pl080_write, 350 .endianness = DEVICE_NATIVE_ENDIAN, 351 }; 352 353 static void pl080_reset(DeviceState *dev) 354 { 355 PL080State *s = PL080(dev); 356 int i; 357 358 s->tc_int = 0; 359 s->tc_mask = 0; 360 s->err_int = 0; 361 s->err_mask = 0; 362 s->conf = 0; 363 s->sync = 0; 364 s->req_single = 0; 365 s->req_burst = 0; 366 s->running = 0; 367 368 for (i = 0; i < s->nchannels; i++) { 369 s->chan[i].src = 0; 370 s->chan[i].dest = 0; 371 s->chan[i].lli = 0; 372 s->chan[i].ctrl = 0; 373 s->chan[i].conf = 0; 374 } 375 } 376 377 static void pl080_init(Object *obj) 378 { 379 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 380 PL080State *s = PL080(obj); 381 382 memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000); 383 sysbus_init_mmio(sbd, &s->iomem); 384 sysbus_init_irq(sbd, &s->irq); 385 sysbus_init_irq(sbd, &s->interr); 386 sysbus_init_irq(sbd, &s->inttc); 387 s->nchannels = 8; 388 } 389 390 static void pl080_realize(DeviceState *dev, Error **errp) 391 { 392 PL080State *s = PL080(dev); 393 394 if (!s->downstream) { 395 error_setg(errp, "PL080 'downstream' link not set"); 396 return; 397 } 398 399 address_space_init(&s->downstream_as, s->downstream, "pl080-downstream"); 400 } 401 402 static void pl081_init(Object *obj) 403 { 404 PL080State *s = PL080(obj); 405 406 s->nchannels = 2; 407 } 408 409 static Property pl080_properties[] = { 410 DEFINE_PROP_LINK("downstream", PL080State, downstream, 411 TYPE_MEMORY_REGION, MemoryRegion *), 412 DEFINE_PROP_END_OF_LIST(), 413 }; 414 415 static void pl080_class_init(ObjectClass *oc, void *data) 416 { 417 DeviceClass *dc = DEVICE_CLASS(oc); 418 419 dc->vmsd = &vmstate_pl080; 420 dc->realize = pl080_realize; 421 dc->props = pl080_properties; 422 dc->reset = pl080_reset; 423 } 424 425 static const TypeInfo pl080_info = { 426 .name = TYPE_PL080, 427 .parent = TYPE_SYS_BUS_DEVICE, 428 .instance_size = sizeof(PL080State), 429 .instance_init = pl080_init, 430 .class_init = pl080_class_init, 431 }; 432 433 static const TypeInfo pl081_info = { 434 .name = TYPE_PL081, 435 .parent = TYPE_PL080, 436 .instance_init = pl081_init, 437 }; 438 439 /* The PL080 and PL081 are the same except for the number of channels 440 they implement (8 and 2 respectively). */ 441 static void pl080_register_types(void) 442 { 443 type_register_static(&pl080_info); 444 type_register_static(&pl081_info); 445 } 446 447 type_init(pl080_register_types) 448