1 /* 2 * Arm PrimeCell PL080/PL081 DMA controller 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "exec/address-spaces.h" 13 #include "qemu/log.h" 14 #include "hw/dma/pl080.h" 15 #include "qapi/error.h" 16 17 #define PL080_CONF_E 0x1 18 #define PL080_CONF_M1 0x2 19 #define PL080_CONF_M2 0x4 20 21 #define PL080_CCONF_H 0x40000 22 #define PL080_CCONF_A 0x20000 23 #define PL080_CCONF_L 0x10000 24 #define PL080_CCONF_ITC 0x08000 25 #define PL080_CCONF_IE 0x04000 26 #define PL080_CCONF_E 0x00001 27 28 #define PL080_CCTRL_I 0x80000000 29 #define PL080_CCTRL_DI 0x08000000 30 #define PL080_CCTRL_SI 0x04000000 31 #define PL080_CCTRL_D 0x02000000 32 #define PL080_CCTRL_S 0x01000000 33 34 static const VMStateDescription vmstate_pl080_channel = { 35 .name = "pl080_channel", 36 .version_id = 1, 37 .minimum_version_id = 1, 38 .fields = (VMStateField[]) { 39 VMSTATE_UINT32(src, pl080_channel), 40 VMSTATE_UINT32(dest, pl080_channel), 41 VMSTATE_UINT32(lli, pl080_channel), 42 VMSTATE_UINT32(ctrl, pl080_channel), 43 VMSTATE_UINT32(conf, pl080_channel), 44 VMSTATE_END_OF_LIST() 45 } 46 }; 47 48 static const VMStateDescription vmstate_pl080 = { 49 .name = "pl080", 50 .version_id = 1, 51 .minimum_version_id = 1, 52 .fields = (VMStateField[]) { 53 VMSTATE_UINT8(tc_int, PL080State), 54 VMSTATE_UINT8(tc_mask, PL080State), 55 VMSTATE_UINT8(err_int, PL080State), 56 VMSTATE_UINT8(err_mask, PL080State), 57 VMSTATE_UINT32(conf, PL080State), 58 VMSTATE_UINT32(sync, PL080State), 59 VMSTATE_UINT32(req_single, PL080State), 60 VMSTATE_UINT32(req_burst, PL080State), 61 VMSTATE_UINT8(tc_int, PL080State), 62 VMSTATE_UINT8(tc_int, PL080State), 63 VMSTATE_UINT8(tc_int, PL080State), 64 VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS, 65 1, vmstate_pl080_channel, pl080_channel), 66 VMSTATE_INT32(running, PL080State), 67 VMSTATE_END_OF_LIST() 68 } 69 }; 70 71 static const unsigned char pl080_id[] = 72 { 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; 73 74 static const unsigned char pl081_id[] = 75 { 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; 76 77 static void pl080_update(PL080State *s) 78 { 79 bool tclevel = (s->tc_int & s->tc_mask); 80 bool errlevel = (s->err_int & s->err_mask); 81 82 qemu_set_irq(s->interr, errlevel); 83 qemu_set_irq(s->inttc, tclevel); 84 qemu_set_irq(s->irq, errlevel || tclevel); 85 } 86 87 static void pl080_run(PL080State *s) 88 { 89 int c; 90 int flow; 91 pl080_channel *ch; 92 int swidth; 93 int dwidth; 94 int xsize; 95 int n; 96 int src_id; 97 int dest_id; 98 int size; 99 uint8_t buff[4]; 100 uint32_t req; 101 102 s->tc_mask = 0; 103 for (c = 0; c < s->nchannels; c++) { 104 if (s->chan[c].conf & PL080_CCONF_ITC) 105 s->tc_mask |= 1 << c; 106 if (s->chan[c].conf & PL080_CCONF_IE) 107 s->err_mask |= 1 << c; 108 } 109 110 if ((s->conf & PL080_CONF_E) == 0) 111 return; 112 113 /* If we are already in the middle of a DMA operation then indicate that 114 there may be new DMA requests and return immediately. */ 115 if (s->running) { 116 s->running++; 117 return; 118 } 119 s->running = 1; 120 while (s->running) { 121 for (c = 0; c < s->nchannels; c++) { 122 ch = &s->chan[c]; 123 again: 124 /* Test if thiws channel has any pending DMA requests. */ 125 if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E)) 126 != PL080_CCONF_E) 127 continue; 128 flow = (ch->conf >> 11) & 7; 129 if (flow >= 4) { 130 hw_error( 131 "pl080_run: Peripheral flow control not implemented\n"); 132 } 133 src_id = (ch->conf >> 1) & 0x1f; 134 dest_id = (ch->conf >> 6) & 0x1f; 135 size = ch->ctrl & 0xfff; 136 req = s->req_single | s->req_burst; 137 switch (flow) { 138 case 0: 139 break; 140 case 1: 141 if ((req & (1u << dest_id)) == 0) 142 size = 0; 143 break; 144 case 2: 145 if ((req & (1u << src_id)) == 0) 146 size = 0; 147 break; 148 case 3: 149 if ((req & (1u << src_id)) == 0 150 || (req & (1u << dest_id)) == 0) 151 size = 0; 152 break; 153 } 154 if (!size) 155 continue; 156 157 /* Transfer one element. */ 158 /* ??? Should transfer multiple elements for a burst request. */ 159 /* ??? Unclear what the proper behavior is when source and 160 destination widths are different. */ 161 swidth = 1 << ((ch->ctrl >> 18) & 7); 162 dwidth = 1 << ((ch->ctrl >> 21) & 7); 163 for (n = 0; n < dwidth; n+= swidth) { 164 address_space_read(&s->downstream_as, ch->src, 165 MEMTXATTRS_UNSPECIFIED, buff + n, swidth); 166 if (ch->ctrl & PL080_CCTRL_SI) 167 ch->src += swidth; 168 } 169 xsize = (dwidth < swidth) ? swidth : dwidth; 170 /* ??? This may pad the value incorrectly for dwidth < 32. */ 171 for (n = 0; n < xsize; n += dwidth) { 172 address_space_write(&s->downstream_as, ch->dest + n, 173 MEMTXATTRS_UNSPECIFIED, buff + n, dwidth); 174 if (ch->ctrl & PL080_CCTRL_DI) 175 ch->dest += swidth; 176 } 177 178 size--; 179 ch->ctrl = (ch->ctrl & 0xfffff000) | size; 180 if (size == 0) { 181 /* Transfer complete. */ 182 if (ch->lli) { 183 ch->src = address_space_ldl_le(&s->downstream_as, 184 ch->lli, 185 MEMTXATTRS_UNSPECIFIED, 186 NULL); 187 ch->dest = address_space_ldl_le(&s->downstream_as, 188 ch->lli + 4, 189 MEMTXATTRS_UNSPECIFIED, 190 NULL); 191 ch->ctrl = address_space_ldl_le(&s->downstream_as, 192 ch->lli + 12, 193 MEMTXATTRS_UNSPECIFIED, 194 NULL); 195 ch->lli = address_space_ldl_le(&s->downstream_as, 196 ch->lli + 8, 197 MEMTXATTRS_UNSPECIFIED, 198 NULL); 199 } else { 200 ch->conf &= ~PL080_CCONF_E; 201 } 202 if (ch->ctrl & PL080_CCTRL_I) { 203 s->tc_int |= 1 << c; 204 } 205 } 206 goto again; 207 } 208 if (--s->running) 209 s->running = 1; 210 } 211 } 212 213 static uint64_t pl080_read(void *opaque, hwaddr offset, 214 unsigned size) 215 { 216 PL080State *s = (PL080State *)opaque; 217 uint32_t i; 218 uint32_t mask; 219 220 if (offset >= 0xfe0 && offset < 0x1000) { 221 if (s->nchannels == 8) { 222 return pl080_id[(offset - 0xfe0) >> 2]; 223 } else { 224 return pl081_id[(offset - 0xfe0) >> 2]; 225 } 226 } 227 if (offset >= 0x100 && offset < 0x200) { 228 i = (offset & 0xe0) >> 5; 229 if (i >= s->nchannels) 230 goto bad_offset; 231 switch ((offset >> 2) & 7) { 232 case 0: /* SrcAddr */ 233 return s->chan[i].src; 234 case 1: /* DestAddr */ 235 return s->chan[i].dest; 236 case 2: /* LLI */ 237 return s->chan[i].lli; 238 case 3: /* Control */ 239 return s->chan[i].ctrl; 240 case 4: /* Configuration */ 241 return s->chan[i].conf; 242 default: 243 goto bad_offset; 244 } 245 } 246 switch (offset >> 2) { 247 case 0: /* IntStatus */ 248 return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask); 249 case 1: /* IntTCStatus */ 250 return (s->tc_int & s->tc_mask); 251 case 3: /* IntErrorStatus */ 252 return (s->err_int & s->err_mask); 253 case 5: /* RawIntTCStatus */ 254 return s->tc_int; 255 case 6: /* RawIntErrorStatus */ 256 return s->err_int; 257 case 7: /* EnbldChns */ 258 mask = 0; 259 for (i = 0; i < s->nchannels; i++) { 260 if (s->chan[i].conf & PL080_CCONF_E) 261 mask |= 1 << i; 262 } 263 return mask; 264 case 8: /* SoftBReq */ 265 case 9: /* SoftSReq */ 266 case 10: /* SoftLBReq */ 267 case 11: /* SoftLSReq */ 268 /* ??? Implement these. */ 269 return 0; 270 case 12: /* Configuration */ 271 return s->conf; 272 case 13: /* Sync */ 273 return s->sync; 274 default: 275 bad_offset: 276 qemu_log_mask(LOG_GUEST_ERROR, 277 "pl080_read: Bad offset %x\n", (int)offset); 278 return 0; 279 } 280 } 281 282 static void pl080_write(void *opaque, hwaddr offset, 283 uint64_t value, unsigned size) 284 { 285 PL080State *s = (PL080State *)opaque; 286 int i; 287 288 if (offset >= 0x100 && offset < 0x200) { 289 i = (offset & 0xe0) >> 5; 290 if (i >= s->nchannels) 291 goto bad_offset; 292 switch ((offset >> 2) & 7) { 293 case 0: /* SrcAddr */ 294 s->chan[i].src = value; 295 break; 296 case 1: /* DestAddr */ 297 s->chan[i].dest = value; 298 break; 299 case 2: /* LLI */ 300 s->chan[i].lli = value; 301 break; 302 case 3: /* Control */ 303 s->chan[i].ctrl = value; 304 break; 305 case 4: /* Configuration */ 306 s->chan[i].conf = value; 307 pl080_run(s); 308 break; 309 } 310 return; 311 } 312 switch (offset >> 2) { 313 case 2: /* IntTCClear */ 314 s->tc_int &= ~value; 315 break; 316 case 4: /* IntErrorClear */ 317 s->err_int &= ~value; 318 break; 319 case 8: /* SoftBReq */ 320 case 9: /* SoftSReq */ 321 case 10: /* SoftLBReq */ 322 case 11: /* SoftLSReq */ 323 /* ??? Implement these. */ 324 qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n"); 325 break; 326 case 12: /* Configuration */ 327 s->conf = value; 328 if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) { 329 qemu_log_mask(LOG_UNIMP, 330 "pl080_write: Big-endian DMA not implemented\n"); 331 } 332 pl080_run(s); 333 break; 334 case 13: /* Sync */ 335 s->sync = value; 336 break; 337 default: 338 bad_offset: 339 qemu_log_mask(LOG_GUEST_ERROR, 340 "pl080_write: Bad offset %x\n", (int)offset); 341 } 342 pl080_update(s); 343 } 344 345 static const MemoryRegionOps pl080_ops = { 346 .read = pl080_read, 347 .write = pl080_write, 348 .endianness = DEVICE_NATIVE_ENDIAN, 349 }; 350 351 static void pl080_reset(DeviceState *dev) 352 { 353 PL080State *s = PL080(dev); 354 int i; 355 356 s->tc_int = 0; 357 s->tc_mask = 0; 358 s->err_int = 0; 359 s->err_mask = 0; 360 s->conf = 0; 361 s->sync = 0; 362 s->req_single = 0; 363 s->req_burst = 0; 364 s->running = 0; 365 366 for (i = 0; i < s->nchannels; i++) { 367 s->chan[i].src = 0; 368 s->chan[i].dest = 0; 369 s->chan[i].lli = 0; 370 s->chan[i].ctrl = 0; 371 s->chan[i].conf = 0; 372 } 373 } 374 375 static void pl080_init(Object *obj) 376 { 377 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 378 PL080State *s = PL080(obj); 379 380 memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000); 381 sysbus_init_mmio(sbd, &s->iomem); 382 sysbus_init_irq(sbd, &s->irq); 383 sysbus_init_irq(sbd, &s->interr); 384 sysbus_init_irq(sbd, &s->inttc); 385 s->nchannels = 8; 386 } 387 388 static void pl080_realize(DeviceState *dev, Error **errp) 389 { 390 PL080State *s = PL080(dev); 391 392 if (!s->downstream) { 393 error_setg(errp, "PL080 'downstream' link not set"); 394 return; 395 } 396 397 address_space_init(&s->downstream_as, s->downstream, "pl080-downstream"); 398 } 399 400 static void pl081_init(Object *obj) 401 { 402 PL080State *s = PL080(obj); 403 404 s->nchannels = 2; 405 } 406 407 static Property pl080_properties[] = { 408 DEFINE_PROP_LINK("downstream", PL080State, downstream, 409 TYPE_MEMORY_REGION, MemoryRegion *), 410 DEFINE_PROP_END_OF_LIST(), 411 }; 412 413 static void pl080_class_init(ObjectClass *oc, void *data) 414 { 415 DeviceClass *dc = DEVICE_CLASS(oc); 416 417 dc->vmsd = &vmstate_pl080; 418 dc->realize = pl080_realize; 419 dc->props = pl080_properties; 420 dc->reset = pl080_reset; 421 } 422 423 static const TypeInfo pl080_info = { 424 .name = TYPE_PL080, 425 .parent = TYPE_SYS_BUS_DEVICE, 426 .instance_size = sizeof(PL080State), 427 .instance_init = pl080_init, 428 .class_init = pl080_class_init, 429 }; 430 431 static const TypeInfo pl081_info = { 432 .name = TYPE_PL081, 433 .parent = TYPE_PL080, 434 .instance_init = pl081_init, 435 }; 436 437 /* The PL080 and PL081 are the same except for the number of channels 438 they implement (8 and 2 respectively). */ 439 static void pl080_register_types(void) 440 { 441 type_register_static(&pl080_info); 442 type_register_static(&pl081_info); 443 } 444 445 type_init(pl080_register_types) 446