1 /* 2 * TI OMAP DMA gigacell. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu-common.h" 21 #include "qemu/timer.h" 22 #include "hw/arm/omap.h" 23 #include "hw/irq.h" 24 #include "hw/arm/soc_dma.h" 25 26 struct omap_dma_channel_s { 27 /* transfer data */ 28 int burst[2]; 29 int pack[2]; 30 int endian[2]; 31 int endian_lock[2]; 32 int translate[2]; 33 enum omap_dma_port port[2]; 34 hwaddr addr[2]; 35 omap_dma_addressing_t mode[2]; 36 uint32_t elements; 37 uint16_t frames; 38 int32_t frame_index[2]; 39 int16_t element_index[2]; 40 int data_type; 41 42 /* transfer type */ 43 int transparent_copy; 44 int constant_fill; 45 uint32_t color; 46 int prefetch; 47 48 /* auto init and linked channel data */ 49 int end_prog; 50 int repeat; 51 int auto_init; 52 int link_enabled; 53 int link_next_ch; 54 55 /* interruption data */ 56 int interrupts; 57 int status; 58 int cstatus; 59 60 /* state data */ 61 int active; 62 int enable; 63 int sync; 64 int src_sync; 65 int pending_request; 66 int waiting_end_prog; 67 uint16_t cpc; 68 int set_update; 69 70 /* sync type */ 71 int fs; 72 int bs; 73 74 /* compatibility */ 75 int omap_3_1_compatible_disable; 76 77 qemu_irq irq; 78 struct omap_dma_channel_s *sibling; 79 80 struct omap_dma_reg_set_s { 81 hwaddr src, dest; 82 int frame; 83 int element; 84 int pck_element; 85 int frame_delta[2]; 86 int elem_delta[2]; 87 int frames; 88 int elements; 89 int pck_elements; 90 } active_set; 91 92 struct soc_dma_ch_s *dma; 93 94 /* unused parameters */ 95 int write_mode; 96 int priority; 97 int interleave_disabled; 98 int type; 99 int suspend; 100 int buf_disable; 101 }; 102 103 struct omap_dma_s { 104 struct soc_dma_s *dma; 105 MemoryRegion iomem; 106 107 struct omap_mpu_state_s *mpu; 108 omap_clk clk; 109 qemu_irq irq[4]; 110 void (*intr_update)(struct omap_dma_s *s); 111 enum omap_dma_model model; 112 int omap_3_1_mapping_disabled; 113 114 uint32_t gcr; 115 uint32_t ocp; 116 uint32_t caps[5]; 117 uint32_t irqen[4]; 118 uint32_t irqstat[4]; 119 120 int chans; 121 struct omap_dma_channel_s ch[32]; 122 struct omap_dma_lcd_channel_s lcd_ch; 123 }; 124 125 /* Interrupts */ 126 #define TIMEOUT_INTR (1 << 0) 127 #define EVENT_DROP_INTR (1 << 1) 128 #define HALF_FRAME_INTR (1 << 2) 129 #define END_FRAME_INTR (1 << 3) 130 #define LAST_FRAME_INTR (1 << 4) 131 #define END_BLOCK_INTR (1 << 5) 132 #define SYNC (1 << 6) 133 #define END_PKT_INTR (1 << 7) 134 #define TRANS_ERR_INTR (1 << 8) 135 #define MISALIGN_INTR (1 << 11) 136 137 static inline void omap_dma_interrupts_update(struct omap_dma_s *s) 138 { 139 s->intr_update(s); 140 } 141 142 static void omap_dma_channel_load(struct omap_dma_channel_s *ch) 143 { 144 struct omap_dma_reg_set_s *a = &ch->active_set; 145 int i, normal; 146 int omap_3_1 = !ch->omap_3_1_compatible_disable; 147 148 /* 149 * TODO: verify address ranges and alignment 150 * TODO: port endianness 151 */ 152 153 a->src = ch->addr[0]; 154 a->dest = ch->addr[1]; 155 a->frames = ch->frames; 156 a->elements = ch->elements; 157 a->pck_elements = ch->frame_index[!ch->src_sync]; 158 a->frame = 0; 159 a->element = 0; 160 a->pck_element = 0; 161 162 if (unlikely(!ch->elements || !ch->frames)) { 163 printf("%s: bad DMA request\n", __FUNCTION__); 164 return; 165 } 166 167 for (i = 0; i < 2; i ++) 168 switch (ch->mode[i]) { 169 case constant: 170 a->elem_delta[i] = 0; 171 a->frame_delta[i] = 0; 172 break; 173 case post_incremented: 174 a->elem_delta[i] = ch->data_type; 175 a->frame_delta[i] = 0; 176 break; 177 case single_index: 178 a->elem_delta[i] = ch->data_type + 179 ch->element_index[omap_3_1 ? 0 : i] - 1; 180 a->frame_delta[i] = 0; 181 break; 182 case double_index: 183 a->elem_delta[i] = ch->data_type + 184 ch->element_index[omap_3_1 ? 0 : i] - 1; 185 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - 186 ch->element_index[omap_3_1 ? 0 : i]; 187 break; 188 default: 189 break; 190 } 191 192 normal = !ch->transparent_copy && !ch->constant_fill && 193 /* FIFO is big-endian so either (ch->endian[n] == 1) OR 194 * (ch->endian_lock[n] == 1) mean no endianism conversion. */ 195 (ch->endian[0] | ch->endian_lock[0]) == 196 (ch->endian[1] | ch->endian_lock[1]); 197 for (i = 0; i < 2; i ++) { 198 /* TODO: for a->frame_delta[i] > 0 still use the fast path, just 199 * limit min_elems in omap_dma_transfer_setup to the nearest frame 200 * end. */ 201 if (!a->elem_delta[i] && normal && 202 (a->frames == 1 || !a->frame_delta[i])) 203 ch->dma->type[i] = soc_dma_access_const; 204 else if (a->elem_delta[i] == ch->data_type && normal && 205 (a->frames == 1 || !a->frame_delta[i])) 206 ch->dma->type[i] = soc_dma_access_linear; 207 else 208 ch->dma->type[i] = soc_dma_access_other; 209 210 ch->dma->vaddr[i] = ch->addr[i]; 211 } 212 soc_dma_ch_update(ch->dma); 213 } 214 215 static void omap_dma_activate_channel(struct omap_dma_s *s, 216 struct omap_dma_channel_s *ch) 217 { 218 if (!ch->active) { 219 if (ch->set_update) { 220 /* It's not clear when the active set is supposed to be 221 * loaded from registers. We're already loading it when the 222 * channel is enabled, and for some guests this is not enough 223 * but that may be also because of a race condition (no 224 * delays in qemu) in the guest code, which we're just 225 * working around here. */ 226 omap_dma_channel_load(ch); 227 ch->set_update = 0; 228 } 229 230 ch->active = 1; 231 soc_dma_set_request(ch->dma, 1); 232 if (ch->sync) 233 ch->status |= SYNC; 234 } 235 } 236 237 static void omap_dma_deactivate_channel(struct omap_dma_s *s, 238 struct omap_dma_channel_s *ch) 239 { 240 /* Update cpc */ 241 ch->cpc = ch->active_set.dest & 0xffff; 242 243 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) { 244 /* Don't deactivate the channel */ 245 ch->pending_request = 0; 246 return; 247 } 248 249 /* Don't deactive the channel if it is synchronized and the DMA request is 250 active */ 251 if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync))) 252 return; 253 254 if (ch->active) { 255 ch->active = 0; 256 ch->status &= ~SYNC; 257 soc_dma_set_request(ch->dma, 0); 258 } 259 } 260 261 static void omap_dma_enable_channel(struct omap_dma_s *s, 262 struct omap_dma_channel_s *ch) 263 { 264 if (!ch->enable) { 265 ch->enable = 1; 266 ch->waiting_end_prog = 0; 267 omap_dma_channel_load(ch); 268 /* TODO: theoretically if ch->sync && ch->prefetch && 269 * !s->dma->drqbmp[ch->sync], we should also activate and fetch 270 * from source and then stall until signalled. */ 271 if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) { 272 omap_dma_activate_channel(s, ch); 273 } 274 } 275 } 276 277 static void omap_dma_disable_channel(struct omap_dma_s *s, 278 struct omap_dma_channel_s *ch) 279 { 280 if (ch->enable) { 281 ch->enable = 0; 282 /* Discard any pending request */ 283 ch->pending_request = 0; 284 omap_dma_deactivate_channel(s, ch); 285 } 286 } 287 288 static void omap_dma_channel_end_prog(struct omap_dma_s *s, 289 struct omap_dma_channel_s *ch) 290 { 291 if (ch->waiting_end_prog) { 292 ch->waiting_end_prog = 0; 293 if (!ch->sync || ch->pending_request) { 294 ch->pending_request = 0; 295 omap_dma_activate_channel(s, ch); 296 } 297 } 298 } 299 300 static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) 301 { 302 struct omap_dma_channel_s *ch = s->ch; 303 304 /* First three interrupts are shared between two channels each. */ 305 if (ch[0].status | ch[6].status) 306 qemu_irq_raise(ch[0].irq); 307 if (ch[1].status | ch[7].status) 308 qemu_irq_raise(ch[1].irq); 309 if (ch[2].status | ch[8].status) 310 qemu_irq_raise(ch[2].irq); 311 if (ch[3].status) 312 qemu_irq_raise(ch[3].irq); 313 if (ch[4].status) 314 qemu_irq_raise(ch[4].irq); 315 if (ch[5].status) 316 qemu_irq_raise(ch[5].irq); 317 } 318 319 static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) 320 { 321 struct omap_dma_channel_s *ch = s->ch; 322 int i; 323 324 for (i = s->chans; i; ch ++, i --) 325 if (ch->status) 326 qemu_irq_raise(ch->irq); 327 } 328 329 static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) 330 { 331 s->omap_3_1_mapping_disabled = 0; 332 s->chans = 9; 333 s->intr_update = omap_dma_interrupts_3_1_update; 334 } 335 336 static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) 337 { 338 s->omap_3_1_mapping_disabled = 1; 339 s->chans = 16; 340 s->intr_update = omap_dma_interrupts_3_2_update; 341 } 342 343 static void omap_dma_process_request(struct omap_dma_s *s, int request) 344 { 345 int channel; 346 int drop_event = 0; 347 struct omap_dma_channel_s *ch = s->ch; 348 349 for (channel = 0; channel < s->chans; channel ++, ch ++) { 350 if (ch->enable && ch->sync == request) { 351 if (!ch->active) 352 omap_dma_activate_channel(s, ch); 353 else if (!ch->pending_request) 354 ch->pending_request = 1; 355 else { 356 /* Request collision */ 357 /* Second request received while processing other request */ 358 ch->status |= EVENT_DROP_INTR; 359 drop_event = 1; 360 } 361 } 362 } 363 364 if (drop_event) 365 omap_dma_interrupts_update(s); 366 } 367 368 static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma) 369 { 370 uint8_t value[4]; 371 struct omap_dma_channel_s *ch = dma->opaque; 372 struct omap_dma_reg_set_s *a = &ch->active_set; 373 int bytes = dma->bytes; 374 #ifdef MULTI_REQ 375 uint16_t status = ch->status; 376 #endif 377 378 do { 379 /* Transfer a single element */ 380 /* FIXME: check the endianness */ 381 if (!ch->constant_fill) 382 cpu_physical_memory_read(a->src, value, ch->data_type); 383 else 384 *(uint32_t *) value = ch->color; 385 386 if (!ch->transparent_copy || *(uint32_t *) value != ch->color) 387 cpu_physical_memory_write(a->dest, value, ch->data_type); 388 389 a->src += a->elem_delta[0]; 390 a->dest += a->elem_delta[1]; 391 a->element ++; 392 393 #ifndef MULTI_REQ 394 if (a->element == a->elements) { 395 /* End of Frame */ 396 a->element = 0; 397 a->src += a->frame_delta[0]; 398 a->dest += a->frame_delta[1]; 399 a->frame ++; 400 401 /* If the channel is async, update cpc */ 402 if (!ch->sync) 403 ch->cpc = a->dest & 0xffff; 404 } 405 } while ((bytes -= ch->data_type)); 406 #else 407 /* If the channel is element synchronized, deactivate it */ 408 if (ch->sync && !ch->fs && !ch->bs) 409 omap_dma_deactivate_channel(s, ch); 410 411 /* If it is the last frame, set the LAST_FRAME interrupt */ 412 if (a->element == 1 && a->frame == a->frames - 1) 413 if (ch->interrupts & LAST_FRAME_INTR) 414 ch->status |= LAST_FRAME_INTR; 415 416 /* If the half of the frame was reached, set the HALF_FRAME 417 interrupt */ 418 if (a->element == (a->elements >> 1)) 419 if (ch->interrupts & HALF_FRAME_INTR) 420 ch->status |= HALF_FRAME_INTR; 421 422 if (ch->fs && ch->bs) { 423 a->pck_element ++; 424 /* Check if a full packet has beed transferred. */ 425 if (a->pck_element == a->pck_elements) { 426 a->pck_element = 0; 427 428 /* Set the END_PKT interrupt */ 429 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) 430 ch->status |= END_PKT_INTR; 431 432 /* If the channel is packet-synchronized, deactivate it */ 433 if (ch->sync) 434 omap_dma_deactivate_channel(s, ch); 435 } 436 } 437 438 if (a->element == a->elements) { 439 /* End of Frame */ 440 a->element = 0; 441 a->src += a->frame_delta[0]; 442 a->dest += a->frame_delta[1]; 443 a->frame ++; 444 445 /* If the channel is frame synchronized, deactivate it */ 446 if (ch->sync && ch->fs && !ch->bs) 447 omap_dma_deactivate_channel(s, ch); 448 449 /* If the channel is async, update cpc */ 450 if (!ch->sync) 451 ch->cpc = a->dest & 0xffff; 452 453 /* Set the END_FRAME interrupt */ 454 if (ch->interrupts & END_FRAME_INTR) 455 ch->status |= END_FRAME_INTR; 456 457 if (a->frame == a->frames) { 458 /* End of Block */ 459 /* Disable the channel */ 460 461 if (ch->omap_3_1_compatible_disable) { 462 omap_dma_disable_channel(s, ch); 463 if (ch->link_enabled) 464 omap_dma_enable_channel(s, 465 &s->ch[ch->link_next_ch]); 466 } else { 467 if (!ch->auto_init) 468 omap_dma_disable_channel(s, ch); 469 else if (ch->repeat || ch->end_prog) 470 omap_dma_channel_load(ch); 471 else { 472 ch->waiting_end_prog = 1; 473 omap_dma_deactivate_channel(s, ch); 474 } 475 } 476 477 if (ch->interrupts & END_BLOCK_INTR) 478 ch->status |= END_BLOCK_INTR; 479 } 480 } 481 } while (status == ch->status && ch->active); 482 483 omap_dma_interrupts_update(s); 484 #endif 485 } 486 487 enum { 488 omap_dma_intr_element_sync, 489 omap_dma_intr_last_frame, 490 omap_dma_intr_half_frame, 491 omap_dma_intr_frame, 492 omap_dma_intr_frame_sync, 493 omap_dma_intr_packet, 494 omap_dma_intr_packet_sync, 495 omap_dma_intr_block, 496 __omap_dma_intr_last, 497 }; 498 499 static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma) 500 { 501 struct omap_dma_port_if_s *src_p, *dest_p; 502 struct omap_dma_reg_set_s *a; 503 struct omap_dma_channel_s *ch = dma->opaque; 504 struct omap_dma_s *s = dma->dma->opaque; 505 int frames, min_elems, elements[__omap_dma_intr_last]; 506 507 a = &ch->active_set; 508 509 src_p = &s->mpu->port[ch->port[0]]; 510 dest_p = &s->mpu->port[ch->port[1]]; 511 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) || 512 (!dest_p->addr_valid(s->mpu, a->dest))) { 513 #if 0 514 /* Bus time-out */ 515 if (ch->interrupts & TIMEOUT_INTR) 516 ch->status |= TIMEOUT_INTR; 517 omap_dma_deactivate_channel(s, ch); 518 continue; 519 #endif 520 printf("%s: Bus time-out in DMA%i operation\n", 521 __FUNCTION__, dma->num); 522 } 523 524 min_elems = INT_MAX; 525 526 /* Check all the conditions that terminate the transfer starting 527 * with those that can occur the soonest. */ 528 #define INTR_CHECK(cond, id, nelements) \ 529 if (cond) { \ 530 elements[id] = nelements; \ 531 if (elements[id] < min_elems) \ 532 min_elems = elements[id]; \ 533 } else \ 534 elements[id] = INT_MAX; 535 536 /* Elements */ 537 INTR_CHECK( 538 ch->sync && !ch->fs && !ch->bs, 539 omap_dma_intr_element_sync, 540 1) 541 542 /* Frames */ 543 /* TODO: for transfers where entire frames can be read and written 544 * using memcpy() but a->frame_delta is non-zero, try to still do 545 * transfers using soc_dma but limit min_elems to a->elements - ... 546 * See also the TODO in omap_dma_channel_load. */ 547 INTR_CHECK( 548 (ch->interrupts & LAST_FRAME_INTR) && 549 ((a->frame < a->frames - 1) || !a->element), 550 omap_dma_intr_last_frame, 551 (a->frames - a->frame - 2) * a->elements + 552 (a->elements - a->element + 1)) 553 INTR_CHECK( 554 ch->interrupts & HALF_FRAME_INTR, 555 omap_dma_intr_half_frame, 556 (a->elements >> 1) + 557 (a->element >= (a->elements >> 1) ? a->elements : 0) - 558 a->element) 559 INTR_CHECK( 560 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR), 561 omap_dma_intr_frame, 562 a->elements - a->element) 563 INTR_CHECK( 564 ch->sync && ch->fs && !ch->bs, 565 omap_dma_intr_frame_sync, 566 a->elements - a->element) 567 568 /* Packets */ 569 INTR_CHECK( 570 ch->fs && ch->bs && 571 (ch->interrupts & END_PKT_INTR) && !ch->src_sync, 572 omap_dma_intr_packet, 573 a->pck_elements - a->pck_element) 574 INTR_CHECK( 575 ch->fs && ch->bs && ch->sync, 576 omap_dma_intr_packet_sync, 577 a->pck_elements - a->pck_element) 578 579 /* Blocks */ 580 INTR_CHECK( 581 1, 582 omap_dma_intr_block, 583 (a->frames - a->frame - 1) * a->elements + 584 (a->elements - a->element)) 585 586 dma->bytes = min_elems * ch->data_type; 587 588 /* Set appropriate interrupts and/or deactivate channels */ 589 590 #ifdef MULTI_REQ 591 /* TODO: should all of this only be done if dma->update, and otherwise 592 * inside omap_dma_transfer_generic below - check what's faster. */ 593 if (dma->update) { 594 #endif 595 596 /* If the channel is element synchronized, deactivate it */ 597 if (min_elems == elements[omap_dma_intr_element_sync]) 598 omap_dma_deactivate_channel(s, ch); 599 600 /* If it is the last frame, set the LAST_FRAME interrupt */ 601 if (min_elems == elements[omap_dma_intr_last_frame]) 602 ch->status |= LAST_FRAME_INTR; 603 604 /* If exactly half of the frame was reached, set the HALF_FRAME 605 interrupt */ 606 if (min_elems == elements[omap_dma_intr_half_frame]) 607 ch->status |= HALF_FRAME_INTR; 608 609 /* If a full packet has been transferred, set the END_PKT interrupt */ 610 if (min_elems == elements[omap_dma_intr_packet]) 611 ch->status |= END_PKT_INTR; 612 613 /* If the channel is packet-synchronized, deactivate it */ 614 if (min_elems == elements[omap_dma_intr_packet_sync]) 615 omap_dma_deactivate_channel(s, ch); 616 617 /* If the channel is frame synchronized, deactivate it */ 618 if (min_elems == elements[omap_dma_intr_frame_sync]) 619 omap_dma_deactivate_channel(s, ch); 620 621 /* Set the END_FRAME interrupt */ 622 if (min_elems == elements[omap_dma_intr_frame]) 623 ch->status |= END_FRAME_INTR; 624 625 if (min_elems == elements[omap_dma_intr_block]) { 626 /* End of Block */ 627 /* Disable the channel */ 628 629 if (ch->omap_3_1_compatible_disable) { 630 omap_dma_disable_channel(s, ch); 631 if (ch->link_enabled) 632 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]); 633 } else { 634 if (!ch->auto_init) 635 omap_dma_disable_channel(s, ch); 636 else if (ch->repeat || ch->end_prog) 637 omap_dma_channel_load(ch); 638 else { 639 ch->waiting_end_prog = 1; 640 omap_dma_deactivate_channel(s, ch); 641 } 642 } 643 644 if (ch->interrupts & END_BLOCK_INTR) 645 ch->status |= END_BLOCK_INTR; 646 } 647 648 /* Update packet number */ 649 if (ch->fs && ch->bs) { 650 a->pck_element += min_elems; 651 a->pck_element %= a->pck_elements; 652 } 653 654 /* TODO: check if we really need to update anything here or perhaps we 655 * can skip part of this. */ 656 #ifndef MULTI_REQ 657 if (dma->update) { 658 #endif 659 a->element += min_elems; 660 661 frames = a->element / a->elements; 662 a->element = a->element % a->elements; 663 a->frame += frames; 664 a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0]; 665 a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1]; 666 667 /* If the channel is async, update cpc */ 668 if (!ch->sync && frames) 669 ch->cpc = a->dest & 0xffff; 670 671 /* TODO: if the destination port is IMIF or EMIFF, set the dirty 672 * bits on it. */ 673 #ifndef MULTI_REQ 674 } 675 #else 676 } 677 #endif 678 679 omap_dma_interrupts_update(s); 680 } 681 682 void omap_dma_reset(struct soc_dma_s *dma) 683 { 684 int i; 685 struct omap_dma_s *s = dma->opaque; 686 687 soc_dma_reset(s->dma); 688 if (s->model < omap_dma_4) 689 s->gcr = 0x0004; 690 else 691 s->gcr = 0x00010010; 692 s->ocp = 0x00000000; 693 memset(&s->irqstat, 0, sizeof(s->irqstat)); 694 memset(&s->irqen, 0, sizeof(s->irqen)); 695 s->lcd_ch.src = emiff; 696 s->lcd_ch.condition = 0; 697 s->lcd_ch.interrupts = 0; 698 s->lcd_ch.dual = 0; 699 if (s->model < omap_dma_4) 700 omap_dma_enable_3_1_mapping(s); 701 for (i = 0; i < s->chans; i ++) { 702 s->ch[i].suspend = 0; 703 s->ch[i].prefetch = 0; 704 s->ch[i].buf_disable = 0; 705 s->ch[i].src_sync = 0; 706 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); 707 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); 708 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); 709 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); 710 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); 711 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); 712 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); 713 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); 714 s->ch[i].write_mode = 0; 715 s->ch[i].data_type = 0; 716 s->ch[i].transparent_copy = 0; 717 s->ch[i].constant_fill = 0; 718 s->ch[i].color = 0x00000000; 719 s->ch[i].end_prog = 0; 720 s->ch[i].repeat = 0; 721 s->ch[i].auto_init = 0; 722 s->ch[i].link_enabled = 0; 723 if (s->model < omap_dma_4) 724 s->ch[i].interrupts = 0x0003; 725 else 726 s->ch[i].interrupts = 0x0000; 727 s->ch[i].status = 0; 728 s->ch[i].cstatus = 0; 729 s->ch[i].active = 0; 730 s->ch[i].enable = 0; 731 s->ch[i].sync = 0; 732 s->ch[i].pending_request = 0; 733 s->ch[i].waiting_end_prog = 0; 734 s->ch[i].cpc = 0x0000; 735 s->ch[i].fs = 0; 736 s->ch[i].bs = 0; 737 s->ch[i].omap_3_1_compatible_disable = 0; 738 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); 739 s->ch[i].priority = 0; 740 s->ch[i].interleave_disabled = 0; 741 s->ch[i].type = 0; 742 } 743 } 744 745 static int omap_dma_ch_reg_read(struct omap_dma_s *s, 746 struct omap_dma_channel_s *ch, int reg, uint16_t *value) 747 { 748 switch (reg) { 749 case 0x00: /* SYS_DMA_CSDP_CH0 */ 750 *value = (ch->burst[1] << 14) | 751 (ch->pack[1] << 13) | 752 (ch->port[1] << 9) | 753 (ch->burst[0] << 7) | 754 (ch->pack[0] << 6) | 755 (ch->port[0] << 2) | 756 (ch->data_type >> 1); 757 break; 758 759 case 0x02: /* SYS_DMA_CCR_CH0 */ 760 if (s->model <= omap_dma_3_1) 761 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ 762 else 763 *value = ch->omap_3_1_compatible_disable << 10; 764 *value |= (ch->mode[1] << 14) | 765 (ch->mode[0] << 12) | 766 (ch->end_prog << 11) | 767 (ch->repeat << 9) | 768 (ch->auto_init << 8) | 769 (ch->enable << 7) | 770 (ch->priority << 6) | 771 (ch->fs << 5) | ch->sync; 772 break; 773 774 case 0x04: /* SYS_DMA_CICR_CH0 */ 775 *value = ch->interrupts; 776 break; 777 778 case 0x06: /* SYS_DMA_CSR_CH0 */ 779 *value = ch->status; 780 ch->status &= SYNC; 781 if (!ch->omap_3_1_compatible_disable && ch->sibling) { 782 *value |= (ch->sibling->status & 0x3f) << 6; 783 ch->sibling->status &= SYNC; 784 } 785 qemu_irq_lower(ch->irq); 786 break; 787 788 case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 789 *value = ch->addr[0] & 0x0000ffff; 790 break; 791 792 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 793 *value = ch->addr[0] >> 16; 794 break; 795 796 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 797 *value = ch->addr[1] & 0x0000ffff; 798 break; 799 800 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 801 *value = ch->addr[1] >> 16; 802 break; 803 804 case 0x10: /* SYS_DMA_CEN_CH0 */ 805 *value = ch->elements; 806 break; 807 808 case 0x12: /* SYS_DMA_CFN_CH0 */ 809 *value = ch->frames; 810 break; 811 812 case 0x14: /* SYS_DMA_CFI_CH0 */ 813 *value = ch->frame_index[0]; 814 break; 815 816 case 0x16: /* SYS_DMA_CEI_CH0 */ 817 *value = ch->element_index[0]; 818 break; 819 820 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 821 if (ch->omap_3_1_compatible_disable) 822 *value = ch->active_set.src & 0xffff; /* CSAC */ 823 else 824 *value = ch->cpc; 825 break; 826 827 case 0x1a: /* DMA_CDAC */ 828 *value = ch->active_set.dest & 0xffff; /* CDAC */ 829 break; 830 831 case 0x1c: /* DMA_CDEI */ 832 *value = ch->element_index[1]; 833 break; 834 835 case 0x1e: /* DMA_CDFI */ 836 *value = ch->frame_index[1]; 837 break; 838 839 case 0x20: /* DMA_COLOR_L */ 840 *value = ch->color & 0xffff; 841 break; 842 843 case 0x22: /* DMA_COLOR_U */ 844 *value = ch->color >> 16; 845 break; 846 847 case 0x24: /* DMA_CCR2 */ 848 *value = (ch->bs << 2) | 849 (ch->transparent_copy << 1) | 850 ch->constant_fill; 851 break; 852 853 case 0x28: /* DMA_CLNK_CTRL */ 854 *value = (ch->link_enabled << 15) | 855 (ch->link_next_ch & 0xf); 856 break; 857 858 case 0x2a: /* DMA_LCH_CTRL */ 859 *value = (ch->interleave_disabled << 15) | 860 ch->type; 861 break; 862 863 default: 864 return 1; 865 } 866 return 0; 867 } 868 869 static int omap_dma_ch_reg_write(struct omap_dma_s *s, 870 struct omap_dma_channel_s *ch, int reg, uint16_t value) 871 { 872 switch (reg) { 873 case 0x00: /* SYS_DMA_CSDP_CH0 */ 874 ch->burst[1] = (value & 0xc000) >> 14; 875 ch->pack[1] = (value & 0x2000) >> 13; 876 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); 877 ch->burst[0] = (value & 0x0180) >> 7; 878 ch->pack[0] = (value & 0x0040) >> 6; 879 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); 880 ch->data_type = 1 << (value & 3); 881 if (ch->port[0] >= __omap_dma_port_last) 882 printf("%s: invalid DMA port %i\n", __FUNCTION__, 883 ch->port[0]); 884 if (ch->port[1] >= __omap_dma_port_last) 885 printf("%s: invalid DMA port %i\n", __FUNCTION__, 886 ch->port[1]); 887 if ((value & 3) == 3) 888 printf("%s: bad data_type for DMA channel\n", __FUNCTION__); 889 break; 890 891 case 0x02: /* SYS_DMA_CCR_CH0 */ 892 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); 893 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); 894 ch->end_prog = (value & 0x0800) >> 11; 895 if (s->model >= omap_dma_3_2) 896 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; 897 ch->repeat = (value & 0x0200) >> 9; 898 ch->auto_init = (value & 0x0100) >> 8; 899 ch->priority = (value & 0x0040) >> 6; 900 ch->fs = (value & 0x0020) >> 5; 901 ch->sync = value & 0x001f; 902 903 if (value & 0x0080) 904 omap_dma_enable_channel(s, ch); 905 else 906 omap_dma_disable_channel(s, ch); 907 908 if (ch->end_prog) 909 omap_dma_channel_end_prog(s, ch); 910 911 break; 912 913 case 0x04: /* SYS_DMA_CICR_CH0 */ 914 ch->interrupts = value & 0x3f; 915 break; 916 917 case 0x06: /* SYS_DMA_CSR_CH0 */ 918 OMAP_RO_REG((hwaddr) reg); 919 break; 920 921 case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 922 ch->addr[0] &= 0xffff0000; 923 ch->addr[0] |= value; 924 break; 925 926 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 927 ch->addr[0] &= 0x0000ffff; 928 ch->addr[0] |= (uint32_t) value << 16; 929 break; 930 931 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 932 ch->addr[1] &= 0xffff0000; 933 ch->addr[1] |= value; 934 break; 935 936 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 937 ch->addr[1] &= 0x0000ffff; 938 ch->addr[1] |= (uint32_t) value << 16; 939 break; 940 941 case 0x10: /* SYS_DMA_CEN_CH0 */ 942 ch->elements = value; 943 break; 944 945 case 0x12: /* SYS_DMA_CFN_CH0 */ 946 ch->frames = value; 947 break; 948 949 case 0x14: /* SYS_DMA_CFI_CH0 */ 950 ch->frame_index[0] = (int16_t) value; 951 break; 952 953 case 0x16: /* SYS_DMA_CEI_CH0 */ 954 ch->element_index[0] = (int16_t) value; 955 break; 956 957 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 958 OMAP_RO_REG((hwaddr) reg); 959 break; 960 961 case 0x1c: /* DMA_CDEI */ 962 ch->element_index[1] = (int16_t) value; 963 break; 964 965 case 0x1e: /* DMA_CDFI */ 966 ch->frame_index[1] = (int16_t) value; 967 break; 968 969 case 0x20: /* DMA_COLOR_L */ 970 ch->color &= 0xffff0000; 971 ch->color |= value; 972 break; 973 974 case 0x22: /* DMA_COLOR_U */ 975 ch->color &= 0xffff; 976 ch->color |= (uint32_t)value << 16; 977 break; 978 979 case 0x24: /* DMA_CCR2 */ 980 ch->bs = (value >> 2) & 0x1; 981 ch->transparent_copy = (value >> 1) & 0x1; 982 ch->constant_fill = value & 0x1; 983 break; 984 985 case 0x28: /* DMA_CLNK_CTRL */ 986 ch->link_enabled = (value >> 15) & 0x1; 987 if (value & (1 << 14)) { /* Stop_Lnk */ 988 ch->link_enabled = 0; 989 omap_dma_disable_channel(s, ch); 990 } 991 ch->link_next_ch = value & 0x1f; 992 break; 993 994 case 0x2a: /* DMA_LCH_CTRL */ 995 ch->interleave_disabled = (value >> 15) & 0x1; 996 ch->type = value & 0xf; 997 break; 998 999 default: 1000 return 1; 1001 } 1002 return 0; 1003 } 1004 1005 static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, 1006 uint16_t value) 1007 { 1008 switch (offset) { 1009 case 0xbc0: /* DMA_LCD_CSDP */ 1010 s->brust_f2 = (value >> 14) & 0x3; 1011 s->pack_f2 = (value >> 13) & 0x1; 1012 s->data_type_f2 = (1 << ((value >> 11) & 0x3)); 1013 s->brust_f1 = (value >> 7) & 0x3; 1014 s->pack_f1 = (value >> 6) & 0x1; 1015 s->data_type_f1 = (1 << ((value >> 0) & 0x3)); 1016 break; 1017 1018 case 0xbc2: /* DMA_LCD_CCR */ 1019 s->mode_f2 = (value >> 14) & 0x3; 1020 s->mode_f1 = (value >> 12) & 0x3; 1021 s->end_prog = (value >> 11) & 0x1; 1022 s->omap_3_1_compatible_disable = (value >> 10) & 0x1; 1023 s->repeat = (value >> 9) & 0x1; 1024 s->auto_init = (value >> 8) & 0x1; 1025 s->running = (value >> 7) & 0x1; 1026 s->priority = (value >> 6) & 0x1; 1027 s->bs = (value >> 4) & 0x1; 1028 break; 1029 1030 case 0xbc4: /* DMA_LCD_CTRL */ 1031 s->dst = (value >> 8) & 0x1; 1032 s->src = ((value >> 6) & 0x3) << 1; 1033 s->condition = 0; 1034 /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1035 s->interrupts = (value >> 1) & 1; 1036 s->dual = value & 1; 1037 break; 1038 1039 case 0xbc8: /* TOP_B1_L */ 1040 s->src_f1_top &= 0xffff0000; 1041 s->src_f1_top |= 0x0000ffff & value; 1042 break; 1043 1044 case 0xbca: /* TOP_B1_U */ 1045 s->src_f1_top &= 0x0000ffff; 1046 s->src_f1_top |= (uint32_t)value << 16; 1047 break; 1048 1049 case 0xbcc: /* BOT_B1_L */ 1050 s->src_f1_bottom &= 0xffff0000; 1051 s->src_f1_bottom |= 0x0000ffff & value; 1052 break; 1053 1054 case 0xbce: /* BOT_B1_U */ 1055 s->src_f1_bottom &= 0x0000ffff; 1056 s->src_f1_bottom |= (uint32_t) value << 16; 1057 break; 1058 1059 case 0xbd0: /* TOP_B2_L */ 1060 s->src_f2_top &= 0xffff0000; 1061 s->src_f2_top |= 0x0000ffff & value; 1062 break; 1063 1064 case 0xbd2: /* TOP_B2_U */ 1065 s->src_f2_top &= 0x0000ffff; 1066 s->src_f2_top |= (uint32_t) value << 16; 1067 break; 1068 1069 case 0xbd4: /* BOT_B2_L */ 1070 s->src_f2_bottom &= 0xffff0000; 1071 s->src_f2_bottom |= 0x0000ffff & value; 1072 break; 1073 1074 case 0xbd6: /* BOT_B2_U */ 1075 s->src_f2_bottom &= 0x0000ffff; 1076 s->src_f2_bottom |= (uint32_t) value << 16; 1077 break; 1078 1079 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1080 s->element_index_f1 = value; 1081 break; 1082 1083 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1084 s->frame_index_f1 &= 0xffff0000; 1085 s->frame_index_f1 |= 0x0000ffff & value; 1086 break; 1087 1088 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1089 s->frame_index_f1 &= 0x0000ffff; 1090 s->frame_index_f1 |= (uint32_t) value << 16; 1091 break; 1092 1093 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1094 s->element_index_f2 = value; 1095 break; 1096 1097 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1098 s->frame_index_f2 &= 0xffff0000; 1099 s->frame_index_f2 |= 0x0000ffff & value; 1100 break; 1101 1102 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1103 s->frame_index_f2 &= 0x0000ffff; 1104 s->frame_index_f2 |= (uint32_t) value << 16; 1105 break; 1106 1107 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1108 s->elements_f1 = value; 1109 break; 1110 1111 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1112 s->frames_f1 = value; 1113 break; 1114 1115 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1116 s->elements_f2 = value; 1117 break; 1118 1119 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1120 s->frames_f2 = value; 1121 break; 1122 1123 case 0xbea: /* DMA_LCD_LCH_CTRL */ 1124 s->lch_type = value & 0xf; 1125 break; 1126 1127 default: 1128 return 1; 1129 } 1130 return 0; 1131 } 1132 1133 static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, 1134 uint16_t *ret) 1135 { 1136 switch (offset) { 1137 case 0xbc0: /* DMA_LCD_CSDP */ 1138 *ret = (s->brust_f2 << 14) | 1139 (s->pack_f2 << 13) | 1140 ((s->data_type_f2 >> 1) << 11) | 1141 (s->brust_f1 << 7) | 1142 (s->pack_f1 << 6) | 1143 ((s->data_type_f1 >> 1) << 0); 1144 break; 1145 1146 case 0xbc2: /* DMA_LCD_CCR */ 1147 *ret = (s->mode_f2 << 14) | 1148 (s->mode_f1 << 12) | 1149 (s->end_prog << 11) | 1150 (s->omap_3_1_compatible_disable << 10) | 1151 (s->repeat << 9) | 1152 (s->auto_init << 8) | 1153 (s->running << 7) | 1154 (s->priority << 6) | 1155 (s->bs << 4); 1156 break; 1157 1158 case 0xbc4: /* DMA_LCD_CTRL */ 1159 qemu_irq_lower(s->irq); 1160 *ret = (s->dst << 8) | 1161 ((s->src & 0x6) << 5) | 1162 (s->condition << 3) | 1163 (s->interrupts << 1) | 1164 s->dual; 1165 break; 1166 1167 case 0xbc8: /* TOP_B1_L */ 1168 *ret = s->src_f1_top & 0xffff; 1169 break; 1170 1171 case 0xbca: /* TOP_B1_U */ 1172 *ret = s->src_f1_top >> 16; 1173 break; 1174 1175 case 0xbcc: /* BOT_B1_L */ 1176 *ret = s->src_f1_bottom & 0xffff; 1177 break; 1178 1179 case 0xbce: /* BOT_B1_U */ 1180 *ret = s->src_f1_bottom >> 16; 1181 break; 1182 1183 case 0xbd0: /* TOP_B2_L */ 1184 *ret = s->src_f2_top & 0xffff; 1185 break; 1186 1187 case 0xbd2: /* TOP_B2_U */ 1188 *ret = s->src_f2_top >> 16; 1189 break; 1190 1191 case 0xbd4: /* BOT_B2_L */ 1192 *ret = s->src_f2_bottom & 0xffff; 1193 break; 1194 1195 case 0xbd6: /* BOT_B2_U */ 1196 *ret = s->src_f2_bottom >> 16; 1197 break; 1198 1199 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1200 *ret = s->element_index_f1; 1201 break; 1202 1203 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1204 *ret = s->frame_index_f1 & 0xffff; 1205 break; 1206 1207 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1208 *ret = s->frame_index_f1 >> 16; 1209 break; 1210 1211 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1212 *ret = s->element_index_f2; 1213 break; 1214 1215 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1216 *ret = s->frame_index_f2 & 0xffff; 1217 break; 1218 1219 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1220 *ret = s->frame_index_f2 >> 16; 1221 break; 1222 1223 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1224 *ret = s->elements_f1; 1225 break; 1226 1227 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1228 *ret = s->frames_f1; 1229 break; 1230 1231 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1232 *ret = s->elements_f2; 1233 break; 1234 1235 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1236 *ret = s->frames_f2; 1237 break; 1238 1239 case 0xbea: /* DMA_LCD_LCH_CTRL */ 1240 *ret = s->lch_type; 1241 break; 1242 1243 default: 1244 return 1; 1245 } 1246 return 0; 1247 } 1248 1249 static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, 1250 uint16_t value) 1251 { 1252 switch (offset) { 1253 case 0x300: /* SYS_DMA_LCD_CTRL */ 1254 s->src = (value & 0x40) ? imif : emiff; 1255 s->condition = 0; 1256 /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1257 s->interrupts = (value >> 1) & 1; 1258 s->dual = value & 1; 1259 break; 1260 1261 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1262 s->src_f1_top &= 0xffff0000; 1263 s->src_f1_top |= 0x0000ffff & value; 1264 break; 1265 1266 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1267 s->src_f1_top &= 0x0000ffff; 1268 s->src_f1_top |= (uint32_t)value << 16; 1269 break; 1270 1271 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1272 s->src_f1_bottom &= 0xffff0000; 1273 s->src_f1_bottom |= 0x0000ffff & value; 1274 break; 1275 1276 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1277 s->src_f1_bottom &= 0x0000ffff; 1278 s->src_f1_bottom |= (uint32_t)value << 16; 1279 break; 1280 1281 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1282 s->src_f2_top &= 0xffff0000; 1283 s->src_f2_top |= 0x0000ffff & value; 1284 break; 1285 1286 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1287 s->src_f2_top &= 0x0000ffff; 1288 s->src_f2_top |= (uint32_t)value << 16; 1289 break; 1290 1291 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1292 s->src_f2_bottom &= 0xffff0000; 1293 s->src_f2_bottom |= 0x0000ffff & value; 1294 break; 1295 1296 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1297 s->src_f2_bottom &= 0x0000ffff; 1298 s->src_f2_bottom |= (uint32_t)value << 16; 1299 break; 1300 1301 default: 1302 return 1; 1303 } 1304 return 0; 1305 } 1306 1307 static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, 1308 uint16_t *ret) 1309 { 1310 int i; 1311 1312 switch (offset) { 1313 case 0x300: /* SYS_DMA_LCD_CTRL */ 1314 i = s->condition; 1315 s->condition = 0; 1316 qemu_irq_lower(s->irq); 1317 *ret = ((s->src == imif) << 6) | (i << 3) | 1318 (s->interrupts << 1) | s->dual; 1319 break; 1320 1321 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1322 *ret = s->src_f1_top & 0xffff; 1323 break; 1324 1325 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1326 *ret = s->src_f1_top >> 16; 1327 break; 1328 1329 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1330 *ret = s->src_f1_bottom & 0xffff; 1331 break; 1332 1333 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1334 *ret = s->src_f1_bottom >> 16; 1335 break; 1336 1337 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1338 *ret = s->src_f2_top & 0xffff; 1339 break; 1340 1341 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1342 *ret = s->src_f2_top >> 16; 1343 break; 1344 1345 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1346 *ret = s->src_f2_bottom & 0xffff; 1347 break; 1348 1349 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1350 *ret = s->src_f2_bottom >> 16; 1351 break; 1352 1353 default: 1354 return 1; 1355 } 1356 return 0; 1357 } 1358 1359 static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) 1360 { 1361 switch (offset) { 1362 case 0x400: /* SYS_DMA_GCR */ 1363 s->gcr = value; 1364 break; 1365 1366 case 0x404: /* DMA_GSCR */ 1367 if (value & 0x8) 1368 omap_dma_disable_3_1_mapping(s); 1369 else 1370 omap_dma_enable_3_1_mapping(s); 1371 break; 1372 1373 case 0x408: /* DMA_GRST */ 1374 if (value & 0x1) 1375 omap_dma_reset(s->dma); 1376 break; 1377 1378 default: 1379 return 1; 1380 } 1381 return 0; 1382 } 1383 1384 static int omap_dma_sys_read(struct omap_dma_s *s, int offset, 1385 uint16_t *ret) 1386 { 1387 switch (offset) { 1388 case 0x400: /* SYS_DMA_GCR */ 1389 *ret = s->gcr; 1390 break; 1391 1392 case 0x404: /* DMA_GSCR */ 1393 *ret = s->omap_3_1_mapping_disabled << 3; 1394 break; 1395 1396 case 0x408: /* DMA_GRST */ 1397 *ret = 0; 1398 break; 1399 1400 case 0x442: /* DMA_HW_ID */ 1401 case 0x444: /* DMA_PCh2_ID */ 1402 case 0x446: /* DMA_PCh0_ID */ 1403 case 0x448: /* DMA_PCh1_ID */ 1404 case 0x44a: /* DMA_PChG_ID */ 1405 case 0x44c: /* DMA_PChD_ID */ 1406 *ret = 1; 1407 break; 1408 1409 case 0x44e: /* DMA_CAPS_0_U */ 1410 *ret = (s->caps[0] >> 16) & 0xffff; 1411 break; 1412 case 0x450: /* DMA_CAPS_0_L */ 1413 *ret = (s->caps[0] >> 0) & 0xffff; 1414 break; 1415 1416 case 0x452: /* DMA_CAPS_1_U */ 1417 *ret = (s->caps[1] >> 16) & 0xffff; 1418 break; 1419 case 0x454: /* DMA_CAPS_1_L */ 1420 *ret = (s->caps[1] >> 0) & 0xffff; 1421 break; 1422 1423 case 0x456: /* DMA_CAPS_2 */ 1424 *ret = s->caps[2]; 1425 break; 1426 1427 case 0x458: /* DMA_CAPS_3 */ 1428 *ret = s->caps[3]; 1429 break; 1430 1431 case 0x45a: /* DMA_CAPS_4 */ 1432 *ret = s->caps[4]; 1433 break; 1434 1435 case 0x460: /* DMA_PCh2_SR */ 1436 case 0x480: /* DMA_PCh0_SR */ 1437 case 0x482: /* DMA_PCh1_SR */ 1438 case 0x4c0: /* DMA_PChD_SR_0 */ 1439 printf("%s: Physical Channel Status Registers not implemented.\n", 1440 __FUNCTION__); 1441 *ret = 0xff; 1442 break; 1443 1444 default: 1445 return 1; 1446 } 1447 return 0; 1448 } 1449 1450 static uint64_t omap_dma_read(void *opaque, hwaddr addr, 1451 unsigned size) 1452 { 1453 struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1454 int reg, ch; 1455 uint16_t ret; 1456 1457 if (size != 2) { 1458 return omap_badwidth_read16(opaque, addr); 1459 } 1460 1461 switch (addr) { 1462 case 0x300 ... 0x3fe: 1463 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1464 if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret)) 1465 break; 1466 return ret; 1467 } 1468 /* Fall through. */ 1469 case 0x000 ... 0x2fe: 1470 reg = addr & 0x3f; 1471 ch = (addr >> 6) & 0x0f; 1472 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret)) 1473 break; 1474 return ret; 1475 1476 case 0x404 ... 0x4fe: 1477 if (s->model <= omap_dma_3_1) 1478 break; 1479 /* Fall through. */ 1480 case 0x400: 1481 if (omap_dma_sys_read(s, addr, &ret)) 1482 break; 1483 return ret; 1484 1485 case 0xb00 ... 0xbfe: 1486 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1487 if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret)) 1488 break; 1489 return ret; 1490 } 1491 break; 1492 } 1493 1494 OMAP_BAD_REG(addr); 1495 return 0; 1496 } 1497 1498 static void omap_dma_write(void *opaque, hwaddr addr, 1499 uint64_t value, unsigned size) 1500 { 1501 struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1502 int reg, ch; 1503 1504 if (size != 2) { 1505 omap_badwidth_write16(opaque, addr, value); 1506 return; 1507 } 1508 1509 switch (addr) { 1510 case 0x300 ... 0x3fe: 1511 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1512 if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value)) 1513 break; 1514 return; 1515 } 1516 /* Fall through. */ 1517 case 0x000 ... 0x2fe: 1518 reg = addr & 0x3f; 1519 ch = (addr >> 6) & 0x0f; 1520 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value)) 1521 break; 1522 return; 1523 1524 case 0x404 ... 0x4fe: 1525 if (s->model <= omap_dma_3_1) 1526 break; 1527 case 0x400: 1528 /* Fall through. */ 1529 if (omap_dma_sys_write(s, addr, value)) 1530 break; 1531 return; 1532 1533 case 0xb00 ... 0xbfe: 1534 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1535 if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value)) 1536 break; 1537 return; 1538 } 1539 break; 1540 } 1541 1542 OMAP_BAD_REG(addr); 1543 } 1544 1545 static const MemoryRegionOps omap_dma_ops = { 1546 .read = omap_dma_read, 1547 .write = omap_dma_write, 1548 .endianness = DEVICE_NATIVE_ENDIAN, 1549 }; 1550 1551 static void omap_dma_request(void *opaque, int drq, int req) 1552 { 1553 struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1554 /* The request pins are level triggered in QEMU. */ 1555 if (req) { 1556 if (~s->dma->drqbmp & (1ULL << drq)) { 1557 s->dma->drqbmp |= 1ULL << drq; 1558 omap_dma_process_request(s, drq); 1559 } 1560 } else 1561 s->dma->drqbmp &= ~(1ULL << drq); 1562 } 1563 1564 /* XXX: this won't be needed once soc_dma knows about clocks. */ 1565 static void omap_dma_clk_update(void *opaque, int line, int on) 1566 { 1567 struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1568 int i; 1569 1570 s->dma->freq = omap_clk_getrate(s->clk); 1571 1572 for (i = 0; i < s->chans; i ++) 1573 if (s->ch[i].active) 1574 soc_dma_set_request(s->ch[i].dma, on); 1575 } 1576 1577 static void omap_dma_setcaps(struct omap_dma_s *s) 1578 { 1579 switch (s->model) { 1580 default: 1581 case omap_dma_3_1: 1582 break; 1583 case omap_dma_3_2: 1584 case omap_dma_4: 1585 /* XXX Only available for sDMA */ 1586 s->caps[0] = 1587 (1 << 19) | /* Constant Fill Capability */ 1588 (1 << 18); /* Transparent BLT Capability */ 1589 s->caps[1] = 1590 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ 1591 s->caps[2] = 1592 (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ 1593 (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ 1594 (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ 1595 (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ 1596 (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ 1597 (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ 1598 (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ 1599 (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ 1600 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ 1601 s->caps[3] = 1602 (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ 1603 (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ 1604 (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ 1605 (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ 1606 (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ 1607 (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ 1608 (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ 1609 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ 1610 s->caps[4] = 1611 (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ 1612 (1 << 6) | /* SYNC_STATUS_CPBLTY */ 1613 (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ 1614 (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ 1615 (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ 1616 (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ 1617 (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ 1618 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ 1619 break; 1620 } 1621 } 1622 1623 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 1624 MemoryRegion *sysmem, 1625 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 1626 enum omap_dma_model model) 1627 { 1628 int num_irqs, memsize, i; 1629 struct omap_dma_s *s = (struct omap_dma_s *) 1630 g_malloc0(sizeof(struct omap_dma_s)); 1631 1632 if (model <= omap_dma_3_1) { 1633 num_irqs = 6; 1634 memsize = 0x800; 1635 } else { 1636 num_irqs = 16; 1637 memsize = 0xc00; 1638 } 1639 s->model = model; 1640 s->mpu = mpu; 1641 s->clk = clk; 1642 s->lcd_ch.irq = lcd_irq; 1643 s->lcd_ch.mpu = mpu; 1644 1645 s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16); 1646 s->dma->freq = omap_clk_getrate(clk); 1647 s->dma->transfer_fn = omap_dma_transfer_generic; 1648 s->dma->setup_fn = omap_dma_transfer_setup; 1649 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32); 1650 s->dma->opaque = s; 1651 1652 while (num_irqs --) 1653 s->ch[num_irqs].irq = irqs[num_irqs]; 1654 for (i = 0; i < 3; i ++) { 1655 s->ch[i].sibling = &s->ch[i + 6]; 1656 s->ch[i + 6].sibling = &s->ch[i]; 1657 } 1658 for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) { 1659 s->ch[i].dma = &s->dma->ch[i]; 1660 s->dma->ch[i].opaque = &s->ch[i]; 1661 } 1662 1663 omap_dma_setcaps(s); 1664 omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0)); 1665 omap_dma_reset(s->dma); 1666 omap_dma_clk_update(s, 0, 1); 1667 1668 memory_region_init_io(&s->iomem, NULL, &omap_dma_ops, s, "omap.dma", memsize); 1669 memory_region_add_subregion(sysmem, base, &s->iomem); 1670 1671 mpu->drq = s->dma->drq; 1672 1673 return s->dma; 1674 } 1675 1676 static void omap_dma_interrupts_4_update(struct omap_dma_s *s) 1677 { 1678 struct omap_dma_channel_s *ch = s->ch; 1679 uint32_t bmp, bit; 1680 1681 for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) 1682 if (ch->status) { 1683 bmp |= bit; 1684 ch->cstatus |= ch->status; 1685 ch->status = 0; 1686 } 1687 if ((s->irqstat[0] |= s->irqen[0] & bmp)) 1688 qemu_irq_raise(s->irq[0]); 1689 if ((s->irqstat[1] |= s->irqen[1] & bmp)) 1690 qemu_irq_raise(s->irq[1]); 1691 if ((s->irqstat[2] |= s->irqen[2] & bmp)) 1692 qemu_irq_raise(s->irq[2]); 1693 if ((s->irqstat[3] |= s->irqen[3] & bmp)) 1694 qemu_irq_raise(s->irq[3]); 1695 } 1696 1697 static uint64_t omap_dma4_read(void *opaque, hwaddr addr, 1698 unsigned size) 1699 { 1700 struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1701 int irqn = 0, chnum; 1702 struct omap_dma_channel_s *ch; 1703 1704 if (size == 1) { 1705 return omap_badwidth_read16(opaque, addr); 1706 } 1707 1708 switch (addr) { 1709 case 0x00: /* DMA4_REVISION */ 1710 return 0x40; 1711 1712 case 0x14: /* DMA4_IRQSTATUS_L3 */ 1713 irqn ++; 1714 /* fall through */ 1715 case 0x10: /* DMA4_IRQSTATUS_L2 */ 1716 irqn ++; 1717 /* fall through */ 1718 case 0x0c: /* DMA4_IRQSTATUS_L1 */ 1719 irqn ++; 1720 /* fall through */ 1721 case 0x08: /* DMA4_IRQSTATUS_L0 */ 1722 return s->irqstat[irqn]; 1723 1724 case 0x24: /* DMA4_IRQENABLE_L3 */ 1725 irqn ++; 1726 /* fall through */ 1727 case 0x20: /* DMA4_IRQENABLE_L2 */ 1728 irqn ++; 1729 /* fall through */ 1730 case 0x1c: /* DMA4_IRQENABLE_L1 */ 1731 irqn ++; 1732 /* fall through */ 1733 case 0x18: /* DMA4_IRQENABLE_L0 */ 1734 return s->irqen[irqn]; 1735 1736 case 0x28: /* DMA4_SYSSTATUS */ 1737 return 1; /* RESETDONE */ 1738 1739 case 0x2c: /* DMA4_OCP_SYSCONFIG */ 1740 return s->ocp; 1741 1742 case 0x64: /* DMA4_CAPS_0 */ 1743 return s->caps[0]; 1744 case 0x6c: /* DMA4_CAPS_2 */ 1745 return s->caps[2]; 1746 case 0x70: /* DMA4_CAPS_3 */ 1747 return s->caps[3]; 1748 case 0x74: /* DMA4_CAPS_4 */ 1749 return s->caps[4]; 1750 1751 case 0x78: /* DMA4_GCR */ 1752 return s->gcr; 1753 1754 case 0x80 ... 0xfff: 1755 addr -= 0x80; 1756 chnum = addr / 0x60; 1757 ch = s->ch + chnum; 1758 addr -= chnum * 0x60; 1759 break; 1760 1761 default: 1762 OMAP_BAD_REG(addr); 1763 return 0; 1764 } 1765 1766 /* Per-channel registers */ 1767 switch (addr) { 1768 case 0x00: /* DMA4_CCR */ 1769 return (ch->buf_disable << 25) | 1770 (ch->src_sync << 24) | 1771 (ch->prefetch << 23) | 1772 ((ch->sync & 0x60) << 14) | 1773 (ch->bs << 18) | 1774 (ch->transparent_copy << 17) | 1775 (ch->constant_fill << 16) | 1776 (ch->mode[1] << 14) | 1777 (ch->mode[0] << 12) | 1778 (0 << 10) | (0 << 9) | 1779 (ch->suspend << 8) | 1780 (ch->enable << 7) | 1781 (ch->priority << 6) | 1782 (ch->fs << 5) | (ch->sync & 0x1f); 1783 1784 case 0x04: /* DMA4_CLNK_CTRL */ 1785 return (ch->link_enabled << 15) | ch->link_next_ch; 1786 1787 case 0x08: /* DMA4_CICR */ 1788 return ch->interrupts; 1789 1790 case 0x0c: /* DMA4_CSR */ 1791 return ch->cstatus; 1792 1793 case 0x10: /* DMA4_CSDP */ 1794 return (ch->endian[0] << 21) | 1795 (ch->endian_lock[0] << 20) | 1796 (ch->endian[1] << 19) | 1797 (ch->endian_lock[1] << 18) | 1798 (ch->write_mode << 16) | 1799 (ch->burst[1] << 14) | 1800 (ch->pack[1] << 13) | 1801 (ch->translate[1] << 9) | 1802 (ch->burst[0] << 7) | 1803 (ch->pack[0] << 6) | 1804 (ch->translate[0] << 2) | 1805 (ch->data_type >> 1); 1806 1807 case 0x14: /* DMA4_CEN */ 1808 return ch->elements; 1809 1810 case 0x18: /* DMA4_CFN */ 1811 return ch->frames; 1812 1813 case 0x1c: /* DMA4_CSSA */ 1814 return ch->addr[0]; 1815 1816 case 0x20: /* DMA4_CDSA */ 1817 return ch->addr[1]; 1818 1819 case 0x24: /* DMA4_CSEI */ 1820 return ch->element_index[0]; 1821 1822 case 0x28: /* DMA4_CSFI */ 1823 return ch->frame_index[0]; 1824 1825 case 0x2c: /* DMA4_CDEI */ 1826 return ch->element_index[1]; 1827 1828 case 0x30: /* DMA4_CDFI */ 1829 return ch->frame_index[1]; 1830 1831 case 0x34: /* DMA4_CSAC */ 1832 return ch->active_set.src & 0xffff; 1833 1834 case 0x38: /* DMA4_CDAC */ 1835 return ch->active_set.dest & 0xffff; 1836 1837 case 0x3c: /* DMA4_CCEN */ 1838 return ch->active_set.element; 1839 1840 case 0x40: /* DMA4_CCFN */ 1841 return ch->active_set.frame; 1842 1843 case 0x44: /* DMA4_COLOR */ 1844 /* XXX only in sDMA */ 1845 return ch->color; 1846 1847 default: 1848 OMAP_BAD_REG(addr); 1849 return 0; 1850 } 1851 } 1852 1853 static void omap_dma4_write(void *opaque, hwaddr addr, 1854 uint64_t value, unsigned size) 1855 { 1856 struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1857 int chnum, irqn = 0; 1858 struct omap_dma_channel_s *ch; 1859 1860 if (size == 1) { 1861 omap_badwidth_write16(opaque, addr, value); 1862 return; 1863 } 1864 1865 switch (addr) { 1866 case 0x14: /* DMA4_IRQSTATUS_L3 */ 1867 irqn ++; 1868 /* fall through */ 1869 case 0x10: /* DMA4_IRQSTATUS_L2 */ 1870 irqn ++; 1871 /* fall through */ 1872 case 0x0c: /* DMA4_IRQSTATUS_L1 */ 1873 irqn ++; 1874 /* fall through */ 1875 case 0x08: /* DMA4_IRQSTATUS_L0 */ 1876 s->irqstat[irqn] &= ~value; 1877 if (!s->irqstat[irqn]) 1878 qemu_irq_lower(s->irq[irqn]); 1879 return; 1880 1881 case 0x24: /* DMA4_IRQENABLE_L3 */ 1882 irqn ++; 1883 /* fall through */ 1884 case 0x20: /* DMA4_IRQENABLE_L2 */ 1885 irqn ++; 1886 /* fall through */ 1887 case 0x1c: /* DMA4_IRQENABLE_L1 */ 1888 irqn ++; 1889 /* fall through */ 1890 case 0x18: /* DMA4_IRQENABLE_L0 */ 1891 s->irqen[irqn] = value; 1892 return; 1893 1894 case 0x2c: /* DMA4_OCP_SYSCONFIG */ 1895 if (value & 2) /* SOFTRESET */ 1896 omap_dma_reset(s->dma); 1897 s->ocp = value & 0x3321; 1898 if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ 1899 fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__); 1900 return; 1901 1902 case 0x78: /* DMA4_GCR */ 1903 s->gcr = value & 0x00ff00ff; 1904 if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ 1905 fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__); 1906 return; 1907 1908 case 0x80 ... 0xfff: 1909 addr -= 0x80; 1910 chnum = addr / 0x60; 1911 ch = s->ch + chnum; 1912 addr -= chnum * 0x60; 1913 break; 1914 1915 case 0x00: /* DMA4_REVISION */ 1916 case 0x28: /* DMA4_SYSSTATUS */ 1917 case 0x64: /* DMA4_CAPS_0 */ 1918 case 0x6c: /* DMA4_CAPS_2 */ 1919 case 0x70: /* DMA4_CAPS_3 */ 1920 case 0x74: /* DMA4_CAPS_4 */ 1921 OMAP_RO_REG(addr); 1922 return; 1923 1924 default: 1925 OMAP_BAD_REG(addr); 1926 return; 1927 } 1928 1929 /* Per-channel registers */ 1930 switch (addr) { 1931 case 0x00: /* DMA4_CCR */ 1932 ch->buf_disable = (value >> 25) & 1; 1933 ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ 1934 if (ch->buf_disable && !ch->src_sync) 1935 fprintf(stderr, "%s: Buffering disable is not allowed in " 1936 "destination synchronised mode\n", __FUNCTION__); 1937 ch->prefetch = (value >> 23) & 1; 1938 ch->bs = (value >> 18) & 1; 1939 ch->transparent_copy = (value >> 17) & 1; 1940 ch->constant_fill = (value >> 16) & 1; 1941 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); 1942 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); 1943 ch->suspend = (value & 0x0100) >> 8; 1944 ch->priority = (value & 0x0040) >> 6; 1945 ch->fs = (value & 0x0020) >> 5; 1946 if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) 1947 fprintf(stderr, "%s: For a packet transfer at least one port " 1948 "must be constant-addressed\n", __FUNCTION__); 1949 ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); 1950 /* XXX must be 0x01 for CamDMA */ 1951 1952 if (value & 0x0080) 1953 omap_dma_enable_channel(s, ch); 1954 else 1955 omap_dma_disable_channel(s, ch); 1956 1957 break; 1958 1959 case 0x04: /* DMA4_CLNK_CTRL */ 1960 ch->link_enabled = (value >> 15) & 0x1; 1961 ch->link_next_ch = value & 0x1f; 1962 break; 1963 1964 case 0x08: /* DMA4_CICR */ 1965 ch->interrupts = value & 0x09be; 1966 break; 1967 1968 case 0x0c: /* DMA4_CSR */ 1969 ch->cstatus &= ~value; 1970 break; 1971 1972 case 0x10: /* DMA4_CSDP */ 1973 ch->endian[0] =(value >> 21) & 1; 1974 ch->endian_lock[0] =(value >> 20) & 1; 1975 ch->endian[1] =(value >> 19) & 1; 1976 ch->endian_lock[1] =(value >> 18) & 1; 1977 if (ch->endian[0] != ch->endian[1]) 1978 fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n", 1979 __FUNCTION__); 1980 ch->write_mode = (value >> 16) & 3; 1981 ch->burst[1] = (value & 0xc000) >> 14; 1982 ch->pack[1] = (value & 0x2000) >> 13; 1983 ch->translate[1] = (value & 0x1e00) >> 9; 1984 ch->burst[0] = (value & 0x0180) >> 7; 1985 ch->pack[0] = (value & 0x0040) >> 6; 1986 ch->translate[0] = (value & 0x003c) >> 2; 1987 if (ch->translate[0] | ch->translate[1]) 1988 fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n", 1989 __FUNCTION__); 1990 ch->data_type = 1 << (value & 3); 1991 if ((value & 3) == 3) 1992 printf("%s: bad data_type for DMA channel\n", __FUNCTION__); 1993 break; 1994 1995 case 0x14: /* DMA4_CEN */ 1996 ch->set_update = 1; 1997 ch->elements = value & 0xffffff; 1998 break; 1999 2000 case 0x18: /* DMA4_CFN */ 2001 ch->frames = value & 0xffff; 2002 ch->set_update = 1; 2003 break; 2004 2005 case 0x1c: /* DMA4_CSSA */ 2006 ch->addr[0] = (hwaddr) (uint32_t) value; 2007 ch->set_update = 1; 2008 break; 2009 2010 case 0x20: /* DMA4_CDSA */ 2011 ch->addr[1] = (hwaddr) (uint32_t) value; 2012 ch->set_update = 1; 2013 break; 2014 2015 case 0x24: /* DMA4_CSEI */ 2016 ch->element_index[0] = (int16_t) value; 2017 ch->set_update = 1; 2018 break; 2019 2020 case 0x28: /* DMA4_CSFI */ 2021 ch->frame_index[0] = (int32_t) value; 2022 ch->set_update = 1; 2023 break; 2024 2025 case 0x2c: /* DMA4_CDEI */ 2026 ch->element_index[1] = (int16_t) value; 2027 ch->set_update = 1; 2028 break; 2029 2030 case 0x30: /* DMA4_CDFI */ 2031 ch->frame_index[1] = (int32_t) value; 2032 ch->set_update = 1; 2033 break; 2034 2035 case 0x44: /* DMA4_COLOR */ 2036 /* XXX only in sDMA */ 2037 ch->color = value; 2038 break; 2039 2040 case 0x34: /* DMA4_CSAC */ 2041 case 0x38: /* DMA4_CDAC */ 2042 case 0x3c: /* DMA4_CCEN */ 2043 case 0x40: /* DMA4_CCFN */ 2044 OMAP_RO_REG(addr); 2045 break; 2046 2047 default: 2048 OMAP_BAD_REG(addr); 2049 } 2050 } 2051 2052 static const MemoryRegionOps omap_dma4_ops = { 2053 .read = omap_dma4_read, 2054 .write = omap_dma4_write, 2055 .endianness = DEVICE_NATIVE_ENDIAN, 2056 }; 2057 2058 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 2059 MemoryRegion *sysmem, 2060 struct omap_mpu_state_s *mpu, int fifo, 2061 int chans, omap_clk iclk, omap_clk fclk) 2062 { 2063 int i; 2064 struct omap_dma_s *s = (struct omap_dma_s *) 2065 g_malloc0(sizeof(struct omap_dma_s)); 2066 2067 s->model = omap_dma_4; 2068 s->chans = chans; 2069 s->mpu = mpu; 2070 s->clk = fclk; 2071 2072 s->dma = soc_dma_init(s->chans); 2073 s->dma->freq = omap_clk_getrate(fclk); 2074 s->dma->transfer_fn = omap_dma_transfer_generic; 2075 s->dma->setup_fn = omap_dma_transfer_setup; 2076 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64); 2077 s->dma->opaque = s; 2078 for (i = 0; i < s->chans; i ++) { 2079 s->ch[i].dma = &s->dma->ch[i]; 2080 s->dma->ch[i].opaque = &s->ch[i]; 2081 } 2082 2083 memcpy(&s->irq, irqs, sizeof(s->irq)); 2084 s->intr_update = omap_dma_interrupts_4_update; 2085 2086 omap_dma_setcaps(s); 2087 omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0)); 2088 omap_dma_reset(s->dma); 2089 omap_dma_clk_update(s, 0, !!s->dma->freq); 2090 2091 memory_region_init_io(&s->iomem, NULL, &omap_dma4_ops, s, "omap.dma4", 0x1000); 2092 memory_region_add_subregion(sysmem, base, &s->iomem); 2093 2094 mpu->drq = s->dma->drq; 2095 2096 return s->dma; 2097 } 2098 2099 struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma) 2100 { 2101 struct omap_dma_s *s = dma->opaque; 2102 2103 return &s->lcd_ch; 2104 } 2105