1 /* 2 * QEMU DMA emulation 3 * 4 * Copyright (c) 2003-2004 Vassili Karpov (malc) 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/isa/isa.h" 27 #include "hw/isa/i8257.h" 28 #include "qemu/main-loop.h" 29 #include "trace.h" 30 31 #define I8257(obj) \ 32 OBJECT_CHECK(I8257State, (obj), TYPE_I8257) 33 34 /* #define DEBUG_DMA */ 35 36 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) 37 #ifdef DEBUG_DMA 38 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) 39 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) 40 #else 41 #define linfo(...) 42 #define ldebug(...) 43 #endif 44 45 #define ADDR 0 46 #define COUNT 1 47 48 enum { 49 CMD_MEMORY_TO_MEMORY = 0x01, 50 CMD_FIXED_ADDRESS = 0x02, 51 CMD_BLOCK_CONTROLLER = 0x04, 52 CMD_COMPRESSED_TIME = 0x08, 53 CMD_CYCLIC_PRIORITY = 0x10, 54 CMD_EXTENDED_WRITE = 0x20, 55 CMD_LOW_DREQ = 0x40, 56 CMD_LOW_DACK = 0x80, 57 CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS 58 | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE 59 | CMD_LOW_DREQ | CMD_LOW_DACK 60 61 }; 62 63 static void i8257_dma_run(void *opaque); 64 65 static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; 66 67 static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data) 68 { 69 I8257State *d = opaque; 70 int ichan; 71 72 ichan = channels[nport & 7]; 73 if (-1 == ichan) { 74 dolog ("invalid channel %#x %#x\n", nport, data); 75 return; 76 } 77 d->regs[ichan].page = data; 78 } 79 80 static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data) 81 { 82 I8257State *d = opaque; 83 int ichan; 84 85 ichan = channels[nport & 7]; 86 if (-1 == ichan) { 87 dolog ("invalid channel %#x %#x\n", nport, data); 88 return; 89 } 90 d->regs[ichan].pageh = data; 91 } 92 93 static uint32_t i8257_read_page(void *opaque, uint32_t nport) 94 { 95 I8257State *d = opaque; 96 int ichan; 97 98 ichan = channels[nport & 7]; 99 if (-1 == ichan) { 100 dolog ("invalid channel read %#x\n", nport); 101 return 0; 102 } 103 return d->regs[ichan].page; 104 } 105 106 static uint32_t i8257_read_pageh(void *opaque, uint32_t nport) 107 { 108 I8257State *d = opaque; 109 int ichan; 110 111 ichan = channels[nport & 7]; 112 if (-1 == ichan) { 113 dolog ("invalid channel read %#x\n", nport); 114 return 0; 115 } 116 return d->regs[ichan].pageh; 117 } 118 119 static inline void i8257_init_chan(I8257State *d, int ichan) 120 { 121 I8257Regs *r; 122 123 r = d->regs + ichan; 124 r->now[ADDR] = r->base[ADDR] << d->dshift; 125 r->now[COUNT] = 0; 126 } 127 128 static inline int i8257_getff(I8257State *d) 129 { 130 int ff; 131 132 ff = d->flip_flop; 133 d->flip_flop = !ff; 134 return ff; 135 } 136 137 static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size) 138 { 139 I8257State *d = opaque; 140 int ichan, nreg, iport, ff, val, dir; 141 I8257Regs *r; 142 143 iport = (nport >> d->dshift) & 0x0f; 144 ichan = iport >> 1; 145 nreg = iport & 1; 146 r = d->regs + ichan; 147 148 dir = ((r->mode >> 5) & 1) ? -1 : 1; 149 ff = i8257_getff(d); 150 if (nreg) 151 val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; 152 else 153 val = r->now[ADDR] + r->now[COUNT] * dir; 154 155 ldebug ("read_chan %#x -> %d\n", iport, val); 156 return (val >> (d->dshift + (ff << 3))) & 0xff; 157 } 158 159 static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data, 160 unsigned int size) 161 { 162 I8257State *d = opaque; 163 int iport, ichan, nreg; 164 I8257Regs *r; 165 166 iport = (nport >> d->dshift) & 0x0f; 167 ichan = iport >> 1; 168 nreg = iport & 1; 169 r = d->regs + ichan; 170 if (i8257_getff(d)) { 171 r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); 172 i8257_init_chan(d, ichan); 173 } else { 174 r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); 175 } 176 } 177 178 static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data, 179 unsigned int size) 180 { 181 I8257State *d = opaque; 182 int iport, ichan = 0; 183 184 iport = (nport >> d->dshift) & 0x0f; 185 switch (iport) { 186 case 0x00: /* command */ 187 if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { 188 dolog("command %"PRIx64" not supported\n", data); 189 return; 190 } 191 d->command = data; 192 break; 193 194 case 0x01: 195 ichan = data & 3; 196 if (data & 4) { 197 d->status |= 1 << (ichan + 4); 198 } 199 else { 200 d->status &= ~(1 << (ichan + 4)); 201 } 202 d->status &= ~(1 << ichan); 203 i8257_dma_run(d); 204 break; 205 206 case 0x02: /* single mask */ 207 if (data & 4) 208 d->mask |= 1 << (data & 3); 209 else 210 d->mask &= ~(1 << (data & 3)); 211 i8257_dma_run(d); 212 break; 213 214 case 0x03: /* mode */ 215 { 216 ichan = data & 3; 217 #ifdef DEBUG_DMA 218 { 219 int op, ai, dir, opmode; 220 op = (data >> 2) & 3; 221 ai = (data >> 4) & 1; 222 dir = (data >> 5) & 1; 223 opmode = (data >> 6) & 3; 224 225 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n", 226 ichan, op, ai, dir, opmode); 227 } 228 #endif 229 d->regs[ichan].mode = data; 230 break; 231 } 232 233 case 0x04: /* clear flip flop */ 234 d->flip_flop = 0; 235 break; 236 237 case 0x05: /* reset */ 238 d->flip_flop = 0; 239 d->mask = ~0; 240 d->status = 0; 241 d->command = 0; 242 break; 243 244 case 0x06: /* clear mask for all channels */ 245 d->mask = 0; 246 i8257_dma_run(d); 247 break; 248 249 case 0x07: /* write mask for all channels */ 250 d->mask = data; 251 i8257_dma_run(d); 252 break; 253 254 default: 255 dolog ("unknown iport %#x\n", iport); 256 break; 257 } 258 259 #ifdef DEBUG_DMA 260 if (0xc != iport) { 261 linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n", 262 nport, ichan, data); 263 } 264 #endif 265 } 266 267 static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size) 268 { 269 I8257State *d = opaque; 270 int iport, val; 271 272 iport = (nport >> d->dshift) & 0x0f; 273 switch (iport) { 274 case 0x00: /* status */ 275 val = d->status; 276 d->status &= 0xf0; 277 break; 278 case 0x01: /* mask */ 279 val = d->mask; 280 break; 281 default: 282 val = 0; 283 break; 284 } 285 286 ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val); 287 return val; 288 } 289 290 static IsaDmaTransferMode i8257_dma_get_transfer_mode(IsaDma *obj, int nchan) 291 { 292 I8257State *d = I8257(obj); 293 return (d->regs[nchan & 3].mode >> 2) & 3; 294 } 295 296 static bool i8257_dma_has_autoinitialization(IsaDma *obj, int nchan) 297 { 298 I8257State *d = I8257(obj); 299 return (d->regs[nchan & 3].mode >> 4) & 1; 300 } 301 302 static void i8257_dma_hold_DREQ(IsaDma *obj, int nchan) 303 { 304 I8257State *d = I8257(obj); 305 int ichan; 306 307 ichan = nchan & 3; 308 d->status |= 1 << (ichan + 4); 309 i8257_dma_run(d); 310 } 311 312 static void i8257_dma_release_DREQ(IsaDma *obj, int nchan) 313 { 314 I8257State *d = I8257(obj); 315 int ichan; 316 317 ichan = nchan & 3; 318 d->status &= ~(1 << (ichan + 4)); 319 i8257_dma_run(d); 320 } 321 322 static void i8257_channel_run(I8257State *d, int ichan) 323 { 324 int ncont = d->dshift; 325 int n; 326 I8257Regs *r = &d->regs[ichan]; 327 #ifdef DEBUG_DMA 328 int dir, opmode; 329 330 dir = (r->mode >> 5) & 1; 331 opmode = (r->mode >> 6) & 3; 332 333 if (dir) { 334 dolog ("DMA in address decrement mode\n"); 335 } 336 if (opmode != 1) { 337 dolog ("DMA not in single mode select %#x\n", opmode); 338 } 339 #endif 340 341 n = r->transfer_handler (r->opaque, ichan + (ncont << 2), 342 r->now[COUNT], (r->base[COUNT] + 1) << ncont); 343 r->now[COUNT] = n; 344 ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); 345 } 346 347 static void i8257_dma_run(void *opaque) 348 { 349 I8257State *d = opaque; 350 int ichan; 351 int rearm = 0; 352 353 if (d->running) { 354 rearm = 1; 355 goto out; 356 } else { 357 d->running = 1; 358 } 359 360 for (ichan = 0; ichan < 4; ichan++) { 361 int mask; 362 363 mask = 1 << ichan; 364 365 if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { 366 i8257_channel_run(d, ichan); 367 rearm = 1; 368 } 369 } 370 371 d->running = 0; 372 out: 373 if (rearm) { 374 qemu_bh_schedule_idle(d->dma_bh); 375 d->dma_bh_scheduled = true; 376 } 377 } 378 379 static void i8257_dma_register_channel(IsaDma *obj, int nchan, 380 DMA_transfer_handler transfer_handler, 381 void *opaque) 382 { 383 I8257State *d = I8257(obj); 384 I8257Regs *r; 385 int ichan; 386 387 ichan = nchan & 3; 388 389 r = d->regs + ichan; 390 r->transfer_handler = transfer_handler; 391 r->opaque = opaque; 392 } 393 394 static int i8257_dma_read_memory(IsaDma *obj, int nchan, void *buf, int pos, 395 int len) 396 { 397 I8257State *d = I8257(obj); 398 I8257Regs *r = &d->regs[nchan & 3]; 399 hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; 400 401 if (r->mode & 0x20) { 402 int i; 403 uint8_t *p = buf; 404 405 cpu_physical_memory_read (addr - pos - len, buf, len); 406 /* What about 16bit transfers? */ 407 for (i = 0; i < len >> 1; i++) { 408 uint8_t b = p[len - i - 1]; 409 p[i] = b; 410 } 411 } 412 else 413 cpu_physical_memory_read (addr + pos, buf, len); 414 415 return len; 416 } 417 418 static int i8257_dma_write_memory(IsaDma *obj, int nchan, void *buf, int pos, 419 int len) 420 { 421 I8257State *s = I8257(obj); 422 I8257Regs *r = &s->regs[nchan & 3]; 423 hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; 424 425 if (r->mode & 0x20) { 426 int i; 427 uint8_t *p = buf; 428 429 cpu_physical_memory_write (addr - pos - len, buf, len); 430 /* What about 16bit transfers? */ 431 for (i = 0; i < len; i++) { 432 uint8_t b = p[len - i - 1]; 433 p[i] = b; 434 } 435 } 436 else 437 cpu_physical_memory_write (addr + pos, buf, len); 438 439 return len; 440 } 441 442 /* request the emulator to transfer a new DMA memory block ASAP (even 443 * if the idle bottom half would not have exited the iothread yet). 444 */ 445 static void i8257_dma_schedule(IsaDma *obj) 446 { 447 I8257State *d = I8257(obj); 448 if (d->dma_bh_scheduled) { 449 qemu_notify_event(); 450 } 451 } 452 453 static void i8257_reset(DeviceState *dev) 454 { 455 I8257State *d = I8257(dev); 456 i8257_write_cont(d, (0x05 << d->dshift), 0, 1); 457 } 458 459 static int i8257_phony_handler(void *opaque, int nchan, int dma_pos, 460 int dma_len) 461 { 462 trace_i8257_unregistered_dma(nchan, dma_pos, dma_len); 463 return dma_pos; 464 } 465 466 467 static const MemoryRegionOps channel_io_ops = { 468 .read = i8257_read_chan, 469 .write = i8257_write_chan, 470 .endianness = DEVICE_NATIVE_ENDIAN, 471 .impl = { 472 .min_access_size = 1, 473 .max_access_size = 1, 474 }, 475 }; 476 477 /* IOport from page_base */ 478 static const MemoryRegionPortio page_portio_list[] = { 479 { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, }, 480 { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, }, 481 PORTIO_END_OF_LIST(), 482 }; 483 484 /* IOport from pageh_base */ 485 static const MemoryRegionPortio pageh_portio_list[] = { 486 { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, 487 { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, 488 PORTIO_END_OF_LIST(), 489 }; 490 491 static const MemoryRegionOps cont_io_ops = { 492 .read = i8257_read_cont, 493 .write = i8257_write_cont, 494 .endianness = DEVICE_NATIVE_ENDIAN, 495 .impl = { 496 .min_access_size = 1, 497 .max_access_size = 1, 498 }, 499 }; 500 501 static const VMStateDescription vmstate_i8257_regs = { 502 .name = "dma_regs", 503 .version_id = 1, 504 .minimum_version_id = 1, 505 .fields = (VMStateField[]) { 506 VMSTATE_INT32_ARRAY(now, I8257Regs, 2), 507 VMSTATE_UINT16_ARRAY(base, I8257Regs, 2), 508 VMSTATE_UINT8(mode, I8257Regs), 509 VMSTATE_UINT8(page, I8257Regs), 510 VMSTATE_UINT8(pageh, I8257Regs), 511 VMSTATE_UINT8(dack, I8257Regs), 512 VMSTATE_UINT8(eop, I8257Regs), 513 VMSTATE_END_OF_LIST() 514 } 515 }; 516 517 static int i8257_post_load(void *opaque, int version_id) 518 { 519 I8257State *d = opaque; 520 i8257_dma_run(d); 521 522 return 0; 523 } 524 525 static const VMStateDescription vmstate_i8257 = { 526 .name = "dma", 527 .version_id = 1, 528 .minimum_version_id = 1, 529 .post_load = i8257_post_load, 530 .fields = (VMStateField[]) { 531 VMSTATE_UINT8(command, I8257State), 532 VMSTATE_UINT8(mask, I8257State), 533 VMSTATE_UINT8(flip_flop, I8257State), 534 VMSTATE_INT32(dshift, I8257State), 535 VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs, 536 I8257Regs), 537 VMSTATE_END_OF_LIST() 538 } 539 }; 540 541 static void i8257_realize(DeviceState *dev, Error **errp) 542 { 543 ISADevice *isa = ISA_DEVICE(dev); 544 I8257State *d = I8257(dev); 545 int i; 546 547 memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d, 548 "dma-chan", 8 << d->dshift); 549 memory_region_add_subregion(isa_address_space_io(isa), 550 d->base, &d->channel_io); 551 552 isa_register_portio_list(isa, d->page_base, page_portio_list, d, 553 "dma-page"); 554 if (d->pageh_base >= 0) { 555 isa_register_portio_list(isa, d->pageh_base, pageh_portio_list, d, 556 "dma-pageh"); 557 } 558 559 memory_region_init_io(&d->cont_io, OBJECT(isa), &cont_io_ops, d, 560 "dma-cont", 8 << d->dshift); 561 memory_region_add_subregion(isa_address_space_io(isa), 562 d->base + (8 << d->dshift), &d->cont_io); 563 564 for (i = 0; i < ARRAY_SIZE(d->regs); ++i) { 565 d->regs[i].transfer_handler = i8257_phony_handler; 566 } 567 568 d->dma_bh = qemu_bh_new(i8257_dma_run, d); 569 } 570 571 static Property i8257_properties[] = { 572 DEFINE_PROP_INT32("base", I8257State, base, 0x00), 573 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80), 574 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480), 575 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0), 576 DEFINE_PROP_END_OF_LIST() 577 }; 578 579 static void i8257_class_init(ObjectClass *klass, void *data) 580 { 581 DeviceClass *dc = DEVICE_CLASS(klass); 582 IsaDmaClass *idc = ISADMA_CLASS(klass); 583 584 dc->realize = i8257_realize; 585 dc->reset = i8257_reset; 586 dc->vmsd = &vmstate_i8257; 587 dc->props = i8257_properties; 588 589 idc->get_transfer_mode = i8257_dma_get_transfer_mode; 590 idc->has_autoinitialization = i8257_dma_has_autoinitialization; 591 idc->read_memory = i8257_dma_read_memory; 592 idc->write_memory = i8257_dma_write_memory; 593 idc->hold_DREQ = i8257_dma_hold_DREQ; 594 idc->release_DREQ = i8257_dma_release_DREQ; 595 idc->schedule = i8257_dma_schedule; 596 idc->register_channel = i8257_dma_register_channel; 597 } 598 599 static const TypeInfo i8257_info = { 600 .name = TYPE_I8257, 601 .parent = TYPE_ISA_DEVICE, 602 .instance_size = sizeof(I8257State), 603 .class_init = i8257_class_init, 604 .interfaces = (InterfaceInfo[]) { 605 { TYPE_ISADMA }, 606 { } 607 } 608 }; 609 610 static void i8257_register_types(void) 611 { 612 type_register_static(&i8257_info); 613 } 614 615 type_init(i8257_register_types) 616 617 void DMA_init(ISABus *bus, int high_page_enable) 618 { 619 ISADevice *isa1, *isa2; 620 DeviceState *d; 621 622 isa1 = isa_create(bus, TYPE_I8257); 623 d = DEVICE(isa1); 624 qdev_prop_set_int32(d, "base", 0x00); 625 qdev_prop_set_int32(d, "page-base", 0x80); 626 qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1); 627 qdev_prop_set_int32(d, "dshift", 0); 628 qdev_init_nofail(d); 629 630 isa2 = isa_create(bus, TYPE_I8257); 631 d = DEVICE(isa2); 632 qdev_prop_set_int32(d, "base", 0xc0); 633 qdev_prop_set_int32(d, "page-base", 0x88); 634 qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1); 635 qdev_prop_set_int32(d, "dshift", 1); 636 qdev_init_nofail(d); 637 638 isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2)); 639 } 640