1 /* 2 * QEMU DMA emulation 3 * 4 * Copyright (c) 2003-2004 Vassili Karpov (malc) 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/isa/isa.h" 27 #include "hw/qdev-properties.h" 28 #include "migration/vmstate.h" 29 #include "hw/dma/i8257.h" 30 #include "qapi/error.h" 31 #include "qemu/main-loop.h" 32 #include "qemu/module.h" 33 #include "qemu/log.h" 34 #include "trace.h" 35 36 #define I8257(obj) \ 37 OBJECT_CHECK(I8257State, (obj), TYPE_I8257) 38 39 /* #define DEBUG_DMA */ 40 41 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) 42 #ifdef DEBUG_DMA 43 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) 44 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) 45 #else 46 #define linfo(...) 47 #define ldebug(...) 48 #endif 49 50 #define ADDR 0 51 #define COUNT 1 52 53 enum { 54 CMD_MEMORY_TO_MEMORY = 0x01, 55 CMD_FIXED_ADDRESS = 0x02, 56 CMD_BLOCK_CONTROLLER = 0x04, 57 CMD_COMPRESSED_TIME = 0x08, 58 CMD_CYCLIC_PRIORITY = 0x10, 59 CMD_EXTENDED_WRITE = 0x20, 60 CMD_LOW_DREQ = 0x40, 61 CMD_LOW_DACK = 0x80, 62 CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS 63 | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE 64 | CMD_LOW_DREQ | CMD_LOW_DACK 65 66 }; 67 68 static void i8257_dma_run(void *opaque); 69 70 static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; 71 72 static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data) 73 { 74 I8257State *d = opaque; 75 int ichan; 76 77 ichan = channels[nport & 7]; 78 if (-1 == ichan) { 79 dolog ("invalid channel %#x %#x\n", nport, data); 80 return; 81 } 82 d->regs[ichan].page = data; 83 } 84 85 static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data) 86 { 87 I8257State *d = opaque; 88 int ichan; 89 90 ichan = channels[nport & 7]; 91 if (-1 == ichan) { 92 dolog ("invalid channel %#x %#x\n", nport, data); 93 return; 94 } 95 d->regs[ichan].pageh = data; 96 } 97 98 static uint32_t i8257_read_page(void *opaque, uint32_t nport) 99 { 100 I8257State *d = opaque; 101 int ichan; 102 103 ichan = channels[nport & 7]; 104 if (-1 == ichan) { 105 dolog ("invalid channel read %#x\n", nport); 106 return 0; 107 } 108 return d->regs[ichan].page; 109 } 110 111 static uint32_t i8257_read_pageh(void *opaque, uint32_t nport) 112 { 113 I8257State *d = opaque; 114 int ichan; 115 116 ichan = channels[nport & 7]; 117 if (-1 == ichan) { 118 dolog ("invalid channel read %#x\n", nport); 119 return 0; 120 } 121 return d->regs[ichan].pageh; 122 } 123 124 static inline void i8257_init_chan(I8257State *d, int ichan) 125 { 126 I8257Regs *r; 127 128 r = d->regs + ichan; 129 r->now[ADDR] = r->base[ADDR] << d->dshift; 130 r->now[COUNT] = 0; 131 } 132 133 static inline int i8257_getff(I8257State *d) 134 { 135 int ff; 136 137 ff = d->flip_flop; 138 d->flip_flop = !ff; 139 return ff; 140 } 141 142 static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size) 143 { 144 I8257State *d = opaque; 145 int ichan, nreg, iport, ff, val, dir; 146 I8257Regs *r; 147 148 iport = (nport >> d->dshift) & 0x0f; 149 ichan = iport >> 1; 150 nreg = iport & 1; 151 r = d->regs + ichan; 152 153 dir = ((r->mode >> 5) & 1) ? -1 : 1; 154 ff = i8257_getff(d); 155 if (nreg) 156 val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; 157 else 158 val = r->now[ADDR] + r->now[COUNT] * dir; 159 160 ldebug ("read_chan %#x -> %d\n", iport, val); 161 return (val >> (d->dshift + (ff << 3))) & 0xff; 162 } 163 164 static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data, 165 unsigned int size) 166 { 167 I8257State *d = opaque; 168 int iport, ichan, nreg; 169 I8257Regs *r; 170 171 iport = (nport >> d->dshift) & 0x0f; 172 ichan = iport >> 1; 173 nreg = iport & 1; 174 r = d->regs + ichan; 175 if (i8257_getff(d)) { 176 r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); 177 i8257_init_chan(d, ichan); 178 } else { 179 r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); 180 } 181 } 182 183 static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data, 184 unsigned int size) 185 { 186 I8257State *d = opaque; 187 int iport, ichan = 0; 188 189 iport = (nport >> d->dshift) & 0x0f; 190 switch (iport) { 191 case 0x00: /* command */ 192 if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { 193 qemu_log_mask(LOG_UNIMP, "%s: cmd 0x%02"PRIx64" not supported\n", 194 __func__, data); 195 return; 196 } 197 d->command = data; 198 break; 199 200 case 0x01: 201 ichan = data & 3; 202 if (data & 4) { 203 d->status |= 1 << (ichan + 4); 204 } 205 else { 206 d->status &= ~(1 << (ichan + 4)); 207 } 208 d->status &= ~(1 << ichan); 209 i8257_dma_run(d); 210 break; 211 212 case 0x02: /* single mask */ 213 if (data & 4) 214 d->mask |= 1 << (data & 3); 215 else 216 d->mask &= ~(1 << (data & 3)); 217 i8257_dma_run(d); 218 break; 219 220 case 0x03: /* mode */ 221 { 222 ichan = data & 3; 223 #ifdef DEBUG_DMA 224 { 225 int op, ai, dir, opmode; 226 op = (data >> 2) & 3; 227 ai = (data >> 4) & 1; 228 dir = (data >> 5) & 1; 229 opmode = (data >> 6) & 3; 230 231 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n", 232 ichan, op, ai, dir, opmode); 233 } 234 #endif 235 d->regs[ichan].mode = data; 236 break; 237 } 238 239 case 0x04: /* clear flip flop */ 240 d->flip_flop = 0; 241 break; 242 243 case 0x05: /* reset */ 244 d->flip_flop = 0; 245 d->mask = ~0; 246 d->status = 0; 247 d->command = 0; 248 break; 249 250 case 0x06: /* clear mask for all channels */ 251 d->mask = 0; 252 i8257_dma_run(d); 253 break; 254 255 case 0x07: /* write mask for all channels */ 256 d->mask = data; 257 i8257_dma_run(d); 258 break; 259 260 default: 261 dolog ("unknown iport %#x\n", iport); 262 break; 263 } 264 265 #ifdef DEBUG_DMA 266 if (0xc != iport) { 267 linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n", 268 nport, ichan, data); 269 } 270 #endif 271 } 272 273 static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size) 274 { 275 I8257State *d = opaque; 276 int iport, val; 277 278 iport = (nport >> d->dshift) & 0x0f; 279 switch (iport) { 280 case 0x00: /* status */ 281 val = d->status; 282 d->status &= 0xf0; 283 break; 284 case 0x01: /* mask */ 285 val = d->mask; 286 break; 287 default: 288 val = 0; 289 break; 290 } 291 292 ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val); 293 return val; 294 } 295 296 static bool i8257_dma_has_autoinitialization(IsaDma *obj, int nchan) 297 { 298 I8257State *d = I8257(obj); 299 return (d->regs[nchan & 3].mode >> 4) & 1; 300 } 301 302 static void i8257_dma_hold_DREQ(IsaDma *obj, int nchan) 303 { 304 I8257State *d = I8257(obj); 305 int ichan; 306 307 ichan = nchan & 3; 308 d->status |= 1 << (ichan + 4); 309 i8257_dma_run(d); 310 } 311 312 static void i8257_dma_release_DREQ(IsaDma *obj, int nchan) 313 { 314 I8257State *d = I8257(obj); 315 int ichan; 316 317 ichan = nchan & 3; 318 d->status &= ~(1 << (ichan + 4)); 319 i8257_dma_run(d); 320 } 321 322 static void i8257_channel_run(I8257State *d, int ichan) 323 { 324 int ncont = d->dshift; 325 int n; 326 I8257Regs *r = &d->regs[ichan]; 327 #ifdef DEBUG_DMA 328 int dir, opmode; 329 330 dir = (r->mode >> 5) & 1; 331 opmode = (r->mode >> 6) & 3; 332 333 if (dir) { 334 dolog ("DMA in address decrement mode\n"); 335 } 336 if (opmode != 1) { 337 dolog ("DMA not in single mode select %#x\n", opmode); 338 } 339 #endif 340 341 n = r->transfer_handler (r->opaque, ichan + (ncont << 2), 342 r->now[COUNT], (r->base[COUNT] + 1) << ncont); 343 r->now[COUNT] = n; 344 ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); 345 if (n == (r->base[COUNT] + 1) << ncont) { 346 ldebug("transfer done\n"); 347 d->status |= (1 << ichan); 348 } 349 } 350 351 static void i8257_dma_run(void *opaque) 352 { 353 I8257State *d = opaque; 354 int ichan; 355 int rearm = 0; 356 357 if (d->running) { 358 rearm = 1; 359 goto out; 360 } else { 361 d->running = 1; 362 } 363 364 for (ichan = 0; ichan < 4; ichan++) { 365 int mask; 366 367 mask = 1 << ichan; 368 369 if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { 370 i8257_channel_run(d, ichan); 371 rearm = 1; 372 } 373 } 374 375 d->running = 0; 376 out: 377 if (rearm) { 378 qemu_bh_schedule_idle(d->dma_bh); 379 d->dma_bh_scheduled = true; 380 } 381 } 382 383 static void i8257_dma_register_channel(IsaDma *obj, int nchan, 384 IsaDmaTransferHandler transfer_handler, 385 void *opaque) 386 { 387 I8257State *d = I8257(obj); 388 I8257Regs *r; 389 int ichan; 390 391 ichan = nchan & 3; 392 393 r = d->regs + ichan; 394 r->transfer_handler = transfer_handler; 395 r->opaque = opaque; 396 } 397 398 static bool i8257_is_verify_transfer(I8257Regs *r) 399 { 400 return (r->mode & 0x0c) == 0; 401 } 402 403 static int i8257_dma_read_memory(IsaDma *obj, int nchan, void *buf, int pos, 404 int len) 405 { 406 I8257State *d = I8257(obj); 407 I8257Regs *r = &d->regs[nchan & 3]; 408 hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; 409 410 if (i8257_is_verify_transfer(r)) { 411 return len; 412 } 413 414 if (r->mode & 0x20) { 415 int i; 416 uint8_t *p = buf; 417 418 cpu_physical_memory_read (addr - pos - len, buf, len); 419 /* What about 16bit transfers? */ 420 for (i = 0; i < len >> 1; i++) { 421 uint8_t b = p[len - i - 1]; 422 p[i] = b; 423 } 424 } 425 else 426 cpu_physical_memory_read (addr + pos, buf, len); 427 428 return len; 429 } 430 431 static int i8257_dma_write_memory(IsaDma *obj, int nchan, void *buf, int pos, 432 int len) 433 { 434 I8257State *s = I8257(obj); 435 I8257Regs *r = &s->regs[nchan & 3]; 436 hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; 437 438 if (i8257_is_verify_transfer(r)) { 439 return len; 440 } 441 442 if (r->mode & 0x20) { 443 int i; 444 uint8_t *p = buf; 445 446 cpu_physical_memory_write (addr - pos - len, buf, len); 447 /* What about 16bit transfers? */ 448 for (i = 0; i < len; i++) { 449 uint8_t b = p[len - i - 1]; 450 p[i] = b; 451 } 452 } 453 else 454 cpu_physical_memory_write (addr + pos, buf, len); 455 456 return len; 457 } 458 459 /* request the emulator to transfer a new DMA memory block ASAP (even 460 * if the idle bottom half would not have exited the iothread yet). 461 */ 462 static void i8257_dma_schedule(IsaDma *obj) 463 { 464 I8257State *d = I8257(obj); 465 if (d->dma_bh_scheduled) { 466 qemu_notify_event(); 467 } 468 } 469 470 static void i8257_reset(DeviceState *dev) 471 { 472 I8257State *d = I8257(dev); 473 i8257_write_cont(d, (0x05 << d->dshift), 0, 1); 474 } 475 476 static int i8257_phony_handler(void *opaque, int nchan, int dma_pos, 477 int dma_len) 478 { 479 trace_i8257_unregistered_dma(nchan, dma_pos, dma_len); 480 return dma_pos; 481 } 482 483 484 static const MemoryRegionOps channel_io_ops = { 485 .read = i8257_read_chan, 486 .write = i8257_write_chan, 487 .endianness = DEVICE_NATIVE_ENDIAN, 488 .impl = { 489 .min_access_size = 1, 490 .max_access_size = 1, 491 }, 492 }; 493 494 /* IOport from page_base */ 495 static const MemoryRegionPortio page_portio_list[] = { 496 { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, }, 497 { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, }, 498 PORTIO_END_OF_LIST(), 499 }; 500 501 /* IOport from pageh_base */ 502 static const MemoryRegionPortio pageh_portio_list[] = { 503 { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, 504 { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, 505 PORTIO_END_OF_LIST(), 506 }; 507 508 static const MemoryRegionOps cont_io_ops = { 509 .read = i8257_read_cont, 510 .write = i8257_write_cont, 511 .endianness = DEVICE_NATIVE_ENDIAN, 512 .impl = { 513 .min_access_size = 1, 514 .max_access_size = 1, 515 }, 516 }; 517 518 static const VMStateDescription vmstate_i8257_regs = { 519 .name = "dma_regs", 520 .version_id = 1, 521 .minimum_version_id = 1, 522 .fields = (VMStateField[]) { 523 VMSTATE_INT32_ARRAY(now, I8257Regs, 2), 524 VMSTATE_UINT16_ARRAY(base, I8257Regs, 2), 525 VMSTATE_UINT8(mode, I8257Regs), 526 VMSTATE_UINT8(page, I8257Regs), 527 VMSTATE_UINT8(pageh, I8257Regs), 528 VMSTATE_UINT8(dack, I8257Regs), 529 VMSTATE_UINT8(eop, I8257Regs), 530 VMSTATE_END_OF_LIST() 531 } 532 }; 533 534 static int i8257_post_load(void *opaque, int version_id) 535 { 536 I8257State *d = opaque; 537 i8257_dma_run(d); 538 539 return 0; 540 } 541 542 static const VMStateDescription vmstate_i8257 = { 543 .name = "dma", 544 .version_id = 1, 545 .minimum_version_id = 1, 546 .post_load = i8257_post_load, 547 .fields = (VMStateField[]) { 548 VMSTATE_UINT8(command, I8257State), 549 VMSTATE_UINT8(mask, I8257State), 550 VMSTATE_UINT8(flip_flop, I8257State), 551 VMSTATE_INT32(dshift, I8257State), 552 VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs, 553 I8257Regs), 554 VMSTATE_END_OF_LIST() 555 } 556 }; 557 558 static void i8257_realize(DeviceState *dev, Error **errp) 559 { 560 ISADevice *isa = ISA_DEVICE(dev); 561 I8257State *d = I8257(dev); 562 int i; 563 564 memory_region_init_io(&d->channel_io, OBJECT(dev), &channel_io_ops, d, 565 "dma-chan", 8 << d->dshift); 566 memory_region_add_subregion(isa_address_space_io(isa), 567 d->base, &d->channel_io); 568 569 isa_register_portio_list(isa, &d->portio_page, 570 d->page_base, page_portio_list, d, 571 "dma-page"); 572 if (d->pageh_base >= 0) { 573 isa_register_portio_list(isa, &d->portio_pageh, 574 d->pageh_base, pageh_portio_list, d, 575 "dma-pageh"); 576 } 577 578 memory_region_init_io(&d->cont_io, OBJECT(isa), &cont_io_ops, d, 579 "dma-cont", 8 << d->dshift); 580 memory_region_add_subregion(isa_address_space_io(isa), 581 d->base + (8 << d->dshift), &d->cont_io); 582 583 for (i = 0; i < ARRAY_SIZE(d->regs); ++i) { 584 d->regs[i].transfer_handler = i8257_phony_handler; 585 } 586 587 d->dma_bh = qemu_bh_new(i8257_dma_run, d); 588 } 589 590 static Property i8257_properties[] = { 591 DEFINE_PROP_INT32("base", I8257State, base, 0x00), 592 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80), 593 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480), 594 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0), 595 DEFINE_PROP_END_OF_LIST() 596 }; 597 598 static void i8257_class_init(ObjectClass *klass, void *data) 599 { 600 DeviceClass *dc = DEVICE_CLASS(klass); 601 IsaDmaClass *idc = ISADMA_CLASS(klass); 602 603 dc->realize = i8257_realize; 604 dc->reset = i8257_reset; 605 dc->vmsd = &vmstate_i8257; 606 device_class_set_props(dc, i8257_properties); 607 608 idc->has_autoinitialization = i8257_dma_has_autoinitialization; 609 idc->read_memory = i8257_dma_read_memory; 610 idc->write_memory = i8257_dma_write_memory; 611 idc->hold_DREQ = i8257_dma_hold_DREQ; 612 idc->release_DREQ = i8257_dma_release_DREQ; 613 idc->schedule = i8257_dma_schedule; 614 idc->register_channel = i8257_dma_register_channel; 615 /* Reason: needs to be wired up by isa_bus_dma() to work */ 616 dc->user_creatable = false; 617 } 618 619 static const TypeInfo i8257_info = { 620 .name = TYPE_I8257, 621 .parent = TYPE_ISA_DEVICE, 622 .instance_size = sizeof(I8257State), 623 .class_init = i8257_class_init, 624 .interfaces = (InterfaceInfo[]) { 625 { TYPE_ISADMA }, 626 { } 627 } 628 }; 629 630 static void i8257_register_types(void) 631 { 632 type_register_static(&i8257_info); 633 } 634 635 type_init(i8257_register_types) 636 637 void i8257_dma_init(ISABus *bus, bool high_page_enable) 638 { 639 ISADevice *isa1, *isa2; 640 DeviceState *d; 641 642 isa1 = isa_new(TYPE_I8257); 643 d = DEVICE(isa1); 644 qdev_prop_set_int32(d, "base", 0x00); 645 qdev_prop_set_int32(d, "page-base", 0x80); 646 qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1); 647 qdev_prop_set_int32(d, "dshift", 0); 648 isa_realize_and_unref(isa1, bus, &error_fatal); 649 650 isa2 = isa_new(TYPE_I8257); 651 d = DEVICE(isa2); 652 qdev_prop_set_int32(d, "base", 0xc0); 653 qdev_prop_set_int32(d, "page-base", 0x88); 654 qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1); 655 qdev_prop_set_int32(d, "dshift", 1); 656 isa_realize_and_unref(isa2, bus, &error_fatal); 657 658 isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2)); 659 } 660