1 /* 2 * QEMU ETRAX DMA Controller. 3 * 4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "exec/address-spaces.h" 27 #include "qemu-common.h" 28 #include "sysemu/sysemu.h" 29 30 #include "hw/cris/etraxfs_dma.h" 31 32 #define D(x) 33 34 #define RW_DATA (0x0 / 4) 35 #define RW_SAVED_DATA (0x58 / 4) 36 #define RW_SAVED_DATA_BUF (0x5c / 4) 37 #define RW_GROUP (0x60 / 4) 38 #define RW_GROUP_DOWN (0x7c / 4) 39 #define RW_CMD (0x80 / 4) 40 #define RW_CFG (0x84 / 4) 41 #define RW_STAT (0x88 / 4) 42 #define RW_INTR_MASK (0x8c / 4) 43 #define RW_ACK_INTR (0x90 / 4) 44 #define R_INTR (0x94 / 4) 45 #define R_MASKED_INTR (0x98 / 4) 46 #define RW_STREAM_CMD (0x9c / 4) 47 48 #define DMA_REG_MAX (0x100 / 4) 49 50 /* descriptors */ 51 52 // ------------------------------------------------------------ dma_descr_group 53 typedef struct dma_descr_group { 54 uint32_t next; 55 unsigned eol : 1; 56 unsigned tol : 1; 57 unsigned bol : 1; 58 unsigned : 1; 59 unsigned intr : 1; 60 unsigned : 2; 61 unsigned en : 1; 62 unsigned : 7; 63 unsigned dis : 1; 64 unsigned md : 16; 65 struct dma_descr_group *up; 66 union { 67 struct dma_descr_context *context; 68 struct dma_descr_group *group; 69 } down; 70 } dma_descr_group; 71 72 // ---------------------------------------------------------- dma_descr_context 73 typedef struct dma_descr_context { 74 uint32_t next; 75 unsigned eol : 1; 76 unsigned : 3; 77 unsigned intr : 1; 78 unsigned : 1; 79 unsigned store_mode : 1; 80 unsigned en : 1; 81 unsigned : 7; 82 unsigned dis : 1; 83 unsigned md0 : 16; 84 unsigned md1; 85 unsigned md2; 86 unsigned md3; 87 unsigned md4; 88 uint32_t saved_data; 89 uint32_t saved_data_buf; 90 } dma_descr_context; 91 92 // ------------------------------------------------------------- dma_descr_data 93 typedef struct dma_descr_data { 94 uint32_t next; 95 uint32_t buf; 96 unsigned eol : 1; 97 unsigned : 2; 98 unsigned out_eop : 1; 99 unsigned intr : 1; 100 unsigned wait : 1; 101 unsigned : 2; 102 unsigned : 3; 103 unsigned in_eop : 1; 104 unsigned : 4; 105 unsigned md : 16; 106 uint32_t after; 107 } dma_descr_data; 108 109 /* Constants */ 110 enum { 111 regk_dma_ack_pkt = 0x00000100, 112 regk_dma_anytime = 0x00000001, 113 regk_dma_array = 0x00000008, 114 regk_dma_burst = 0x00000020, 115 regk_dma_client = 0x00000002, 116 regk_dma_copy_next = 0x00000010, 117 regk_dma_copy_up = 0x00000020, 118 regk_dma_data_at_eol = 0x00000001, 119 regk_dma_dis_c = 0x00000010, 120 regk_dma_dis_g = 0x00000020, 121 regk_dma_idle = 0x00000001, 122 regk_dma_intern = 0x00000004, 123 regk_dma_load_c = 0x00000200, 124 regk_dma_load_c_n = 0x00000280, 125 regk_dma_load_c_next = 0x00000240, 126 regk_dma_load_d = 0x00000140, 127 regk_dma_load_g = 0x00000300, 128 regk_dma_load_g_down = 0x000003c0, 129 regk_dma_load_g_next = 0x00000340, 130 regk_dma_load_g_up = 0x00000380, 131 regk_dma_next_en = 0x00000010, 132 regk_dma_next_pkt = 0x00000010, 133 regk_dma_no = 0x00000000, 134 regk_dma_only_at_wait = 0x00000000, 135 regk_dma_restore = 0x00000020, 136 regk_dma_rst = 0x00000001, 137 regk_dma_running = 0x00000004, 138 regk_dma_rw_cfg_default = 0x00000000, 139 regk_dma_rw_cmd_default = 0x00000000, 140 regk_dma_rw_intr_mask_default = 0x00000000, 141 regk_dma_rw_stat_default = 0x00000101, 142 regk_dma_rw_stream_cmd_default = 0x00000000, 143 regk_dma_save_down = 0x00000020, 144 regk_dma_save_up = 0x00000020, 145 regk_dma_set_reg = 0x00000050, 146 regk_dma_set_w_size1 = 0x00000190, 147 regk_dma_set_w_size2 = 0x000001a0, 148 regk_dma_set_w_size4 = 0x000001c0, 149 regk_dma_stopped = 0x00000002, 150 regk_dma_store_c = 0x00000002, 151 regk_dma_store_descr = 0x00000000, 152 regk_dma_store_g = 0x00000004, 153 regk_dma_store_md = 0x00000001, 154 regk_dma_sw = 0x00000008, 155 regk_dma_update_down = 0x00000020, 156 regk_dma_yes = 0x00000001 157 }; 158 159 enum dma_ch_state 160 { 161 RST = 1, 162 STOPPED = 2, 163 RUNNING = 4 164 }; 165 166 struct fs_dma_channel 167 { 168 qemu_irq irq; 169 struct etraxfs_dma_client *client; 170 171 /* Internal status. */ 172 int stream_cmd_src; 173 enum dma_ch_state state; 174 175 unsigned int input : 1; 176 unsigned int eol : 1; 177 178 struct dma_descr_group current_g; 179 struct dma_descr_context current_c; 180 struct dma_descr_data current_d; 181 182 /* Control registers. */ 183 uint32_t regs[DMA_REG_MAX]; 184 }; 185 186 struct fs_dma_ctrl 187 { 188 MemoryRegion mmio; 189 int nr_channels; 190 struct fs_dma_channel *channels; 191 192 QEMUBH *bh; 193 }; 194 195 static void DMA_run(void *opaque); 196 static int channel_out_run(struct fs_dma_ctrl *ctrl, int c); 197 198 static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) 199 { 200 return ctrl->channels[c].regs[reg]; 201 } 202 203 static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) 204 { 205 return channel_reg(ctrl, c, RW_CFG) & 2; 206 } 207 208 static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) 209 { 210 return (channel_reg(ctrl, c, RW_CFG) & 1) 211 && ctrl->channels[c].client; 212 } 213 214 static inline int fs_channel(hwaddr addr) 215 { 216 /* Every channel has a 0x2000 ctrl register map. */ 217 return addr >> 13; 218 } 219 220 #ifdef USE_THIS_DEAD_CODE 221 static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) 222 { 223 hwaddr addr = channel_reg(ctrl, c, RW_GROUP); 224 225 /* Load and decode. FIXME: handle endianness. */ 226 cpu_physical_memory_read (addr, 227 (void *) &ctrl->channels[c].current_g, 228 sizeof ctrl->channels[c].current_g); 229 } 230 231 static void dump_c(int ch, struct dma_descr_context *c) 232 { 233 printf("%s ch=%d\n", __func__, ch); 234 printf("next=%x\n", c->next); 235 printf("saved_data=%x\n", c->saved_data); 236 printf("saved_data_buf=%x\n", c->saved_data_buf); 237 printf("eol=%x\n", (uint32_t) c->eol); 238 } 239 240 static void dump_d(int ch, struct dma_descr_data *d) 241 { 242 printf("%s ch=%d\n", __func__, ch); 243 printf("next=%x\n", d->next); 244 printf("buf=%x\n", d->buf); 245 printf("after=%x\n", d->after); 246 printf("intr=%x\n", (uint32_t) d->intr); 247 printf("out_eop=%x\n", (uint32_t) d->out_eop); 248 printf("in_eop=%x\n", (uint32_t) d->in_eop); 249 printf("eol=%x\n", (uint32_t) d->eol); 250 } 251 #endif 252 253 static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) 254 { 255 hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); 256 257 /* Load and decode. FIXME: handle endianness. */ 258 cpu_physical_memory_read (addr, 259 (void *) &ctrl->channels[c].current_c, 260 sizeof ctrl->channels[c].current_c); 261 262 D(dump_c(c, &ctrl->channels[c].current_c)); 263 /* I guess this should update the current pos. */ 264 ctrl->channels[c].regs[RW_SAVED_DATA] = 265 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; 266 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = 267 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; 268 } 269 270 static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) 271 { 272 hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); 273 274 /* Load and decode. FIXME: handle endianness. */ 275 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); 276 cpu_physical_memory_read (addr, 277 (void *) &ctrl->channels[c].current_d, 278 sizeof ctrl->channels[c].current_d); 279 280 D(dump_d(c, &ctrl->channels[c].current_d)); 281 ctrl->channels[c].regs[RW_DATA] = addr; 282 } 283 284 static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) 285 { 286 hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); 287 288 /* Encode and store. FIXME: handle endianness. */ 289 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); 290 D(dump_d(c, &ctrl->channels[c].current_d)); 291 cpu_physical_memory_write (addr, 292 (void *) &ctrl->channels[c].current_c, 293 sizeof ctrl->channels[c].current_c); 294 } 295 296 static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) 297 { 298 hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); 299 300 /* Encode and store. FIXME: handle endianness. */ 301 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); 302 cpu_physical_memory_write (addr, 303 (void *) &ctrl->channels[c].current_d, 304 sizeof ctrl->channels[c].current_d); 305 } 306 307 static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) 308 { 309 /* FIXME: */ 310 } 311 312 static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) 313 { 314 if (ctrl->channels[c].client) 315 { 316 ctrl->channels[c].eol = 0; 317 ctrl->channels[c].state = RUNNING; 318 if (!ctrl->channels[c].input) 319 channel_out_run(ctrl, c); 320 } else 321 printf("WARNING: starting DMA ch %d with no client\n", c); 322 323 qemu_bh_schedule_idle(ctrl->bh); 324 } 325 326 static void channel_continue(struct fs_dma_ctrl *ctrl, int c) 327 { 328 if (!channel_en(ctrl, c) 329 || channel_stopped(ctrl, c) 330 || ctrl->channels[c].state != RUNNING 331 /* Only reload the current data descriptor if it has eol set. */ 332 || !ctrl->channels[c].current_d.eol) { 333 D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n", 334 c, ctrl->channels[c].state, 335 channel_stopped(ctrl, c), 336 channel_en(ctrl,c), 337 ctrl->channels[c].eol)); 338 D(dump_d(c, &ctrl->channels[c].current_d)); 339 return; 340 } 341 342 /* Reload the current descriptor. */ 343 channel_load_d(ctrl, c); 344 345 /* If the current descriptor cleared the eol flag and we had already 346 reached eol state, do the continue. */ 347 if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) { 348 D(printf("continue %d ok %x\n", c, 349 ctrl->channels[c].current_d.next)); 350 ctrl->channels[c].regs[RW_SAVED_DATA] = 351 (uint32_t)(unsigned long)ctrl->channels[c].current_d.next; 352 channel_load_d(ctrl, c); 353 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = 354 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; 355 356 channel_start(ctrl, c); 357 } 358 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = 359 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; 360 } 361 362 static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) 363 { 364 unsigned int cmd = v & ((1 << 10) - 1); 365 366 D(printf("%s ch=%d cmd=%x\n", 367 __func__, c, cmd)); 368 if (cmd & regk_dma_load_d) { 369 channel_load_d(ctrl, c); 370 if (cmd & regk_dma_burst) 371 channel_start(ctrl, c); 372 } 373 374 if (cmd & regk_dma_load_c) { 375 channel_load_c(ctrl, c); 376 } 377 } 378 379 static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) 380 { 381 D(printf("%s %d\n", __func__, c)); 382 ctrl->channels[c].regs[R_INTR] &= 383 ~(ctrl->channels[c].regs[RW_ACK_INTR]); 384 385 ctrl->channels[c].regs[R_MASKED_INTR] = 386 ctrl->channels[c].regs[R_INTR] 387 & ctrl->channels[c].regs[RW_INTR_MASK]; 388 389 D(printf("%s: chan=%d masked_intr=%x\n", __func__, 390 c, 391 ctrl->channels[c].regs[R_MASKED_INTR])); 392 393 qemu_set_irq(ctrl->channels[c].irq, 394 !!ctrl->channels[c].regs[R_MASKED_INTR]); 395 } 396 397 static int channel_out_run(struct fs_dma_ctrl *ctrl, int c) 398 { 399 uint32_t len; 400 uint32_t saved_data_buf; 401 unsigned char buf[2 * 1024]; 402 403 struct dma_context_metadata meta; 404 bool send_context = true; 405 406 if (ctrl->channels[c].eol) 407 return 0; 408 409 do { 410 bool out_eop; 411 D(printf("ch=%d buf=%x after=%x\n", 412 c, 413 (uint32_t)ctrl->channels[c].current_d.buf, 414 (uint32_t)ctrl->channels[c].current_d.after)); 415 416 if (send_context) { 417 if (ctrl->channels[c].client->client.metadata_push) { 418 meta.metadata = ctrl->channels[c].current_d.md; 419 ctrl->channels[c].client->client.metadata_push( 420 ctrl->channels[c].client->client.opaque, 421 &meta); 422 } 423 send_context = false; 424 } 425 426 channel_load_d(ctrl, c); 427 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); 428 len = (uint32_t)(unsigned long) 429 ctrl->channels[c].current_d.after; 430 len -= saved_data_buf; 431 432 if (len > sizeof buf) 433 len = sizeof buf; 434 cpu_physical_memory_read (saved_data_buf, buf, len); 435 436 out_eop = ((saved_data_buf + len) == 437 ctrl->channels[c].current_d.after) && 438 ctrl->channels[c].current_d.out_eop; 439 440 D(printf("channel %d pushes %x %u bytes eop=%u\n", c, 441 saved_data_buf, len, out_eop)); 442 443 if (ctrl->channels[c].client->client.push) { 444 if (len > 0) { 445 ctrl->channels[c].client->client.push( 446 ctrl->channels[c].client->client.opaque, 447 buf, len, out_eop); 448 } 449 } else { 450 printf("WARNING: DMA ch%d dataloss," 451 " no attached client.\n", c); 452 } 453 454 saved_data_buf += len; 455 456 if (saved_data_buf == (uint32_t)(unsigned long) 457 ctrl->channels[c].current_d.after) { 458 /* Done. Step to next. */ 459 if (ctrl->channels[c].current_d.out_eop) { 460 send_context = true; 461 } 462 if (ctrl->channels[c].current_d.intr) { 463 /* data intr. */ 464 D(printf("signal intr %d eol=%d\n", 465 len, ctrl->channels[c].current_d.eol)); 466 ctrl->channels[c].regs[R_INTR] |= (1 << 2); 467 channel_update_irq(ctrl, c); 468 } 469 channel_store_d(ctrl, c); 470 if (ctrl->channels[c].current_d.eol) { 471 D(printf("channel %d EOL\n", c)); 472 ctrl->channels[c].eol = 1; 473 474 /* Mark the context as disabled. */ 475 ctrl->channels[c].current_c.dis = 1; 476 channel_store_c(ctrl, c); 477 478 channel_stop(ctrl, c); 479 } else { 480 ctrl->channels[c].regs[RW_SAVED_DATA] = 481 (uint32_t)(unsigned long)ctrl-> 482 channels[c].current_d.next; 483 /* Load new descriptor. */ 484 channel_load_d(ctrl, c); 485 saved_data_buf = (uint32_t)(unsigned long) 486 ctrl->channels[c].current_d.buf; 487 } 488 489 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = 490 saved_data_buf; 491 D(dump_d(c, &ctrl->channels[c].current_d)); 492 } 493 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; 494 } while (!ctrl->channels[c].eol); 495 return 1; 496 } 497 498 static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, 499 unsigned char *buf, int buflen, int eop) 500 { 501 uint32_t len; 502 uint32_t saved_data_buf; 503 504 if (ctrl->channels[c].eol == 1) 505 return 0; 506 507 channel_load_d(ctrl, c); 508 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); 509 len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after; 510 len -= saved_data_buf; 511 512 if (len > buflen) 513 len = buflen; 514 515 cpu_physical_memory_write (saved_data_buf, buf, len); 516 saved_data_buf += len; 517 518 if (saved_data_buf == 519 (uint32_t)(unsigned long)ctrl->channels[c].current_d.after 520 || eop) { 521 uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; 522 523 D(printf("in dscr end len=%d\n", 524 ctrl->channels[c].current_d.after 525 - ctrl->channels[c].current_d.buf)); 526 ctrl->channels[c].current_d.after = saved_data_buf; 527 528 /* Done. Step to next. */ 529 if (ctrl->channels[c].current_d.intr) { 530 /* TODO: signal eop to the client. */ 531 /* data intr. */ 532 ctrl->channels[c].regs[R_INTR] |= 3; 533 } 534 if (eop) { 535 ctrl->channels[c].current_d.in_eop = 1; 536 ctrl->channels[c].regs[R_INTR] |= 8; 537 } 538 if (r_intr != ctrl->channels[c].regs[R_INTR]) 539 channel_update_irq(ctrl, c); 540 541 channel_store_d(ctrl, c); 542 D(dump_d(c, &ctrl->channels[c].current_d)); 543 544 if (ctrl->channels[c].current_d.eol) { 545 D(printf("channel %d EOL\n", c)); 546 ctrl->channels[c].eol = 1; 547 548 /* Mark the context as disabled. */ 549 ctrl->channels[c].current_c.dis = 1; 550 channel_store_c(ctrl, c); 551 552 channel_stop(ctrl, c); 553 } else { 554 ctrl->channels[c].regs[RW_SAVED_DATA] = 555 (uint32_t)(unsigned long)ctrl-> 556 channels[c].current_d.next; 557 /* Load new descriptor. */ 558 channel_load_d(ctrl, c); 559 saved_data_buf = (uint32_t)(unsigned long) 560 ctrl->channels[c].current_d.buf; 561 } 562 } 563 564 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; 565 return len; 566 } 567 568 static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) 569 { 570 if (ctrl->channels[c].client->client.pull) { 571 ctrl->channels[c].client->client.pull( 572 ctrl->channels[c].client->client.opaque); 573 return 1; 574 } else 575 return 0; 576 } 577 578 static uint32_t dma_rinvalid (void *opaque, hwaddr addr) 579 { 580 hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr); 581 return 0; 582 } 583 584 static uint64_t 585 dma_read(void *opaque, hwaddr addr, unsigned int size) 586 { 587 struct fs_dma_ctrl *ctrl = opaque; 588 int c; 589 uint32_t r = 0; 590 591 if (size != 4) { 592 dma_rinvalid(opaque, addr); 593 } 594 595 /* Make addr relative to this channel and bounded to nr regs. */ 596 c = fs_channel(addr); 597 addr &= 0xff; 598 addr >>= 2; 599 switch (addr) 600 { 601 case RW_STAT: 602 r = ctrl->channels[c].state & 7; 603 r |= ctrl->channels[c].eol << 5; 604 r |= ctrl->channels[c].stream_cmd_src << 8; 605 break; 606 607 default: 608 r = ctrl->channels[c].regs[addr]; 609 D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n", 610 __func__, c, addr)); 611 break; 612 } 613 return r; 614 } 615 616 static void 617 dma_winvalid (void *opaque, hwaddr addr, uint32_t value) 618 { 619 hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); 620 } 621 622 static void 623 dma_update_state(struct fs_dma_ctrl *ctrl, int c) 624 { 625 if (ctrl->channels[c].regs[RW_CFG] & 2) 626 ctrl->channels[c].state = STOPPED; 627 if (!(ctrl->channels[c].regs[RW_CFG] & 1)) 628 ctrl->channels[c].state = RST; 629 } 630 631 static void 632 dma_write(void *opaque, hwaddr addr, 633 uint64_t val64, unsigned int size) 634 { 635 struct fs_dma_ctrl *ctrl = opaque; 636 uint32_t value = val64; 637 int c; 638 639 if (size != 4) { 640 dma_winvalid(opaque, addr, value); 641 } 642 643 /* Make addr relative to this channel and bounded to nr regs. */ 644 c = fs_channel(addr); 645 addr &= 0xff; 646 addr >>= 2; 647 switch (addr) 648 { 649 case RW_DATA: 650 ctrl->channels[c].regs[addr] = value; 651 break; 652 653 case RW_CFG: 654 ctrl->channels[c].regs[addr] = value; 655 dma_update_state(ctrl, c); 656 break; 657 case RW_CMD: 658 /* continue. */ 659 if (value & ~1) 660 printf("Invalid store to ch=%d RW_CMD %x\n", 661 c, value); 662 ctrl->channels[c].regs[addr] = value; 663 channel_continue(ctrl, c); 664 break; 665 666 case RW_SAVED_DATA: 667 case RW_SAVED_DATA_BUF: 668 case RW_GROUP: 669 case RW_GROUP_DOWN: 670 ctrl->channels[c].regs[addr] = value; 671 break; 672 673 case RW_ACK_INTR: 674 case RW_INTR_MASK: 675 ctrl->channels[c].regs[addr] = value; 676 channel_update_irq(ctrl, c); 677 if (addr == RW_ACK_INTR) 678 ctrl->channels[c].regs[RW_ACK_INTR] = 0; 679 break; 680 681 case RW_STREAM_CMD: 682 if (value & ~1023) 683 printf("Invalid store to ch=%d " 684 "RW_STREAMCMD %x\n", 685 c, value); 686 ctrl->channels[c].regs[addr] = value; 687 D(printf("stream_cmd ch=%d\n", c)); 688 channel_stream_cmd(ctrl, c, value); 689 break; 690 691 default: 692 D(printf ("%s c=%d " TARGET_FMT_plx "\n", 693 __func__, c, addr)); 694 break; 695 } 696 } 697 698 static const MemoryRegionOps dma_ops = { 699 .read = dma_read, 700 .write = dma_write, 701 .endianness = DEVICE_NATIVE_ENDIAN, 702 .valid = { 703 .min_access_size = 1, 704 .max_access_size = 4 705 } 706 }; 707 708 static int etraxfs_dmac_run(void *opaque) 709 { 710 struct fs_dma_ctrl *ctrl = opaque; 711 int i; 712 int p = 0; 713 714 for (i = 0; 715 i < ctrl->nr_channels; 716 i++) 717 { 718 if (ctrl->channels[i].state == RUNNING) 719 { 720 if (ctrl->channels[i].input) { 721 p += channel_in_run(ctrl, i); 722 } else { 723 p += channel_out_run(ctrl, i); 724 } 725 } 726 } 727 return p; 728 } 729 730 int etraxfs_dmac_input(struct etraxfs_dma_client *client, 731 void *buf, int len, int eop) 732 { 733 return channel_in_process(client->ctrl, client->channel, 734 buf, len, eop); 735 } 736 737 /* Connect an IRQ line with a channel. */ 738 void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) 739 { 740 struct fs_dma_ctrl *ctrl = opaque; 741 ctrl->channels[c].irq = *line; 742 ctrl->channels[c].input = input; 743 } 744 745 void etraxfs_dmac_connect_client(void *opaque, int c, 746 struct etraxfs_dma_client *cl) 747 { 748 struct fs_dma_ctrl *ctrl = opaque; 749 cl->ctrl = ctrl; 750 cl->channel = c; 751 ctrl->channels[c].client = cl; 752 } 753 754 755 static void DMA_run(void *opaque) 756 { 757 struct fs_dma_ctrl *etraxfs_dmac = opaque; 758 int p = 1; 759 760 if (runstate_is_running()) 761 p = etraxfs_dmac_run(etraxfs_dmac); 762 763 if (p) 764 qemu_bh_schedule_idle(etraxfs_dmac->bh); 765 } 766 767 void *etraxfs_dmac_init(hwaddr base, int nr_channels) 768 { 769 struct fs_dma_ctrl *ctrl = NULL; 770 771 ctrl = g_malloc0(sizeof *ctrl); 772 773 ctrl->bh = qemu_bh_new(DMA_run, ctrl); 774 775 ctrl->nr_channels = nr_channels; 776 ctrl->channels = g_malloc0(sizeof ctrl->channels[0] * nr_channels); 777 778 memory_region_init_io(&ctrl->mmio, NULL, &dma_ops, ctrl, "etraxfs-dma", 779 nr_channels * 0x2000); 780 memory_region_add_subregion(get_system_memory(), base, &ctrl->mmio); 781 782 return ctrl; 783 } 784