1 /* 2 * xlnx_dp.c 3 * 4 * Copyright (C) 2015 : GreenSocs Ltd 5 * http://www.greensocs.com/ , email: info@greensocs.com 6 * 7 * Developed by : 8 * Frederic Konrad <fred.konrad@greensocs.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option)any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 * 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu/log.h" 28 #include "qemu/module.h" 29 #include "hw/display/xlnx_dp.h" 30 #include "hw/irq.h" 31 #include "migration/vmstate.h" 32 33 #ifndef DEBUG_DP 34 #define DEBUG_DP 0 35 #endif 36 37 #define DPRINTF(fmt, ...) do { \ 38 if (DEBUG_DP) { \ 39 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \ 40 } \ 41 } while (0) 42 43 /* 44 * Register offset for DP. 45 */ 46 #define DP_LINK_BW_SET (0x0000 >> 2) 47 #define DP_LANE_COUNT_SET (0x0004 >> 2) 48 #define DP_ENHANCED_FRAME_EN (0x0008 >> 2) 49 #define DP_TRAINING_PATTERN_SET (0x000C >> 2) 50 #define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2) 51 #define DP_SCRAMBLING_DISABLE (0x0014 >> 2) 52 #define DP_DOWNSPREAD_CTRL (0x0018 >> 2) 53 #define DP_SOFTWARE_RESET (0x001C >> 2) 54 #define DP_TRANSMITTER_ENABLE (0x0080 >> 2) 55 #define DP_MAIN_STREAM_ENABLE (0x0084 >> 2) 56 #define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2) 57 #define DP_VERSION_REGISTER (0x00F8 >> 2) 58 #define DP_CORE_ID (0x00FC >> 2) 59 60 #define DP_AUX_COMMAND_REGISTER (0x0100 >> 2) 61 #define AUX_ADDR_ONLY_MASK (0x1000) 62 #define AUX_COMMAND_MASK (0x0F00) 63 #define AUX_COMMAND_SHIFT (8) 64 #define AUX_COMMAND_NBYTES (0x000F) 65 66 #define DP_AUX_WRITE_FIFO (0x0104 >> 2) 67 #define DP_AUX_ADDRESS (0x0108 >> 2) 68 #define DP_AUX_CLOCK_DIVIDER (0x010C >> 2) 69 #define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2) 70 #define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2) 71 #define DP_AUX_REPLY_DATA (0x0134 >> 2) 72 #define DP_AUX_REPLY_CODE (0x0138 >> 2) 73 #define DP_AUX_REPLY_COUNT (0x013C >> 2) 74 #define DP_REPLY_DATA_COUNT (0x0148 >> 2) 75 #define DP_REPLY_STATUS (0x014C >> 2) 76 #define DP_HPD_DURATION (0x0150 >> 2) 77 #define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2) 78 #define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2) 79 #define DP_MAIN_STREAM_POLARITY (0x0188 >> 2) 80 #define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2) 81 #define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2) 82 #define DP_MAIN_STREAM_HRES (0x0194 >> 2) 83 #define DP_MAIN_STREAM_VRES (0x0198 >> 2) 84 #define DP_MAIN_STREAM_HSTART (0x019C >> 2) 85 #define DP_MAIN_STREAM_VSTART (0x01A0 >> 2) 86 #define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2) 87 #define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2) 88 #define DP_MAIN_STREAM_M_VID (0x01AC >> 2) 89 #define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2) 90 #define DP_MAIN_STREAM_N_VID (0x01B4 >> 2) 91 #define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2) 92 #define DP_MIN_BYTES_PER_TU (0x01C4 >> 2) 93 #define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2) 94 #define DP_INIT_WAIT (0x01CC >> 2) 95 #define DP_PHY_RESET (0x0200 >> 2) 96 #define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2) 97 #define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2) 98 #define DP_TRANSMIT_PRBS7 (0x0230 >> 2) 99 #define DP_PHY_CLOCK_SELECT (0x0234 >> 2) 100 #define DP_TX_PHY_POWER_DOWN (0x0238 >> 2) 101 #define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2) 102 #define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2) 103 #define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2) 104 #define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2) 105 #define DP_PHY_STATUS (0x0280 >> 2) 106 107 #define DP_TX_AUDIO_CONTROL (0x0300 >> 2) 108 #define DP_TX_AUD_CTRL (1) 109 110 #define DP_TX_AUDIO_CHANNELS (0x0304 >> 2) 111 #define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2) 112 #define DP_TX_M_AUD (0x0328 >> 2) 113 #define DP_TX_N_AUD (0x032C >> 2) 114 #define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2) 115 #define DP_INT_STATUS (0x03A0 >> 2) 116 #define DP_INT_MASK (0x03A4 >> 2) 117 #define DP_INT_EN (0x03A8 >> 2) 118 #define DP_INT_DS (0x03AC >> 2) 119 120 /* 121 * Registers offset for Audio Video Buffer configuration. 122 */ 123 #define V_BLEND_OFFSET (0xA000) 124 #define V_BLEND_BG_CLR_0 (0x0000 >> 2) 125 #define V_BLEND_BG_CLR_1 (0x0004 >> 2) 126 #define V_BLEND_BG_CLR_2 (0x0008 >> 2) 127 #define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2) 128 #define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2) 129 #define V_BLEND_LAYER0_CONTROL (0x0018 >> 2) 130 #define V_BLEND_LAYER1_CONTROL (0x001C >> 2) 131 132 #define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2) 133 #define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2) 134 135 #define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2) 136 #define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2) 137 #define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2) 138 #define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2) 139 #define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2) 140 #define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2) 141 142 #define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2) 143 144 #define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2) 145 #define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2) 146 #define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2) 147 #define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2) 148 #define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2) 149 #define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2) 150 #define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2) 151 152 /* 153 * Registers offset for Audio Video Buffer configuration. 154 */ 155 #define AV_BUF_MANAGER_OFFSET (0xB000) 156 #define AV_BUF_FORMAT (0x0000 >> 2) 157 #define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2) 158 #define AV_CHBUF0 (0x0010 >> 2) 159 #define AV_CHBUF1 (0x0014 >> 2) 160 #define AV_CHBUF2 (0x0018 >> 2) 161 #define AV_CHBUF3 (0x001C >> 2) 162 #define AV_CHBUF4 (0x0020 >> 2) 163 #define AV_CHBUF5 (0x0024 >> 2) 164 #define AV_BUF_STC_CONTROL (0x002C >> 2) 165 #define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2) 166 #define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2) 167 #define AV_BUF_STC_ADJ (0x0038 >> 2) 168 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2) 169 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2) 170 #define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2) 171 #define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2) 172 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2) 173 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2) 174 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2) 175 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2) 176 #define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2) 177 #define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2) 178 #define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2) 179 #define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2) 180 #define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2) 181 #define AV_BUF_DITHER_CONFIG (0x007C >> 2) 182 #define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2) 183 #define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2) 184 #define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2) 185 #define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2) 186 #define AV_BUF_SRST_REG (0x0124 >> 2) 187 #define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2) 188 #define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2) 189 190 #define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2) 191 192 #define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2) 193 194 #define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2) 195 196 #define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2) 197 198 #define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2) 199 200 #define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2) 201 202 #define AUDIO_MIXER_REGISTER_OFFSET (0xC000) 203 #define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2) 204 #define AUDIO_MIXER_META_DATA (0x0004 >> 2) 205 #define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2) 206 #define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2) 207 #define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2) 208 209 #define DP_AUDIO_DMA_CHANNEL(n) (4 + n) 210 #define DP_GRAPHIC_DMA_CHANNEL (3) 211 #define DP_VIDEO_DMA_CHANNEL (0) 212 213 enum DPGraphicFmt { 214 DP_GRAPHIC_RGBA8888 = 0 << 8, 215 DP_GRAPHIC_ABGR8888 = 1 << 8, 216 DP_GRAPHIC_RGB888 = 2 << 8, 217 DP_GRAPHIC_BGR888 = 3 << 8, 218 DP_GRAPHIC_RGBA5551 = 4 << 8, 219 DP_GRAPHIC_RGBA4444 = 5 << 8, 220 DP_GRAPHIC_RGB565 = 6 << 8, 221 DP_GRAPHIC_8BPP = 7 << 8, 222 DP_GRAPHIC_4BPP = 8 << 8, 223 DP_GRAPHIC_2BPP = 9 << 8, 224 DP_GRAPHIC_1BPP = 10 << 8, 225 DP_GRAPHIC_MASK = 0xF << 8 226 }; 227 228 enum DPVideoFmt { 229 DP_NL_VID_CB_Y0_CR_Y1 = 0, 230 DP_NL_VID_CR_Y0_CB_Y1 = 1, 231 DP_NL_VID_Y0_CR_Y1_CB = 2, 232 DP_NL_VID_Y0_CB_Y1_CR = 3, 233 DP_NL_VID_YV16 = 4, 234 DP_NL_VID_YV24 = 5, 235 DP_NL_VID_YV16CL = 6, 236 DP_NL_VID_MONO = 7, 237 DP_NL_VID_YV16CL2 = 8, 238 DP_NL_VID_YUV444 = 9, 239 DP_NL_VID_RGB888 = 10, 240 DP_NL_VID_RGBA8880 = 11, 241 DP_NL_VID_RGB888_10BPC = 12, 242 DP_NL_VID_YUV444_10BPC = 13, 243 DP_NL_VID_YV16CL2_10BPC = 14, 244 DP_NL_VID_YV16CL_10BPC = 15, 245 DP_NL_VID_YV16_10BPC = 16, 246 DP_NL_VID_YV24_10BPC = 17, 247 DP_NL_VID_Y_ONLY_10BPC = 18, 248 DP_NL_VID_YV16_420 = 19, 249 DP_NL_VID_YV16CL_420 = 20, 250 DP_NL_VID_YV16CL2_420 = 21, 251 DP_NL_VID_YV16_420_10BPC = 22, 252 DP_NL_VID_YV16CL_420_10BPC = 23, 253 DP_NL_VID_YV16CL2_420_10BPC = 24, 254 DP_NL_VID_FMT_MASK = 0x1F 255 }; 256 257 typedef enum DPGraphicFmt DPGraphicFmt; 258 typedef enum DPVideoFmt DPVideoFmt; 259 260 static const VMStateDescription vmstate_dp = { 261 .name = TYPE_XLNX_DP, 262 .version_id = 1, 263 .fields = (VMStateField[]){ 264 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState, 265 DP_CORE_REG_ARRAY_SIZE), 266 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState, 267 DP_AVBUF_REG_ARRAY_SIZE), 268 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState, 269 DP_VBLEND_REG_ARRAY_SIZE), 270 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState, 271 DP_AUDIO_REG_ARRAY_SIZE), 272 VMSTATE_END_OF_LIST() 273 } 274 }; 275 276 static void xlnx_dp_update_irq(XlnxDPState *s); 277 278 static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size) 279 { 280 XlnxDPState *s = XLNX_DP(opaque); 281 282 offset = offset >> 2; 283 return s->audio_registers[offset]; 284 } 285 286 static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value, 287 unsigned size) 288 { 289 XlnxDPState *s = XLNX_DP(opaque); 290 291 offset = offset >> 2; 292 293 switch (offset) { 294 case AUDIO_MIXER_META_DATA: 295 s->audio_registers[offset] = value & 0x00000001; 296 break; 297 default: 298 s->audio_registers[offset] = value; 299 break; 300 } 301 } 302 303 static const MemoryRegionOps audio_ops = { 304 .read = xlnx_dp_audio_read, 305 .write = xlnx_dp_audio_write, 306 .endianness = DEVICE_NATIVE_ENDIAN, 307 }; 308 309 static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s, 310 uint8_t channel) 311 { 312 switch (channel) { 313 case 0: 314 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16); 315 case 1: 316 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16, 317 16); 318 default: 319 return 0; 320 } 321 } 322 323 static inline void xlnx_dp_audio_activate(XlnxDPState *s) 324 { 325 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL] 326 & DP_TX_AUD_CTRL) != 0); 327 AUD_set_active_out(s->amixer_output_stream, activated); 328 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0), 329 &s->audio_buffer_0); 330 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1), 331 &s->audio_buffer_1); 332 } 333 334 static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s) 335 { 336 /* 337 * Audio packets are signed and have this shape: 338 * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 339 * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 | 340 * 341 * Output audio is 16bits saturated. 342 */ 343 int i; 344 345 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) { 346 for (i = 0; i < s->audio_data_available[0] / 2; i++) { 347 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i]) 348 * xlnx_dp_audio_get_volume(s, 0) / 8192; 349 } 350 s->byte_left = s->audio_data_available[0]; 351 } else { 352 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2); 353 } 354 355 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) { 356 if ((s->audio_data_available[0] == 0) 357 || (s->audio_data_available[1] == s->audio_data_available[0])) { 358 for (i = 0; i < s->audio_data_available[1] / 2; i++) { 359 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i]) 360 * xlnx_dp_audio_get_volume(s, 1) / 8192; 361 } 362 s->byte_left = s->audio_data_available[1]; 363 } 364 } 365 366 for (i = 0; i < s->byte_left / 2; i++) { 367 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767)); 368 } 369 370 s->data_ptr = 0; 371 } 372 373 static void xlnx_dp_audio_callback(void *opaque, int avail) 374 { 375 /* 376 * Get some data from the DPDMA and compute these datas. 377 * Then wait for QEMU's audio subsystem to call this callback. 378 */ 379 XlnxDPState *s = XLNX_DP(opaque); 380 size_t written = 0; 381 382 /* If there are already some data don't get more data. */ 383 if (s->byte_left == 0) { 384 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4, 385 true); 386 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5, 387 true); 388 xlnx_dp_audio_mix_buffer(s); 389 } 390 391 /* Send the buffer through the audio. */ 392 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) { 393 if (s->byte_left != 0) { 394 written = AUD_write(s->amixer_output_stream, 395 &s->out_buffer[s->data_ptr], s->byte_left); 396 } else { 397 int len_to_copy; 398 /* 399 * There is nothing to play.. We don't have any data! Fill the 400 * buffer with zero's and send it. 401 */ 402 written = 0; 403 while (avail) { 404 len_to_copy = MIN(AUD_CHBUF_MAX_DEPTH, avail); 405 memset(s->out_buffer, 0, len_to_copy); 406 avail -= AUD_write(s->amixer_output_stream, s->out_buffer, 407 len_to_copy); 408 } 409 } 410 } else { 411 written = AUD_write(s->amixer_output_stream, 412 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE); 413 } 414 s->byte_left -= written; 415 s->data_ptr += written; 416 } 417 418 /* 419 * AUX channel related function. 420 */ 421 static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s) 422 { 423 fifo8_reset(&s->rx_fifo); 424 } 425 426 static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) 427 { 428 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len); 429 fifo8_push_all(&s->rx_fifo, buf, len); 430 } 431 432 static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s) 433 { 434 uint8_t ret; 435 436 if (fifo8_is_empty(&s->rx_fifo)) { 437 qemu_log_mask(LOG_GUEST_ERROR, 438 "%s: Reading empty RX_FIFO\n", 439 __func__); 440 /* 441 * The datasheet is not clear about the reset value, it seems 442 * to be unspecified. We choose to return '0'. 443 */ 444 ret = 0; 445 } else { 446 ret = fifo8_pop(&s->rx_fifo); 447 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret); 448 } 449 return ret; 450 } 451 452 static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s) 453 { 454 fifo8_reset(&s->tx_fifo); 455 } 456 457 static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) 458 { 459 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len); 460 fifo8_push_all(&s->tx_fifo, buf, len); 461 } 462 463 static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s) 464 { 465 uint8_t ret; 466 467 if (fifo8_is_empty(&s->tx_fifo)) { 468 DPRINTF("tx_fifo underflow..\n"); 469 abort(); 470 } 471 ret = fifo8_pop(&s->tx_fifo); 472 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret); 473 return ret; 474 } 475 476 static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s) 477 { 478 return s->core_registers[DP_AUX_ADDRESS]; 479 } 480 481 /* 482 * Get command from the register. 483 */ 484 static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value) 485 { 486 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0; 487 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT; 488 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1; 489 uint8_t buf[16]; 490 int i; 491 492 /* 493 * When an address_only command is executed nothing happen to the fifo, so 494 * just make nbytes = 0. 495 */ 496 if (address_only) { 497 nbytes = 0; 498 } 499 500 switch (cmd) { 501 case READ_AUX: 502 case READ_I2C: 503 case READ_I2C_MOT: 504 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, 505 xlnx_dp_aux_get_address(s), 506 nbytes, buf); 507 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes; 508 509 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) { 510 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes); 511 } 512 break; 513 case WRITE_AUX: 514 case WRITE_I2C: 515 case WRITE_I2C_MOT: 516 for (i = 0; i < nbytes; i++) { 517 buf[i] = xlnx_dp_aux_pop_tx_fifo(s); 518 } 519 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, 520 xlnx_dp_aux_get_address(s), 521 nbytes, buf); 522 xlnx_dp_aux_clear_tx_fifo(s); 523 break; 524 case WRITE_I2C_STATUS: 525 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n"); 526 break; 527 default: 528 abort(); 529 } 530 531 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04; 532 } 533 534 static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val, 535 Error **errp) 536 { 537 XlnxDPState *s = XLNX_DP(obj); 538 if (s->console) { 539 DisplaySurface *surface = qemu_console_surface(s->console); 540 XlnxDPDMAState *dma = XLNX_DPDMA(val); 541 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL, 542 surface_data(surface)); 543 } 544 } 545 546 static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s) 547 { 548 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1; 549 } 550 551 static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s) 552 { 553 /* 554 * If the alpha is totally opaque (255) we consider the alpha is disabled to 555 * reduce CPU consumption. 556 */ 557 return ((xlnx_dp_global_alpha_value(s) != 0xFF) && 558 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0)); 559 } 560 561 static void xlnx_dp_recreate_surface(XlnxDPState *s) 562 { 563 /* 564 * Two possibilities, if blending is enabled the console displays 565 * bout_plane, if not g_plane is displayed. 566 */ 567 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES]; 568 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES]; 569 DisplaySurface *current_console_surface = qemu_console_surface(s->console); 570 571 if ((width != 0) && (height != 0)) { 572 /* 573 * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the 574 * surface we need to be careful and don't free the surface associated 575 * to the console or double free will happen. 576 */ 577 if (s->bout_plane.surface != current_console_surface) { 578 qemu_free_displaysurface(s->bout_plane.surface); 579 } 580 if (s->v_plane.surface != current_console_surface) { 581 qemu_free_displaysurface(s->v_plane.surface); 582 } 583 if (s->g_plane.surface != current_console_surface) { 584 qemu_free_displaysurface(s->g_plane.surface); 585 } 586 587 s->g_plane.surface 588 = qemu_create_displaysurface_from(width, height, 589 s->g_plane.format, 0, NULL); 590 s->v_plane.surface 591 = qemu_create_displaysurface_from(width, height, 592 s->v_plane.format, 0, NULL); 593 if (xlnx_dp_global_alpha_enabled(s)) { 594 s->bout_plane.surface = 595 qemu_create_displaysurface_from(width, 596 height, 597 s->g_plane.format, 598 0, NULL); 599 dpy_gfx_replace_surface(s->console, s->bout_plane.surface); 600 } else { 601 s->bout_plane.surface = NULL; 602 dpy_gfx_replace_surface(s->console, s->g_plane.surface); 603 } 604 605 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, 606 surface_data(s->g_plane.surface)); 607 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL, 608 surface_data(s->v_plane.surface)); 609 } 610 } 611 612 /* 613 * Change the graphic format of the surface. 614 */ 615 static void xlnx_dp_change_graphic_fmt(XlnxDPState *s) 616 { 617 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) { 618 case DP_GRAPHIC_RGBA8888: 619 s->g_plane.format = PIXMAN_r8g8b8a8; 620 break; 621 case DP_GRAPHIC_ABGR8888: 622 s->g_plane.format = PIXMAN_a8b8g8r8; 623 break; 624 case DP_GRAPHIC_RGB565: 625 s->g_plane.format = PIXMAN_r5g6b5; 626 break; 627 case DP_GRAPHIC_RGB888: 628 s->g_plane.format = PIXMAN_r8g8b8; 629 break; 630 case DP_GRAPHIC_BGR888: 631 s->g_plane.format = PIXMAN_b8g8r8; 632 break; 633 default: 634 DPRINTF("error: unsupported graphic format %u.\n", 635 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK); 636 abort(); 637 } 638 639 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) { 640 case 0: 641 s->v_plane.format = PIXMAN_x8b8g8r8; 642 break; 643 case DP_NL_VID_Y0_CB_Y1_CR: 644 s->v_plane.format = PIXMAN_yuy2; 645 break; 646 case DP_NL_VID_RGBA8880: 647 s->v_plane.format = PIXMAN_x8b8g8r8; 648 break; 649 default: 650 DPRINTF("error: unsupported video format %u.\n", 651 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK); 652 abort(); 653 } 654 655 xlnx_dp_recreate_surface(s); 656 } 657 658 static void xlnx_dp_update_irq(XlnxDPState *s) 659 { 660 uint32_t flags; 661 662 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK]; 663 DPRINTF("update IRQ value = %" PRIx32 "\n", flags); 664 qemu_set_irq(s->irq, flags != 0); 665 } 666 667 static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size) 668 { 669 XlnxDPState *s = XLNX_DP(opaque); 670 uint64_t ret = 0; 671 672 offset = offset >> 2; 673 674 switch (offset) { 675 case DP_TX_USER_FIFO_OVERFLOW: 676 /* This register is cleared after a read */ 677 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW]; 678 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0; 679 break; 680 case DP_AUX_REPLY_DATA: 681 ret = xlnx_dp_aux_pop_rx_fifo(s); 682 break; 683 case DP_INTERRUPT_SIGNAL_STATE: 684 /* 685 * XXX: Not sure it is the right thing to do actually. 686 * The register is not written by the device driver so it's stuck 687 * to 0x04. 688 */ 689 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE]; 690 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04; 691 break; 692 case DP_AUX_WRITE_FIFO: 693 case DP_TX_AUDIO_INFO_DATA(0): 694 case DP_TX_AUDIO_INFO_DATA(1): 695 case DP_TX_AUDIO_INFO_DATA(2): 696 case DP_TX_AUDIO_INFO_DATA(3): 697 case DP_TX_AUDIO_INFO_DATA(4): 698 case DP_TX_AUDIO_INFO_DATA(5): 699 case DP_TX_AUDIO_INFO_DATA(6): 700 case DP_TX_AUDIO_INFO_DATA(7): 701 case DP_TX_AUDIO_EXT_DATA(0): 702 case DP_TX_AUDIO_EXT_DATA(1): 703 case DP_TX_AUDIO_EXT_DATA(2): 704 case DP_TX_AUDIO_EXT_DATA(3): 705 case DP_TX_AUDIO_EXT_DATA(4): 706 case DP_TX_AUDIO_EXT_DATA(5): 707 case DP_TX_AUDIO_EXT_DATA(6): 708 case DP_TX_AUDIO_EXT_DATA(7): 709 case DP_TX_AUDIO_EXT_DATA(8): 710 /* write only registers */ 711 ret = 0; 712 break; 713 default: 714 assert(offset <= (0x3AC >> 2)); 715 ret = s->core_registers[offset]; 716 break; 717 } 718 719 DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret); 720 return ret; 721 } 722 723 static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, 724 unsigned size) 725 { 726 XlnxDPState *s = XLNX_DP(opaque); 727 728 DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value); 729 730 offset = offset >> 2; 731 732 switch (offset) { 733 /* 734 * Only special write case are handled. 735 */ 736 case DP_LINK_BW_SET: 737 s->core_registers[offset] = value & 0x000000FF; 738 break; 739 case DP_LANE_COUNT_SET: 740 case DP_MAIN_STREAM_MISC0: 741 s->core_registers[offset] = value & 0x0000000F; 742 break; 743 case DP_TRAINING_PATTERN_SET: 744 case DP_LINK_QUAL_PATTERN_SET: 745 case DP_MAIN_STREAM_POLARITY: 746 case DP_PHY_VOLTAGE_DIFF_LANE_0: 747 case DP_PHY_VOLTAGE_DIFF_LANE_1: 748 s->core_registers[offset] = value & 0x00000003; 749 break; 750 case DP_ENHANCED_FRAME_EN: 751 case DP_SCRAMBLING_DISABLE: 752 case DP_DOWNSPREAD_CTRL: 753 case DP_MAIN_STREAM_ENABLE: 754 case DP_TRANSMIT_PRBS7: 755 s->core_registers[offset] = value & 0x00000001; 756 break; 757 case DP_PHY_CLOCK_SELECT: 758 s->core_registers[offset] = value & 0x00000007; 759 break; 760 case DP_SOFTWARE_RESET: 761 /* 762 * No need to update this bit as it's read '0'. 763 */ 764 /* 765 * TODO: reset IP. 766 */ 767 break; 768 case DP_TRANSMITTER_ENABLE: 769 s->core_registers[offset] = value & 0x01; 770 break; 771 case DP_FORCE_SCRAMBLER_RESET: 772 /* 773 * No need to update this bit as it's read '0'. 774 */ 775 /* 776 * TODO: force a scrambler reset?? 777 */ 778 break; 779 case DP_AUX_COMMAND_REGISTER: 780 s->core_registers[offset] = value & 0x00001F0F; 781 xlnx_dp_aux_set_command(s, s->core_registers[offset]); 782 break; 783 case DP_MAIN_STREAM_HTOTAL: 784 case DP_MAIN_STREAM_VTOTAL: 785 case DP_MAIN_STREAM_HSTART: 786 case DP_MAIN_STREAM_VSTART: 787 s->core_registers[offset] = value & 0x0000FFFF; 788 break; 789 case DP_MAIN_STREAM_HRES: 790 case DP_MAIN_STREAM_VRES: 791 s->core_registers[offset] = value & 0x0000FFFF; 792 xlnx_dp_recreate_surface(s); 793 break; 794 case DP_MAIN_STREAM_HSWIDTH: 795 case DP_MAIN_STREAM_VSWIDTH: 796 s->core_registers[offset] = value & 0x00007FFF; 797 break; 798 case DP_MAIN_STREAM_MISC1: 799 s->core_registers[offset] = value & 0x00000086; 800 break; 801 case DP_MAIN_STREAM_M_VID: 802 case DP_MAIN_STREAM_N_VID: 803 s->core_registers[offset] = value & 0x00FFFFFF; 804 break; 805 case DP_MSA_TRANSFER_UNIT_SIZE: 806 case DP_MIN_BYTES_PER_TU: 807 case DP_INIT_WAIT: 808 s->core_registers[offset] = value & 0x00000007; 809 break; 810 case DP_USER_DATA_COUNT_PER_LANE: 811 s->core_registers[offset] = value & 0x0003FFFF; 812 break; 813 case DP_FRAC_BYTES_PER_TU: 814 s->core_registers[offset] = value & 0x000003FF; 815 break; 816 case DP_PHY_RESET: 817 s->core_registers[offset] = value & 0x00010003; 818 /* 819 * TODO: Reset something? 820 */ 821 break; 822 case DP_TX_PHY_POWER_DOWN: 823 s->core_registers[offset] = value & 0x0000000F; 824 /* 825 * TODO: Power down things? 826 */ 827 break; 828 case DP_AUX_WRITE_FIFO: { 829 uint8_t c = value; 830 xlnx_dp_aux_push_tx_fifo(s, &c, 1); 831 break; 832 } 833 case DP_AUX_CLOCK_DIVIDER: 834 break; 835 case DP_AUX_REPLY_COUNT: 836 /* 837 * Writing to this register clear the counter. 838 */ 839 s->core_registers[offset] = 0x00000000; 840 break; 841 case DP_AUX_ADDRESS: 842 s->core_registers[offset] = value & 0x000FFFFF; 843 break; 844 case DP_VERSION_REGISTER: 845 case DP_CORE_ID: 846 case DP_TX_USER_FIFO_OVERFLOW: 847 case DP_AUX_REPLY_DATA: 848 case DP_AUX_REPLY_CODE: 849 case DP_REPLY_DATA_COUNT: 850 case DP_REPLY_STATUS: 851 case DP_HPD_DURATION: 852 /* 853 * Write to read only location.. 854 */ 855 break; 856 case DP_TX_AUDIO_CONTROL: 857 s->core_registers[offset] = value & 0x00000001; 858 xlnx_dp_audio_activate(s); 859 break; 860 case DP_TX_AUDIO_CHANNELS: 861 s->core_registers[offset] = value & 0x00000007; 862 xlnx_dp_audio_activate(s); 863 break; 864 case DP_INT_STATUS: 865 s->core_registers[DP_INT_STATUS] &= ~value; 866 xlnx_dp_update_irq(s); 867 break; 868 case DP_INT_EN: 869 s->core_registers[DP_INT_MASK] &= ~value; 870 xlnx_dp_update_irq(s); 871 break; 872 case DP_INT_DS: 873 s->core_registers[DP_INT_MASK] |= ~value; 874 xlnx_dp_update_irq(s); 875 break; 876 default: 877 assert(offset <= (0x504C >> 2)); 878 s->core_registers[offset] = value; 879 break; 880 } 881 } 882 883 static const MemoryRegionOps dp_ops = { 884 .read = xlnx_dp_read, 885 .write = xlnx_dp_write, 886 .endianness = DEVICE_NATIVE_ENDIAN, 887 .valid = { 888 .min_access_size = 4, 889 .max_access_size = 4, 890 }, 891 .impl = { 892 .min_access_size = 4, 893 .max_access_size = 4, 894 }, 895 }; 896 897 /* 898 * This is to handle Read/Write to the Video Blender. 899 */ 900 static void xlnx_dp_vblend_write(void *opaque, hwaddr offset, 901 uint64_t value, unsigned size) 902 { 903 XlnxDPState *s = XLNX_DP(opaque); 904 bool alpha_was_enabled; 905 906 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 907 (uint32_t)value); 908 offset = offset >> 2; 909 910 switch (offset) { 911 case V_BLEND_BG_CLR_0: 912 case V_BLEND_BG_CLR_1: 913 case V_BLEND_BG_CLR_2: 914 s->vblend_registers[offset] = value & 0x00000FFF; 915 break; 916 case V_BLEND_SET_GLOBAL_ALPHA_REG: 917 /* 918 * A write to this register can enable or disable blending. Thus we need 919 * to recreate the surfaces. 920 */ 921 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s); 922 s->vblend_registers[offset] = value & 0x000001FF; 923 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) { 924 xlnx_dp_recreate_surface(s); 925 } 926 break; 927 case V_BLEND_OUTPUT_VID_FORMAT: 928 s->vblend_registers[offset] = value & 0x00000017; 929 break; 930 case V_BLEND_LAYER0_CONTROL: 931 case V_BLEND_LAYER1_CONTROL: 932 s->vblend_registers[offset] = value & 0x00000103; 933 break; 934 case V_BLEND_RGB2YCBCR_COEFF(0): 935 case V_BLEND_RGB2YCBCR_COEFF(1): 936 case V_BLEND_RGB2YCBCR_COEFF(2): 937 case V_BLEND_RGB2YCBCR_COEFF(3): 938 case V_BLEND_RGB2YCBCR_COEFF(4): 939 case V_BLEND_RGB2YCBCR_COEFF(5): 940 case V_BLEND_RGB2YCBCR_COEFF(6): 941 case V_BLEND_RGB2YCBCR_COEFF(7): 942 case V_BLEND_RGB2YCBCR_COEFF(8): 943 case V_BLEND_IN1CSC_COEFF(0): 944 case V_BLEND_IN1CSC_COEFF(1): 945 case V_BLEND_IN1CSC_COEFF(2): 946 case V_BLEND_IN1CSC_COEFF(3): 947 case V_BLEND_IN1CSC_COEFF(4): 948 case V_BLEND_IN1CSC_COEFF(5): 949 case V_BLEND_IN1CSC_COEFF(6): 950 case V_BLEND_IN1CSC_COEFF(7): 951 case V_BLEND_IN1CSC_COEFF(8): 952 case V_BLEND_IN2CSC_COEFF(0): 953 case V_BLEND_IN2CSC_COEFF(1): 954 case V_BLEND_IN2CSC_COEFF(2): 955 case V_BLEND_IN2CSC_COEFF(3): 956 case V_BLEND_IN2CSC_COEFF(4): 957 case V_BLEND_IN2CSC_COEFF(5): 958 case V_BLEND_IN2CSC_COEFF(6): 959 case V_BLEND_IN2CSC_COEFF(7): 960 case V_BLEND_IN2CSC_COEFF(8): 961 s->vblend_registers[offset] = value & 0x0000FFFF; 962 break; 963 case V_BLEND_LUMA_IN1CSC_OFFSET: 964 case V_BLEND_CR_IN1CSC_OFFSET: 965 case V_BLEND_CB_IN1CSC_OFFSET: 966 case V_BLEND_LUMA_IN2CSC_OFFSET: 967 case V_BLEND_CR_IN2CSC_OFFSET: 968 case V_BLEND_CB_IN2CSC_OFFSET: 969 case V_BLEND_LUMA_OUTCSC_OFFSET: 970 case V_BLEND_CR_OUTCSC_OFFSET: 971 case V_BLEND_CB_OUTCSC_OFFSET: 972 s->vblend_registers[offset] = value & 0x3FFF7FFF; 973 break; 974 case V_BLEND_CHROMA_KEY_ENABLE: 975 s->vblend_registers[offset] = value & 0x00000003; 976 break; 977 case V_BLEND_CHROMA_KEY_COMP1: 978 case V_BLEND_CHROMA_KEY_COMP2: 979 case V_BLEND_CHROMA_KEY_COMP3: 980 s->vblend_registers[offset] = value & 0x0FFF0FFF; 981 break; 982 default: 983 s->vblend_registers[offset] = value; 984 break; 985 } 986 } 987 988 static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset, 989 unsigned size) 990 { 991 XlnxDPState *s = XLNX_DP(opaque); 992 993 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 994 s->vblend_registers[offset >> 2]); 995 return s->vblend_registers[offset >> 2]; 996 } 997 998 static const MemoryRegionOps vblend_ops = { 999 .read = xlnx_dp_vblend_read, 1000 .write = xlnx_dp_vblend_write, 1001 .endianness = DEVICE_NATIVE_ENDIAN, 1002 .valid = { 1003 .min_access_size = 4, 1004 .max_access_size = 4, 1005 }, 1006 .impl = { 1007 .min_access_size = 4, 1008 .max_access_size = 4, 1009 }, 1010 }; 1011 1012 /* 1013 * This is to handle Read/Write to the Audio Video buffer manager. 1014 */ 1015 static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value, 1016 unsigned size) 1017 { 1018 XlnxDPState *s = XLNX_DP(opaque); 1019 1020 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 1021 (uint32_t)value); 1022 offset = offset >> 2; 1023 1024 switch (offset) { 1025 case AV_BUF_FORMAT: 1026 s->avbufm_registers[offset] = value & 0x00000FFF; 1027 xlnx_dp_change_graphic_fmt(s); 1028 break; 1029 case AV_CHBUF0: 1030 case AV_CHBUF1: 1031 case AV_CHBUF2: 1032 case AV_CHBUF3: 1033 case AV_CHBUF4: 1034 case AV_CHBUF5: 1035 s->avbufm_registers[offset] = value & 0x0000007F; 1036 break; 1037 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT: 1038 s->avbufm_registers[offset] = value & 0x0000007F; 1039 break; 1040 case AV_BUF_DITHER_CONFIG: 1041 s->avbufm_registers[offset] = value & 0x000007FF; 1042 break; 1043 case AV_BUF_DITHER_CONFIG_MAX: 1044 case AV_BUF_DITHER_CONFIG_MIN: 1045 s->avbufm_registers[offset] = value & 0x00000FFF; 1046 break; 1047 case AV_BUF_PATTERN_GEN_SELECT: 1048 s->avbufm_registers[offset] = value & 0xFFFFFF03; 1049 break; 1050 case AV_BUF_AUD_VID_CLK_SOURCE: 1051 s->avbufm_registers[offset] = value & 0x00000007; 1052 break; 1053 case AV_BUF_SRST_REG: 1054 s->avbufm_registers[offset] = value & 0x00000002; 1055 break; 1056 case AV_BUF_AUDIO_CH_CONFIG: 1057 s->avbufm_registers[offset] = value & 0x00000003; 1058 break; 1059 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0): 1060 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1): 1061 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2): 1062 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0): 1063 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1): 1064 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2): 1065 s->avbufm_registers[offset] = value & 0x0000FFFF; 1066 break; 1067 case AV_BUF_LIVE_VIDEO_COMP_SF(0): 1068 case AV_BUF_LIVE_VIDEO_COMP_SF(1): 1069 case AV_BUF_LIVE_VIDEO_COMP_SF(2): 1070 case AV_BUF_LIVE_VID_CONFIG: 1071 case AV_BUF_LIVE_GFX_COMP_SF(0): 1072 case AV_BUF_LIVE_GFX_COMP_SF(1): 1073 case AV_BUF_LIVE_GFX_COMP_SF(2): 1074 case AV_BUF_LIVE_GFX_CONFIG: 1075 case AV_BUF_NON_LIVE_LATENCY: 1076 case AV_BUF_STC_CONTROL: 1077 case AV_BUF_STC_INIT_VALUE0: 1078 case AV_BUF_STC_INIT_VALUE1: 1079 case AV_BUF_STC_ADJ: 1080 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0: 1081 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1: 1082 case AV_BUF_STC_EXT_VSYNC_TS_REG0: 1083 case AV_BUF_STC_EXT_VSYNC_TS_REG1: 1084 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0: 1085 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1: 1086 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0: 1087 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1: 1088 case AV_BUF_STC_SNAPSHOT0: 1089 case AV_BUF_STC_SNAPSHOT1: 1090 case AV_BUF_HCOUNT_VCOUNT_INT0: 1091 case AV_BUF_HCOUNT_VCOUNT_INT1: 1092 qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04" 1093 PRIx64 "\n", 1094 offset << 2); 1095 break; 1096 default: 1097 s->avbufm_registers[offset] = value; 1098 break; 1099 } 1100 } 1101 1102 static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset, 1103 unsigned size) 1104 { 1105 XlnxDPState *s = XLNX_DP(opaque); 1106 1107 offset = offset >> 2; 1108 return s->avbufm_registers[offset]; 1109 } 1110 1111 static const MemoryRegionOps avbufm_ops = { 1112 .read = xlnx_dp_avbufm_read, 1113 .write = xlnx_dp_avbufm_write, 1114 .endianness = DEVICE_NATIVE_ENDIAN, 1115 .valid = { 1116 .min_access_size = 4, 1117 .max_access_size = 4, 1118 }, 1119 .impl = { 1120 .min_access_size = 4, 1121 .max_access_size = 4, 1122 }, 1123 }; 1124 1125 /* 1126 * This is a global alpha blending using pixman. 1127 * Both graphic and video planes are multiplied with the global alpha 1128 * coefficient and added. 1129 */ 1130 static inline void xlnx_dp_blend_surface(XlnxDPState *s) 1131 { 1132 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1), 1133 pixman_double_to_fixed(1), 1134 pixman_double_to_fixed(1.0) }; 1135 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1), 1136 pixman_double_to_fixed(1), 1137 pixman_double_to_fixed(1.0) }; 1138 1139 if ((surface_width(s->g_plane.surface) 1140 != surface_width(s->v_plane.surface)) || 1141 (surface_height(s->g_plane.surface) 1142 != surface_height(s->v_plane.surface))) { 1143 return; 1144 } 1145 1146 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s)) 1147 / 256.0); 1148 alpha2[2] = pixman_double_to_fixed((255.0 1149 - (double)xlnx_dp_global_alpha_value(s)) 1150 / 256.0); 1151 1152 pixman_image_set_filter(s->g_plane.surface->image, 1153 PIXMAN_FILTER_CONVOLUTION, alpha1, 3); 1154 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0, 1155 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, 1156 surface_width(s->g_plane.surface), 1157 surface_height(s->g_plane.surface)); 1158 pixman_image_set_filter(s->v_plane.surface->image, 1159 PIXMAN_FILTER_CONVOLUTION, alpha2, 3); 1160 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0, 1161 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, 1162 surface_width(s->g_plane.surface), 1163 surface_height(s->g_plane.surface)); 1164 } 1165 1166 static void xlnx_dp_update_display(void *opaque) 1167 { 1168 XlnxDPState *s = XLNX_DP(opaque); 1169 1170 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) { 1171 return; 1172 } 1173 1174 s->core_registers[DP_INT_STATUS] |= (1 << 13); 1175 xlnx_dp_update_irq(s); 1176 1177 xlnx_dpdma_trigger_vsync_irq(s->dpdma); 1178 1179 /* 1180 * Trigger the DMA channel. 1181 */ 1182 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) { 1183 /* 1184 * An error occurred don't do anything with the data.. 1185 * Trigger an underflow interrupt. 1186 */ 1187 s->core_registers[DP_INT_STATUS] |= (1 << 21); 1188 xlnx_dp_update_irq(s); 1189 return; 1190 } 1191 1192 if (xlnx_dp_global_alpha_enabled(s)) { 1193 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) { 1194 s->core_registers[DP_INT_STATUS] |= (1 << 21); 1195 xlnx_dp_update_irq(s); 1196 return; 1197 } 1198 xlnx_dp_blend_surface(s); 1199 } 1200 1201 /* 1202 * XXX: We might want to update only what changed. 1203 */ 1204 dpy_gfx_update_full(s->console); 1205 } 1206 1207 static const GraphicHwOps xlnx_dp_gfx_ops = { 1208 .gfx_update = xlnx_dp_update_display, 1209 }; 1210 1211 static void xlnx_dp_init(Object *obj) 1212 { 1213 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1214 XlnxDPState *s = XLNX_DP(obj); 1215 1216 memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050); 1217 1218 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP 1219 ".core", 0x3AF); 1220 memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem); 1221 1222 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP 1223 ".v_blend", 0x1DF); 1224 memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem); 1225 1226 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP 1227 ".av_buffer_manager", 0x238); 1228 memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem); 1229 1230 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP 1231 ".audio", sizeof(s->audio_registers)); 1232 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem); 1233 1234 sysbus_init_mmio(sbd, &s->container); 1235 sysbus_init_irq(sbd, &s->irq); 1236 1237 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA, 1238 (Object **) &s->dpdma, 1239 xlnx_dp_set_dpdma, 1240 OBJ_PROP_LINK_STRONG, 1241 &error_abort); 1242 1243 /* 1244 * Initialize AUX Bus. 1245 */ 1246 s->aux_bus = aux_init_bus(DEVICE(obj), "aux"); 1247 1248 /* 1249 * Initialize DPCD and EDID.. 1250 */ 1251 s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd")); 1252 object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd), NULL); 1253 1254 s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc")); 1255 i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50); 1256 object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid), NULL); 1257 1258 fifo8_create(&s->rx_fifo, 16); 1259 fifo8_create(&s->tx_fifo, 16); 1260 } 1261 1262 static void xlnx_dp_realize(DeviceState *dev, Error **errp) 1263 { 1264 XlnxDPState *s = XLNX_DP(dev); 1265 DisplaySurface *surface; 1266 struct audsettings as; 1267 1268 qdev_init_nofail(DEVICE(s->dpcd)); 1269 aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000); 1270 1271 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s); 1272 surface = qemu_console_surface(s->console); 1273 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, 1274 surface_data(surface)); 1275 1276 as.freq = 44100; 1277 as.nchannels = 2; 1278 as.fmt = AUDIO_FORMAT_S16; 1279 as.endianness = 0; 1280 1281 AUD_register_card("xlnx_dp.audio", &s->aud_card); 1282 1283 s->amixer_output_stream = AUD_open_out(&s->aud_card, 1284 s->amixer_output_stream, 1285 "xlnx_dp.audio.out", 1286 s, 1287 xlnx_dp_audio_callback, 1288 &as); 1289 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255); 1290 xlnx_dp_audio_activate(s); 1291 } 1292 1293 static void xlnx_dp_reset(DeviceState *dev) 1294 { 1295 XlnxDPState *s = XLNX_DP(dev); 1296 1297 memset(s->core_registers, 0, sizeof(s->core_registers)); 1298 s->core_registers[DP_VERSION_REGISTER] = 0x04010000; 1299 s->core_registers[DP_CORE_ID] = 0x01020000; 1300 s->core_registers[DP_REPLY_STATUS] = 0x00000010; 1301 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040; 1302 s->core_registers[DP_INIT_WAIT] = 0x00000020; 1303 s->core_registers[DP_PHY_RESET] = 0x00010003; 1304 s->core_registers[DP_INT_MASK] = 0xFFFFF03F; 1305 s->core_registers[DP_PHY_STATUS] = 0x00000043; 1306 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001; 1307 1308 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000; 1309 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000; 1310 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000; 1311 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000; 1312 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000; 1313 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000; 1314 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000; 1315 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000; 1316 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000; 1317 1318 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180; 1319 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008; 1320 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF; 1321 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101; 1322 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101; 1323 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101; 1324 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101; 1325 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101; 1326 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101; 1327 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101; 1328 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101; 1329 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101; 1330 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101; 1331 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101; 1332 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101; 1333 1334 memset(s->audio_registers, 0, sizeof(s->audio_registers)); 1335 s->byte_left = 0; 1336 1337 xlnx_dp_aux_clear_rx_fifo(s); 1338 xlnx_dp_change_graphic_fmt(s); 1339 xlnx_dp_update_irq(s); 1340 } 1341 1342 static void xlnx_dp_class_init(ObjectClass *oc, void *data) 1343 { 1344 DeviceClass *dc = DEVICE_CLASS(oc); 1345 1346 dc->realize = xlnx_dp_realize; 1347 dc->vmsd = &vmstate_dp; 1348 dc->reset = xlnx_dp_reset; 1349 } 1350 1351 static const TypeInfo xlnx_dp_info = { 1352 .name = TYPE_XLNX_DP, 1353 .parent = TYPE_SYS_BUS_DEVICE, 1354 .instance_size = sizeof(XlnxDPState), 1355 .instance_init = xlnx_dp_init, 1356 .class_init = xlnx_dp_class_init, 1357 }; 1358 1359 static void xlnx_dp_register_types(void) 1360 { 1361 type_register_static(&xlnx_dp_info); 1362 } 1363 1364 type_init(xlnx_dp_register_types) 1365