1 /* 2 * xlnx_dp.c 3 * 4 * Copyright (C) 2015 : GreenSocs Ltd 5 * http://www.greensocs.com/ , email: info@greensocs.com 6 * 7 * Developed by : 8 * Frederic Konrad <fred.konrad@greensocs.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option)any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 * 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu/log.h" 28 #include "qemu/module.h" 29 #include "hw/display/xlnx_dp.h" 30 #include "hw/irq.h" 31 32 #ifndef DEBUG_DP 33 #define DEBUG_DP 0 34 #endif 35 36 #define DPRINTF(fmt, ...) do { \ 37 if (DEBUG_DP) { \ 38 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \ 39 } \ 40 } while (0) 41 42 /* 43 * Register offset for DP. 44 */ 45 #define DP_LINK_BW_SET (0x0000 >> 2) 46 #define DP_LANE_COUNT_SET (0x0004 >> 2) 47 #define DP_ENHANCED_FRAME_EN (0x0008 >> 2) 48 #define DP_TRAINING_PATTERN_SET (0x000C >> 2) 49 #define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2) 50 #define DP_SCRAMBLING_DISABLE (0x0014 >> 2) 51 #define DP_DOWNSPREAD_CTRL (0x0018 >> 2) 52 #define DP_SOFTWARE_RESET (0x001C >> 2) 53 #define DP_TRANSMITTER_ENABLE (0x0080 >> 2) 54 #define DP_MAIN_STREAM_ENABLE (0x0084 >> 2) 55 #define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2) 56 #define DP_VERSION_REGISTER (0x00F8 >> 2) 57 #define DP_CORE_ID (0x00FC >> 2) 58 59 #define DP_AUX_COMMAND_REGISTER (0x0100 >> 2) 60 #define AUX_ADDR_ONLY_MASK (0x1000) 61 #define AUX_COMMAND_MASK (0x0F00) 62 #define AUX_COMMAND_SHIFT (8) 63 #define AUX_COMMAND_NBYTES (0x000F) 64 65 #define DP_AUX_WRITE_FIFO (0x0104 >> 2) 66 #define DP_AUX_ADDRESS (0x0108 >> 2) 67 #define DP_AUX_CLOCK_DIVIDER (0x010C >> 2) 68 #define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2) 69 #define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2) 70 #define DP_AUX_REPLY_DATA (0x0134 >> 2) 71 #define DP_AUX_REPLY_CODE (0x0138 >> 2) 72 #define DP_AUX_REPLY_COUNT (0x013C >> 2) 73 #define DP_REPLY_DATA_COUNT (0x0148 >> 2) 74 #define DP_REPLY_STATUS (0x014C >> 2) 75 #define DP_HPD_DURATION (0x0150 >> 2) 76 #define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2) 77 #define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2) 78 #define DP_MAIN_STREAM_POLARITY (0x0188 >> 2) 79 #define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2) 80 #define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2) 81 #define DP_MAIN_STREAM_HRES (0x0194 >> 2) 82 #define DP_MAIN_STREAM_VRES (0x0198 >> 2) 83 #define DP_MAIN_STREAM_HSTART (0x019C >> 2) 84 #define DP_MAIN_STREAM_VSTART (0x01A0 >> 2) 85 #define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2) 86 #define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2) 87 #define DP_MAIN_STREAM_M_VID (0x01AC >> 2) 88 #define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2) 89 #define DP_MAIN_STREAM_N_VID (0x01B4 >> 2) 90 #define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2) 91 #define DP_MIN_BYTES_PER_TU (0x01C4 >> 2) 92 #define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2) 93 #define DP_INIT_WAIT (0x01CC >> 2) 94 #define DP_PHY_RESET (0x0200 >> 2) 95 #define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2) 96 #define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2) 97 #define DP_TRANSMIT_PRBS7 (0x0230 >> 2) 98 #define DP_PHY_CLOCK_SELECT (0x0234 >> 2) 99 #define DP_TX_PHY_POWER_DOWN (0x0238 >> 2) 100 #define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2) 101 #define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2) 102 #define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2) 103 #define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2) 104 #define DP_PHY_STATUS (0x0280 >> 2) 105 106 #define DP_TX_AUDIO_CONTROL (0x0300 >> 2) 107 #define DP_TX_AUD_CTRL (1) 108 109 #define DP_TX_AUDIO_CHANNELS (0x0304 >> 2) 110 #define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2) 111 #define DP_TX_M_AUD (0x0328 >> 2) 112 #define DP_TX_N_AUD (0x032C >> 2) 113 #define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2) 114 #define DP_INT_STATUS (0x03A0 >> 2) 115 #define DP_INT_MASK (0x03A4 >> 2) 116 #define DP_INT_EN (0x03A8 >> 2) 117 #define DP_INT_DS (0x03AC >> 2) 118 119 /* 120 * Registers offset for Audio Video Buffer configuration. 121 */ 122 #define V_BLEND_OFFSET (0xA000) 123 #define V_BLEND_BG_CLR_0 (0x0000 >> 2) 124 #define V_BLEND_BG_CLR_1 (0x0004 >> 2) 125 #define V_BLEND_BG_CLR_2 (0x0008 >> 2) 126 #define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2) 127 #define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2) 128 #define V_BLEND_LAYER0_CONTROL (0x0018 >> 2) 129 #define V_BLEND_LAYER1_CONTROL (0x001C >> 2) 130 131 #define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2) 132 #define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2) 133 134 #define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2) 135 #define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2) 136 #define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2) 137 #define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2) 138 #define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2) 139 #define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2) 140 141 #define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2) 142 143 #define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2) 144 #define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2) 145 #define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2) 146 #define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2) 147 #define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2) 148 #define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2) 149 #define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2) 150 151 /* 152 * Registers offset for Audio Video Buffer configuration. 153 */ 154 #define AV_BUF_MANAGER_OFFSET (0xB000) 155 #define AV_BUF_FORMAT (0x0000 >> 2) 156 #define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2) 157 #define AV_CHBUF0 (0x0010 >> 2) 158 #define AV_CHBUF1 (0x0014 >> 2) 159 #define AV_CHBUF2 (0x0018 >> 2) 160 #define AV_CHBUF3 (0x001C >> 2) 161 #define AV_CHBUF4 (0x0020 >> 2) 162 #define AV_CHBUF5 (0x0024 >> 2) 163 #define AV_BUF_STC_CONTROL (0x002C >> 2) 164 #define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2) 165 #define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2) 166 #define AV_BUF_STC_ADJ (0x0038 >> 2) 167 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2) 168 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2) 169 #define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2) 170 #define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2) 171 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2) 172 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2) 173 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2) 174 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2) 175 #define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2) 176 #define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2) 177 #define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2) 178 #define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2) 179 #define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2) 180 #define AV_BUF_DITHER_CONFIG (0x007C >> 2) 181 #define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2) 182 #define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2) 183 #define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2) 184 #define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2) 185 #define AV_BUF_SRST_REG (0x0124 >> 2) 186 #define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2) 187 #define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2) 188 189 #define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2) 190 191 #define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2) 192 193 #define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2) 194 195 #define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2) 196 197 #define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2) 198 199 #define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2) 200 201 #define AUDIO_MIXER_REGISTER_OFFSET (0xC000) 202 #define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2) 203 #define AUDIO_MIXER_META_DATA (0x0004 >> 2) 204 #define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2) 205 #define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2) 206 #define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2) 207 208 #define DP_AUDIO_DMA_CHANNEL(n) (4 + n) 209 #define DP_GRAPHIC_DMA_CHANNEL (3) 210 #define DP_VIDEO_DMA_CHANNEL (0) 211 212 enum DPGraphicFmt { 213 DP_GRAPHIC_RGBA8888 = 0 << 8, 214 DP_GRAPHIC_ABGR8888 = 1 << 8, 215 DP_GRAPHIC_RGB888 = 2 << 8, 216 DP_GRAPHIC_BGR888 = 3 << 8, 217 DP_GRAPHIC_RGBA5551 = 4 << 8, 218 DP_GRAPHIC_RGBA4444 = 5 << 8, 219 DP_GRAPHIC_RGB565 = 6 << 8, 220 DP_GRAPHIC_8BPP = 7 << 8, 221 DP_GRAPHIC_4BPP = 8 << 8, 222 DP_GRAPHIC_2BPP = 9 << 8, 223 DP_GRAPHIC_1BPP = 10 << 8, 224 DP_GRAPHIC_MASK = 0xF << 8 225 }; 226 227 enum DPVideoFmt { 228 DP_NL_VID_CB_Y0_CR_Y1 = 0, 229 DP_NL_VID_CR_Y0_CB_Y1 = 1, 230 DP_NL_VID_Y0_CR_Y1_CB = 2, 231 DP_NL_VID_Y0_CB_Y1_CR = 3, 232 DP_NL_VID_YV16 = 4, 233 DP_NL_VID_YV24 = 5, 234 DP_NL_VID_YV16CL = 6, 235 DP_NL_VID_MONO = 7, 236 DP_NL_VID_YV16CL2 = 8, 237 DP_NL_VID_YUV444 = 9, 238 DP_NL_VID_RGB888 = 10, 239 DP_NL_VID_RGBA8880 = 11, 240 DP_NL_VID_RGB888_10BPC = 12, 241 DP_NL_VID_YUV444_10BPC = 13, 242 DP_NL_VID_YV16CL2_10BPC = 14, 243 DP_NL_VID_YV16CL_10BPC = 15, 244 DP_NL_VID_YV16_10BPC = 16, 245 DP_NL_VID_YV24_10BPC = 17, 246 DP_NL_VID_Y_ONLY_10BPC = 18, 247 DP_NL_VID_YV16_420 = 19, 248 DP_NL_VID_YV16CL_420 = 20, 249 DP_NL_VID_YV16CL2_420 = 21, 250 DP_NL_VID_YV16_420_10BPC = 22, 251 DP_NL_VID_YV16CL_420_10BPC = 23, 252 DP_NL_VID_YV16CL2_420_10BPC = 24, 253 DP_NL_VID_FMT_MASK = 0x1F 254 }; 255 256 typedef enum DPGraphicFmt DPGraphicFmt; 257 typedef enum DPVideoFmt DPVideoFmt; 258 259 static const VMStateDescription vmstate_dp = { 260 .name = TYPE_XLNX_DP, 261 .version_id = 1, 262 .fields = (VMStateField[]){ 263 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState, 264 DP_CORE_REG_ARRAY_SIZE), 265 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState, 266 DP_AVBUF_REG_ARRAY_SIZE), 267 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState, 268 DP_VBLEND_REG_ARRAY_SIZE), 269 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState, 270 DP_AUDIO_REG_ARRAY_SIZE), 271 VMSTATE_END_OF_LIST() 272 } 273 }; 274 275 static void xlnx_dp_update_irq(XlnxDPState *s); 276 277 static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size) 278 { 279 XlnxDPState *s = XLNX_DP(opaque); 280 281 offset = offset >> 2; 282 return s->audio_registers[offset]; 283 } 284 285 static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value, 286 unsigned size) 287 { 288 XlnxDPState *s = XLNX_DP(opaque); 289 290 offset = offset >> 2; 291 292 switch (offset) { 293 case AUDIO_MIXER_META_DATA: 294 s->audio_registers[offset] = value & 0x00000001; 295 break; 296 default: 297 s->audio_registers[offset] = value; 298 break; 299 } 300 } 301 302 static const MemoryRegionOps audio_ops = { 303 .read = xlnx_dp_audio_read, 304 .write = xlnx_dp_audio_write, 305 .endianness = DEVICE_NATIVE_ENDIAN, 306 }; 307 308 static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s, 309 uint8_t channel) 310 { 311 switch (channel) { 312 case 0: 313 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16); 314 case 1: 315 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16, 316 16); 317 default: 318 return 0; 319 } 320 } 321 322 static inline void xlnx_dp_audio_activate(XlnxDPState *s) 323 { 324 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL] 325 & DP_TX_AUD_CTRL) != 0); 326 AUD_set_active_out(s->amixer_output_stream, activated); 327 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0), 328 &s->audio_buffer_0); 329 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1), 330 &s->audio_buffer_1); 331 } 332 333 static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s) 334 { 335 /* 336 * Audio packets are signed and have this shape: 337 * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 338 * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 | 339 * 340 * Output audio is 16bits saturated. 341 */ 342 int i; 343 344 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) { 345 for (i = 0; i < s->audio_data_available[0] / 2; i++) { 346 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i]) 347 * xlnx_dp_audio_get_volume(s, 0) / 8192; 348 } 349 s->byte_left = s->audio_data_available[0]; 350 } else { 351 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2); 352 } 353 354 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) { 355 if ((s->audio_data_available[0] == 0) 356 || (s->audio_data_available[1] == s->audio_data_available[0])) { 357 for (i = 0; i < s->audio_data_available[1] / 2; i++) { 358 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i]) 359 * xlnx_dp_audio_get_volume(s, 1) / 8192; 360 } 361 s->byte_left = s->audio_data_available[1]; 362 } 363 } 364 365 for (i = 0; i < s->byte_left / 2; i++) { 366 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767)); 367 } 368 369 s->data_ptr = 0; 370 } 371 372 static void xlnx_dp_audio_callback(void *opaque, int avail) 373 { 374 /* 375 * Get some data from the DPDMA and compute these datas. 376 * Then wait for QEMU's audio subsystem to call this callback. 377 */ 378 XlnxDPState *s = XLNX_DP(opaque); 379 size_t written = 0; 380 381 /* If there are already some data don't get more data. */ 382 if (s->byte_left == 0) { 383 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4, 384 true); 385 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5, 386 true); 387 xlnx_dp_audio_mix_buffer(s); 388 } 389 390 /* Send the buffer through the audio. */ 391 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) { 392 if (s->byte_left != 0) { 393 written = AUD_write(s->amixer_output_stream, 394 &s->out_buffer[s->data_ptr], s->byte_left); 395 } else { 396 /* 397 * There is nothing to play.. We don't have any data! Fill the 398 * buffer with zero's and send it. 399 */ 400 written = 0; 401 memset(s->out_buffer, 0, 1024); 402 AUD_write(s->amixer_output_stream, s->out_buffer, 1024); 403 } 404 } else { 405 written = AUD_write(s->amixer_output_stream, 406 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE); 407 } 408 s->byte_left -= written; 409 s->data_ptr += written; 410 } 411 412 /* 413 * AUX channel related function. 414 */ 415 static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s) 416 { 417 fifo8_reset(&s->rx_fifo); 418 } 419 420 static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) 421 { 422 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len); 423 fifo8_push_all(&s->rx_fifo, buf, len); 424 } 425 426 static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s) 427 { 428 uint8_t ret; 429 430 if (fifo8_is_empty(&s->rx_fifo)) { 431 qemu_log_mask(LOG_GUEST_ERROR, 432 "%s: Reading empty RX_FIFO\n", 433 __func__); 434 /* 435 * The datasheet is not clear about the reset value, it seems 436 * to be unspecified. We choose to return '0'. 437 */ 438 ret = 0; 439 } else { 440 ret = fifo8_pop(&s->rx_fifo); 441 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret); 442 } 443 return ret; 444 } 445 446 static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s) 447 { 448 fifo8_reset(&s->tx_fifo); 449 } 450 451 static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) 452 { 453 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len); 454 fifo8_push_all(&s->tx_fifo, buf, len); 455 } 456 457 static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s) 458 { 459 uint8_t ret; 460 461 if (fifo8_is_empty(&s->tx_fifo)) { 462 DPRINTF("tx_fifo underflow..\n"); 463 abort(); 464 } 465 ret = fifo8_pop(&s->tx_fifo); 466 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret); 467 return ret; 468 } 469 470 static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s) 471 { 472 return s->core_registers[DP_AUX_ADDRESS]; 473 } 474 475 /* 476 * Get command from the register. 477 */ 478 static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value) 479 { 480 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0; 481 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT; 482 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1; 483 uint8_t buf[16]; 484 int i; 485 486 /* 487 * When an address_only command is executed nothing happen to the fifo, so 488 * just make nbytes = 0. 489 */ 490 if (address_only) { 491 nbytes = 0; 492 } 493 494 switch (cmd) { 495 case READ_AUX: 496 case READ_I2C: 497 case READ_I2C_MOT: 498 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, 499 xlnx_dp_aux_get_address(s), 500 nbytes, buf); 501 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes; 502 503 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) { 504 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes); 505 } 506 break; 507 case WRITE_AUX: 508 case WRITE_I2C: 509 case WRITE_I2C_MOT: 510 for (i = 0; i < nbytes; i++) { 511 buf[i] = xlnx_dp_aux_pop_tx_fifo(s); 512 } 513 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, 514 xlnx_dp_aux_get_address(s), 515 nbytes, buf); 516 xlnx_dp_aux_clear_tx_fifo(s); 517 break; 518 case WRITE_I2C_STATUS: 519 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n"); 520 break; 521 default: 522 abort(); 523 } 524 525 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04; 526 } 527 528 static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val, 529 Error **errp) 530 { 531 XlnxDPState *s = XLNX_DP(obj); 532 if (s->console) { 533 DisplaySurface *surface = qemu_console_surface(s->console); 534 XlnxDPDMAState *dma = XLNX_DPDMA(val); 535 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL, 536 surface_data(surface)); 537 } 538 } 539 540 static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s) 541 { 542 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1; 543 } 544 545 static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s) 546 { 547 /* 548 * If the alpha is totally opaque (255) we consider the alpha is disabled to 549 * reduce CPU consumption. 550 */ 551 return ((xlnx_dp_global_alpha_value(s) != 0xFF) && 552 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0)); 553 } 554 555 static void xlnx_dp_recreate_surface(XlnxDPState *s) 556 { 557 /* 558 * Two possibilities, if blending is enabled the console displays 559 * bout_plane, if not g_plane is displayed. 560 */ 561 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES]; 562 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES]; 563 DisplaySurface *current_console_surface = qemu_console_surface(s->console); 564 565 if ((width != 0) && (height != 0)) { 566 /* 567 * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the 568 * surface we need to be careful and don't free the surface associated 569 * to the console or double free will happen. 570 */ 571 if (s->bout_plane.surface != current_console_surface) { 572 qemu_free_displaysurface(s->bout_plane.surface); 573 } 574 if (s->v_plane.surface != current_console_surface) { 575 qemu_free_displaysurface(s->v_plane.surface); 576 } 577 if (s->g_plane.surface != current_console_surface) { 578 qemu_free_displaysurface(s->g_plane.surface); 579 } 580 581 s->g_plane.surface 582 = qemu_create_displaysurface_from(width, height, 583 s->g_plane.format, 0, NULL); 584 s->v_plane.surface 585 = qemu_create_displaysurface_from(width, height, 586 s->v_plane.format, 0, NULL); 587 if (xlnx_dp_global_alpha_enabled(s)) { 588 s->bout_plane.surface = 589 qemu_create_displaysurface_from(width, 590 height, 591 s->g_plane.format, 592 0, NULL); 593 dpy_gfx_replace_surface(s->console, s->bout_plane.surface); 594 } else { 595 s->bout_plane.surface = NULL; 596 dpy_gfx_replace_surface(s->console, s->g_plane.surface); 597 } 598 599 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, 600 surface_data(s->g_plane.surface)); 601 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL, 602 surface_data(s->v_plane.surface)); 603 } 604 } 605 606 /* 607 * Change the graphic format of the surface. 608 */ 609 static void xlnx_dp_change_graphic_fmt(XlnxDPState *s) 610 { 611 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) { 612 case DP_GRAPHIC_RGBA8888: 613 s->g_plane.format = PIXMAN_r8g8b8a8; 614 break; 615 case DP_GRAPHIC_ABGR8888: 616 s->g_plane.format = PIXMAN_a8b8g8r8; 617 break; 618 case DP_GRAPHIC_RGB565: 619 s->g_plane.format = PIXMAN_r5g6b5; 620 break; 621 case DP_GRAPHIC_RGB888: 622 s->g_plane.format = PIXMAN_r8g8b8; 623 break; 624 case DP_GRAPHIC_BGR888: 625 s->g_plane.format = PIXMAN_b8g8r8; 626 break; 627 default: 628 DPRINTF("error: unsupported graphic format %u.\n", 629 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK); 630 abort(); 631 } 632 633 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) { 634 case 0: 635 s->v_plane.format = PIXMAN_x8b8g8r8; 636 break; 637 case DP_NL_VID_Y0_CB_Y1_CR: 638 s->v_plane.format = PIXMAN_yuy2; 639 break; 640 case DP_NL_VID_RGBA8880: 641 s->v_plane.format = PIXMAN_x8b8g8r8; 642 break; 643 default: 644 DPRINTF("error: unsupported video format %u.\n", 645 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK); 646 abort(); 647 } 648 649 xlnx_dp_recreate_surface(s); 650 } 651 652 static void xlnx_dp_update_irq(XlnxDPState *s) 653 { 654 uint32_t flags; 655 656 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK]; 657 DPRINTF("update IRQ value = %" PRIx32 "\n", flags); 658 qemu_set_irq(s->irq, flags != 0); 659 } 660 661 static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size) 662 { 663 XlnxDPState *s = XLNX_DP(opaque); 664 uint64_t ret = 0; 665 666 offset = offset >> 2; 667 668 switch (offset) { 669 case DP_TX_USER_FIFO_OVERFLOW: 670 /* This register is cleared after a read */ 671 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW]; 672 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0; 673 break; 674 case DP_AUX_REPLY_DATA: 675 ret = xlnx_dp_aux_pop_rx_fifo(s); 676 break; 677 case DP_INTERRUPT_SIGNAL_STATE: 678 /* 679 * XXX: Not sure it is the right thing to do actually. 680 * The register is not written by the device driver so it's stuck 681 * to 0x04. 682 */ 683 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE]; 684 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04; 685 break; 686 case DP_AUX_WRITE_FIFO: 687 case DP_TX_AUDIO_INFO_DATA(0): 688 case DP_TX_AUDIO_INFO_DATA(1): 689 case DP_TX_AUDIO_INFO_DATA(2): 690 case DP_TX_AUDIO_INFO_DATA(3): 691 case DP_TX_AUDIO_INFO_DATA(4): 692 case DP_TX_AUDIO_INFO_DATA(5): 693 case DP_TX_AUDIO_INFO_DATA(6): 694 case DP_TX_AUDIO_INFO_DATA(7): 695 case DP_TX_AUDIO_EXT_DATA(0): 696 case DP_TX_AUDIO_EXT_DATA(1): 697 case DP_TX_AUDIO_EXT_DATA(2): 698 case DP_TX_AUDIO_EXT_DATA(3): 699 case DP_TX_AUDIO_EXT_DATA(4): 700 case DP_TX_AUDIO_EXT_DATA(5): 701 case DP_TX_AUDIO_EXT_DATA(6): 702 case DP_TX_AUDIO_EXT_DATA(7): 703 case DP_TX_AUDIO_EXT_DATA(8): 704 /* write only registers */ 705 ret = 0; 706 break; 707 default: 708 assert(offset <= (0x3AC >> 2)); 709 ret = s->core_registers[offset]; 710 break; 711 } 712 713 DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret); 714 return ret; 715 } 716 717 static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, 718 unsigned size) 719 { 720 XlnxDPState *s = XLNX_DP(opaque); 721 722 DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value); 723 724 offset = offset >> 2; 725 726 switch (offset) { 727 /* 728 * Only special write case are handled. 729 */ 730 case DP_LINK_BW_SET: 731 s->core_registers[offset] = value & 0x000000FF; 732 break; 733 case DP_LANE_COUNT_SET: 734 case DP_MAIN_STREAM_MISC0: 735 s->core_registers[offset] = value & 0x0000000F; 736 break; 737 case DP_TRAINING_PATTERN_SET: 738 case DP_LINK_QUAL_PATTERN_SET: 739 case DP_MAIN_STREAM_POLARITY: 740 case DP_PHY_VOLTAGE_DIFF_LANE_0: 741 case DP_PHY_VOLTAGE_DIFF_LANE_1: 742 s->core_registers[offset] = value & 0x00000003; 743 break; 744 case DP_ENHANCED_FRAME_EN: 745 case DP_SCRAMBLING_DISABLE: 746 case DP_DOWNSPREAD_CTRL: 747 case DP_MAIN_STREAM_ENABLE: 748 case DP_TRANSMIT_PRBS7: 749 s->core_registers[offset] = value & 0x00000001; 750 break; 751 case DP_PHY_CLOCK_SELECT: 752 s->core_registers[offset] = value & 0x00000007; 753 break; 754 case DP_SOFTWARE_RESET: 755 /* 756 * No need to update this bit as it's read '0'. 757 */ 758 /* 759 * TODO: reset IP. 760 */ 761 break; 762 case DP_TRANSMITTER_ENABLE: 763 s->core_registers[offset] = value & 0x01; 764 break; 765 case DP_FORCE_SCRAMBLER_RESET: 766 /* 767 * No need to update this bit as it's read '0'. 768 */ 769 /* 770 * TODO: force a scrambler reset?? 771 */ 772 break; 773 case DP_AUX_COMMAND_REGISTER: 774 s->core_registers[offset] = value & 0x00001F0F; 775 xlnx_dp_aux_set_command(s, s->core_registers[offset]); 776 break; 777 case DP_MAIN_STREAM_HTOTAL: 778 case DP_MAIN_STREAM_VTOTAL: 779 case DP_MAIN_STREAM_HSTART: 780 case DP_MAIN_STREAM_VSTART: 781 s->core_registers[offset] = value & 0x0000FFFF; 782 break; 783 case DP_MAIN_STREAM_HRES: 784 case DP_MAIN_STREAM_VRES: 785 s->core_registers[offset] = value & 0x0000FFFF; 786 xlnx_dp_recreate_surface(s); 787 break; 788 case DP_MAIN_STREAM_HSWIDTH: 789 case DP_MAIN_STREAM_VSWIDTH: 790 s->core_registers[offset] = value & 0x00007FFF; 791 break; 792 case DP_MAIN_STREAM_MISC1: 793 s->core_registers[offset] = value & 0x00000086; 794 break; 795 case DP_MAIN_STREAM_M_VID: 796 case DP_MAIN_STREAM_N_VID: 797 s->core_registers[offset] = value & 0x00FFFFFF; 798 break; 799 case DP_MSA_TRANSFER_UNIT_SIZE: 800 case DP_MIN_BYTES_PER_TU: 801 case DP_INIT_WAIT: 802 s->core_registers[offset] = value & 0x00000007; 803 break; 804 case DP_USER_DATA_COUNT_PER_LANE: 805 s->core_registers[offset] = value & 0x0003FFFF; 806 break; 807 case DP_FRAC_BYTES_PER_TU: 808 s->core_registers[offset] = value & 0x000003FF; 809 break; 810 case DP_PHY_RESET: 811 s->core_registers[offset] = value & 0x00010003; 812 /* 813 * TODO: Reset something? 814 */ 815 break; 816 case DP_TX_PHY_POWER_DOWN: 817 s->core_registers[offset] = value & 0x0000000F; 818 /* 819 * TODO: Power down things? 820 */ 821 break; 822 case DP_AUX_WRITE_FIFO: { 823 uint8_t c = value; 824 xlnx_dp_aux_push_tx_fifo(s, &c, 1); 825 break; 826 } 827 case DP_AUX_CLOCK_DIVIDER: 828 break; 829 case DP_AUX_REPLY_COUNT: 830 /* 831 * Writing to this register clear the counter. 832 */ 833 s->core_registers[offset] = 0x00000000; 834 break; 835 case DP_AUX_ADDRESS: 836 s->core_registers[offset] = value & 0x000FFFFF; 837 break; 838 case DP_VERSION_REGISTER: 839 case DP_CORE_ID: 840 case DP_TX_USER_FIFO_OVERFLOW: 841 case DP_AUX_REPLY_DATA: 842 case DP_AUX_REPLY_CODE: 843 case DP_REPLY_DATA_COUNT: 844 case DP_REPLY_STATUS: 845 case DP_HPD_DURATION: 846 /* 847 * Write to read only location.. 848 */ 849 break; 850 case DP_TX_AUDIO_CONTROL: 851 s->core_registers[offset] = value & 0x00000001; 852 xlnx_dp_audio_activate(s); 853 break; 854 case DP_TX_AUDIO_CHANNELS: 855 s->core_registers[offset] = value & 0x00000007; 856 xlnx_dp_audio_activate(s); 857 break; 858 case DP_INT_STATUS: 859 s->core_registers[DP_INT_STATUS] &= ~value; 860 xlnx_dp_update_irq(s); 861 break; 862 case DP_INT_EN: 863 s->core_registers[DP_INT_MASK] &= ~value; 864 xlnx_dp_update_irq(s); 865 break; 866 case DP_INT_DS: 867 s->core_registers[DP_INT_MASK] |= ~value; 868 xlnx_dp_update_irq(s); 869 break; 870 default: 871 assert(offset <= (0x504C >> 2)); 872 s->core_registers[offset] = value; 873 break; 874 } 875 } 876 877 static const MemoryRegionOps dp_ops = { 878 .read = xlnx_dp_read, 879 .write = xlnx_dp_write, 880 .endianness = DEVICE_NATIVE_ENDIAN, 881 .valid = { 882 .min_access_size = 4, 883 .max_access_size = 4, 884 }, 885 .impl = { 886 .min_access_size = 4, 887 .max_access_size = 4, 888 }, 889 }; 890 891 /* 892 * This is to handle Read/Write to the Video Blender. 893 */ 894 static void xlnx_dp_vblend_write(void *opaque, hwaddr offset, 895 uint64_t value, unsigned size) 896 { 897 XlnxDPState *s = XLNX_DP(opaque); 898 bool alpha_was_enabled; 899 900 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 901 (uint32_t)value); 902 offset = offset >> 2; 903 904 switch (offset) { 905 case V_BLEND_BG_CLR_0: 906 case V_BLEND_BG_CLR_1: 907 case V_BLEND_BG_CLR_2: 908 s->vblend_registers[offset] = value & 0x00000FFF; 909 break; 910 case V_BLEND_SET_GLOBAL_ALPHA_REG: 911 /* 912 * A write to this register can enable or disable blending. Thus we need 913 * to recreate the surfaces. 914 */ 915 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s); 916 s->vblend_registers[offset] = value & 0x000001FF; 917 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) { 918 xlnx_dp_recreate_surface(s); 919 } 920 break; 921 case V_BLEND_OUTPUT_VID_FORMAT: 922 s->vblend_registers[offset] = value & 0x00000017; 923 break; 924 case V_BLEND_LAYER0_CONTROL: 925 case V_BLEND_LAYER1_CONTROL: 926 s->vblend_registers[offset] = value & 0x00000103; 927 break; 928 case V_BLEND_RGB2YCBCR_COEFF(0): 929 case V_BLEND_RGB2YCBCR_COEFF(1): 930 case V_BLEND_RGB2YCBCR_COEFF(2): 931 case V_BLEND_RGB2YCBCR_COEFF(3): 932 case V_BLEND_RGB2YCBCR_COEFF(4): 933 case V_BLEND_RGB2YCBCR_COEFF(5): 934 case V_BLEND_RGB2YCBCR_COEFF(6): 935 case V_BLEND_RGB2YCBCR_COEFF(7): 936 case V_BLEND_RGB2YCBCR_COEFF(8): 937 case V_BLEND_IN1CSC_COEFF(0): 938 case V_BLEND_IN1CSC_COEFF(1): 939 case V_BLEND_IN1CSC_COEFF(2): 940 case V_BLEND_IN1CSC_COEFF(3): 941 case V_BLEND_IN1CSC_COEFF(4): 942 case V_BLEND_IN1CSC_COEFF(5): 943 case V_BLEND_IN1CSC_COEFF(6): 944 case V_BLEND_IN1CSC_COEFF(7): 945 case V_BLEND_IN1CSC_COEFF(8): 946 case V_BLEND_IN2CSC_COEFF(0): 947 case V_BLEND_IN2CSC_COEFF(1): 948 case V_BLEND_IN2CSC_COEFF(2): 949 case V_BLEND_IN2CSC_COEFF(3): 950 case V_BLEND_IN2CSC_COEFF(4): 951 case V_BLEND_IN2CSC_COEFF(5): 952 case V_BLEND_IN2CSC_COEFF(6): 953 case V_BLEND_IN2CSC_COEFF(7): 954 case V_BLEND_IN2CSC_COEFF(8): 955 s->vblend_registers[offset] = value & 0x0000FFFF; 956 break; 957 case V_BLEND_LUMA_IN1CSC_OFFSET: 958 case V_BLEND_CR_IN1CSC_OFFSET: 959 case V_BLEND_CB_IN1CSC_OFFSET: 960 case V_BLEND_LUMA_IN2CSC_OFFSET: 961 case V_BLEND_CR_IN2CSC_OFFSET: 962 case V_BLEND_CB_IN2CSC_OFFSET: 963 case V_BLEND_LUMA_OUTCSC_OFFSET: 964 case V_BLEND_CR_OUTCSC_OFFSET: 965 case V_BLEND_CB_OUTCSC_OFFSET: 966 s->vblend_registers[offset] = value & 0x3FFF7FFF; 967 break; 968 case V_BLEND_CHROMA_KEY_ENABLE: 969 s->vblend_registers[offset] = value & 0x00000003; 970 break; 971 case V_BLEND_CHROMA_KEY_COMP1: 972 case V_BLEND_CHROMA_KEY_COMP2: 973 case V_BLEND_CHROMA_KEY_COMP3: 974 s->vblend_registers[offset] = value & 0x0FFF0FFF; 975 break; 976 default: 977 s->vblend_registers[offset] = value; 978 break; 979 } 980 } 981 982 static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset, 983 unsigned size) 984 { 985 XlnxDPState *s = XLNX_DP(opaque); 986 987 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 988 s->vblend_registers[offset >> 2]); 989 return s->vblend_registers[offset >> 2]; 990 } 991 992 static const MemoryRegionOps vblend_ops = { 993 .read = xlnx_dp_vblend_read, 994 .write = xlnx_dp_vblend_write, 995 .endianness = DEVICE_NATIVE_ENDIAN, 996 .valid = { 997 .min_access_size = 4, 998 .max_access_size = 4, 999 }, 1000 .impl = { 1001 .min_access_size = 4, 1002 .max_access_size = 4, 1003 }, 1004 }; 1005 1006 /* 1007 * This is to handle Read/Write to the Audio Video buffer manager. 1008 */ 1009 static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value, 1010 unsigned size) 1011 { 1012 XlnxDPState *s = XLNX_DP(opaque); 1013 1014 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 1015 (uint32_t)value); 1016 offset = offset >> 2; 1017 1018 switch (offset) { 1019 case AV_BUF_FORMAT: 1020 s->avbufm_registers[offset] = value & 0x00000FFF; 1021 xlnx_dp_change_graphic_fmt(s); 1022 break; 1023 case AV_CHBUF0: 1024 case AV_CHBUF1: 1025 case AV_CHBUF2: 1026 case AV_CHBUF3: 1027 case AV_CHBUF4: 1028 case AV_CHBUF5: 1029 s->avbufm_registers[offset] = value & 0x0000007F; 1030 break; 1031 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT: 1032 s->avbufm_registers[offset] = value & 0x0000007F; 1033 break; 1034 case AV_BUF_DITHER_CONFIG: 1035 s->avbufm_registers[offset] = value & 0x000007FF; 1036 break; 1037 case AV_BUF_DITHER_CONFIG_MAX: 1038 case AV_BUF_DITHER_CONFIG_MIN: 1039 s->avbufm_registers[offset] = value & 0x00000FFF; 1040 break; 1041 case AV_BUF_PATTERN_GEN_SELECT: 1042 s->avbufm_registers[offset] = value & 0xFFFFFF03; 1043 break; 1044 case AV_BUF_AUD_VID_CLK_SOURCE: 1045 s->avbufm_registers[offset] = value & 0x00000007; 1046 break; 1047 case AV_BUF_SRST_REG: 1048 s->avbufm_registers[offset] = value & 0x00000002; 1049 break; 1050 case AV_BUF_AUDIO_CH_CONFIG: 1051 s->avbufm_registers[offset] = value & 0x00000003; 1052 break; 1053 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0): 1054 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1): 1055 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2): 1056 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0): 1057 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1): 1058 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2): 1059 s->avbufm_registers[offset] = value & 0x0000FFFF; 1060 break; 1061 case AV_BUF_LIVE_VIDEO_COMP_SF(0): 1062 case AV_BUF_LIVE_VIDEO_COMP_SF(1): 1063 case AV_BUF_LIVE_VIDEO_COMP_SF(2): 1064 case AV_BUF_LIVE_VID_CONFIG: 1065 case AV_BUF_LIVE_GFX_COMP_SF(0): 1066 case AV_BUF_LIVE_GFX_COMP_SF(1): 1067 case AV_BUF_LIVE_GFX_COMP_SF(2): 1068 case AV_BUF_LIVE_GFX_CONFIG: 1069 case AV_BUF_NON_LIVE_LATENCY: 1070 case AV_BUF_STC_CONTROL: 1071 case AV_BUF_STC_INIT_VALUE0: 1072 case AV_BUF_STC_INIT_VALUE1: 1073 case AV_BUF_STC_ADJ: 1074 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0: 1075 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1: 1076 case AV_BUF_STC_EXT_VSYNC_TS_REG0: 1077 case AV_BUF_STC_EXT_VSYNC_TS_REG1: 1078 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0: 1079 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1: 1080 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0: 1081 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1: 1082 case AV_BUF_STC_SNAPSHOT0: 1083 case AV_BUF_STC_SNAPSHOT1: 1084 case AV_BUF_HCOUNT_VCOUNT_INT0: 1085 case AV_BUF_HCOUNT_VCOUNT_INT1: 1086 qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04" 1087 PRIx64 "\n", 1088 offset << 2); 1089 break; 1090 default: 1091 s->avbufm_registers[offset] = value; 1092 break; 1093 } 1094 } 1095 1096 static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset, 1097 unsigned size) 1098 { 1099 XlnxDPState *s = XLNX_DP(opaque); 1100 1101 offset = offset >> 2; 1102 return s->avbufm_registers[offset]; 1103 } 1104 1105 static const MemoryRegionOps avbufm_ops = { 1106 .read = xlnx_dp_avbufm_read, 1107 .write = xlnx_dp_avbufm_write, 1108 .endianness = DEVICE_NATIVE_ENDIAN, 1109 .valid = { 1110 .min_access_size = 4, 1111 .max_access_size = 4, 1112 }, 1113 .impl = { 1114 .min_access_size = 4, 1115 .max_access_size = 4, 1116 }, 1117 }; 1118 1119 /* 1120 * This is a global alpha blending using pixman. 1121 * Both graphic and video planes are multiplied with the global alpha 1122 * coefficient and added. 1123 */ 1124 static inline void xlnx_dp_blend_surface(XlnxDPState *s) 1125 { 1126 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1), 1127 pixman_double_to_fixed(1), 1128 pixman_double_to_fixed(1.0) }; 1129 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1), 1130 pixman_double_to_fixed(1), 1131 pixman_double_to_fixed(1.0) }; 1132 1133 if ((surface_width(s->g_plane.surface) 1134 != surface_width(s->v_plane.surface)) || 1135 (surface_height(s->g_plane.surface) 1136 != surface_height(s->v_plane.surface))) { 1137 return; 1138 } 1139 1140 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s)) 1141 / 256.0); 1142 alpha2[2] = pixman_double_to_fixed((255.0 1143 - (double)xlnx_dp_global_alpha_value(s)) 1144 / 256.0); 1145 1146 pixman_image_set_filter(s->g_plane.surface->image, 1147 PIXMAN_FILTER_CONVOLUTION, alpha1, 3); 1148 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0, 1149 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, 1150 surface_width(s->g_plane.surface), 1151 surface_height(s->g_plane.surface)); 1152 pixman_image_set_filter(s->v_plane.surface->image, 1153 PIXMAN_FILTER_CONVOLUTION, alpha2, 3); 1154 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0, 1155 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, 1156 surface_width(s->g_plane.surface), 1157 surface_height(s->g_plane.surface)); 1158 } 1159 1160 static void xlnx_dp_update_display(void *opaque) 1161 { 1162 XlnxDPState *s = XLNX_DP(opaque); 1163 1164 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) { 1165 return; 1166 } 1167 1168 s->core_registers[DP_INT_STATUS] |= (1 << 13); 1169 xlnx_dp_update_irq(s); 1170 1171 xlnx_dpdma_trigger_vsync_irq(s->dpdma); 1172 1173 /* 1174 * Trigger the DMA channel. 1175 */ 1176 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) { 1177 /* 1178 * An error occurred don't do anything with the data.. 1179 * Trigger an underflow interrupt. 1180 */ 1181 s->core_registers[DP_INT_STATUS] |= (1 << 21); 1182 xlnx_dp_update_irq(s); 1183 return; 1184 } 1185 1186 if (xlnx_dp_global_alpha_enabled(s)) { 1187 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) { 1188 s->core_registers[DP_INT_STATUS] |= (1 << 21); 1189 xlnx_dp_update_irq(s); 1190 return; 1191 } 1192 xlnx_dp_blend_surface(s); 1193 } 1194 1195 /* 1196 * XXX: We might want to update only what changed. 1197 */ 1198 dpy_gfx_update_full(s->console); 1199 } 1200 1201 static const GraphicHwOps xlnx_dp_gfx_ops = { 1202 .gfx_update = xlnx_dp_update_display, 1203 }; 1204 1205 static void xlnx_dp_init(Object *obj) 1206 { 1207 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1208 XlnxDPState *s = XLNX_DP(obj); 1209 1210 memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050); 1211 1212 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP 1213 ".core", 0x3AF); 1214 memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem); 1215 1216 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP 1217 ".v_blend", 0x1DF); 1218 memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem); 1219 1220 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP 1221 ".av_buffer_manager", 0x238); 1222 memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem); 1223 1224 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP 1225 ".audio", sizeof(s->audio_registers)); 1226 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem); 1227 1228 sysbus_init_mmio(sbd, &s->container); 1229 sysbus_init_irq(sbd, &s->irq); 1230 1231 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA, 1232 (Object **) &s->dpdma, 1233 xlnx_dp_set_dpdma, 1234 OBJ_PROP_LINK_STRONG, 1235 &error_abort); 1236 1237 /* 1238 * Initialize AUX Bus. 1239 */ 1240 s->aux_bus = aux_init_bus(DEVICE(obj), "aux"); 1241 1242 /* 1243 * Initialize DPCD and EDID.. 1244 */ 1245 s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd")); 1246 object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd), NULL); 1247 1248 s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc")); 1249 i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50); 1250 object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid), NULL); 1251 1252 fifo8_create(&s->rx_fifo, 16); 1253 fifo8_create(&s->tx_fifo, 16); 1254 } 1255 1256 static void xlnx_dp_realize(DeviceState *dev, Error **errp) 1257 { 1258 XlnxDPState *s = XLNX_DP(dev); 1259 DisplaySurface *surface; 1260 struct audsettings as; 1261 1262 qdev_init_nofail(DEVICE(s->dpcd)); 1263 aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000); 1264 1265 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s); 1266 surface = qemu_console_surface(s->console); 1267 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, 1268 surface_data(surface)); 1269 1270 as.freq = 44100; 1271 as.nchannels = 2; 1272 as.fmt = AUDIO_FORMAT_S16; 1273 as.endianness = 0; 1274 1275 AUD_register_card("xlnx_dp.audio", &s->aud_card); 1276 1277 s->amixer_output_stream = AUD_open_out(&s->aud_card, 1278 s->amixer_output_stream, 1279 "xlnx_dp.audio.out", 1280 s, 1281 xlnx_dp_audio_callback, 1282 &as); 1283 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255); 1284 xlnx_dp_audio_activate(s); 1285 } 1286 1287 static void xlnx_dp_reset(DeviceState *dev) 1288 { 1289 XlnxDPState *s = XLNX_DP(dev); 1290 1291 memset(s->core_registers, 0, sizeof(s->core_registers)); 1292 s->core_registers[DP_VERSION_REGISTER] = 0x04010000; 1293 s->core_registers[DP_CORE_ID] = 0x01020000; 1294 s->core_registers[DP_REPLY_STATUS] = 0x00000010; 1295 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040; 1296 s->core_registers[DP_INIT_WAIT] = 0x00000020; 1297 s->core_registers[DP_PHY_RESET] = 0x00010003; 1298 s->core_registers[DP_INT_MASK] = 0xFFFFF03F; 1299 s->core_registers[DP_PHY_STATUS] = 0x00000043; 1300 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001; 1301 1302 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000; 1303 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000; 1304 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000; 1305 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000; 1306 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000; 1307 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000; 1308 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000; 1309 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000; 1310 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000; 1311 1312 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180; 1313 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008; 1314 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF; 1315 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101; 1316 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101; 1317 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101; 1318 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101; 1319 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101; 1320 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101; 1321 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101; 1322 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101; 1323 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101; 1324 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101; 1325 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101; 1326 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101; 1327 1328 memset(s->audio_registers, 0, sizeof(s->audio_registers)); 1329 s->byte_left = 0; 1330 1331 xlnx_dp_aux_clear_rx_fifo(s); 1332 xlnx_dp_change_graphic_fmt(s); 1333 xlnx_dp_update_irq(s); 1334 } 1335 1336 static void xlnx_dp_class_init(ObjectClass *oc, void *data) 1337 { 1338 DeviceClass *dc = DEVICE_CLASS(oc); 1339 1340 dc->realize = xlnx_dp_realize; 1341 dc->vmsd = &vmstate_dp; 1342 dc->reset = xlnx_dp_reset; 1343 } 1344 1345 static const TypeInfo xlnx_dp_info = { 1346 .name = TYPE_XLNX_DP, 1347 .parent = TYPE_SYS_BUS_DEVICE, 1348 .instance_size = sizeof(XlnxDPState), 1349 .instance_init = xlnx_dp_init, 1350 .class_init = xlnx_dp_class_init, 1351 }; 1352 1353 static void xlnx_dp_register_types(void) 1354 { 1355 type_register_static(&xlnx_dp_info); 1356 } 1357 1358 type_init(xlnx_dp_register_types) 1359