1 /* 2 * xlnx_dp.c 3 * 4 * Copyright (C) 2015 : GreenSocs Ltd 5 * http://www.greensocs.com/ , email: info@greensocs.com 6 * 7 * Developed by : 8 * Frederic Konrad <fred.konrad@greensocs.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option)any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 * 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu/log.h" 28 #include "qemu/module.h" 29 #include "hw/display/xlnx_dp.h" 30 31 #ifndef DEBUG_DP 32 #define DEBUG_DP 0 33 #endif 34 35 #define DPRINTF(fmt, ...) do { \ 36 if (DEBUG_DP) { \ 37 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \ 38 } \ 39 } while (0) 40 41 /* 42 * Register offset for DP. 43 */ 44 #define DP_LINK_BW_SET (0x0000 >> 2) 45 #define DP_LANE_COUNT_SET (0x0004 >> 2) 46 #define DP_ENHANCED_FRAME_EN (0x0008 >> 2) 47 #define DP_TRAINING_PATTERN_SET (0x000C >> 2) 48 #define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2) 49 #define DP_SCRAMBLING_DISABLE (0x0014 >> 2) 50 #define DP_DOWNSPREAD_CTRL (0x0018 >> 2) 51 #define DP_SOFTWARE_RESET (0x001C >> 2) 52 #define DP_TRANSMITTER_ENABLE (0x0080 >> 2) 53 #define DP_MAIN_STREAM_ENABLE (0x0084 >> 2) 54 #define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2) 55 #define DP_VERSION_REGISTER (0x00F8 >> 2) 56 #define DP_CORE_ID (0x00FC >> 2) 57 58 #define DP_AUX_COMMAND_REGISTER (0x0100 >> 2) 59 #define AUX_ADDR_ONLY_MASK (0x1000) 60 #define AUX_COMMAND_MASK (0x0F00) 61 #define AUX_COMMAND_SHIFT (8) 62 #define AUX_COMMAND_NBYTES (0x000F) 63 64 #define DP_AUX_WRITE_FIFO (0x0104 >> 2) 65 #define DP_AUX_ADDRESS (0x0108 >> 2) 66 #define DP_AUX_CLOCK_DIVIDER (0x010C >> 2) 67 #define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2) 68 #define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2) 69 #define DP_AUX_REPLY_DATA (0x0134 >> 2) 70 #define DP_AUX_REPLY_CODE (0x0138 >> 2) 71 #define DP_AUX_REPLY_COUNT (0x013C >> 2) 72 #define DP_REPLY_DATA_COUNT (0x0148 >> 2) 73 #define DP_REPLY_STATUS (0x014C >> 2) 74 #define DP_HPD_DURATION (0x0150 >> 2) 75 #define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2) 76 #define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2) 77 #define DP_MAIN_STREAM_POLARITY (0x0188 >> 2) 78 #define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2) 79 #define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2) 80 #define DP_MAIN_STREAM_HRES (0x0194 >> 2) 81 #define DP_MAIN_STREAM_VRES (0x0198 >> 2) 82 #define DP_MAIN_STREAM_HSTART (0x019C >> 2) 83 #define DP_MAIN_STREAM_VSTART (0x01A0 >> 2) 84 #define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2) 85 #define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2) 86 #define DP_MAIN_STREAM_M_VID (0x01AC >> 2) 87 #define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2) 88 #define DP_MAIN_STREAM_N_VID (0x01B4 >> 2) 89 #define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2) 90 #define DP_MIN_BYTES_PER_TU (0x01C4 >> 2) 91 #define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2) 92 #define DP_INIT_WAIT (0x01CC >> 2) 93 #define DP_PHY_RESET (0x0200 >> 2) 94 #define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2) 95 #define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2) 96 #define DP_TRANSMIT_PRBS7 (0x0230 >> 2) 97 #define DP_PHY_CLOCK_SELECT (0x0234 >> 2) 98 #define DP_TX_PHY_POWER_DOWN (0x0238 >> 2) 99 #define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2) 100 #define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2) 101 #define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2) 102 #define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2) 103 #define DP_PHY_STATUS (0x0280 >> 2) 104 105 #define DP_TX_AUDIO_CONTROL (0x0300 >> 2) 106 #define DP_TX_AUD_CTRL (1) 107 108 #define DP_TX_AUDIO_CHANNELS (0x0304 >> 2) 109 #define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2) 110 #define DP_TX_M_AUD (0x0328 >> 2) 111 #define DP_TX_N_AUD (0x032C >> 2) 112 #define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2) 113 #define DP_INT_STATUS (0x03A0 >> 2) 114 #define DP_INT_MASK (0x03A4 >> 2) 115 #define DP_INT_EN (0x03A8 >> 2) 116 #define DP_INT_DS (0x03AC >> 2) 117 118 /* 119 * Registers offset for Audio Video Buffer configuration. 120 */ 121 #define V_BLEND_OFFSET (0xA000) 122 #define V_BLEND_BG_CLR_0 (0x0000 >> 2) 123 #define V_BLEND_BG_CLR_1 (0x0004 >> 2) 124 #define V_BLEND_BG_CLR_2 (0x0008 >> 2) 125 #define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2) 126 #define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2) 127 #define V_BLEND_LAYER0_CONTROL (0x0018 >> 2) 128 #define V_BLEND_LAYER1_CONTROL (0x001C >> 2) 129 130 #define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2) 131 #define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2) 132 133 #define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2) 134 #define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2) 135 #define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2) 136 #define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2) 137 #define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2) 138 #define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2) 139 140 #define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2) 141 142 #define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2) 143 #define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2) 144 #define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2) 145 #define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2) 146 #define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2) 147 #define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2) 148 #define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2) 149 150 /* 151 * Registers offset for Audio Video Buffer configuration. 152 */ 153 #define AV_BUF_MANAGER_OFFSET (0xB000) 154 #define AV_BUF_FORMAT (0x0000 >> 2) 155 #define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2) 156 #define AV_CHBUF0 (0x0010 >> 2) 157 #define AV_CHBUF1 (0x0014 >> 2) 158 #define AV_CHBUF2 (0x0018 >> 2) 159 #define AV_CHBUF3 (0x001C >> 2) 160 #define AV_CHBUF4 (0x0020 >> 2) 161 #define AV_CHBUF5 (0x0024 >> 2) 162 #define AV_BUF_STC_CONTROL (0x002C >> 2) 163 #define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2) 164 #define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2) 165 #define AV_BUF_STC_ADJ (0x0038 >> 2) 166 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2) 167 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2) 168 #define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2) 169 #define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2) 170 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2) 171 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2) 172 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2) 173 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2) 174 #define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2) 175 #define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2) 176 #define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2) 177 #define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2) 178 #define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2) 179 #define AV_BUF_DITHER_CONFIG (0x007C >> 2) 180 #define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2) 181 #define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2) 182 #define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2) 183 #define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2) 184 #define AV_BUF_SRST_REG (0x0124 >> 2) 185 #define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2) 186 #define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2) 187 188 #define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2) 189 190 #define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2) 191 192 #define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2) 193 194 #define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2) 195 196 #define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2) 197 198 #define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2) 199 200 #define AUDIO_MIXER_REGISTER_OFFSET (0xC000) 201 #define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2) 202 #define AUDIO_MIXER_META_DATA (0x0004 >> 2) 203 #define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2) 204 #define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2) 205 #define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2) 206 207 #define DP_AUDIO_DMA_CHANNEL(n) (4 + n) 208 #define DP_GRAPHIC_DMA_CHANNEL (3) 209 #define DP_VIDEO_DMA_CHANNEL (0) 210 211 enum DPGraphicFmt { 212 DP_GRAPHIC_RGBA8888 = 0 << 8, 213 DP_GRAPHIC_ABGR8888 = 1 << 8, 214 DP_GRAPHIC_RGB888 = 2 << 8, 215 DP_GRAPHIC_BGR888 = 3 << 8, 216 DP_GRAPHIC_RGBA5551 = 4 << 8, 217 DP_GRAPHIC_RGBA4444 = 5 << 8, 218 DP_GRAPHIC_RGB565 = 6 << 8, 219 DP_GRAPHIC_8BPP = 7 << 8, 220 DP_GRAPHIC_4BPP = 8 << 8, 221 DP_GRAPHIC_2BPP = 9 << 8, 222 DP_GRAPHIC_1BPP = 10 << 8, 223 DP_GRAPHIC_MASK = 0xF << 8 224 }; 225 226 enum DPVideoFmt { 227 DP_NL_VID_CB_Y0_CR_Y1 = 0, 228 DP_NL_VID_CR_Y0_CB_Y1 = 1, 229 DP_NL_VID_Y0_CR_Y1_CB = 2, 230 DP_NL_VID_Y0_CB_Y1_CR = 3, 231 DP_NL_VID_YV16 = 4, 232 DP_NL_VID_YV24 = 5, 233 DP_NL_VID_YV16CL = 6, 234 DP_NL_VID_MONO = 7, 235 DP_NL_VID_YV16CL2 = 8, 236 DP_NL_VID_YUV444 = 9, 237 DP_NL_VID_RGB888 = 10, 238 DP_NL_VID_RGBA8880 = 11, 239 DP_NL_VID_RGB888_10BPC = 12, 240 DP_NL_VID_YUV444_10BPC = 13, 241 DP_NL_VID_YV16CL2_10BPC = 14, 242 DP_NL_VID_YV16CL_10BPC = 15, 243 DP_NL_VID_YV16_10BPC = 16, 244 DP_NL_VID_YV24_10BPC = 17, 245 DP_NL_VID_Y_ONLY_10BPC = 18, 246 DP_NL_VID_YV16_420 = 19, 247 DP_NL_VID_YV16CL_420 = 20, 248 DP_NL_VID_YV16CL2_420 = 21, 249 DP_NL_VID_YV16_420_10BPC = 22, 250 DP_NL_VID_YV16CL_420_10BPC = 23, 251 DP_NL_VID_YV16CL2_420_10BPC = 24, 252 DP_NL_VID_FMT_MASK = 0x1F 253 }; 254 255 typedef enum DPGraphicFmt DPGraphicFmt; 256 typedef enum DPVideoFmt DPVideoFmt; 257 258 static const VMStateDescription vmstate_dp = { 259 .name = TYPE_XLNX_DP, 260 .version_id = 1, 261 .fields = (VMStateField[]){ 262 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState, 263 DP_CORE_REG_ARRAY_SIZE), 264 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState, 265 DP_AVBUF_REG_ARRAY_SIZE), 266 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState, 267 DP_VBLEND_REG_ARRAY_SIZE), 268 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState, 269 DP_AUDIO_REG_ARRAY_SIZE), 270 VMSTATE_END_OF_LIST() 271 } 272 }; 273 274 static void xlnx_dp_update_irq(XlnxDPState *s); 275 276 static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size) 277 { 278 XlnxDPState *s = XLNX_DP(opaque); 279 280 offset = offset >> 2; 281 return s->audio_registers[offset]; 282 } 283 284 static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value, 285 unsigned size) 286 { 287 XlnxDPState *s = XLNX_DP(opaque); 288 289 offset = offset >> 2; 290 291 switch (offset) { 292 case AUDIO_MIXER_META_DATA: 293 s->audio_registers[offset] = value & 0x00000001; 294 break; 295 default: 296 s->audio_registers[offset] = value; 297 break; 298 } 299 } 300 301 static const MemoryRegionOps audio_ops = { 302 .read = xlnx_dp_audio_read, 303 .write = xlnx_dp_audio_write, 304 .endianness = DEVICE_NATIVE_ENDIAN, 305 }; 306 307 static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s, 308 uint8_t channel) 309 { 310 switch (channel) { 311 case 0: 312 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16); 313 case 1: 314 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16, 315 16); 316 default: 317 return 0; 318 } 319 } 320 321 static inline void xlnx_dp_audio_activate(XlnxDPState *s) 322 { 323 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL] 324 & DP_TX_AUD_CTRL) != 0); 325 AUD_set_active_out(s->amixer_output_stream, activated); 326 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0), 327 &s->audio_buffer_0); 328 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1), 329 &s->audio_buffer_1); 330 } 331 332 static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s) 333 { 334 /* 335 * Audio packets are signed and have this shape: 336 * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 337 * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 | 338 * 339 * Output audio is 16bits saturated. 340 */ 341 int i; 342 343 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) { 344 for (i = 0; i < s->audio_data_available[0] / 2; i++) { 345 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i]) 346 * xlnx_dp_audio_get_volume(s, 0) / 8192; 347 } 348 s->byte_left = s->audio_data_available[0]; 349 } else { 350 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2); 351 } 352 353 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) { 354 if ((s->audio_data_available[0] == 0) 355 || (s->audio_data_available[1] == s->audio_data_available[0])) { 356 for (i = 0; i < s->audio_data_available[1] / 2; i++) { 357 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i]) 358 * xlnx_dp_audio_get_volume(s, 1) / 8192; 359 } 360 s->byte_left = s->audio_data_available[1]; 361 } 362 } 363 364 for (i = 0; i < s->byte_left / 2; i++) { 365 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767)); 366 } 367 368 s->data_ptr = 0; 369 } 370 371 static void xlnx_dp_audio_callback(void *opaque, int avail) 372 { 373 /* 374 * Get some data from the DPDMA and compute these datas. 375 * Then wait for QEMU's audio subsystem to call this callback. 376 */ 377 XlnxDPState *s = XLNX_DP(opaque); 378 size_t written = 0; 379 380 /* If there are already some data don't get more data. */ 381 if (s->byte_left == 0) { 382 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4, 383 true); 384 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5, 385 true); 386 xlnx_dp_audio_mix_buffer(s); 387 } 388 389 /* Send the buffer through the audio. */ 390 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) { 391 if (s->byte_left != 0) { 392 written = AUD_write(s->amixer_output_stream, 393 &s->out_buffer[s->data_ptr], s->byte_left); 394 } else { 395 /* 396 * There is nothing to play.. We don't have any data! Fill the 397 * buffer with zero's and send it. 398 */ 399 written = 0; 400 memset(s->out_buffer, 0, 1024); 401 AUD_write(s->amixer_output_stream, s->out_buffer, 1024); 402 } 403 } else { 404 written = AUD_write(s->amixer_output_stream, 405 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE); 406 } 407 s->byte_left -= written; 408 s->data_ptr += written; 409 } 410 411 /* 412 * AUX channel related function. 413 */ 414 static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s) 415 { 416 fifo8_reset(&s->rx_fifo); 417 } 418 419 static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) 420 { 421 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len); 422 fifo8_push_all(&s->rx_fifo, buf, len); 423 } 424 425 static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s) 426 { 427 uint8_t ret; 428 429 if (fifo8_is_empty(&s->rx_fifo)) { 430 DPRINTF("rx_fifo underflow..\n"); 431 abort(); 432 } 433 ret = fifo8_pop(&s->rx_fifo); 434 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret); 435 return ret; 436 } 437 438 static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s) 439 { 440 fifo8_reset(&s->tx_fifo); 441 } 442 443 static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) 444 { 445 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len); 446 fifo8_push_all(&s->tx_fifo, buf, len); 447 } 448 449 static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s) 450 { 451 uint8_t ret; 452 453 if (fifo8_is_empty(&s->tx_fifo)) { 454 DPRINTF("tx_fifo underflow..\n"); 455 abort(); 456 } 457 ret = fifo8_pop(&s->tx_fifo); 458 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret); 459 return ret; 460 } 461 462 static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s) 463 { 464 return s->core_registers[DP_AUX_ADDRESS]; 465 } 466 467 /* 468 * Get command from the register. 469 */ 470 static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value) 471 { 472 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0; 473 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT; 474 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1; 475 uint8_t buf[16]; 476 int i; 477 478 /* 479 * When an address_only command is executed nothing happen to the fifo, so 480 * just make nbytes = 0. 481 */ 482 if (address_only) { 483 nbytes = 0; 484 } 485 486 switch (cmd) { 487 case READ_AUX: 488 case READ_I2C: 489 case READ_I2C_MOT: 490 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, 491 xlnx_dp_aux_get_address(s), 492 nbytes, buf); 493 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes; 494 495 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) { 496 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes); 497 } 498 break; 499 case WRITE_AUX: 500 case WRITE_I2C: 501 case WRITE_I2C_MOT: 502 for (i = 0; i < nbytes; i++) { 503 buf[i] = xlnx_dp_aux_pop_tx_fifo(s); 504 } 505 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, 506 xlnx_dp_aux_get_address(s), 507 nbytes, buf); 508 xlnx_dp_aux_clear_tx_fifo(s); 509 break; 510 case WRITE_I2C_STATUS: 511 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n"); 512 break; 513 default: 514 abort(); 515 } 516 517 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04; 518 } 519 520 static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val, 521 Error **errp) 522 { 523 XlnxDPState *s = XLNX_DP(obj); 524 if (s->console) { 525 DisplaySurface *surface = qemu_console_surface(s->console); 526 XlnxDPDMAState *dma = XLNX_DPDMA(val); 527 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL, 528 surface_data(surface)); 529 } 530 } 531 532 static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s) 533 { 534 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1; 535 } 536 537 static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s) 538 { 539 /* 540 * If the alpha is totally opaque (255) we consider the alpha is disabled to 541 * reduce CPU consumption. 542 */ 543 return ((xlnx_dp_global_alpha_value(s) != 0xFF) && 544 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0)); 545 } 546 547 static void xlnx_dp_recreate_surface(XlnxDPState *s) 548 { 549 /* 550 * Two possibilities, if blending is enabled the console displays 551 * bout_plane, if not g_plane is displayed. 552 */ 553 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES]; 554 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES]; 555 DisplaySurface *current_console_surface = qemu_console_surface(s->console); 556 557 if ((width != 0) && (height != 0)) { 558 /* 559 * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the 560 * surface we need to be careful and don't free the surface associated 561 * to the console or double free will happen. 562 */ 563 if (s->bout_plane.surface != current_console_surface) { 564 qemu_free_displaysurface(s->bout_plane.surface); 565 } 566 if (s->v_plane.surface != current_console_surface) { 567 qemu_free_displaysurface(s->v_plane.surface); 568 } 569 if (s->g_plane.surface != current_console_surface) { 570 qemu_free_displaysurface(s->g_plane.surface); 571 } 572 573 s->g_plane.surface 574 = qemu_create_displaysurface_from(width, height, 575 s->g_plane.format, 0, NULL); 576 s->v_plane.surface 577 = qemu_create_displaysurface_from(width, height, 578 s->v_plane.format, 0, NULL); 579 if (xlnx_dp_global_alpha_enabled(s)) { 580 s->bout_plane.surface = 581 qemu_create_displaysurface_from(width, 582 height, 583 s->g_plane.format, 584 0, NULL); 585 dpy_gfx_replace_surface(s->console, s->bout_plane.surface); 586 } else { 587 s->bout_plane.surface = NULL; 588 dpy_gfx_replace_surface(s->console, s->g_plane.surface); 589 } 590 591 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, 592 surface_data(s->g_plane.surface)); 593 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL, 594 surface_data(s->v_plane.surface)); 595 } 596 } 597 598 /* 599 * Change the graphic format of the surface. 600 */ 601 static void xlnx_dp_change_graphic_fmt(XlnxDPState *s) 602 { 603 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) { 604 case DP_GRAPHIC_RGBA8888: 605 s->g_plane.format = PIXMAN_r8g8b8a8; 606 break; 607 case DP_GRAPHIC_ABGR8888: 608 s->g_plane.format = PIXMAN_a8b8g8r8; 609 break; 610 case DP_GRAPHIC_RGB565: 611 s->g_plane.format = PIXMAN_r5g6b5; 612 break; 613 case DP_GRAPHIC_RGB888: 614 s->g_plane.format = PIXMAN_r8g8b8; 615 break; 616 case DP_GRAPHIC_BGR888: 617 s->g_plane.format = PIXMAN_b8g8r8; 618 break; 619 default: 620 DPRINTF("error: unsupported graphic format %u.\n", 621 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK); 622 abort(); 623 } 624 625 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) { 626 case 0: 627 s->v_plane.format = PIXMAN_x8b8g8r8; 628 break; 629 case DP_NL_VID_Y0_CB_Y1_CR: 630 s->v_plane.format = PIXMAN_yuy2; 631 break; 632 case DP_NL_VID_RGBA8880: 633 s->v_plane.format = PIXMAN_x8b8g8r8; 634 break; 635 default: 636 DPRINTF("error: unsupported video format %u.\n", 637 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK); 638 abort(); 639 } 640 641 xlnx_dp_recreate_surface(s); 642 } 643 644 static void xlnx_dp_update_irq(XlnxDPState *s) 645 { 646 uint32_t flags; 647 648 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK]; 649 DPRINTF("update IRQ value = %" PRIx32 "\n", flags); 650 qemu_set_irq(s->irq, flags != 0); 651 } 652 653 static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size) 654 { 655 XlnxDPState *s = XLNX_DP(opaque); 656 uint64_t ret = 0; 657 658 offset = offset >> 2; 659 660 switch (offset) { 661 case DP_TX_USER_FIFO_OVERFLOW: 662 /* This register is cleared after a read */ 663 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW]; 664 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0; 665 break; 666 case DP_AUX_REPLY_DATA: 667 ret = xlnx_dp_aux_pop_rx_fifo(s); 668 break; 669 case DP_INTERRUPT_SIGNAL_STATE: 670 /* 671 * XXX: Not sure it is the right thing to do actually. 672 * The register is not written by the device driver so it's stuck 673 * to 0x04. 674 */ 675 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE]; 676 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04; 677 break; 678 case DP_AUX_WRITE_FIFO: 679 case DP_TX_AUDIO_INFO_DATA(0): 680 case DP_TX_AUDIO_INFO_DATA(1): 681 case DP_TX_AUDIO_INFO_DATA(2): 682 case DP_TX_AUDIO_INFO_DATA(3): 683 case DP_TX_AUDIO_INFO_DATA(4): 684 case DP_TX_AUDIO_INFO_DATA(5): 685 case DP_TX_AUDIO_INFO_DATA(6): 686 case DP_TX_AUDIO_INFO_DATA(7): 687 case DP_TX_AUDIO_EXT_DATA(0): 688 case DP_TX_AUDIO_EXT_DATA(1): 689 case DP_TX_AUDIO_EXT_DATA(2): 690 case DP_TX_AUDIO_EXT_DATA(3): 691 case DP_TX_AUDIO_EXT_DATA(4): 692 case DP_TX_AUDIO_EXT_DATA(5): 693 case DP_TX_AUDIO_EXT_DATA(6): 694 case DP_TX_AUDIO_EXT_DATA(7): 695 case DP_TX_AUDIO_EXT_DATA(8): 696 /* write only registers */ 697 ret = 0; 698 break; 699 default: 700 assert(offset <= (0x3AC >> 2)); 701 ret = s->core_registers[offset]; 702 break; 703 } 704 705 DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret); 706 return ret; 707 } 708 709 static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, 710 unsigned size) 711 { 712 XlnxDPState *s = XLNX_DP(opaque); 713 714 DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value); 715 716 offset = offset >> 2; 717 718 switch (offset) { 719 /* 720 * Only special write case are handled. 721 */ 722 case DP_LINK_BW_SET: 723 s->core_registers[offset] = value & 0x000000FF; 724 break; 725 case DP_LANE_COUNT_SET: 726 case DP_MAIN_STREAM_MISC0: 727 s->core_registers[offset] = value & 0x0000000F; 728 break; 729 case DP_TRAINING_PATTERN_SET: 730 case DP_LINK_QUAL_PATTERN_SET: 731 case DP_MAIN_STREAM_POLARITY: 732 case DP_PHY_VOLTAGE_DIFF_LANE_0: 733 case DP_PHY_VOLTAGE_DIFF_LANE_1: 734 s->core_registers[offset] = value & 0x00000003; 735 break; 736 case DP_ENHANCED_FRAME_EN: 737 case DP_SCRAMBLING_DISABLE: 738 case DP_DOWNSPREAD_CTRL: 739 case DP_MAIN_STREAM_ENABLE: 740 case DP_TRANSMIT_PRBS7: 741 s->core_registers[offset] = value & 0x00000001; 742 break; 743 case DP_PHY_CLOCK_SELECT: 744 s->core_registers[offset] = value & 0x00000007; 745 break; 746 case DP_SOFTWARE_RESET: 747 /* 748 * No need to update this bit as it's read '0'. 749 */ 750 /* 751 * TODO: reset IP. 752 */ 753 break; 754 case DP_TRANSMITTER_ENABLE: 755 s->core_registers[offset] = value & 0x01; 756 break; 757 case DP_FORCE_SCRAMBLER_RESET: 758 /* 759 * No need to update this bit as it's read '0'. 760 */ 761 /* 762 * TODO: force a scrambler reset?? 763 */ 764 break; 765 case DP_AUX_COMMAND_REGISTER: 766 s->core_registers[offset] = value & 0x00001F0F; 767 xlnx_dp_aux_set_command(s, s->core_registers[offset]); 768 break; 769 case DP_MAIN_STREAM_HTOTAL: 770 case DP_MAIN_STREAM_VTOTAL: 771 case DP_MAIN_STREAM_HSTART: 772 case DP_MAIN_STREAM_VSTART: 773 s->core_registers[offset] = value & 0x0000FFFF; 774 break; 775 case DP_MAIN_STREAM_HRES: 776 case DP_MAIN_STREAM_VRES: 777 s->core_registers[offset] = value & 0x0000FFFF; 778 xlnx_dp_recreate_surface(s); 779 break; 780 case DP_MAIN_STREAM_HSWIDTH: 781 case DP_MAIN_STREAM_VSWIDTH: 782 s->core_registers[offset] = value & 0x00007FFF; 783 break; 784 case DP_MAIN_STREAM_MISC1: 785 s->core_registers[offset] = value & 0x00000086; 786 break; 787 case DP_MAIN_STREAM_M_VID: 788 case DP_MAIN_STREAM_N_VID: 789 s->core_registers[offset] = value & 0x00FFFFFF; 790 break; 791 case DP_MSA_TRANSFER_UNIT_SIZE: 792 case DP_MIN_BYTES_PER_TU: 793 case DP_INIT_WAIT: 794 s->core_registers[offset] = value & 0x00000007; 795 break; 796 case DP_USER_DATA_COUNT_PER_LANE: 797 s->core_registers[offset] = value & 0x0003FFFF; 798 break; 799 case DP_FRAC_BYTES_PER_TU: 800 s->core_registers[offset] = value & 0x000003FF; 801 break; 802 case DP_PHY_RESET: 803 s->core_registers[offset] = value & 0x00010003; 804 /* 805 * TODO: Reset something? 806 */ 807 break; 808 case DP_TX_PHY_POWER_DOWN: 809 s->core_registers[offset] = value & 0x0000000F; 810 /* 811 * TODO: Power down things? 812 */ 813 break; 814 case DP_AUX_WRITE_FIFO: { 815 uint8_t c = value; 816 xlnx_dp_aux_push_tx_fifo(s, &c, 1); 817 break; 818 } 819 case DP_AUX_CLOCK_DIVIDER: 820 break; 821 case DP_AUX_REPLY_COUNT: 822 /* 823 * Writing to this register clear the counter. 824 */ 825 s->core_registers[offset] = 0x00000000; 826 break; 827 case DP_AUX_ADDRESS: 828 s->core_registers[offset] = value & 0x000FFFFF; 829 break; 830 case DP_VERSION_REGISTER: 831 case DP_CORE_ID: 832 case DP_TX_USER_FIFO_OVERFLOW: 833 case DP_AUX_REPLY_DATA: 834 case DP_AUX_REPLY_CODE: 835 case DP_REPLY_DATA_COUNT: 836 case DP_REPLY_STATUS: 837 case DP_HPD_DURATION: 838 /* 839 * Write to read only location.. 840 */ 841 break; 842 case DP_TX_AUDIO_CONTROL: 843 s->core_registers[offset] = value & 0x00000001; 844 xlnx_dp_audio_activate(s); 845 break; 846 case DP_TX_AUDIO_CHANNELS: 847 s->core_registers[offset] = value & 0x00000007; 848 xlnx_dp_audio_activate(s); 849 break; 850 case DP_INT_STATUS: 851 s->core_registers[DP_INT_STATUS] &= ~value; 852 xlnx_dp_update_irq(s); 853 break; 854 case DP_INT_EN: 855 s->core_registers[DP_INT_MASK] &= ~value; 856 xlnx_dp_update_irq(s); 857 break; 858 case DP_INT_DS: 859 s->core_registers[DP_INT_MASK] |= ~value; 860 xlnx_dp_update_irq(s); 861 break; 862 default: 863 assert(offset <= (0x504C >> 2)); 864 s->core_registers[offset] = value; 865 break; 866 } 867 } 868 869 static const MemoryRegionOps dp_ops = { 870 .read = xlnx_dp_read, 871 .write = xlnx_dp_write, 872 .endianness = DEVICE_NATIVE_ENDIAN, 873 .valid = { 874 .min_access_size = 4, 875 .max_access_size = 4, 876 }, 877 .impl = { 878 .min_access_size = 4, 879 .max_access_size = 4, 880 }, 881 }; 882 883 /* 884 * This is to handle Read/Write to the Video Blender. 885 */ 886 static void xlnx_dp_vblend_write(void *opaque, hwaddr offset, 887 uint64_t value, unsigned size) 888 { 889 XlnxDPState *s = XLNX_DP(opaque); 890 bool alpha_was_enabled; 891 892 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 893 (uint32_t)value); 894 offset = offset >> 2; 895 896 switch (offset) { 897 case V_BLEND_BG_CLR_0: 898 case V_BLEND_BG_CLR_1: 899 case V_BLEND_BG_CLR_2: 900 s->vblend_registers[offset] = value & 0x00000FFF; 901 break; 902 case V_BLEND_SET_GLOBAL_ALPHA_REG: 903 /* 904 * A write to this register can enable or disable blending. Thus we need 905 * to recreate the surfaces. 906 */ 907 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s); 908 s->vblend_registers[offset] = value & 0x000001FF; 909 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) { 910 xlnx_dp_recreate_surface(s); 911 } 912 break; 913 case V_BLEND_OUTPUT_VID_FORMAT: 914 s->vblend_registers[offset] = value & 0x00000017; 915 break; 916 case V_BLEND_LAYER0_CONTROL: 917 case V_BLEND_LAYER1_CONTROL: 918 s->vblend_registers[offset] = value & 0x00000103; 919 break; 920 case V_BLEND_RGB2YCBCR_COEFF(0): 921 case V_BLEND_RGB2YCBCR_COEFF(1): 922 case V_BLEND_RGB2YCBCR_COEFF(2): 923 case V_BLEND_RGB2YCBCR_COEFF(3): 924 case V_BLEND_RGB2YCBCR_COEFF(4): 925 case V_BLEND_RGB2YCBCR_COEFF(5): 926 case V_BLEND_RGB2YCBCR_COEFF(6): 927 case V_BLEND_RGB2YCBCR_COEFF(7): 928 case V_BLEND_RGB2YCBCR_COEFF(8): 929 case V_BLEND_IN1CSC_COEFF(0): 930 case V_BLEND_IN1CSC_COEFF(1): 931 case V_BLEND_IN1CSC_COEFF(2): 932 case V_BLEND_IN1CSC_COEFF(3): 933 case V_BLEND_IN1CSC_COEFF(4): 934 case V_BLEND_IN1CSC_COEFF(5): 935 case V_BLEND_IN1CSC_COEFF(6): 936 case V_BLEND_IN1CSC_COEFF(7): 937 case V_BLEND_IN1CSC_COEFF(8): 938 case V_BLEND_IN2CSC_COEFF(0): 939 case V_BLEND_IN2CSC_COEFF(1): 940 case V_BLEND_IN2CSC_COEFF(2): 941 case V_BLEND_IN2CSC_COEFF(3): 942 case V_BLEND_IN2CSC_COEFF(4): 943 case V_BLEND_IN2CSC_COEFF(5): 944 case V_BLEND_IN2CSC_COEFF(6): 945 case V_BLEND_IN2CSC_COEFF(7): 946 case V_BLEND_IN2CSC_COEFF(8): 947 s->vblend_registers[offset] = value & 0x0000FFFF; 948 break; 949 case V_BLEND_LUMA_IN1CSC_OFFSET: 950 case V_BLEND_CR_IN1CSC_OFFSET: 951 case V_BLEND_CB_IN1CSC_OFFSET: 952 case V_BLEND_LUMA_IN2CSC_OFFSET: 953 case V_BLEND_CR_IN2CSC_OFFSET: 954 case V_BLEND_CB_IN2CSC_OFFSET: 955 case V_BLEND_LUMA_OUTCSC_OFFSET: 956 case V_BLEND_CR_OUTCSC_OFFSET: 957 case V_BLEND_CB_OUTCSC_OFFSET: 958 s->vblend_registers[offset] = value & 0x3FFF7FFF; 959 break; 960 case V_BLEND_CHROMA_KEY_ENABLE: 961 s->vblend_registers[offset] = value & 0x00000003; 962 break; 963 case V_BLEND_CHROMA_KEY_COMP1: 964 case V_BLEND_CHROMA_KEY_COMP2: 965 case V_BLEND_CHROMA_KEY_COMP3: 966 s->vblend_registers[offset] = value & 0x0FFF0FFF; 967 break; 968 default: 969 s->vblend_registers[offset] = value; 970 break; 971 } 972 } 973 974 static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset, 975 unsigned size) 976 { 977 XlnxDPState *s = XLNX_DP(opaque); 978 979 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 980 s->vblend_registers[offset >> 2]); 981 return s->vblend_registers[offset >> 2]; 982 } 983 984 static const MemoryRegionOps vblend_ops = { 985 .read = xlnx_dp_vblend_read, 986 .write = xlnx_dp_vblend_write, 987 .endianness = DEVICE_NATIVE_ENDIAN, 988 .valid = { 989 .min_access_size = 4, 990 .max_access_size = 4, 991 }, 992 .impl = { 993 .min_access_size = 4, 994 .max_access_size = 4, 995 }, 996 }; 997 998 /* 999 * This is to handle Read/Write to the Audio Video buffer manager. 1000 */ 1001 static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value, 1002 unsigned size) 1003 { 1004 XlnxDPState *s = XLNX_DP(opaque); 1005 1006 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 1007 (uint32_t)value); 1008 offset = offset >> 2; 1009 1010 switch (offset) { 1011 case AV_BUF_FORMAT: 1012 s->avbufm_registers[offset] = value & 0x00000FFF; 1013 xlnx_dp_change_graphic_fmt(s); 1014 break; 1015 case AV_CHBUF0: 1016 case AV_CHBUF1: 1017 case AV_CHBUF2: 1018 case AV_CHBUF3: 1019 case AV_CHBUF4: 1020 case AV_CHBUF5: 1021 s->avbufm_registers[offset] = value & 0x0000007F; 1022 break; 1023 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT: 1024 s->avbufm_registers[offset] = value & 0x0000007F; 1025 break; 1026 case AV_BUF_DITHER_CONFIG: 1027 s->avbufm_registers[offset] = value & 0x000007FF; 1028 break; 1029 case AV_BUF_DITHER_CONFIG_MAX: 1030 case AV_BUF_DITHER_CONFIG_MIN: 1031 s->avbufm_registers[offset] = value & 0x00000FFF; 1032 break; 1033 case AV_BUF_PATTERN_GEN_SELECT: 1034 s->avbufm_registers[offset] = value & 0xFFFFFF03; 1035 break; 1036 case AV_BUF_AUD_VID_CLK_SOURCE: 1037 s->avbufm_registers[offset] = value & 0x00000007; 1038 break; 1039 case AV_BUF_SRST_REG: 1040 s->avbufm_registers[offset] = value & 0x00000002; 1041 break; 1042 case AV_BUF_AUDIO_CH_CONFIG: 1043 s->avbufm_registers[offset] = value & 0x00000003; 1044 break; 1045 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0): 1046 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1): 1047 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2): 1048 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0): 1049 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1): 1050 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2): 1051 s->avbufm_registers[offset] = value & 0x0000FFFF; 1052 break; 1053 case AV_BUF_LIVE_VIDEO_COMP_SF(0): 1054 case AV_BUF_LIVE_VIDEO_COMP_SF(1): 1055 case AV_BUF_LIVE_VIDEO_COMP_SF(2): 1056 case AV_BUF_LIVE_VID_CONFIG: 1057 case AV_BUF_LIVE_GFX_COMP_SF(0): 1058 case AV_BUF_LIVE_GFX_COMP_SF(1): 1059 case AV_BUF_LIVE_GFX_COMP_SF(2): 1060 case AV_BUF_LIVE_GFX_CONFIG: 1061 case AV_BUF_NON_LIVE_LATENCY: 1062 case AV_BUF_STC_CONTROL: 1063 case AV_BUF_STC_INIT_VALUE0: 1064 case AV_BUF_STC_INIT_VALUE1: 1065 case AV_BUF_STC_ADJ: 1066 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0: 1067 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1: 1068 case AV_BUF_STC_EXT_VSYNC_TS_REG0: 1069 case AV_BUF_STC_EXT_VSYNC_TS_REG1: 1070 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0: 1071 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1: 1072 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0: 1073 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1: 1074 case AV_BUF_STC_SNAPSHOT0: 1075 case AV_BUF_STC_SNAPSHOT1: 1076 case AV_BUF_HCOUNT_VCOUNT_INT0: 1077 case AV_BUF_HCOUNT_VCOUNT_INT1: 1078 qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04" 1079 PRIx64 "\n", 1080 offset << 2); 1081 break; 1082 default: 1083 s->avbufm_registers[offset] = value; 1084 break; 1085 } 1086 } 1087 1088 static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset, 1089 unsigned size) 1090 { 1091 XlnxDPState *s = XLNX_DP(opaque); 1092 1093 offset = offset >> 2; 1094 return s->avbufm_registers[offset]; 1095 } 1096 1097 static const MemoryRegionOps avbufm_ops = { 1098 .read = xlnx_dp_avbufm_read, 1099 .write = xlnx_dp_avbufm_write, 1100 .endianness = DEVICE_NATIVE_ENDIAN, 1101 .valid = { 1102 .min_access_size = 4, 1103 .max_access_size = 4, 1104 }, 1105 .impl = { 1106 .min_access_size = 4, 1107 .max_access_size = 4, 1108 }, 1109 }; 1110 1111 /* 1112 * This is a global alpha blending using pixman. 1113 * Both graphic and video planes are multiplied with the global alpha 1114 * coefficient and added. 1115 */ 1116 static inline void xlnx_dp_blend_surface(XlnxDPState *s) 1117 { 1118 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1), 1119 pixman_double_to_fixed(1), 1120 pixman_double_to_fixed(1.0) }; 1121 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1), 1122 pixman_double_to_fixed(1), 1123 pixman_double_to_fixed(1.0) }; 1124 1125 if ((surface_width(s->g_plane.surface) 1126 != surface_width(s->v_plane.surface)) || 1127 (surface_height(s->g_plane.surface) 1128 != surface_height(s->v_plane.surface))) { 1129 return; 1130 } 1131 1132 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s)) 1133 / 256.0); 1134 alpha2[2] = pixman_double_to_fixed((255.0 1135 - (double)xlnx_dp_global_alpha_value(s)) 1136 / 256.0); 1137 1138 pixman_image_set_filter(s->g_plane.surface->image, 1139 PIXMAN_FILTER_CONVOLUTION, alpha1, 3); 1140 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0, 1141 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, 1142 surface_width(s->g_plane.surface), 1143 surface_height(s->g_plane.surface)); 1144 pixman_image_set_filter(s->v_plane.surface->image, 1145 PIXMAN_FILTER_CONVOLUTION, alpha2, 3); 1146 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0, 1147 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, 1148 surface_width(s->g_plane.surface), 1149 surface_height(s->g_plane.surface)); 1150 } 1151 1152 static void xlnx_dp_update_display(void *opaque) 1153 { 1154 XlnxDPState *s = XLNX_DP(opaque); 1155 1156 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) { 1157 return; 1158 } 1159 1160 s->core_registers[DP_INT_STATUS] |= (1 << 13); 1161 xlnx_dp_update_irq(s); 1162 1163 xlnx_dpdma_trigger_vsync_irq(s->dpdma); 1164 1165 /* 1166 * Trigger the DMA channel. 1167 */ 1168 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) { 1169 /* 1170 * An error occurred don't do anything with the data.. 1171 * Trigger an underflow interrupt. 1172 */ 1173 s->core_registers[DP_INT_STATUS] |= (1 << 21); 1174 xlnx_dp_update_irq(s); 1175 return; 1176 } 1177 1178 if (xlnx_dp_global_alpha_enabled(s)) { 1179 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) { 1180 s->core_registers[DP_INT_STATUS] |= (1 << 21); 1181 xlnx_dp_update_irq(s); 1182 return; 1183 } 1184 xlnx_dp_blend_surface(s); 1185 } 1186 1187 /* 1188 * XXX: We might want to update only what changed. 1189 */ 1190 dpy_gfx_update_full(s->console); 1191 } 1192 1193 static const GraphicHwOps xlnx_dp_gfx_ops = { 1194 .gfx_update = xlnx_dp_update_display, 1195 }; 1196 1197 static void xlnx_dp_init(Object *obj) 1198 { 1199 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1200 XlnxDPState *s = XLNX_DP(obj); 1201 1202 memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050); 1203 1204 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP 1205 ".core", 0x3AF); 1206 memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem); 1207 1208 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP 1209 ".v_blend", 0x1DF); 1210 memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem); 1211 1212 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP 1213 ".av_buffer_manager", 0x238); 1214 memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem); 1215 1216 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP 1217 ".audio", sizeof(s->audio_registers)); 1218 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem); 1219 1220 sysbus_init_mmio(sbd, &s->container); 1221 sysbus_init_irq(sbd, &s->irq); 1222 1223 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA, 1224 (Object **) &s->dpdma, 1225 xlnx_dp_set_dpdma, 1226 OBJ_PROP_LINK_STRONG, 1227 &error_abort); 1228 1229 /* 1230 * Initialize AUX Bus. 1231 */ 1232 s->aux_bus = aux_init_bus(DEVICE(obj), "aux"); 1233 1234 /* 1235 * Initialize DPCD and EDID.. 1236 */ 1237 s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd")); 1238 object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd), NULL); 1239 1240 s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc")); 1241 i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50); 1242 object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid), NULL); 1243 1244 fifo8_create(&s->rx_fifo, 16); 1245 fifo8_create(&s->tx_fifo, 16); 1246 } 1247 1248 static void xlnx_dp_realize(DeviceState *dev, Error **errp) 1249 { 1250 XlnxDPState *s = XLNX_DP(dev); 1251 DisplaySurface *surface; 1252 struct audsettings as; 1253 1254 qdev_init_nofail(DEVICE(s->dpcd)); 1255 aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000); 1256 1257 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s); 1258 surface = qemu_console_surface(s->console); 1259 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, 1260 surface_data(surface)); 1261 1262 as.freq = 44100; 1263 as.nchannels = 2; 1264 as.fmt = AUDIO_FORMAT_S16; 1265 as.endianness = 0; 1266 1267 AUD_register_card("xlnx_dp.audio", &s->aud_card); 1268 1269 s->amixer_output_stream = AUD_open_out(&s->aud_card, 1270 s->amixer_output_stream, 1271 "xlnx_dp.audio.out", 1272 s, 1273 xlnx_dp_audio_callback, 1274 &as); 1275 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255); 1276 xlnx_dp_audio_activate(s); 1277 } 1278 1279 static void xlnx_dp_reset(DeviceState *dev) 1280 { 1281 XlnxDPState *s = XLNX_DP(dev); 1282 1283 memset(s->core_registers, 0, sizeof(s->core_registers)); 1284 s->core_registers[DP_VERSION_REGISTER] = 0x04010000; 1285 s->core_registers[DP_CORE_ID] = 0x01020000; 1286 s->core_registers[DP_REPLY_STATUS] = 0x00000010; 1287 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040; 1288 s->core_registers[DP_INIT_WAIT] = 0x00000020; 1289 s->core_registers[DP_PHY_RESET] = 0x00010003; 1290 s->core_registers[DP_INT_MASK] = 0xFFFFF03F; 1291 s->core_registers[DP_PHY_STATUS] = 0x00000043; 1292 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001; 1293 1294 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000; 1295 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000; 1296 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000; 1297 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000; 1298 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000; 1299 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000; 1300 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000; 1301 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000; 1302 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000; 1303 1304 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180; 1305 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008; 1306 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF; 1307 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101; 1308 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101; 1309 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101; 1310 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101; 1311 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101; 1312 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101; 1313 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101; 1314 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101; 1315 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101; 1316 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101; 1317 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101; 1318 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101; 1319 1320 memset(s->audio_registers, 0, sizeof(s->audio_registers)); 1321 s->byte_left = 0; 1322 1323 xlnx_dp_aux_clear_rx_fifo(s); 1324 xlnx_dp_change_graphic_fmt(s); 1325 xlnx_dp_update_irq(s); 1326 } 1327 1328 static void xlnx_dp_class_init(ObjectClass *oc, void *data) 1329 { 1330 DeviceClass *dc = DEVICE_CLASS(oc); 1331 1332 dc->realize = xlnx_dp_realize; 1333 dc->vmsd = &vmstate_dp; 1334 dc->reset = xlnx_dp_reset; 1335 } 1336 1337 static const TypeInfo xlnx_dp_info = { 1338 .name = TYPE_XLNX_DP, 1339 .parent = TYPE_SYS_BUS_DEVICE, 1340 .instance_size = sizeof(XlnxDPState), 1341 .instance_init = xlnx_dp_init, 1342 .class_init = xlnx_dp_class_init, 1343 }; 1344 1345 static void xlnx_dp_register_types(void) 1346 { 1347 type_register_static(&xlnx_dp_info); 1348 } 1349 1350 type_init(xlnx_dp_register_types) 1351