1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "hw/hw.h" 27 #include "hw/loader.h" 28 #include "trace.h" 29 #include "ui/vnc.h" 30 #include "hw/pci/pci.h" 31 32 #undef VERBOSE 33 #define HW_RECT_ACCEL 34 #define HW_FILL_ACCEL 35 #define HW_MOUSE_ACCEL 36 37 #include "vga_int.h" 38 39 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 40 41 struct vmsvga_state_s { 42 VGACommonState vga; 43 44 int invalidated; 45 int enable; 46 int config; 47 struct { 48 int id; 49 int x; 50 int y; 51 int on; 52 } cursor; 53 54 int index; 55 int scratch_size; 56 uint32_t *scratch; 57 int new_width; 58 int new_height; 59 int new_depth; 60 uint32_t guest; 61 uint32_t svgaid; 62 int syncing; 63 64 MemoryRegion fifo_ram; 65 uint8_t *fifo_ptr; 66 unsigned int fifo_size; 67 68 uint32_t *fifo; 69 uint32_t fifo_min; 70 uint32_t fifo_max; 71 uint32_t fifo_next; 72 uint32_t fifo_stop; 73 74 #define REDRAW_FIFO_LEN 512 75 struct vmsvga_rect_s { 76 int x, y, w, h; 77 } redraw_fifo[REDRAW_FIFO_LEN]; 78 int redraw_fifo_first, redraw_fifo_last; 79 }; 80 81 #define TYPE_VMWARE_SVGA "vmware-svga" 82 83 #define VMWARE_SVGA(obj) \ 84 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) 85 86 struct pci_vmsvga_state_s { 87 /*< private >*/ 88 PCIDevice parent_obj; 89 /*< public >*/ 90 91 struct vmsvga_state_s chip; 92 MemoryRegion io_bar; 93 }; 94 95 #define SVGA_MAGIC 0x900000UL 96 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 97 #define SVGA_ID_0 SVGA_MAKE_ID(0) 98 #define SVGA_ID_1 SVGA_MAKE_ID(1) 99 #define SVGA_ID_2 SVGA_MAKE_ID(2) 100 101 #define SVGA_LEGACY_BASE_PORT 0x4560 102 #define SVGA_INDEX_PORT 0x0 103 #define SVGA_VALUE_PORT 0x1 104 #define SVGA_BIOS_PORT 0x2 105 106 #define SVGA_VERSION_2 107 108 #ifdef SVGA_VERSION_2 109 # define SVGA_ID SVGA_ID_2 110 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 111 # define SVGA_IO_MUL 1 112 # define SVGA_FIFO_SIZE 0x10000 113 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 114 #else 115 # define SVGA_ID SVGA_ID_1 116 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 117 # define SVGA_IO_MUL 4 118 # define SVGA_FIFO_SIZE 0x10000 119 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 120 #endif 121 122 enum { 123 /* ID 0, 1 and 2 registers */ 124 SVGA_REG_ID = 0, 125 SVGA_REG_ENABLE = 1, 126 SVGA_REG_WIDTH = 2, 127 SVGA_REG_HEIGHT = 3, 128 SVGA_REG_MAX_WIDTH = 4, 129 SVGA_REG_MAX_HEIGHT = 5, 130 SVGA_REG_DEPTH = 6, 131 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 132 SVGA_REG_PSEUDOCOLOR = 8, 133 SVGA_REG_RED_MASK = 9, 134 SVGA_REG_GREEN_MASK = 10, 135 SVGA_REG_BLUE_MASK = 11, 136 SVGA_REG_BYTES_PER_LINE = 12, 137 SVGA_REG_FB_START = 13, 138 SVGA_REG_FB_OFFSET = 14, 139 SVGA_REG_VRAM_SIZE = 15, 140 SVGA_REG_FB_SIZE = 16, 141 142 /* ID 1 and 2 registers */ 143 SVGA_REG_CAPABILITIES = 17, 144 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 145 SVGA_REG_MEM_SIZE = 19, 146 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 147 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 148 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 149 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 150 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 151 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 152 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 153 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 154 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 155 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 156 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 157 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 158 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 159 160 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 161 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 162 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 163 }; 164 165 #define SVGA_CAP_NONE 0 166 #define SVGA_CAP_RECT_FILL (1 << 0) 167 #define SVGA_CAP_RECT_COPY (1 << 1) 168 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 169 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 170 #define SVGA_CAP_RASTER_OP (1 << 4) 171 #define SVGA_CAP_CURSOR (1 << 5) 172 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 173 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 174 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 175 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 176 #define SVGA_CAP_GLYPH (1 << 10) 177 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 178 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 179 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 180 #define SVGA_CAP_3D (1 << 14) 181 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 182 #define SVGA_CAP_MULTIMON (1 << 16) 183 #define SVGA_CAP_PITCHLOCK (1 << 17) 184 185 /* 186 * FIFO offsets (seen as an array of 32-bit words) 187 */ 188 enum { 189 /* 190 * The original defined FIFO offsets 191 */ 192 SVGA_FIFO_MIN = 0, 193 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 194 SVGA_FIFO_NEXT, 195 SVGA_FIFO_STOP, 196 197 /* 198 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 199 */ 200 SVGA_FIFO_CAPABILITIES = 4, 201 SVGA_FIFO_FLAGS, 202 SVGA_FIFO_FENCE, 203 SVGA_FIFO_3D_HWVERSION, 204 SVGA_FIFO_PITCHLOCK, 205 }; 206 207 #define SVGA_FIFO_CAP_NONE 0 208 #define SVGA_FIFO_CAP_FENCE (1 << 0) 209 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 210 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 211 212 #define SVGA_FIFO_FLAG_NONE 0 213 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 214 215 /* These values can probably be changed arbitrarily. */ 216 #define SVGA_SCRATCH_SIZE 0x8000 217 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) 218 #define SVGA_MAX_HEIGHT 1770 219 220 #ifdef VERBOSE 221 # define GUEST_OS_BASE 0x5001 222 static const char *vmsvga_guest_id[] = { 223 [0x00] = "Dos", 224 [0x01] = "Windows 3.1", 225 [0x02] = "Windows 95", 226 [0x03] = "Windows 98", 227 [0x04] = "Windows ME", 228 [0x05] = "Windows NT", 229 [0x06] = "Windows 2000", 230 [0x07] = "Linux", 231 [0x08] = "OS/2", 232 [0x09] = "an unknown OS", 233 [0x0a] = "BSD", 234 [0x0b] = "Whistler", 235 [0x0c] = "an unknown OS", 236 [0x0d] = "an unknown OS", 237 [0x0e] = "an unknown OS", 238 [0x0f] = "an unknown OS", 239 [0x10] = "an unknown OS", 240 [0x11] = "an unknown OS", 241 [0x12] = "an unknown OS", 242 [0x13] = "an unknown OS", 243 [0x14] = "an unknown OS", 244 [0x15] = "Windows 2003", 245 }; 246 #endif 247 248 enum { 249 SVGA_CMD_INVALID_CMD = 0, 250 SVGA_CMD_UPDATE = 1, 251 SVGA_CMD_RECT_FILL = 2, 252 SVGA_CMD_RECT_COPY = 3, 253 SVGA_CMD_DEFINE_BITMAP = 4, 254 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 255 SVGA_CMD_DEFINE_PIXMAP = 6, 256 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 257 SVGA_CMD_RECT_BITMAP_FILL = 8, 258 SVGA_CMD_RECT_PIXMAP_FILL = 9, 259 SVGA_CMD_RECT_BITMAP_COPY = 10, 260 SVGA_CMD_RECT_PIXMAP_COPY = 11, 261 SVGA_CMD_FREE_OBJECT = 12, 262 SVGA_CMD_RECT_ROP_FILL = 13, 263 SVGA_CMD_RECT_ROP_COPY = 14, 264 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 265 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 266 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 267 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 268 SVGA_CMD_DEFINE_CURSOR = 19, 269 SVGA_CMD_DISPLAY_CURSOR = 20, 270 SVGA_CMD_MOVE_CURSOR = 21, 271 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 272 SVGA_CMD_DRAW_GLYPH = 23, 273 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 274 SVGA_CMD_UPDATE_VERBOSE = 25, 275 SVGA_CMD_SURFACE_FILL = 26, 276 SVGA_CMD_SURFACE_COPY = 27, 277 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 278 SVGA_CMD_FRONT_ROP_FILL = 29, 279 SVGA_CMD_FENCE = 30, 280 }; 281 282 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 283 enum { 284 SVGA_CURSOR_ON_HIDE = 0, 285 SVGA_CURSOR_ON_SHOW = 1, 286 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 287 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 288 }; 289 290 static inline bool vmsvga_verify_rect(DisplaySurface *surface, 291 const char *name, 292 int x, int y, int w, int h) 293 { 294 if (x < 0) { 295 fprintf(stderr, "%s: x was < 0 (%d)\n", name, x); 296 return false; 297 } 298 if (x > SVGA_MAX_WIDTH) { 299 fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x); 300 return false; 301 } 302 if (w < 0) { 303 fprintf(stderr, "%s: w was < 0 (%d)\n", name, w); 304 return false; 305 } 306 if (w > SVGA_MAX_WIDTH) { 307 fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w); 308 return false; 309 } 310 if (x + w > surface_width(surface)) { 311 fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n", 312 name, surface_width(surface), x, w); 313 return false; 314 } 315 316 if (y < 0) { 317 fprintf(stderr, "%s: y was < 0 (%d)\n", name, y); 318 return false; 319 } 320 if (y > SVGA_MAX_HEIGHT) { 321 fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y); 322 return false; 323 } 324 if (h < 0) { 325 fprintf(stderr, "%s: h was < 0 (%d)\n", name, h); 326 return false; 327 } 328 if (h > SVGA_MAX_HEIGHT) { 329 fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h); 330 return false; 331 } 332 if (y + h > surface_height(surface)) { 333 fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n", 334 name, surface_height(surface), y, h); 335 return false; 336 } 337 338 return true; 339 } 340 341 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 342 int x, int y, int w, int h) 343 { 344 DisplaySurface *surface = qemu_console_surface(s->vga.con); 345 int line; 346 int bypl; 347 int width; 348 int start; 349 uint8_t *src; 350 uint8_t *dst; 351 352 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { 353 /* go for a fullscreen update as fallback */ 354 x = 0; 355 y = 0; 356 w = surface_width(surface); 357 h = surface_height(surface); 358 } 359 360 bypl = surface_stride(surface); 361 width = surface_bytes_per_pixel(surface) * w; 362 start = surface_bytes_per_pixel(surface) * x + bypl * y; 363 src = s->vga.vram_ptr + start; 364 dst = surface_data(surface) + start; 365 366 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 367 memcpy(dst, src, width); 368 } 369 dpy_gfx_update(s->vga.con, x, y, w, h); 370 } 371 372 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 373 int x, int y, int w, int h) 374 { 375 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 376 377 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 378 rect->x = x; 379 rect->y = y; 380 rect->w = w; 381 rect->h = h; 382 } 383 384 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 385 { 386 struct vmsvga_rect_s *rect; 387 388 if (s->invalidated) { 389 s->redraw_fifo_first = s->redraw_fifo_last; 390 return; 391 } 392 /* Overlapping region updates can be optimised out here - if someone 393 * knows a smart algorithm to do that, please share. */ 394 while (s->redraw_fifo_first != s->redraw_fifo_last) { 395 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 396 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 397 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 398 } 399 } 400 401 #ifdef HW_RECT_ACCEL 402 static inline int vmsvga_copy_rect(struct vmsvga_state_s *s, 403 int x0, int y0, int x1, int y1, int w, int h) 404 { 405 DisplaySurface *surface = qemu_console_surface(s->vga.con); 406 uint8_t *vram = s->vga.vram_ptr; 407 int bypl = surface_stride(surface); 408 int bypp = surface_bytes_per_pixel(surface); 409 int width = bypp * w; 410 int line = h; 411 uint8_t *ptr[2]; 412 413 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) { 414 return -1; 415 } 416 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) { 417 return -1; 418 } 419 420 if (y1 > y0) { 421 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 422 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 423 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 424 memmove(ptr[1], ptr[0], width); 425 } 426 } else { 427 ptr[0] = vram + bypp * x0 + bypl * y0; 428 ptr[1] = vram + bypp * x1 + bypl * y1; 429 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 430 memmove(ptr[1], ptr[0], width); 431 } 432 } 433 434 vmsvga_update_rect_delayed(s, x1, y1, w, h); 435 return 0; 436 } 437 #endif 438 439 #ifdef HW_FILL_ACCEL 440 static inline int vmsvga_fill_rect(struct vmsvga_state_s *s, 441 uint32_t c, int x, int y, int w, int h) 442 { 443 DisplaySurface *surface = qemu_console_surface(s->vga.con); 444 int bypl = surface_stride(surface); 445 int width = surface_bytes_per_pixel(surface) * w; 446 int line = h; 447 int column; 448 uint8_t *fst; 449 uint8_t *dst; 450 uint8_t *src; 451 uint8_t col[4]; 452 453 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { 454 return -1; 455 } 456 457 col[0] = c; 458 col[1] = c >> 8; 459 col[2] = c >> 16; 460 col[3] = c >> 24; 461 462 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 463 464 if (line--) { 465 dst = fst; 466 src = col; 467 for (column = width; column > 0; column--) { 468 *(dst++) = *(src++); 469 if (src - col == surface_bytes_per_pixel(surface)) { 470 src = col; 471 } 472 } 473 dst = fst; 474 for (; line > 0; line--) { 475 dst += bypl; 476 memcpy(dst, fst, width); 477 } 478 } 479 480 vmsvga_update_rect_delayed(s, x, y, w, h); 481 return 0; 482 } 483 #endif 484 485 struct vmsvga_cursor_definition_s { 486 uint32_t width; 487 uint32_t height; 488 int id; 489 uint32_t bpp; 490 int hot_x; 491 int hot_y; 492 uint32_t mask[1024]; 493 uint32_t image[4096]; 494 }; 495 496 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 497 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 498 499 #ifdef HW_MOUSE_ACCEL 500 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 501 struct vmsvga_cursor_definition_s *c) 502 { 503 QEMUCursor *qc; 504 int i, pixels; 505 506 qc = cursor_alloc(c->width, c->height); 507 qc->hot_x = c->hot_x; 508 qc->hot_y = c->hot_y; 509 switch (c->bpp) { 510 case 1: 511 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 512 1, (void *)c->mask); 513 #ifdef DEBUG 514 cursor_print_ascii_art(qc, "vmware/mono"); 515 #endif 516 break; 517 case 32: 518 /* fill alpha channel from mask, set color to zero */ 519 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 520 1, (void *)c->mask); 521 /* add in rgb values */ 522 pixels = c->width * c->height; 523 for (i = 0; i < pixels; i++) { 524 qc->data[i] |= c->image[i] & 0xffffff; 525 } 526 #ifdef DEBUG 527 cursor_print_ascii_art(qc, "vmware/32bit"); 528 #endif 529 break; 530 default: 531 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 532 __func__, c->bpp); 533 cursor_put(qc); 534 qc = cursor_builtin_left_ptr(); 535 } 536 537 dpy_cursor_define(s->vga.con, qc); 538 cursor_put(qc); 539 } 540 #endif 541 542 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 543 { 544 int num; 545 546 if (!s->config || !s->enable) { 547 return 0; 548 } 549 550 s->fifo_min = le32_to_cpu(s->fifo[SVGA_FIFO_MIN]); 551 s->fifo_max = le32_to_cpu(s->fifo[SVGA_FIFO_MAX]); 552 s->fifo_next = le32_to_cpu(s->fifo[SVGA_FIFO_NEXT]); 553 s->fifo_stop = le32_to_cpu(s->fifo[SVGA_FIFO_STOP]); 554 555 /* Check range and alignment. */ 556 if ((s->fifo_min | s->fifo_max | s->fifo_next | s->fifo_stop) & 3) { 557 return 0; 558 } 559 if (s->fifo_min < sizeof(uint32_t) * 4) { 560 return 0; 561 } 562 if (s->fifo_max > SVGA_FIFO_SIZE || 563 s->fifo_min >= SVGA_FIFO_SIZE || 564 s->fifo_stop >= SVGA_FIFO_SIZE || 565 s->fifo_next >= SVGA_FIFO_SIZE) { 566 return 0; 567 } 568 if (s->fifo_max < s->fifo_min + 10 * 1024) { 569 return 0; 570 } 571 572 num = s->fifo_next - s->fifo_stop; 573 if (num < 0) { 574 num += s->fifo_max - s->fifo_min; 575 } 576 return num >> 2; 577 } 578 579 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 580 { 581 uint32_t cmd = s->fifo[s->fifo_stop >> 2]; 582 583 s->fifo_stop += 4; 584 if (s->fifo_stop >= s->fifo_max) { 585 s->fifo_stop = s->fifo_min; 586 } 587 s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop); 588 return cmd; 589 } 590 591 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 592 { 593 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 594 } 595 596 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 597 { 598 uint32_t cmd, colour; 599 int args, len, maxloop = 1024; 600 int x, y, dx, dy, width, height; 601 struct vmsvga_cursor_definition_s cursor; 602 uint32_t cmd_start; 603 604 len = vmsvga_fifo_length(s); 605 while (len > 0 && --maxloop > 0) { 606 /* May need to go back to the start of the command if incomplete */ 607 cmd_start = s->fifo_stop; 608 609 switch (cmd = vmsvga_fifo_read(s)) { 610 case SVGA_CMD_UPDATE: 611 case SVGA_CMD_UPDATE_VERBOSE: 612 len -= 5; 613 if (len < 0) { 614 goto rewind; 615 } 616 617 x = vmsvga_fifo_read(s); 618 y = vmsvga_fifo_read(s); 619 width = vmsvga_fifo_read(s); 620 height = vmsvga_fifo_read(s); 621 vmsvga_update_rect_delayed(s, x, y, width, height); 622 break; 623 624 case SVGA_CMD_RECT_FILL: 625 len -= 6; 626 if (len < 0) { 627 goto rewind; 628 } 629 630 colour = vmsvga_fifo_read(s); 631 x = vmsvga_fifo_read(s); 632 y = vmsvga_fifo_read(s); 633 width = vmsvga_fifo_read(s); 634 height = vmsvga_fifo_read(s); 635 #ifdef HW_FILL_ACCEL 636 if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) { 637 break; 638 } 639 #endif 640 args = 0; 641 goto badcmd; 642 643 case SVGA_CMD_RECT_COPY: 644 len -= 7; 645 if (len < 0) { 646 goto rewind; 647 } 648 649 x = vmsvga_fifo_read(s); 650 y = vmsvga_fifo_read(s); 651 dx = vmsvga_fifo_read(s); 652 dy = vmsvga_fifo_read(s); 653 width = vmsvga_fifo_read(s); 654 height = vmsvga_fifo_read(s); 655 #ifdef HW_RECT_ACCEL 656 if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) { 657 break; 658 } 659 #endif 660 args = 0; 661 goto badcmd; 662 663 case SVGA_CMD_DEFINE_CURSOR: 664 len -= 8; 665 if (len < 0) { 666 goto rewind; 667 } 668 669 cursor.id = vmsvga_fifo_read(s); 670 cursor.hot_x = vmsvga_fifo_read(s); 671 cursor.hot_y = vmsvga_fifo_read(s); 672 cursor.width = x = vmsvga_fifo_read(s); 673 cursor.height = y = vmsvga_fifo_read(s); 674 vmsvga_fifo_read(s); 675 cursor.bpp = vmsvga_fifo_read(s); 676 677 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 678 if (cursor.width > 256 679 || cursor.height > 256 680 || cursor.bpp > 32 681 || SVGA_BITMAP_SIZE(x, y) > ARRAY_SIZE(cursor.mask) 682 || SVGA_PIXMAP_SIZE(x, y, cursor.bpp) 683 > ARRAY_SIZE(cursor.image)) { 684 goto badcmd; 685 } 686 687 len -= args; 688 if (len < 0) { 689 goto rewind; 690 } 691 692 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 693 cursor.mask[args] = vmsvga_fifo_read_raw(s); 694 } 695 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 696 cursor.image[args] = vmsvga_fifo_read_raw(s); 697 } 698 #ifdef HW_MOUSE_ACCEL 699 vmsvga_cursor_define(s, &cursor); 700 break; 701 #else 702 args = 0; 703 goto badcmd; 704 #endif 705 706 /* 707 * Other commands that we at least know the number of arguments 708 * for so we can avoid FIFO desync if driver uses them illegally. 709 */ 710 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 711 len -= 6; 712 if (len < 0) { 713 goto rewind; 714 } 715 vmsvga_fifo_read(s); 716 vmsvga_fifo_read(s); 717 vmsvga_fifo_read(s); 718 x = vmsvga_fifo_read(s); 719 y = vmsvga_fifo_read(s); 720 args = x * y; 721 goto badcmd; 722 case SVGA_CMD_RECT_ROP_FILL: 723 args = 6; 724 goto badcmd; 725 case SVGA_CMD_RECT_ROP_COPY: 726 args = 7; 727 goto badcmd; 728 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 729 len -= 4; 730 if (len < 0) { 731 goto rewind; 732 } 733 vmsvga_fifo_read(s); 734 vmsvga_fifo_read(s); 735 args = 7 + (vmsvga_fifo_read(s) >> 2); 736 goto badcmd; 737 case SVGA_CMD_SURFACE_ALPHA_BLEND: 738 args = 12; 739 goto badcmd; 740 741 /* 742 * Other commands that are not listed as depending on any 743 * CAPABILITIES bits, but are not described in the README either. 744 */ 745 case SVGA_CMD_SURFACE_FILL: 746 case SVGA_CMD_SURFACE_COPY: 747 case SVGA_CMD_FRONT_ROP_FILL: 748 case SVGA_CMD_FENCE: 749 case SVGA_CMD_INVALID_CMD: 750 break; /* Nop */ 751 752 default: 753 args = 0; 754 badcmd: 755 len -= args; 756 if (len < 0) { 757 goto rewind; 758 } 759 while (args--) { 760 vmsvga_fifo_read(s); 761 } 762 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 763 __func__, cmd); 764 break; 765 766 rewind: 767 s->fifo_stop = cmd_start; 768 s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop); 769 break; 770 } 771 } 772 773 s->syncing = 0; 774 } 775 776 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 777 { 778 struct vmsvga_state_s *s = opaque; 779 780 return s->index; 781 } 782 783 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 784 { 785 struct vmsvga_state_s *s = opaque; 786 787 s->index = index; 788 } 789 790 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 791 { 792 uint32_t caps; 793 struct vmsvga_state_s *s = opaque; 794 DisplaySurface *surface = qemu_console_surface(s->vga.con); 795 PixelFormat pf; 796 uint32_t ret; 797 798 switch (s->index) { 799 case SVGA_REG_ID: 800 ret = s->svgaid; 801 break; 802 803 case SVGA_REG_ENABLE: 804 ret = s->enable; 805 break; 806 807 case SVGA_REG_WIDTH: 808 ret = s->new_width ? s->new_width : surface_width(surface); 809 break; 810 811 case SVGA_REG_HEIGHT: 812 ret = s->new_height ? s->new_height : surface_height(surface); 813 break; 814 815 case SVGA_REG_MAX_WIDTH: 816 ret = SVGA_MAX_WIDTH; 817 break; 818 819 case SVGA_REG_MAX_HEIGHT: 820 ret = SVGA_MAX_HEIGHT; 821 break; 822 823 case SVGA_REG_DEPTH: 824 ret = (s->new_depth == 32) ? 24 : s->new_depth; 825 break; 826 827 case SVGA_REG_BITS_PER_PIXEL: 828 case SVGA_REG_HOST_BITS_PER_PIXEL: 829 ret = s->new_depth; 830 break; 831 832 case SVGA_REG_PSEUDOCOLOR: 833 ret = 0x0; 834 break; 835 836 case SVGA_REG_RED_MASK: 837 pf = qemu_default_pixelformat(s->new_depth); 838 ret = pf.rmask; 839 break; 840 841 case SVGA_REG_GREEN_MASK: 842 pf = qemu_default_pixelformat(s->new_depth); 843 ret = pf.gmask; 844 break; 845 846 case SVGA_REG_BLUE_MASK: 847 pf = qemu_default_pixelformat(s->new_depth); 848 ret = pf.bmask; 849 break; 850 851 case SVGA_REG_BYTES_PER_LINE: 852 if (s->new_width) { 853 ret = (s->new_depth * s->new_width) / 8; 854 } else { 855 ret = surface_stride(surface); 856 } 857 break; 858 859 case SVGA_REG_FB_START: { 860 struct pci_vmsvga_state_s *pci_vmsvga 861 = container_of(s, struct pci_vmsvga_state_s, chip); 862 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1); 863 break; 864 } 865 866 case SVGA_REG_FB_OFFSET: 867 ret = 0x0; 868 break; 869 870 case SVGA_REG_VRAM_SIZE: 871 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 872 break; 873 874 case SVGA_REG_FB_SIZE: 875 ret = s->vga.vram_size; 876 break; 877 878 case SVGA_REG_CAPABILITIES: 879 caps = SVGA_CAP_NONE; 880 #ifdef HW_RECT_ACCEL 881 caps |= SVGA_CAP_RECT_COPY; 882 #endif 883 #ifdef HW_FILL_ACCEL 884 caps |= SVGA_CAP_RECT_FILL; 885 #endif 886 #ifdef HW_MOUSE_ACCEL 887 if (dpy_cursor_define_supported(s->vga.con)) { 888 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 889 SVGA_CAP_CURSOR_BYPASS; 890 } 891 #endif 892 ret = caps; 893 break; 894 895 case SVGA_REG_MEM_START: { 896 struct pci_vmsvga_state_s *pci_vmsvga 897 = container_of(s, struct pci_vmsvga_state_s, chip); 898 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2); 899 break; 900 } 901 902 case SVGA_REG_MEM_SIZE: 903 ret = s->fifo_size; 904 break; 905 906 case SVGA_REG_CONFIG_DONE: 907 ret = s->config; 908 break; 909 910 case SVGA_REG_SYNC: 911 case SVGA_REG_BUSY: 912 ret = s->syncing; 913 break; 914 915 case SVGA_REG_GUEST_ID: 916 ret = s->guest; 917 break; 918 919 case SVGA_REG_CURSOR_ID: 920 ret = s->cursor.id; 921 break; 922 923 case SVGA_REG_CURSOR_X: 924 ret = s->cursor.x; 925 break; 926 927 case SVGA_REG_CURSOR_Y: 928 ret = s->cursor.y; 929 break; 930 931 case SVGA_REG_CURSOR_ON: 932 ret = s->cursor.on; 933 break; 934 935 case SVGA_REG_SCRATCH_SIZE: 936 ret = s->scratch_size; 937 break; 938 939 case SVGA_REG_MEM_REGS: 940 case SVGA_REG_NUM_DISPLAYS: 941 case SVGA_REG_PITCHLOCK: 942 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 943 ret = 0; 944 break; 945 946 default: 947 if (s->index >= SVGA_SCRATCH_BASE && 948 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 949 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 950 break; 951 } 952 printf("%s: Bad register %02x\n", __func__, s->index); 953 ret = 0; 954 break; 955 } 956 957 if (s->index >= SVGA_SCRATCH_BASE) { 958 trace_vmware_scratch_read(s->index, ret); 959 } else if (s->index >= SVGA_PALETTE_BASE) { 960 trace_vmware_palette_read(s->index, ret); 961 } else { 962 trace_vmware_value_read(s->index, ret); 963 } 964 return ret; 965 } 966 967 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 968 { 969 struct vmsvga_state_s *s = opaque; 970 971 if (s->index >= SVGA_SCRATCH_BASE) { 972 trace_vmware_scratch_write(s->index, value); 973 } else if (s->index >= SVGA_PALETTE_BASE) { 974 trace_vmware_palette_write(s->index, value); 975 } else { 976 trace_vmware_value_write(s->index, value); 977 } 978 switch (s->index) { 979 case SVGA_REG_ID: 980 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 981 s->svgaid = value; 982 } 983 break; 984 985 case SVGA_REG_ENABLE: 986 s->enable = !!value; 987 s->invalidated = 1; 988 s->vga.hw_ops->invalidate(&s->vga); 989 if (s->enable && s->config) { 990 vga_dirty_log_stop(&s->vga); 991 } else { 992 vga_dirty_log_start(&s->vga); 993 } 994 break; 995 996 case SVGA_REG_WIDTH: 997 if (value <= SVGA_MAX_WIDTH) { 998 s->new_width = value; 999 s->invalidated = 1; 1000 } else { 1001 printf("%s: Bad width: %i\n", __func__, value); 1002 } 1003 break; 1004 1005 case SVGA_REG_HEIGHT: 1006 if (value <= SVGA_MAX_HEIGHT) { 1007 s->new_height = value; 1008 s->invalidated = 1; 1009 } else { 1010 printf("%s: Bad height: %i\n", __func__, value); 1011 } 1012 break; 1013 1014 case SVGA_REG_BITS_PER_PIXEL: 1015 if (value != 32) { 1016 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 1017 s->config = 0; 1018 s->invalidated = 1; 1019 } 1020 break; 1021 1022 case SVGA_REG_CONFIG_DONE: 1023 if (value) { 1024 s->fifo = (uint32_t *) s->fifo_ptr; 1025 vga_dirty_log_stop(&s->vga); 1026 } 1027 s->config = !!value; 1028 break; 1029 1030 case SVGA_REG_SYNC: 1031 s->syncing = 1; 1032 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 1033 break; 1034 1035 case SVGA_REG_GUEST_ID: 1036 s->guest = value; 1037 #ifdef VERBOSE 1038 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 1039 ARRAY_SIZE(vmsvga_guest_id)) { 1040 printf("%s: guest runs %s.\n", __func__, 1041 vmsvga_guest_id[value - GUEST_OS_BASE]); 1042 } 1043 #endif 1044 break; 1045 1046 case SVGA_REG_CURSOR_ID: 1047 s->cursor.id = value; 1048 break; 1049 1050 case SVGA_REG_CURSOR_X: 1051 s->cursor.x = value; 1052 break; 1053 1054 case SVGA_REG_CURSOR_Y: 1055 s->cursor.y = value; 1056 break; 1057 1058 case SVGA_REG_CURSOR_ON: 1059 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 1060 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 1061 #ifdef HW_MOUSE_ACCEL 1062 if (value <= SVGA_CURSOR_ON_SHOW) { 1063 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1064 } 1065 #endif 1066 break; 1067 1068 case SVGA_REG_DEPTH: 1069 case SVGA_REG_MEM_REGS: 1070 case SVGA_REG_NUM_DISPLAYS: 1071 case SVGA_REG_PITCHLOCK: 1072 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1073 break; 1074 1075 default: 1076 if (s->index >= SVGA_SCRATCH_BASE && 1077 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1078 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1079 break; 1080 } 1081 printf("%s: Bad register %02x\n", __func__, s->index); 1082 } 1083 } 1084 1085 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1086 { 1087 printf("%s: what are we supposed to return?\n", __func__); 1088 return 0xcafe; 1089 } 1090 1091 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1092 { 1093 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1094 } 1095 1096 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1097 { 1098 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1099 1100 if (s->new_width != surface_width(surface) || 1101 s->new_height != surface_height(surface) || 1102 s->new_depth != surface_bits_per_pixel(surface)) { 1103 int stride = (s->new_depth * s->new_width) / 8; 1104 pixman_format_code_t format = 1105 qemu_default_pixman_format(s->new_depth, true); 1106 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); 1107 surface = qemu_create_displaysurface_from(s->new_width, s->new_height, 1108 format, stride, 1109 s->vga.vram_ptr); 1110 dpy_gfx_replace_surface(s->vga.con, surface); 1111 s->invalidated = 1; 1112 } 1113 } 1114 1115 static void vmsvga_update_display(void *opaque) 1116 { 1117 struct vmsvga_state_s *s = opaque; 1118 DisplaySurface *surface; 1119 1120 if (!s->enable || !s->config) { 1121 /* in standard vga mode */ 1122 s->vga.hw_ops->gfx_update(&s->vga); 1123 return; 1124 } 1125 1126 vmsvga_check_size(s); 1127 surface = qemu_console_surface(s->vga.con); 1128 1129 vmsvga_fifo_run(s); 1130 vmsvga_update_rect_flush(s); 1131 1132 if (s->invalidated) { 1133 s->invalidated = 0; 1134 dpy_gfx_update(s->vga.con, 0, 0, 1135 surface_width(surface), surface_height(surface)); 1136 } 1137 } 1138 1139 static void vmsvga_reset(DeviceState *dev) 1140 { 1141 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); 1142 struct vmsvga_state_s *s = &pci->chip; 1143 1144 s->index = 0; 1145 s->enable = 0; 1146 s->config = 0; 1147 s->svgaid = SVGA_ID; 1148 s->cursor.on = 0; 1149 s->redraw_fifo_first = 0; 1150 s->redraw_fifo_last = 0; 1151 s->syncing = 0; 1152 1153 vga_dirty_log_start(&s->vga); 1154 } 1155 1156 static void vmsvga_invalidate_display(void *opaque) 1157 { 1158 struct vmsvga_state_s *s = opaque; 1159 if (!s->enable) { 1160 s->vga.hw_ops->invalidate(&s->vga); 1161 return; 1162 } 1163 1164 s->invalidated = 1; 1165 } 1166 1167 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1168 { 1169 struct vmsvga_state_s *s = opaque; 1170 1171 if (s->vga.hw_ops->text_update) { 1172 s->vga.hw_ops->text_update(&s->vga, chardata); 1173 } 1174 } 1175 1176 static int vmsvga_post_load(void *opaque, int version_id) 1177 { 1178 struct vmsvga_state_s *s = opaque; 1179 1180 s->invalidated = 1; 1181 if (s->config) { 1182 s->fifo = (uint32_t *) s->fifo_ptr; 1183 } 1184 return 0; 1185 } 1186 1187 static const VMStateDescription vmstate_vmware_vga_internal = { 1188 .name = "vmware_vga_internal", 1189 .version_id = 0, 1190 .minimum_version_id = 0, 1191 .post_load = vmsvga_post_load, 1192 .fields = (VMStateField[]) { 1193 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s, NULL), 1194 VMSTATE_INT32(enable, struct vmsvga_state_s), 1195 VMSTATE_INT32(config, struct vmsvga_state_s), 1196 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1197 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1198 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1199 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1200 VMSTATE_INT32(index, struct vmsvga_state_s), 1201 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1202 scratch_size, 0, vmstate_info_uint32, uint32_t), 1203 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1204 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1205 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1206 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1207 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1208 VMSTATE_UNUSED(4), /* was fb_size */ 1209 VMSTATE_END_OF_LIST() 1210 } 1211 }; 1212 1213 static const VMStateDescription vmstate_vmware_vga = { 1214 .name = "vmware_vga", 1215 .version_id = 0, 1216 .minimum_version_id = 0, 1217 .fields = (VMStateField[]) { 1218 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s), 1219 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1220 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1221 VMSTATE_END_OF_LIST() 1222 } 1223 }; 1224 1225 static const GraphicHwOps vmsvga_ops = { 1226 .invalidate = vmsvga_invalidate_display, 1227 .gfx_update = vmsvga_update_display, 1228 .text_update = vmsvga_text_update, 1229 }; 1230 1231 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, 1232 MemoryRegion *address_space, MemoryRegion *io) 1233 { 1234 s->scratch_size = SVGA_SCRATCH_SIZE; 1235 s->scratch = g_malloc(s->scratch_size * 4); 1236 1237 s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s); 1238 1239 s->fifo_size = SVGA_FIFO_SIZE; 1240 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, 1241 &error_fatal); 1242 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1243 1244 vga_common_init(&s->vga, OBJECT(dev), true); 1245 vga_init(&s->vga, OBJECT(dev), address_space, io, true); 1246 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1247 s->new_depth = 32; 1248 } 1249 1250 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1251 { 1252 struct vmsvga_state_s *s = opaque; 1253 1254 switch (addr) { 1255 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1256 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1257 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1258 default: return -1u; 1259 } 1260 } 1261 1262 static void vmsvga_io_write(void *opaque, hwaddr addr, 1263 uint64_t data, unsigned size) 1264 { 1265 struct vmsvga_state_s *s = opaque; 1266 1267 switch (addr) { 1268 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1269 vmsvga_index_write(s, addr, data); 1270 break; 1271 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1272 vmsvga_value_write(s, addr, data); 1273 break; 1274 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1275 vmsvga_bios_write(s, addr, data); 1276 break; 1277 } 1278 } 1279 1280 static const MemoryRegionOps vmsvga_io_ops = { 1281 .read = vmsvga_io_read, 1282 .write = vmsvga_io_write, 1283 .endianness = DEVICE_LITTLE_ENDIAN, 1284 .valid = { 1285 .min_access_size = 4, 1286 .max_access_size = 4, 1287 .unaligned = true, 1288 }, 1289 .impl = { 1290 .unaligned = true, 1291 }, 1292 }; 1293 1294 static void pci_vmsvga_realize(PCIDevice *dev, Error **errp) 1295 { 1296 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); 1297 1298 dev->config[PCI_CACHE_LINE_SIZE] = 0x08; 1299 dev->config[PCI_LATENCY_TIMER] = 0x40; 1300 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1301 1302 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, 1303 "vmsvga-io", 0x10); 1304 memory_region_set_flush_coalesced(&s->io_bar); 1305 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1306 1307 vmsvga_init(DEVICE(dev), &s->chip, 1308 pci_address_space(dev), pci_address_space_io(dev)); 1309 1310 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1311 &s->chip.vga.vram); 1312 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1313 &s->chip.fifo_ram); 1314 1315 if (!dev->rom_bar) { 1316 /* compatibility with pc-0.13 and older */ 1317 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); 1318 } 1319 } 1320 1321 static Property vga_vmware_properties[] = { 1322 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1323 chip.vga.vram_size_mb, 16), 1324 DEFINE_PROP_END_OF_LIST(), 1325 }; 1326 1327 static void vmsvga_class_init(ObjectClass *klass, void *data) 1328 { 1329 DeviceClass *dc = DEVICE_CLASS(klass); 1330 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1331 1332 k->realize = pci_vmsvga_realize; 1333 k->romfile = "vgabios-vmware.bin"; 1334 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1335 k->device_id = SVGA_PCI_DEVICE_ID; 1336 k->class_id = PCI_CLASS_DISPLAY_VGA; 1337 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1338 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1339 dc->reset = vmsvga_reset; 1340 dc->vmsd = &vmstate_vmware_vga; 1341 dc->props = vga_vmware_properties; 1342 dc->hotpluggable = false; 1343 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1344 } 1345 1346 static const TypeInfo vmsvga_info = { 1347 .name = TYPE_VMWARE_SVGA, 1348 .parent = TYPE_PCI_DEVICE, 1349 .instance_size = sizeof(struct pci_vmsvga_state_s), 1350 .class_init = vmsvga_class_init, 1351 .interfaces = (InterfaceInfo[]) { 1352 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1353 { }, 1354 }, 1355 }; 1356 1357 static void vmsvga_register_types(void) 1358 { 1359 type_register_static(&vmsvga_info); 1360 } 1361 1362 type_init(vmsvga_register_types) 1363