1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/loader.h" 26 #include "ui/console.h" 27 #include "hw/pci/pci.h" 28 29 #undef VERBOSE 30 #define HW_RECT_ACCEL 31 #define HW_FILL_ACCEL 32 #define HW_MOUSE_ACCEL 33 34 #include "vga_int.h" 35 36 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 37 38 struct vmsvga_state_s { 39 VGACommonState vga; 40 41 int invalidated; 42 int enable; 43 int config; 44 struct { 45 int id; 46 int x; 47 int y; 48 int on; 49 } cursor; 50 51 int index; 52 int scratch_size; 53 uint32_t *scratch; 54 int new_width; 55 int new_height; 56 int new_depth; 57 uint32_t guest; 58 uint32_t svgaid; 59 int syncing; 60 61 MemoryRegion fifo_ram; 62 uint8_t *fifo_ptr; 63 unsigned int fifo_size; 64 65 union { 66 uint32_t *fifo; 67 struct QEMU_PACKED { 68 uint32_t min; 69 uint32_t max; 70 uint32_t next_cmd; 71 uint32_t stop; 72 /* Add registers here when adding capabilities. */ 73 uint32_t fifo[0]; 74 } *cmd; 75 }; 76 77 #define REDRAW_FIFO_LEN 512 78 struct vmsvga_rect_s { 79 int x, y, w, h; 80 } redraw_fifo[REDRAW_FIFO_LEN]; 81 int redraw_fifo_first, redraw_fifo_last; 82 }; 83 84 struct pci_vmsvga_state_s { 85 PCIDevice card; 86 struct vmsvga_state_s chip; 87 MemoryRegion io_bar; 88 }; 89 90 #define SVGA_MAGIC 0x900000UL 91 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 92 #define SVGA_ID_0 SVGA_MAKE_ID(0) 93 #define SVGA_ID_1 SVGA_MAKE_ID(1) 94 #define SVGA_ID_2 SVGA_MAKE_ID(2) 95 96 #define SVGA_LEGACY_BASE_PORT 0x4560 97 #define SVGA_INDEX_PORT 0x0 98 #define SVGA_VALUE_PORT 0x1 99 #define SVGA_BIOS_PORT 0x2 100 101 #define SVGA_VERSION_2 102 103 #ifdef SVGA_VERSION_2 104 # define SVGA_ID SVGA_ID_2 105 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 106 # define SVGA_IO_MUL 1 107 # define SVGA_FIFO_SIZE 0x10000 108 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 109 #else 110 # define SVGA_ID SVGA_ID_1 111 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 112 # define SVGA_IO_MUL 4 113 # define SVGA_FIFO_SIZE 0x10000 114 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 115 #endif 116 117 enum { 118 /* ID 0, 1 and 2 registers */ 119 SVGA_REG_ID = 0, 120 SVGA_REG_ENABLE = 1, 121 SVGA_REG_WIDTH = 2, 122 SVGA_REG_HEIGHT = 3, 123 SVGA_REG_MAX_WIDTH = 4, 124 SVGA_REG_MAX_HEIGHT = 5, 125 SVGA_REG_DEPTH = 6, 126 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 127 SVGA_REG_PSEUDOCOLOR = 8, 128 SVGA_REG_RED_MASK = 9, 129 SVGA_REG_GREEN_MASK = 10, 130 SVGA_REG_BLUE_MASK = 11, 131 SVGA_REG_BYTES_PER_LINE = 12, 132 SVGA_REG_FB_START = 13, 133 SVGA_REG_FB_OFFSET = 14, 134 SVGA_REG_VRAM_SIZE = 15, 135 SVGA_REG_FB_SIZE = 16, 136 137 /* ID 1 and 2 registers */ 138 SVGA_REG_CAPABILITIES = 17, 139 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 140 SVGA_REG_MEM_SIZE = 19, 141 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 142 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 143 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 144 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 145 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 146 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 147 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 148 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 149 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 150 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 151 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 152 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 153 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 154 155 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 156 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 157 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 158 }; 159 160 #define SVGA_CAP_NONE 0 161 #define SVGA_CAP_RECT_FILL (1 << 0) 162 #define SVGA_CAP_RECT_COPY (1 << 1) 163 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 164 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 165 #define SVGA_CAP_RASTER_OP (1 << 4) 166 #define SVGA_CAP_CURSOR (1 << 5) 167 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 168 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 169 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 170 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 171 #define SVGA_CAP_GLYPH (1 << 10) 172 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 173 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 174 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 175 #define SVGA_CAP_3D (1 << 14) 176 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 177 #define SVGA_CAP_MULTIMON (1 << 16) 178 #define SVGA_CAP_PITCHLOCK (1 << 17) 179 180 /* 181 * FIFO offsets (seen as an array of 32-bit words) 182 */ 183 enum { 184 /* 185 * The original defined FIFO offsets 186 */ 187 SVGA_FIFO_MIN = 0, 188 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 189 SVGA_FIFO_NEXT_CMD, 190 SVGA_FIFO_STOP, 191 192 /* 193 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 194 */ 195 SVGA_FIFO_CAPABILITIES = 4, 196 SVGA_FIFO_FLAGS, 197 SVGA_FIFO_FENCE, 198 SVGA_FIFO_3D_HWVERSION, 199 SVGA_FIFO_PITCHLOCK, 200 }; 201 202 #define SVGA_FIFO_CAP_NONE 0 203 #define SVGA_FIFO_CAP_FENCE (1 << 0) 204 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 205 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 206 207 #define SVGA_FIFO_FLAG_NONE 0 208 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 209 210 /* These values can probably be changed arbitrarily. */ 211 #define SVGA_SCRATCH_SIZE 0x8000 212 #define SVGA_MAX_WIDTH 2360 213 #define SVGA_MAX_HEIGHT 1770 214 215 #ifdef VERBOSE 216 # define GUEST_OS_BASE 0x5001 217 static const char *vmsvga_guest_id[] = { 218 [0x00] = "Dos", 219 [0x01] = "Windows 3.1", 220 [0x02] = "Windows 95", 221 [0x03] = "Windows 98", 222 [0x04] = "Windows ME", 223 [0x05] = "Windows NT", 224 [0x06] = "Windows 2000", 225 [0x07] = "Linux", 226 [0x08] = "OS/2", 227 [0x09] = "an unknown OS", 228 [0x0a] = "BSD", 229 [0x0b] = "Whistler", 230 [0x0c] = "an unknown OS", 231 [0x0d] = "an unknown OS", 232 [0x0e] = "an unknown OS", 233 [0x0f] = "an unknown OS", 234 [0x10] = "an unknown OS", 235 [0x11] = "an unknown OS", 236 [0x12] = "an unknown OS", 237 [0x13] = "an unknown OS", 238 [0x14] = "an unknown OS", 239 [0x15] = "Windows 2003", 240 }; 241 #endif 242 243 enum { 244 SVGA_CMD_INVALID_CMD = 0, 245 SVGA_CMD_UPDATE = 1, 246 SVGA_CMD_RECT_FILL = 2, 247 SVGA_CMD_RECT_COPY = 3, 248 SVGA_CMD_DEFINE_BITMAP = 4, 249 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 250 SVGA_CMD_DEFINE_PIXMAP = 6, 251 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 252 SVGA_CMD_RECT_BITMAP_FILL = 8, 253 SVGA_CMD_RECT_PIXMAP_FILL = 9, 254 SVGA_CMD_RECT_BITMAP_COPY = 10, 255 SVGA_CMD_RECT_PIXMAP_COPY = 11, 256 SVGA_CMD_FREE_OBJECT = 12, 257 SVGA_CMD_RECT_ROP_FILL = 13, 258 SVGA_CMD_RECT_ROP_COPY = 14, 259 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 260 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 261 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 262 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 263 SVGA_CMD_DEFINE_CURSOR = 19, 264 SVGA_CMD_DISPLAY_CURSOR = 20, 265 SVGA_CMD_MOVE_CURSOR = 21, 266 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 267 SVGA_CMD_DRAW_GLYPH = 23, 268 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 269 SVGA_CMD_UPDATE_VERBOSE = 25, 270 SVGA_CMD_SURFACE_FILL = 26, 271 SVGA_CMD_SURFACE_COPY = 27, 272 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 273 SVGA_CMD_FRONT_ROP_FILL = 29, 274 SVGA_CMD_FENCE = 30, 275 }; 276 277 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 278 enum { 279 SVGA_CURSOR_ON_HIDE = 0, 280 SVGA_CURSOR_ON_SHOW = 1, 281 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 282 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 283 }; 284 285 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 286 int x, int y, int w, int h) 287 { 288 DisplaySurface *surface = qemu_console_surface(s->vga.con); 289 int line; 290 int bypl; 291 int width; 292 int start; 293 uint8_t *src; 294 uint8_t *dst; 295 296 if (x < 0) { 297 fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x); 298 w += x; 299 x = 0; 300 } 301 if (w < 0) { 302 fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w); 303 w = 0; 304 } 305 if (x + w > surface_width(surface)) { 306 fprintf(stderr, "%s: update width too large x: %d, w: %d\n", 307 __func__, x, w); 308 x = MIN(x, surface_width(surface)); 309 w = surface_width(surface) - x; 310 } 311 312 if (y < 0) { 313 fprintf(stderr, "%s: update y was < 0 (%d)\n", __func__, y); 314 h += y; 315 y = 0; 316 } 317 if (h < 0) { 318 fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h); 319 h = 0; 320 } 321 if (y + h > surface_height(surface)) { 322 fprintf(stderr, "%s: update height too large y: %d, h: %d\n", 323 __func__, y, h); 324 y = MIN(y, surface_height(surface)); 325 h = surface_height(surface) - y; 326 } 327 328 bypl = surface_stride(surface); 329 width = surface_bytes_per_pixel(surface) * w; 330 start = surface_bytes_per_pixel(surface) * x + bypl * y; 331 src = s->vga.vram_ptr + start; 332 dst = surface_data(surface) + start; 333 334 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 335 memcpy(dst, src, width); 336 } 337 dpy_gfx_update(s->vga.con, x, y, w, h); 338 } 339 340 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 341 int x, int y, int w, int h) 342 { 343 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 344 345 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 346 rect->x = x; 347 rect->y = y; 348 rect->w = w; 349 rect->h = h; 350 } 351 352 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 353 { 354 struct vmsvga_rect_s *rect; 355 356 if (s->invalidated) { 357 s->redraw_fifo_first = s->redraw_fifo_last; 358 return; 359 } 360 /* Overlapping region updates can be optimised out here - if someone 361 * knows a smart algorithm to do that, please share. */ 362 while (s->redraw_fifo_first != s->redraw_fifo_last) { 363 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 364 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 365 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 366 } 367 } 368 369 #ifdef HW_RECT_ACCEL 370 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, 371 int x0, int y0, int x1, int y1, int w, int h) 372 { 373 DisplaySurface *surface = qemu_console_surface(s->vga.con); 374 uint8_t *vram = s->vga.vram_ptr; 375 int bypl = surface_stride(surface); 376 int bypp = surface_bytes_per_pixel(surface); 377 int width = bypp * w; 378 int line = h; 379 uint8_t *ptr[2]; 380 381 if (y1 > y0) { 382 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 383 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 384 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 385 memmove(ptr[1], ptr[0], width); 386 } 387 } else { 388 ptr[0] = vram + bypp * x0 + bypl * y0; 389 ptr[1] = vram + bypp * x1 + bypl * y1; 390 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 391 memmove(ptr[1], ptr[0], width); 392 } 393 } 394 395 vmsvga_update_rect_delayed(s, x1, y1, w, h); 396 } 397 #endif 398 399 #ifdef HW_FILL_ACCEL 400 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, 401 uint32_t c, int x, int y, int w, int h) 402 { 403 DisplaySurface *surface = qemu_console_surface(s->vga.con); 404 int bypl = surface_stride(surface); 405 int width = surface_bytes_per_pixel(surface) * w; 406 int line = h; 407 int column; 408 uint8_t *fst; 409 uint8_t *dst; 410 uint8_t *src; 411 uint8_t col[4]; 412 413 col[0] = c; 414 col[1] = c >> 8; 415 col[2] = c >> 16; 416 col[3] = c >> 24; 417 418 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 419 420 if (line--) { 421 dst = fst; 422 src = col; 423 for (column = width; column > 0; column--) { 424 *(dst++) = *(src++); 425 if (src - col == surface_bytes_per_pixel(surface)) { 426 src = col; 427 } 428 } 429 dst = fst; 430 for (; line > 0; line--) { 431 dst += bypl; 432 memcpy(dst, fst, width); 433 } 434 } 435 436 vmsvga_update_rect_delayed(s, x, y, w, h); 437 } 438 #endif 439 440 struct vmsvga_cursor_definition_s { 441 int width; 442 int height; 443 int id; 444 int bpp; 445 int hot_x; 446 int hot_y; 447 uint32_t mask[1024]; 448 uint32_t image[4096]; 449 }; 450 451 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 452 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 453 454 #ifdef HW_MOUSE_ACCEL 455 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 456 struct vmsvga_cursor_definition_s *c) 457 { 458 QEMUCursor *qc; 459 int i, pixels; 460 461 qc = cursor_alloc(c->width, c->height); 462 qc->hot_x = c->hot_x; 463 qc->hot_y = c->hot_y; 464 switch (c->bpp) { 465 case 1: 466 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 467 1, (void *)c->mask); 468 #ifdef DEBUG 469 cursor_print_ascii_art(qc, "vmware/mono"); 470 #endif 471 break; 472 case 32: 473 /* fill alpha channel from mask, set color to zero */ 474 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 475 1, (void *)c->mask); 476 /* add in rgb values */ 477 pixels = c->width * c->height; 478 for (i = 0; i < pixels; i++) { 479 qc->data[i] |= c->image[i] & 0xffffff; 480 } 481 #ifdef DEBUG 482 cursor_print_ascii_art(qc, "vmware/32bit"); 483 #endif 484 break; 485 default: 486 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 487 __func__, c->bpp); 488 cursor_put(qc); 489 qc = cursor_builtin_left_ptr(); 490 } 491 492 dpy_cursor_define(s->vga.con, qc); 493 cursor_put(qc); 494 } 495 #endif 496 497 #define CMD(f) le32_to_cpu(s->cmd->f) 498 499 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 500 { 501 int num; 502 503 if (!s->config || !s->enable) { 504 return 0; 505 } 506 num = CMD(next_cmd) - CMD(stop); 507 if (num < 0) { 508 num += CMD(max) - CMD(min); 509 } 510 return num >> 2; 511 } 512 513 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 514 { 515 uint32_t cmd = s->fifo[CMD(stop) >> 2]; 516 517 s->cmd->stop = cpu_to_le32(CMD(stop) + 4); 518 if (CMD(stop) >= CMD(max)) { 519 s->cmd->stop = s->cmd->min; 520 } 521 return cmd; 522 } 523 524 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 525 { 526 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 527 } 528 529 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 530 { 531 uint32_t cmd, colour; 532 int args, len; 533 int x, y, dx, dy, width, height; 534 struct vmsvga_cursor_definition_s cursor; 535 uint32_t cmd_start; 536 537 len = vmsvga_fifo_length(s); 538 while (len > 0) { 539 /* May need to go back to the start of the command if incomplete */ 540 cmd_start = s->cmd->stop; 541 542 switch (cmd = vmsvga_fifo_read(s)) { 543 case SVGA_CMD_UPDATE: 544 case SVGA_CMD_UPDATE_VERBOSE: 545 len -= 5; 546 if (len < 0) { 547 goto rewind; 548 } 549 550 x = vmsvga_fifo_read(s); 551 y = vmsvga_fifo_read(s); 552 width = vmsvga_fifo_read(s); 553 height = vmsvga_fifo_read(s); 554 vmsvga_update_rect_delayed(s, x, y, width, height); 555 break; 556 557 case SVGA_CMD_RECT_FILL: 558 len -= 6; 559 if (len < 0) { 560 goto rewind; 561 } 562 563 colour = vmsvga_fifo_read(s); 564 x = vmsvga_fifo_read(s); 565 y = vmsvga_fifo_read(s); 566 width = vmsvga_fifo_read(s); 567 height = vmsvga_fifo_read(s); 568 #ifdef HW_FILL_ACCEL 569 vmsvga_fill_rect(s, colour, x, y, width, height); 570 break; 571 #else 572 args = 0; 573 goto badcmd; 574 #endif 575 576 case SVGA_CMD_RECT_COPY: 577 len -= 7; 578 if (len < 0) { 579 goto rewind; 580 } 581 582 x = vmsvga_fifo_read(s); 583 y = vmsvga_fifo_read(s); 584 dx = vmsvga_fifo_read(s); 585 dy = vmsvga_fifo_read(s); 586 width = vmsvga_fifo_read(s); 587 height = vmsvga_fifo_read(s); 588 #ifdef HW_RECT_ACCEL 589 vmsvga_copy_rect(s, x, y, dx, dy, width, height); 590 break; 591 #else 592 args = 0; 593 goto badcmd; 594 #endif 595 596 case SVGA_CMD_DEFINE_CURSOR: 597 len -= 8; 598 if (len < 0) { 599 goto rewind; 600 } 601 602 cursor.id = vmsvga_fifo_read(s); 603 cursor.hot_x = vmsvga_fifo_read(s); 604 cursor.hot_y = vmsvga_fifo_read(s); 605 cursor.width = x = vmsvga_fifo_read(s); 606 cursor.height = y = vmsvga_fifo_read(s); 607 vmsvga_fifo_read(s); 608 cursor.bpp = vmsvga_fifo_read(s); 609 610 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 611 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || 612 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { 613 goto badcmd; 614 } 615 616 len -= args; 617 if (len < 0) { 618 goto rewind; 619 } 620 621 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 622 cursor.mask[args] = vmsvga_fifo_read_raw(s); 623 } 624 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 625 cursor.image[args] = vmsvga_fifo_read_raw(s); 626 } 627 #ifdef HW_MOUSE_ACCEL 628 vmsvga_cursor_define(s, &cursor); 629 break; 630 #else 631 args = 0; 632 goto badcmd; 633 #endif 634 635 /* 636 * Other commands that we at least know the number of arguments 637 * for so we can avoid FIFO desync if driver uses them illegally. 638 */ 639 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 640 len -= 6; 641 if (len < 0) { 642 goto rewind; 643 } 644 vmsvga_fifo_read(s); 645 vmsvga_fifo_read(s); 646 vmsvga_fifo_read(s); 647 x = vmsvga_fifo_read(s); 648 y = vmsvga_fifo_read(s); 649 args = x * y; 650 goto badcmd; 651 case SVGA_CMD_RECT_ROP_FILL: 652 args = 6; 653 goto badcmd; 654 case SVGA_CMD_RECT_ROP_COPY: 655 args = 7; 656 goto badcmd; 657 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 658 len -= 4; 659 if (len < 0) { 660 goto rewind; 661 } 662 vmsvga_fifo_read(s); 663 vmsvga_fifo_read(s); 664 args = 7 + (vmsvga_fifo_read(s) >> 2); 665 goto badcmd; 666 case SVGA_CMD_SURFACE_ALPHA_BLEND: 667 args = 12; 668 goto badcmd; 669 670 /* 671 * Other commands that are not listed as depending on any 672 * CAPABILITIES bits, but are not described in the README either. 673 */ 674 case SVGA_CMD_SURFACE_FILL: 675 case SVGA_CMD_SURFACE_COPY: 676 case SVGA_CMD_FRONT_ROP_FILL: 677 case SVGA_CMD_FENCE: 678 case SVGA_CMD_INVALID_CMD: 679 break; /* Nop */ 680 681 default: 682 args = 0; 683 badcmd: 684 len -= args; 685 if (len < 0) { 686 goto rewind; 687 } 688 while (args--) { 689 vmsvga_fifo_read(s); 690 } 691 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 692 __func__, cmd); 693 break; 694 695 rewind: 696 s->cmd->stop = cmd_start; 697 break; 698 } 699 } 700 701 s->syncing = 0; 702 } 703 704 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 705 { 706 struct vmsvga_state_s *s = opaque; 707 708 return s->index; 709 } 710 711 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 712 { 713 struct vmsvga_state_s *s = opaque; 714 715 s->index = index; 716 } 717 718 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 719 { 720 uint32_t caps; 721 struct vmsvga_state_s *s = opaque; 722 DisplaySurface *surface = qemu_console_surface(s->vga.con); 723 PixelFormat pf; 724 uint32_t ret; 725 726 switch (s->index) { 727 case SVGA_REG_ID: 728 ret = s->svgaid; 729 break; 730 731 case SVGA_REG_ENABLE: 732 ret = s->enable; 733 break; 734 735 case SVGA_REG_WIDTH: 736 ret = s->new_width ? s->new_width : surface_width(surface); 737 break; 738 739 case SVGA_REG_HEIGHT: 740 ret = s->new_height ? s->new_height : surface_height(surface); 741 break; 742 743 case SVGA_REG_MAX_WIDTH: 744 ret = SVGA_MAX_WIDTH; 745 break; 746 747 case SVGA_REG_MAX_HEIGHT: 748 ret = SVGA_MAX_HEIGHT; 749 break; 750 751 case SVGA_REG_DEPTH: 752 ret = (s->new_depth == 32) ? 24 : s->new_depth; 753 break; 754 755 case SVGA_REG_BITS_PER_PIXEL: 756 case SVGA_REG_HOST_BITS_PER_PIXEL: 757 ret = s->new_depth; 758 break; 759 760 case SVGA_REG_PSEUDOCOLOR: 761 ret = 0x0; 762 break; 763 764 case SVGA_REG_RED_MASK: 765 pf = qemu_default_pixelformat(s->new_depth); 766 ret = pf.rmask; 767 break; 768 769 case SVGA_REG_GREEN_MASK: 770 pf = qemu_default_pixelformat(s->new_depth); 771 ret = pf.gmask; 772 break; 773 774 case SVGA_REG_BLUE_MASK: 775 pf = qemu_default_pixelformat(s->new_depth); 776 ret = pf.bmask; 777 break; 778 779 case SVGA_REG_BYTES_PER_LINE: 780 if (s->new_width) { 781 ret = (s->new_depth * s->new_width) / 8; 782 } else { 783 ret = surface_stride(surface); 784 } 785 break; 786 787 case SVGA_REG_FB_START: { 788 struct pci_vmsvga_state_s *pci_vmsvga 789 = container_of(s, struct pci_vmsvga_state_s, chip); 790 ret = pci_get_bar_addr(&pci_vmsvga->card, 1); 791 break; 792 } 793 794 case SVGA_REG_FB_OFFSET: 795 ret = 0x0; 796 break; 797 798 case SVGA_REG_VRAM_SIZE: 799 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 800 break; 801 802 case SVGA_REG_FB_SIZE: 803 ret = s->vga.vram_size; 804 break; 805 806 case SVGA_REG_CAPABILITIES: 807 caps = SVGA_CAP_NONE; 808 #ifdef HW_RECT_ACCEL 809 caps |= SVGA_CAP_RECT_COPY; 810 #endif 811 #ifdef HW_FILL_ACCEL 812 caps |= SVGA_CAP_RECT_FILL; 813 #endif 814 #ifdef HW_MOUSE_ACCEL 815 if (dpy_cursor_define_supported(s->vga.con)) { 816 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 817 SVGA_CAP_CURSOR_BYPASS; 818 } 819 #endif 820 ret = caps; 821 break; 822 823 case SVGA_REG_MEM_START: { 824 struct pci_vmsvga_state_s *pci_vmsvga 825 = container_of(s, struct pci_vmsvga_state_s, chip); 826 ret = pci_get_bar_addr(&pci_vmsvga->card, 2); 827 break; 828 } 829 830 case SVGA_REG_MEM_SIZE: 831 ret = s->fifo_size; 832 break; 833 834 case SVGA_REG_CONFIG_DONE: 835 ret = s->config; 836 break; 837 838 case SVGA_REG_SYNC: 839 case SVGA_REG_BUSY: 840 ret = s->syncing; 841 break; 842 843 case SVGA_REG_GUEST_ID: 844 ret = s->guest; 845 break; 846 847 case SVGA_REG_CURSOR_ID: 848 ret = s->cursor.id; 849 break; 850 851 case SVGA_REG_CURSOR_X: 852 ret = s->cursor.x; 853 break; 854 855 case SVGA_REG_CURSOR_Y: 856 ret = s->cursor.x; 857 break; 858 859 case SVGA_REG_CURSOR_ON: 860 ret = s->cursor.on; 861 break; 862 863 case SVGA_REG_SCRATCH_SIZE: 864 ret = s->scratch_size; 865 break; 866 867 case SVGA_REG_MEM_REGS: 868 case SVGA_REG_NUM_DISPLAYS: 869 case SVGA_REG_PITCHLOCK: 870 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 871 ret = 0; 872 break; 873 874 default: 875 if (s->index >= SVGA_SCRATCH_BASE && 876 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 877 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 878 break; 879 } 880 printf("%s: Bad register %02x\n", __func__, s->index); 881 ret = 0; 882 break; 883 } 884 885 if (s->index >= SVGA_SCRATCH_BASE) { 886 trace_vmware_scratch_read(s->index, ret); 887 } else if (s->index >= SVGA_PALETTE_BASE) { 888 trace_vmware_palette_read(s->index, ret); 889 } else { 890 trace_vmware_value_read(s->index, ret); 891 } 892 return ret; 893 } 894 895 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 896 { 897 struct vmsvga_state_s *s = opaque; 898 899 if (s->index >= SVGA_SCRATCH_BASE) { 900 trace_vmware_scratch_write(s->index, value); 901 } else if (s->index >= SVGA_PALETTE_BASE) { 902 trace_vmware_palette_write(s->index, value); 903 } else { 904 trace_vmware_value_write(s->index, value); 905 } 906 switch (s->index) { 907 case SVGA_REG_ID: 908 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 909 s->svgaid = value; 910 } 911 break; 912 913 case SVGA_REG_ENABLE: 914 s->enable = !!value; 915 s->invalidated = 1; 916 s->vga.hw_ops->invalidate(&s->vga); 917 if (s->enable && s->config) { 918 vga_dirty_log_stop(&s->vga); 919 } else { 920 vga_dirty_log_start(&s->vga); 921 } 922 break; 923 924 case SVGA_REG_WIDTH: 925 if (value <= SVGA_MAX_WIDTH) { 926 s->new_width = value; 927 s->invalidated = 1; 928 } else { 929 printf("%s: Bad width: %i\n", __func__, value); 930 } 931 break; 932 933 case SVGA_REG_HEIGHT: 934 if (value <= SVGA_MAX_HEIGHT) { 935 s->new_height = value; 936 s->invalidated = 1; 937 } else { 938 printf("%s: Bad height: %i\n", __func__, value); 939 } 940 break; 941 942 case SVGA_REG_BITS_PER_PIXEL: 943 if (value != 32) { 944 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 945 s->config = 0; 946 s->invalidated = 1; 947 } 948 break; 949 950 case SVGA_REG_CONFIG_DONE: 951 if (value) { 952 s->fifo = (uint32_t *) s->fifo_ptr; 953 /* Check range and alignment. */ 954 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { 955 break; 956 } 957 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { 958 break; 959 } 960 if (CMD(max) > SVGA_FIFO_SIZE) { 961 break; 962 } 963 if (CMD(max) < CMD(min) + 10 * 1024) { 964 break; 965 } 966 vga_dirty_log_stop(&s->vga); 967 } 968 s->config = !!value; 969 break; 970 971 case SVGA_REG_SYNC: 972 s->syncing = 1; 973 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 974 break; 975 976 case SVGA_REG_GUEST_ID: 977 s->guest = value; 978 #ifdef VERBOSE 979 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 980 ARRAY_SIZE(vmsvga_guest_id)) { 981 printf("%s: guest runs %s.\n", __func__, 982 vmsvga_guest_id[value - GUEST_OS_BASE]); 983 } 984 #endif 985 break; 986 987 case SVGA_REG_CURSOR_ID: 988 s->cursor.id = value; 989 break; 990 991 case SVGA_REG_CURSOR_X: 992 s->cursor.x = value; 993 break; 994 995 case SVGA_REG_CURSOR_Y: 996 s->cursor.y = value; 997 break; 998 999 case SVGA_REG_CURSOR_ON: 1000 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 1001 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 1002 #ifdef HW_MOUSE_ACCEL 1003 if (value <= SVGA_CURSOR_ON_SHOW) { 1004 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1005 } 1006 #endif 1007 break; 1008 1009 case SVGA_REG_DEPTH: 1010 case SVGA_REG_MEM_REGS: 1011 case SVGA_REG_NUM_DISPLAYS: 1012 case SVGA_REG_PITCHLOCK: 1013 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1014 break; 1015 1016 default: 1017 if (s->index >= SVGA_SCRATCH_BASE && 1018 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1019 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1020 break; 1021 } 1022 printf("%s: Bad register %02x\n", __func__, s->index); 1023 } 1024 } 1025 1026 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1027 { 1028 printf("%s: what are we supposed to return?\n", __func__); 1029 return 0xcafe; 1030 } 1031 1032 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1033 { 1034 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1035 } 1036 1037 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1038 { 1039 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1040 1041 if (s->new_width != surface_width(surface) || 1042 s->new_height != surface_height(surface) || 1043 s->new_depth != surface_bits_per_pixel(surface)) { 1044 int stride = (s->new_depth * s->new_width) / 8; 1045 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); 1046 surface = qemu_create_displaysurface_from(s->new_width, s->new_height, 1047 s->new_depth, stride, 1048 s->vga.vram_ptr, false); 1049 dpy_gfx_replace_surface(s->vga.con, surface); 1050 s->invalidated = 1; 1051 } 1052 } 1053 1054 static void vmsvga_update_display(void *opaque) 1055 { 1056 struct vmsvga_state_s *s = opaque; 1057 DisplaySurface *surface; 1058 bool dirty = false; 1059 1060 if (!s->enable) { 1061 s->vga.hw_ops->gfx_update(&s->vga); 1062 return; 1063 } 1064 1065 vmsvga_check_size(s); 1066 surface = qemu_console_surface(s->vga.con); 1067 1068 vmsvga_fifo_run(s); 1069 vmsvga_update_rect_flush(s); 1070 1071 /* 1072 * Is it more efficient to look at vram VGA-dirty bits or wait 1073 * for the driver to issue SVGA_CMD_UPDATE? 1074 */ 1075 if (memory_region_is_logging(&s->vga.vram)) { 1076 vga_sync_dirty_bitmap(&s->vga); 1077 dirty = memory_region_get_dirty(&s->vga.vram, 0, 1078 surface_stride(surface) * surface_height(surface), 1079 DIRTY_MEMORY_VGA); 1080 } 1081 if (s->invalidated || dirty) { 1082 s->invalidated = 0; 1083 dpy_gfx_update(s->vga.con, 0, 0, 1084 surface_width(surface), surface_height(surface)); 1085 } 1086 if (dirty) { 1087 memory_region_reset_dirty(&s->vga.vram, 0, 1088 surface_stride(surface) * surface_height(surface), 1089 DIRTY_MEMORY_VGA); 1090 } 1091 } 1092 1093 static void vmsvga_reset(DeviceState *dev) 1094 { 1095 struct pci_vmsvga_state_s *pci = 1096 DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev); 1097 struct vmsvga_state_s *s = &pci->chip; 1098 1099 s->index = 0; 1100 s->enable = 0; 1101 s->config = 0; 1102 s->svgaid = SVGA_ID; 1103 s->cursor.on = 0; 1104 s->redraw_fifo_first = 0; 1105 s->redraw_fifo_last = 0; 1106 s->syncing = 0; 1107 1108 vga_dirty_log_start(&s->vga); 1109 } 1110 1111 static void vmsvga_invalidate_display(void *opaque) 1112 { 1113 struct vmsvga_state_s *s = opaque; 1114 if (!s->enable) { 1115 s->vga.hw_ops->invalidate(&s->vga); 1116 return; 1117 } 1118 1119 s->invalidated = 1; 1120 } 1121 1122 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1123 { 1124 struct vmsvga_state_s *s = opaque; 1125 1126 if (s->vga.hw_ops->text_update) { 1127 s->vga.hw_ops->text_update(&s->vga, chardata); 1128 } 1129 } 1130 1131 static int vmsvga_post_load(void *opaque, int version_id) 1132 { 1133 struct vmsvga_state_s *s = opaque; 1134 1135 s->invalidated = 1; 1136 if (s->config) { 1137 s->fifo = (uint32_t *) s->fifo_ptr; 1138 } 1139 return 0; 1140 } 1141 1142 static const VMStateDescription vmstate_vmware_vga_internal = { 1143 .name = "vmware_vga_internal", 1144 .version_id = 0, 1145 .minimum_version_id = 0, 1146 .minimum_version_id_old = 0, 1147 .post_load = vmsvga_post_load, 1148 .fields = (VMStateField[]) { 1149 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), 1150 VMSTATE_INT32(enable, struct vmsvga_state_s), 1151 VMSTATE_INT32(config, struct vmsvga_state_s), 1152 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1153 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1154 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1155 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1156 VMSTATE_INT32(index, struct vmsvga_state_s), 1157 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1158 scratch_size, 0, vmstate_info_uint32, uint32_t), 1159 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1160 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1161 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1162 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1163 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1164 VMSTATE_UNUSED(4), /* was fb_size */ 1165 VMSTATE_END_OF_LIST() 1166 } 1167 }; 1168 1169 static const VMStateDescription vmstate_vmware_vga = { 1170 .name = "vmware_vga", 1171 .version_id = 0, 1172 .minimum_version_id = 0, 1173 .minimum_version_id_old = 0, 1174 .fields = (VMStateField[]) { 1175 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s), 1176 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1177 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1178 VMSTATE_END_OF_LIST() 1179 } 1180 }; 1181 1182 static const GraphicHwOps vmsvga_ops = { 1183 .invalidate = vmsvga_invalidate_display, 1184 .gfx_update = vmsvga_update_display, 1185 .text_update = vmsvga_text_update, 1186 }; 1187 1188 static void vmsvga_init(struct vmsvga_state_s *s, 1189 MemoryRegion *address_space, MemoryRegion *io) 1190 { 1191 s->scratch_size = SVGA_SCRATCH_SIZE; 1192 s->scratch = g_malloc(s->scratch_size * 4); 1193 1194 s->vga.con = graphic_console_init(&vmsvga_ops, s); 1195 1196 s->fifo_size = SVGA_FIFO_SIZE; 1197 memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size); 1198 vmstate_register_ram_global(&s->fifo_ram); 1199 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1200 1201 vga_common_init(&s->vga); 1202 vga_init(&s->vga, address_space, io, true); 1203 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1204 s->new_depth = 32; 1205 } 1206 1207 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1208 { 1209 struct vmsvga_state_s *s = opaque; 1210 1211 switch (addr) { 1212 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1213 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1214 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1215 default: return -1u; 1216 } 1217 } 1218 1219 static void vmsvga_io_write(void *opaque, hwaddr addr, 1220 uint64_t data, unsigned size) 1221 { 1222 struct vmsvga_state_s *s = opaque; 1223 1224 switch (addr) { 1225 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1226 vmsvga_index_write(s, addr, data); 1227 break; 1228 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1229 vmsvga_value_write(s, addr, data); 1230 break; 1231 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1232 vmsvga_bios_write(s, addr, data); 1233 break; 1234 } 1235 } 1236 1237 static const MemoryRegionOps vmsvga_io_ops = { 1238 .read = vmsvga_io_read, 1239 .write = vmsvga_io_write, 1240 .endianness = DEVICE_LITTLE_ENDIAN, 1241 .valid = { 1242 .min_access_size = 4, 1243 .max_access_size = 4, 1244 }, 1245 }; 1246 1247 static int pci_vmsvga_initfn(PCIDevice *dev) 1248 { 1249 struct pci_vmsvga_state_s *s = 1250 DO_UPCAST(struct pci_vmsvga_state_s, card, dev); 1251 1252 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ 1253 s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ 1254 s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1255 1256 memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip, 1257 "vmsvga-io", 0x10); 1258 memory_region_set_flush_coalesced(&s->io_bar); 1259 pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1260 1261 vmsvga_init(&s->chip, pci_address_space(dev), pci_address_space_io(dev)); 1262 1263 pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1264 &s->chip.vga.vram); 1265 pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1266 &s->chip.fifo_ram); 1267 1268 if (!dev->rom_bar) { 1269 /* compatibility with pc-0.13 and older */ 1270 vga_init_vbe(&s->chip.vga, pci_address_space(dev)); 1271 } 1272 1273 return 0; 1274 } 1275 1276 static Property vga_vmware_properties[] = { 1277 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1278 chip.vga.vram_size_mb, 16), 1279 DEFINE_PROP_END_OF_LIST(), 1280 }; 1281 1282 static void vmsvga_class_init(ObjectClass *klass, void *data) 1283 { 1284 DeviceClass *dc = DEVICE_CLASS(klass); 1285 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1286 1287 k->no_hotplug = 1; 1288 k->init = pci_vmsvga_initfn; 1289 k->romfile = "vgabios-vmware.bin"; 1290 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1291 k->device_id = SVGA_PCI_DEVICE_ID; 1292 k->class_id = PCI_CLASS_DISPLAY_VGA; 1293 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1294 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1295 dc->reset = vmsvga_reset; 1296 dc->vmsd = &vmstate_vmware_vga; 1297 dc->props = vga_vmware_properties; 1298 } 1299 1300 static const TypeInfo vmsvga_info = { 1301 .name = "vmware-svga", 1302 .parent = TYPE_PCI_DEVICE, 1303 .instance_size = sizeof(struct pci_vmsvga_state_s), 1304 .class_init = vmsvga_class_init, 1305 }; 1306 1307 static void vmsvga_register_types(void) 1308 { 1309 type_register_static(&vmsvga_info); 1310 } 1311 1312 type_init(vmsvga_register_types) 1313