1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "hw/hw.h" 27 #include "hw/loader.h" 28 #include "trace.h" 29 #include "ui/console.h" 30 #include "ui/vnc.h" 31 #include "hw/pci/pci.h" 32 33 #undef VERBOSE 34 #define HW_RECT_ACCEL 35 #define HW_FILL_ACCEL 36 #define HW_MOUSE_ACCEL 37 38 #include "vga_int.h" 39 40 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 41 42 struct vmsvga_state_s { 43 VGACommonState vga; 44 45 int invalidated; 46 int enable; 47 int config; 48 struct { 49 int id; 50 int x; 51 int y; 52 int on; 53 } cursor; 54 55 int index; 56 int scratch_size; 57 uint32_t *scratch; 58 int new_width; 59 int new_height; 60 int new_depth; 61 uint32_t guest; 62 uint32_t svgaid; 63 int syncing; 64 65 MemoryRegion fifo_ram; 66 uint8_t *fifo_ptr; 67 unsigned int fifo_size; 68 69 union { 70 uint32_t *fifo; 71 struct QEMU_PACKED { 72 uint32_t min; 73 uint32_t max; 74 uint32_t next_cmd; 75 uint32_t stop; 76 /* Add registers here when adding capabilities. */ 77 uint32_t fifo[0]; 78 } *cmd; 79 }; 80 81 #define REDRAW_FIFO_LEN 512 82 struct vmsvga_rect_s { 83 int x, y, w, h; 84 } redraw_fifo[REDRAW_FIFO_LEN]; 85 int redraw_fifo_first, redraw_fifo_last; 86 }; 87 88 #define TYPE_VMWARE_SVGA "vmware-svga" 89 90 #define VMWARE_SVGA(obj) \ 91 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) 92 93 struct pci_vmsvga_state_s { 94 /*< private >*/ 95 PCIDevice parent_obj; 96 /*< public >*/ 97 98 struct vmsvga_state_s chip; 99 MemoryRegion io_bar; 100 }; 101 102 #define SVGA_MAGIC 0x900000UL 103 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 104 #define SVGA_ID_0 SVGA_MAKE_ID(0) 105 #define SVGA_ID_1 SVGA_MAKE_ID(1) 106 #define SVGA_ID_2 SVGA_MAKE_ID(2) 107 108 #define SVGA_LEGACY_BASE_PORT 0x4560 109 #define SVGA_INDEX_PORT 0x0 110 #define SVGA_VALUE_PORT 0x1 111 #define SVGA_BIOS_PORT 0x2 112 113 #define SVGA_VERSION_2 114 115 #ifdef SVGA_VERSION_2 116 # define SVGA_ID SVGA_ID_2 117 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 118 # define SVGA_IO_MUL 1 119 # define SVGA_FIFO_SIZE 0x10000 120 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 121 #else 122 # define SVGA_ID SVGA_ID_1 123 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 124 # define SVGA_IO_MUL 4 125 # define SVGA_FIFO_SIZE 0x10000 126 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 127 #endif 128 129 enum { 130 /* ID 0, 1 and 2 registers */ 131 SVGA_REG_ID = 0, 132 SVGA_REG_ENABLE = 1, 133 SVGA_REG_WIDTH = 2, 134 SVGA_REG_HEIGHT = 3, 135 SVGA_REG_MAX_WIDTH = 4, 136 SVGA_REG_MAX_HEIGHT = 5, 137 SVGA_REG_DEPTH = 6, 138 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 139 SVGA_REG_PSEUDOCOLOR = 8, 140 SVGA_REG_RED_MASK = 9, 141 SVGA_REG_GREEN_MASK = 10, 142 SVGA_REG_BLUE_MASK = 11, 143 SVGA_REG_BYTES_PER_LINE = 12, 144 SVGA_REG_FB_START = 13, 145 SVGA_REG_FB_OFFSET = 14, 146 SVGA_REG_VRAM_SIZE = 15, 147 SVGA_REG_FB_SIZE = 16, 148 149 /* ID 1 and 2 registers */ 150 SVGA_REG_CAPABILITIES = 17, 151 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 152 SVGA_REG_MEM_SIZE = 19, 153 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 154 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 155 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 156 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 157 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 158 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 159 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 160 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 161 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 162 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 163 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 164 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 165 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 166 167 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 168 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 169 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 170 }; 171 172 #define SVGA_CAP_NONE 0 173 #define SVGA_CAP_RECT_FILL (1 << 0) 174 #define SVGA_CAP_RECT_COPY (1 << 1) 175 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 176 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 177 #define SVGA_CAP_RASTER_OP (1 << 4) 178 #define SVGA_CAP_CURSOR (1 << 5) 179 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 180 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 181 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 182 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 183 #define SVGA_CAP_GLYPH (1 << 10) 184 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 185 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 186 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 187 #define SVGA_CAP_3D (1 << 14) 188 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 189 #define SVGA_CAP_MULTIMON (1 << 16) 190 #define SVGA_CAP_PITCHLOCK (1 << 17) 191 192 /* 193 * FIFO offsets (seen as an array of 32-bit words) 194 */ 195 enum { 196 /* 197 * The original defined FIFO offsets 198 */ 199 SVGA_FIFO_MIN = 0, 200 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 201 SVGA_FIFO_NEXT_CMD, 202 SVGA_FIFO_STOP, 203 204 /* 205 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 206 */ 207 SVGA_FIFO_CAPABILITIES = 4, 208 SVGA_FIFO_FLAGS, 209 SVGA_FIFO_FENCE, 210 SVGA_FIFO_3D_HWVERSION, 211 SVGA_FIFO_PITCHLOCK, 212 }; 213 214 #define SVGA_FIFO_CAP_NONE 0 215 #define SVGA_FIFO_CAP_FENCE (1 << 0) 216 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 217 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 218 219 #define SVGA_FIFO_FLAG_NONE 0 220 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 221 222 /* These values can probably be changed arbitrarily. */ 223 #define SVGA_SCRATCH_SIZE 0x8000 224 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) 225 #define SVGA_MAX_HEIGHT 1770 226 227 #ifdef VERBOSE 228 # define GUEST_OS_BASE 0x5001 229 static const char *vmsvga_guest_id[] = { 230 [0x00] = "Dos", 231 [0x01] = "Windows 3.1", 232 [0x02] = "Windows 95", 233 [0x03] = "Windows 98", 234 [0x04] = "Windows ME", 235 [0x05] = "Windows NT", 236 [0x06] = "Windows 2000", 237 [0x07] = "Linux", 238 [0x08] = "OS/2", 239 [0x09] = "an unknown OS", 240 [0x0a] = "BSD", 241 [0x0b] = "Whistler", 242 [0x0c] = "an unknown OS", 243 [0x0d] = "an unknown OS", 244 [0x0e] = "an unknown OS", 245 [0x0f] = "an unknown OS", 246 [0x10] = "an unknown OS", 247 [0x11] = "an unknown OS", 248 [0x12] = "an unknown OS", 249 [0x13] = "an unknown OS", 250 [0x14] = "an unknown OS", 251 [0x15] = "Windows 2003", 252 }; 253 #endif 254 255 enum { 256 SVGA_CMD_INVALID_CMD = 0, 257 SVGA_CMD_UPDATE = 1, 258 SVGA_CMD_RECT_FILL = 2, 259 SVGA_CMD_RECT_COPY = 3, 260 SVGA_CMD_DEFINE_BITMAP = 4, 261 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 262 SVGA_CMD_DEFINE_PIXMAP = 6, 263 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 264 SVGA_CMD_RECT_BITMAP_FILL = 8, 265 SVGA_CMD_RECT_PIXMAP_FILL = 9, 266 SVGA_CMD_RECT_BITMAP_COPY = 10, 267 SVGA_CMD_RECT_PIXMAP_COPY = 11, 268 SVGA_CMD_FREE_OBJECT = 12, 269 SVGA_CMD_RECT_ROP_FILL = 13, 270 SVGA_CMD_RECT_ROP_COPY = 14, 271 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 272 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 273 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 274 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 275 SVGA_CMD_DEFINE_CURSOR = 19, 276 SVGA_CMD_DISPLAY_CURSOR = 20, 277 SVGA_CMD_MOVE_CURSOR = 21, 278 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 279 SVGA_CMD_DRAW_GLYPH = 23, 280 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 281 SVGA_CMD_UPDATE_VERBOSE = 25, 282 SVGA_CMD_SURFACE_FILL = 26, 283 SVGA_CMD_SURFACE_COPY = 27, 284 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 285 SVGA_CMD_FRONT_ROP_FILL = 29, 286 SVGA_CMD_FENCE = 30, 287 }; 288 289 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 290 enum { 291 SVGA_CURSOR_ON_HIDE = 0, 292 SVGA_CURSOR_ON_SHOW = 1, 293 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 294 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 295 }; 296 297 static inline bool vmsvga_verify_rect(DisplaySurface *surface, 298 const char *name, 299 int x, int y, int w, int h) 300 { 301 if (x < 0) { 302 fprintf(stderr, "%s: x was < 0 (%d)\n", name, x); 303 return false; 304 } 305 if (x > SVGA_MAX_WIDTH) { 306 fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x); 307 return false; 308 } 309 if (w < 0) { 310 fprintf(stderr, "%s: w was < 0 (%d)\n", name, w); 311 return false; 312 } 313 if (w > SVGA_MAX_WIDTH) { 314 fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w); 315 return false; 316 } 317 if (x + w > surface_width(surface)) { 318 fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n", 319 name, surface_width(surface), x, w); 320 return false; 321 } 322 323 if (y < 0) { 324 fprintf(stderr, "%s: y was < 0 (%d)\n", name, y); 325 return false; 326 } 327 if (y > SVGA_MAX_HEIGHT) { 328 fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y); 329 return false; 330 } 331 if (h < 0) { 332 fprintf(stderr, "%s: h was < 0 (%d)\n", name, h); 333 return false; 334 } 335 if (h > SVGA_MAX_HEIGHT) { 336 fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h); 337 return false; 338 } 339 if (y + h > surface_height(surface)) { 340 fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n", 341 name, surface_height(surface), y, h); 342 return false; 343 } 344 345 return true; 346 } 347 348 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 349 int x, int y, int w, int h) 350 { 351 DisplaySurface *surface = qemu_console_surface(s->vga.con); 352 int line; 353 int bypl; 354 int width; 355 int start; 356 uint8_t *src; 357 uint8_t *dst; 358 359 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { 360 /* go for a fullscreen update as fallback */ 361 x = 0; 362 y = 0; 363 w = surface_width(surface); 364 h = surface_height(surface); 365 } 366 367 bypl = surface_stride(surface); 368 width = surface_bytes_per_pixel(surface) * w; 369 start = surface_bytes_per_pixel(surface) * x + bypl * y; 370 src = s->vga.vram_ptr + start; 371 dst = surface_data(surface) + start; 372 373 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 374 memcpy(dst, src, width); 375 } 376 dpy_gfx_update(s->vga.con, x, y, w, h); 377 } 378 379 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 380 int x, int y, int w, int h) 381 { 382 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 383 384 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 385 rect->x = x; 386 rect->y = y; 387 rect->w = w; 388 rect->h = h; 389 } 390 391 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 392 { 393 struct vmsvga_rect_s *rect; 394 395 if (s->invalidated) { 396 s->redraw_fifo_first = s->redraw_fifo_last; 397 return; 398 } 399 /* Overlapping region updates can be optimised out here - if someone 400 * knows a smart algorithm to do that, please share. */ 401 while (s->redraw_fifo_first != s->redraw_fifo_last) { 402 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 403 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 404 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 405 } 406 } 407 408 #ifdef HW_RECT_ACCEL 409 static inline int vmsvga_copy_rect(struct vmsvga_state_s *s, 410 int x0, int y0, int x1, int y1, int w, int h) 411 { 412 DisplaySurface *surface = qemu_console_surface(s->vga.con); 413 uint8_t *vram = s->vga.vram_ptr; 414 int bypl = surface_stride(surface); 415 int bypp = surface_bytes_per_pixel(surface); 416 int width = bypp * w; 417 int line = h; 418 uint8_t *ptr[2]; 419 420 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) { 421 return -1; 422 } 423 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) { 424 return -1; 425 } 426 427 if (y1 > y0) { 428 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 429 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 430 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 431 memmove(ptr[1], ptr[0], width); 432 } 433 } else { 434 ptr[0] = vram + bypp * x0 + bypl * y0; 435 ptr[1] = vram + bypp * x1 + bypl * y1; 436 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 437 memmove(ptr[1], ptr[0], width); 438 } 439 } 440 441 vmsvga_update_rect_delayed(s, x1, y1, w, h); 442 return 0; 443 } 444 #endif 445 446 #ifdef HW_FILL_ACCEL 447 static inline int vmsvga_fill_rect(struct vmsvga_state_s *s, 448 uint32_t c, int x, int y, int w, int h) 449 { 450 DisplaySurface *surface = qemu_console_surface(s->vga.con); 451 int bypl = surface_stride(surface); 452 int width = surface_bytes_per_pixel(surface) * w; 453 int line = h; 454 int column; 455 uint8_t *fst; 456 uint8_t *dst; 457 uint8_t *src; 458 uint8_t col[4]; 459 460 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { 461 return -1; 462 } 463 464 col[0] = c; 465 col[1] = c >> 8; 466 col[2] = c >> 16; 467 col[3] = c >> 24; 468 469 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 470 471 if (line--) { 472 dst = fst; 473 src = col; 474 for (column = width; column > 0; column--) { 475 *(dst++) = *(src++); 476 if (src - col == surface_bytes_per_pixel(surface)) { 477 src = col; 478 } 479 } 480 dst = fst; 481 for (; line > 0; line--) { 482 dst += bypl; 483 memcpy(dst, fst, width); 484 } 485 } 486 487 vmsvga_update_rect_delayed(s, x, y, w, h); 488 return 0; 489 } 490 #endif 491 492 struct vmsvga_cursor_definition_s { 493 uint32_t width; 494 uint32_t height; 495 int id; 496 uint32_t bpp; 497 int hot_x; 498 int hot_y; 499 uint32_t mask[1024]; 500 uint32_t image[4096]; 501 }; 502 503 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 504 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 505 506 #ifdef HW_MOUSE_ACCEL 507 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 508 struct vmsvga_cursor_definition_s *c) 509 { 510 QEMUCursor *qc; 511 int i, pixels; 512 513 qc = cursor_alloc(c->width, c->height); 514 qc->hot_x = c->hot_x; 515 qc->hot_y = c->hot_y; 516 switch (c->bpp) { 517 case 1: 518 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 519 1, (void *)c->mask); 520 #ifdef DEBUG 521 cursor_print_ascii_art(qc, "vmware/mono"); 522 #endif 523 break; 524 case 32: 525 /* fill alpha channel from mask, set color to zero */ 526 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 527 1, (void *)c->mask); 528 /* add in rgb values */ 529 pixels = c->width * c->height; 530 for (i = 0; i < pixels; i++) { 531 qc->data[i] |= c->image[i] & 0xffffff; 532 } 533 #ifdef DEBUG 534 cursor_print_ascii_art(qc, "vmware/32bit"); 535 #endif 536 break; 537 default: 538 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 539 __func__, c->bpp); 540 cursor_put(qc); 541 qc = cursor_builtin_left_ptr(); 542 } 543 544 dpy_cursor_define(s->vga.con, qc); 545 cursor_put(qc); 546 } 547 #endif 548 549 #define CMD(f) le32_to_cpu(s->cmd->f) 550 551 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 552 { 553 int num; 554 555 if (!s->config || !s->enable) { 556 return 0; 557 } 558 num = CMD(next_cmd) - CMD(stop); 559 if (num < 0) { 560 num += CMD(max) - CMD(min); 561 } 562 return num >> 2; 563 } 564 565 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 566 { 567 uint32_t cmd = s->fifo[CMD(stop) >> 2]; 568 569 s->cmd->stop = cpu_to_le32(CMD(stop) + 4); 570 if (CMD(stop) >= CMD(max)) { 571 s->cmd->stop = s->cmd->min; 572 } 573 return cmd; 574 } 575 576 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 577 { 578 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 579 } 580 581 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 582 { 583 uint32_t cmd, colour; 584 int args, len; 585 int x, y, dx, dy, width, height; 586 struct vmsvga_cursor_definition_s cursor; 587 uint32_t cmd_start; 588 589 len = vmsvga_fifo_length(s); 590 while (len > 0) { 591 /* May need to go back to the start of the command if incomplete */ 592 cmd_start = s->cmd->stop; 593 594 switch (cmd = vmsvga_fifo_read(s)) { 595 case SVGA_CMD_UPDATE: 596 case SVGA_CMD_UPDATE_VERBOSE: 597 len -= 5; 598 if (len < 0) { 599 goto rewind; 600 } 601 602 x = vmsvga_fifo_read(s); 603 y = vmsvga_fifo_read(s); 604 width = vmsvga_fifo_read(s); 605 height = vmsvga_fifo_read(s); 606 vmsvga_update_rect_delayed(s, x, y, width, height); 607 break; 608 609 case SVGA_CMD_RECT_FILL: 610 len -= 6; 611 if (len < 0) { 612 goto rewind; 613 } 614 615 colour = vmsvga_fifo_read(s); 616 x = vmsvga_fifo_read(s); 617 y = vmsvga_fifo_read(s); 618 width = vmsvga_fifo_read(s); 619 height = vmsvga_fifo_read(s); 620 #ifdef HW_FILL_ACCEL 621 if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) { 622 break; 623 } 624 #endif 625 args = 0; 626 goto badcmd; 627 628 case SVGA_CMD_RECT_COPY: 629 len -= 7; 630 if (len < 0) { 631 goto rewind; 632 } 633 634 x = vmsvga_fifo_read(s); 635 y = vmsvga_fifo_read(s); 636 dx = vmsvga_fifo_read(s); 637 dy = vmsvga_fifo_read(s); 638 width = vmsvga_fifo_read(s); 639 height = vmsvga_fifo_read(s); 640 #ifdef HW_RECT_ACCEL 641 if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) { 642 break; 643 } 644 #endif 645 args = 0; 646 goto badcmd; 647 648 case SVGA_CMD_DEFINE_CURSOR: 649 len -= 8; 650 if (len < 0) { 651 goto rewind; 652 } 653 654 cursor.id = vmsvga_fifo_read(s); 655 cursor.hot_x = vmsvga_fifo_read(s); 656 cursor.hot_y = vmsvga_fifo_read(s); 657 cursor.width = x = vmsvga_fifo_read(s); 658 cursor.height = y = vmsvga_fifo_read(s); 659 vmsvga_fifo_read(s); 660 cursor.bpp = vmsvga_fifo_read(s); 661 662 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 663 if (cursor.width > 256 || 664 cursor.height > 256 || 665 cursor.bpp > 32 || 666 SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || 667 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { 668 goto badcmd; 669 } 670 671 len -= args; 672 if (len < 0) { 673 goto rewind; 674 } 675 676 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 677 cursor.mask[args] = vmsvga_fifo_read_raw(s); 678 } 679 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 680 cursor.image[args] = vmsvga_fifo_read_raw(s); 681 } 682 #ifdef HW_MOUSE_ACCEL 683 vmsvga_cursor_define(s, &cursor); 684 break; 685 #else 686 args = 0; 687 goto badcmd; 688 #endif 689 690 /* 691 * Other commands that we at least know the number of arguments 692 * for so we can avoid FIFO desync if driver uses them illegally. 693 */ 694 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 695 len -= 6; 696 if (len < 0) { 697 goto rewind; 698 } 699 vmsvga_fifo_read(s); 700 vmsvga_fifo_read(s); 701 vmsvga_fifo_read(s); 702 x = vmsvga_fifo_read(s); 703 y = vmsvga_fifo_read(s); 704 args = x * y; 705 goto badcmd; 706 case SVGA_CMD_RECT_ROP_FILL: 707 args = 6; 708 goto badcmd; 709 case SVGA_CMD_RECT_ROP_COPY: 710 args = 7; 711 goto badcmd; 712 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 713 len -= 4; 714 if (len < 0) { 715 goto rewind; 716 } 717 vmsvga_fifo_read(s); 718 vmsvga_fifo_read(s); 719 args = 7 + (vmsvga_fifo_read(s) >> 2); 720 goto badcmd; 721 case SVGA_CMD_SURFACE_ALPHA_BLEND: 722 args = 12; 723 goto badcmd; 724 725 /* 726 * Other commands that are not listed as depending on any 727 * CAPABILITIES bits, but are not described in the README either. 728 */ 729 case SVGA_CMD_SURFACE_FILL: 730 case SVGA_CMD_SURFACE_COPY: 731 case SVGA_CMD_FRONT_ROP_FILL: 732 case SVGA_CMD_FENCE: 733 case SVGA_CMD_INVALID_CMD: 734 break; /* Nop */ 735 736 default: 737 args = 0; 738 badcmd: 739 len -= args; 740 if (len < 0) { 741 goto rewind; 742 } 743 while (args--) { 744 vmsvga_fifo_read(s); 745 } 746 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 747 __func__, cmd); 748 break; 749 750 rewind: 751 s->cmd->stop = cmd_start; 752 break; 753 } 754 } 755 756 s->syncing = 0; 757 } 758 759 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 760 { 761 struct vmsvga_state_s *s = opaque; 762 763 return s->index; 764 } 765 766 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 767 { 768 struct vmsvga_state_s *s = opaque; 769 770 s->index = index; 771 } 772 773 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 774 { 775 uint32_t caps; 776 struct vmsvga_state_s *s = opaque; 777 DisplaySurface *surface = qemu_console_surface(s->vga.con); 778 PixelFormat pf; 779 uint32_t ret; 780 781 switch (s->index) { 782 case SVGA_REG_ID: 783 ret = s->svgaid; 784 break; 785 786 case SVGA_REG_ENABLE: 787 ret = s->enable; 788 break; 789 790 case SVGA_REG_WIDTH: 791 ret = s->new_width ? s->new_width : surface_width(surface); 792 break; 793 794 case SVGA_REG_HEIGHT: 795 ret = s->new_height ? s->new_height : surface_height(surface); 796 break; 797 798 case SVGA_REG_MAX_WIDTH: 799 ret = SVGA_MAX_WIDTH; 800 break; 801 802 case SVGA_REG_MAX_HEIGHT: 803 ret = SVGA_MAX_HEIGHT; 804 break; 805 806 case SVGA_REG_DEPTH: 807 ret = (s->new_depth == 32) ? 24 : s->new_depth; 808 break; 809 810 case SVGA_REG_BITS_PER_PIXEL: 811 case SVGA_REG_HOST_BITS_PER_PIXEL: 812 ret = s->new_depth; 813 break; 814 815 case SVGA_REG_PSEUDOCOLOR: 816 ret = 0x0; 817 break; 818 819 case SVGA_REG_RED_MASK: 820 pf = qemu_default_pixelformat(s->new_depth); 821 ret = pf.rmask; 822 break; 823 824 case SVGA_REG_GREEN_MASK: 825 pf = qemu_default_pixelformat(s->new_depth); 826 ret = pf.gmask; 827 break; 828 829 case SVGA_REG_BLUE_MASK: 830 pf = qemu_default_pixelformat(s->new_depth); 831 ret = pf.bmask; 832 break; 833 834 case SVGA_REG_BYTES_PER_LINE: 835 if (s->new_width) { 836 ret = (s->new_depth * s->new_width) / 8; 837 } else { 838 ret = surface_stride(surface); 839 } 840 break; 841 842 case SVGA_REG_FB_START: { 843 struct pci_vmsvga_state_s *pci_vmsvga 844 = container_of(s, struct pci_vmsvga_state_s, chip); 845 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1); 846 break; 847 } 848 849 case SVGA_REG_FB_OFFSET: 850 ret = 0x0; 851 break; 852 853 case SVGA_REG_VRAM_SIZE: 854 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 855 break; 856 857 case SVGA_REG_FB_SIZE: 858 ret = s->vga.vram_size; 859 break; 860 861 case SVGA_REG_CAPABILITIES: 862 caps = SVGA_CAP_NONE; 863 #ifdef HW_RECT_ACCEL 864 caps |= SVGA_CAP_RECT_COPY; 865 #endif 866 #ifdef HW_FILL_ACCEL 867 caps |= SVGA_CAP_RECT_FILL; 868 #endif 869 #ifdef HW_MOUSE_ACCEL 870 if (dpy_cursor_define_supported(s->vga.con)) { 871 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 872 SVGA_CAP_CURSOR_BYPASS; 873 } 874 #endif 875 ret = caps; 876 break; 877 878 case SVGA_REG_MEM_START: { 879 struct pci_vmsvga_state_s *pci_vmsvga 880 = container_of(s, struct pci_vmsvga_state_s, chip); 881 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2); 882 break; 883 } 884 885 case SVGA_REG_MEM_SIZE: 886 ret = s->fifo_size; 887 break; 888 889 case SVGA_REG_CONFIG_DONE: 890 ret = s->config; 891 break; 892 893 case SVGA_REG_SYNC: 894 case SVGA_REG_BUSY: 895 ret = s->syncing; 896 break; 897 898 case SVGA_REG_GUEST_ID: 899 ret = s->guest; 900 break; 901 902 case SVGA_REG_CURSOR_ID: 903 ret = s->cursor.id; 904 break; 905 906 case SVGA_REG_CURSOR_X: 907 ret = s->cursor.x; 908 break; 909 910 case SVGA_REG_CURSOR_Y: 911 ret = s->cursor.y; 912 break; 913 914 case SVGA_REG_CURSOR_ON: 915 ret = s->cursor.on; 916 break; 917 918 case SVGA_REG_SCRATCH_SIZE: 919 ret = s->scratch_size; 920 break; 921 922 case SVGA_REG_MEM_REGS: 923 case SVGA_REG_NUM_DISPLAYS: 924 case SVGA_REG_PITCHLOCK: 925 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 926 ret = 0; 927 break; 928 929 default: 930 if (s->index >= SVGA_SCRATCH_BASE && 931 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 932 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 933 break; 934 } 935 printf("%s: Bad register %02x\n", __func__, s->index); 936 ret = 0; 937 break; 938 } 939 940 if (s->index >= SVGA_SCRATCH_BASE) { 941 trace_vmware_scratch_read(s->index, ret); 942 } else if (s->index >= SVGA_PALETTE_BASE) { 943 trace_vmware_palette_read(s->index, ret); 944 } else { 945 trace_vmware_value_read(s->index, ret); 946 } 947 return ret; 948 } 949 950 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 951 { 952 struct vmsvga_state_s *s = opaque; 953 954 if (s->index >= SVGA_SCRATCH_BASE) { 955 trace_vmware_scratch_write(s->index, value); 956 } else if (s->index >= SVGA_PALETTE_BASE) { 957 trace_vmware_palette_write(s->index, value); 958 } else { 959 trace_vmware_value_write(s->index, value); 960 } 961 switch (s->index) { 962 case SVGA_REG_ID: 963 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 964 s->svgaid = value; 965 } 966 break; 967 968 case SVGA_REG_ENABLE: 969 s->enable = !!value; 970 s->invalidated = 1; 971 s->vga.hw_ops->invalidate(&s->vga); 972 if (s->enable && s->config) { 973 vga_dirty_log_stop(&s->vga); 974 } else { 975 vga_dirty_log_start(&s->vga); 976 } 977 break; 978 979 case SVGA_REG_WIDTH: 980 if (value <= SVGA_MAX_WIDTH) { 981 s->new_width = value; 982 s->invalidated = 1; 983 } else { 984 printf("%s: Bad width: %i\n", __func__, value); 985 } 986 break; 987 988 case SVGA_REG_HEIGHT: 989 if (value <= SVGA_MAX_HEIGHT) { 990 s->new_height = value; 991 s->invalidated = 1; 992 } else { 993 printf("%s: Bad height: %i\n", __func__, value); 994 } 995 break; 996 997 case SVGA_REG_BITS_PER_PIXEL: 998 if (value != 32) { 999 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 1000 s->config = 0; 1001 s->invalidated = 1; 1002 } 1003 break; 1004 1005 case SVGA_REG_CONFIG_DONE: 1006 if (value) { 1007 s->fifo = (uint32_t *) s->fifo_ptr; 1008 /* Check range and alignment. */ 1009 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { 1010 break; 1011 } 1012 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { 1013 break; 1014 } 1015 if (CMD(max) > SVGA_FIFO_SIZE) { 1016 break; 1017 } 1018 if (CMD(max) < CMD(min) + 10 * 1024) { 1019 break; 1020 } 1021 vga_dirty_log_stop(&s->vga); 1022 } 1023 s->config = !!value; 1024 break; 1025 1026 case SVGA_REG_SYNC: 1027 s->syncing = 1; 1028 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 1029 break; 1030 1031 case SVGA_REG_GUEST_ID: 1032 s->guest = value; 1033 #ifdef VERBOSE 1034 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 1035 ARRAY_SIZE(vmsvga_guest_id)) { 1036 printf("%s: guest runs %s.\n", __func__, 1037 vmsvga_guest_id[value - GUEST_OS_BASE]); 1038 } 1039 #endif 1040 break; 1041 1042 case SVGA_REG_CURSOR_ID: 1043 s->cursor.id = value; 1044 break; 1045 1046 case SVGA_REG_CURSOR_X: 1047 s->cursor.x = value; 1048 break; 1049 1050 case SVGA_REG_CURSOR_Y: 1051 s->cursor.y = value; 1052 break; 1053 1054 case SVGA_REG_CURSOR_ON: 1055 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 1056 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 1057 #ifdef HW_MOUSE_ACCEL 1058 if (value <= SVGA_CURSOR_ON_SHOW) { 1059 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1060 } 1061 #endif 1062 break; 1063 1064 case SVGA_REG_DEPTH: 1065 case SVGA_REG_MEM_REGS: 1066 case SVGA_REG_NUM_DISPLAYS: 1067 case SVGA_REG_PITCHLOCK: 1068 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1069 break; 1070 1071 default: 1072 if (s->index >= SVGA_SCRATCH_BASE && 1073 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1074 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1075 break; 1076 } 1077 printf("%s: Bad register %02x\n", __func__, s->index); 1078 } 1079 } 1080 1081 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1082 { 1083 printf("%s: what are we supposed to return?\n", __func__); 1084 return 0xcafe; 1085 } 1086 1087 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1088 { 1089 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1090 } 1091 1092 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1093 { 1094 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1095 1096 if (s->new_width != surface_width(surface) || 1097 s->new_height != surface_height(surface) || 1098 s->new_depth != surface_bits_per_pixel(surface)) { 1099 int stride = (s->new_depth * s->new_width) / 8; 1100 pixman_format_code_t format = 1101 qemu_default_pixman_format(s->new_depth, true); 1102 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); 1103 surface = qemu_create_displaysurface_from(s->new_width, s->new_height, 1104 format, stride, 1105 s->vga.vram_ptr); 1106 dpy_gfx_replace_surface(s->vga.con, surface); 1107 s->invalidated = 1; 1108 } 1109 } 1110 1111 static void vmsvga_update_display(void *opaque) 1112 { 1113 struct vmsvga_state_s *s = opaque; 1114 DisplaySurface *surface; 1115 bool dirty = false; 1116 1117 if (!s->enable) { 1118 s->vga.hw_ops->gfx_update(&s->vga); 1119 return; 1120 } 1121 1122 vmsvga_check_size(s); 1123 surface = qemu_console_surface(s->vga.con); 1124 1125 vmsvga_fifo_run(s); 1126 vmsvga_update_rect_flush(s); 1127 1128 /* 1129 * Is it more efficient to look at vram VGA-dirty bits or wait 1130 * for the driver to issue SVGA_CMD_UPDATE? 1131 */ 1132 if (memory_region_is_logging(&s->vga.vram, DIRTY_MEMORY_VGA)) { 1133 vga_sync_dirty_bitmap(&s->vga); 1134 dirty = memory_region_get_dirty(&s->vga.vram, 0, 1135 surface_stride(surface) * surface_height(surface), 1136 DIRTY_MEMORY_VGA); 1137 } 1138 if (s->invalidated || dirty) { 1139 s->invalidated = 0; 1140 dpy_gfx_update(s->vga.con, 0, 0, 1141 surface_width(surface), surface_height(surface)); 1142 } 1143 if (dirty) { 1144 memory_region_reset_dirty(&s->vga.vram, 0, 1145 surface_stride(surface) * surface_height(surface), 1146 DIRTY_MEMORY_VGA); 1147 } 1148 } 1149 1150 static void vmsvga_reset(DeviceState *dev) 1151 { 1152 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); 1153 struct vmsvga_state_s *s = &pci->chip; 1154 1155 s->index = 0; 1156 s->enable = 0; 1157 s->config = 0; 1158 s->svgaid = SVGA_ID; 1159 s->cursor.on = 0; 1160 s->redraw_fifo_first = 0; 1161 s->redraw_fifo_last = 0; 1162 s->syncing = 0; 1163 1164 vga_dirty_log_start(&s->vga); 1165 } 1166 1167 static void vmsvga_invalidate_display(void *opaque) 1168 { 1169 struct vmsvga_state_s *s = opaque; 1170 if (!s->enable) { 1171 s->vga.hw_ops->invalidate(&s->vga); 1172 return; 1173 } 1174 1175 s->invalidated = 1; 1176 } 1177 1178 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1179 { 1180 struct vmsvga_state_s *s = opaque; 1181 1182 if (s->vga.hw_ops->text_update) { 1183 s->vga.hw_ops->text_update(&s->vga, chardata); 1184 } 1185 } 1186 1187 static int vmsvga_post_load(void *opaque, int version_id) 1188 { 1189 struct vmsvga_state_s *s = opaque; 1190 1191 s->invalidated = 1; 1192 if (s->config) { 1193 s->fifo = (uint32_t *) s->fifo_ptr; 1194 } 1195 return 0; 1196 } 1197 1198 static const VMStateDescription vmstate_vmware_vga_internal = { 1199 .name = "vmware_vga_internal", 1200 .version_id = 0, 1201 .minimum_version_id = 0, 1202 .post_load = vmsvga_post_load, 1203 .fields = (VMStateField[]) { 1204 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), 1205 VMSTATE_INT32(enable, struct vmsvga_state_s), 1206 VMSTATE_INT32(config, struct vmsvga_state_s), 1207 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1208 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1209 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1210 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1211 VMSTATE_INT32(index, struct vmsvga_state_s), 1212 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1213 scratch_size, 0, vmstate_info_uint32, uint32_t), 1214 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1215 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1216 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1217 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1218 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1219 VMSTATE_UNUSED(4), /* was fb_size */ 1220 VMSTATE_END_OF_LIST() 1221 } 1222 }; 1223 1224 static const VMStateDescription vmstate_vmware_vga = { 1225 .name = "vmware_vga", 1226 .version_id = 0, 1227 .minimum_version_id = 0, 1228 .fields = (VMStateField[]) { 1229 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s), 1230 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1231 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1232 VMSTATE_END_OF_LIST() 1233 } 1234 }; 1235 1236 static const GraphicHwOps vmsvga_ops = { 1237 .invalidate = vmsvga_invalidate_display, 1238 .gfx_update = vmsvga_update_display, 1239 .text_update = vmsvga_text_update, 1240 }; 1241 1242 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, 1243 MemoryRegion *address_space, MemoryRegion *io) 1244 { 1245 s->scratch_size = SVGA_SCRATCH_SIZE; 1246 s->scratch = g_malloc(s->scratch_size * 4); 1247 1248 s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s); 1249 1250 s->fifo_size = SVGA_FIFO_SIZE; 1251 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, 1252 &error_fatal); 1253 vmstate_register_ram_global(&s->fifo_ram); 1254 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1255 1256 vga_common_init(&s->vga, OBJECT(dev), true); 1257 vga_init(&s->vga, OBJECT(dev), address_space, io, true); 1258 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1259 s->new_depth = 32; 1260 } 1261 1262 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1263 { 1264 struct vmsvga_state_s *s = opaque; 1265 1266 switch (addr) { 1267 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1268 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1269 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1270 default: return -1u; 1271 } 1272 } 1273 1274 static void vmsvga_io_write(void *opaque, hwaddr addr, 1275 uint64_t data, unsigned size) 1276 { 1277 struct vmsvga_state_s *s = opaque; 1278 1279 switch (addr) { 1280 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1281 vmsvga_index_write(s, addr, data); 1282 break; 1283 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1284 vmsvga_value_write(s, addr, data); 1285 break; 1286 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1287 vmsvga_bios_write(s, addr, data); 1288 break; 1289 } 1290 } 1291 1292 static const MemoryRegionOps vmsvga_io_ops = { 1293 .read = vmsvga_io_read, 1294 .write = vmsvga_io_write, 1295 .endianness = DEVICE_LITTLE_ENDIAN, 1296 .valid = { 1297 .min_access_size = 4, 1298 .max_access_size = 4, 1299 .unaligned = true, 1300 }, 1301 .impl = { 1302 .unaligned = true, 1303 }, 1304 }; 1305 1306 static void pci_vmsvga_realize(PCIDevice *dev, Error **errp) 1307 { 1308 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); 1309 1310 dev->config[PCI_CACHE_LINE_SIZE] = 0x08; 1311 dev->config[PCI_LATENCY_TIMER] = 0x40; 1312 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1313 1314 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, 1315 "vmsvga-io", 0x10); 1316 memory_region_set_flush_coalesced(&s->io_bar); 1317 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1318 1319 vmsvga_init(DEVICE(dev), &s->chip, 1320 pci_address_space(dev), pci_address_space_io(dev)); 1321 1322 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1323 &s->chip.vga.vram); 1324 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1325 &s->chip.fifo_ram); 1326 1327 if (!dev->rom_bar) { 1328 /* compatibility with pc-0.13 and older */ 1329 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); 1330 } 1331 } 1332 1333 static Property vga_vmware_properties[] = { 1334 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1335 chip.vga.vram_size_mb, 16), 1336 DEFINE_PROP_END_OF_LIST(), 1337 }; 1338 1339 static void vmsvga_class_init(ObjectClass *klass, void *data) 1340 { 1341 DeviceClass *dc = DEVICE_CLASS(klass); 1342 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1343 1344 k->realize = pci_vmsvga_realize; 1345 k->romfile = "vgabios-vmware.bin"; 1346 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1347 k->device_id = SVGA_PCI_DEVICE_ID; 1348 k->class_id = PCI_CLASS_DISPLAY_VGA; 1349 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1350 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1351 dc->reset = vmsvga_reset; 1352 dc->vmsd = &vmstate_vmware_vga; 1353 dc->props = vga_vmware_properties; 1354 dc->hotpluggable = false; 1355 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1356 } 1357 1358 static const TypeInfo vmsvga_info = { 1359 .name = TYPE_VMWARE_SVGA, 1360 .parent = TYPE_PCI_DEVICE, 1361 .instance_size = sizeof(struct pci_vmsvga_state_s), 1362 .class_init = vmsvga_class_init, 1363 }; 1364 1365 static void vmsvga_register_types(void) 1366 { 1367 type_register_static(&vmsvga_info); 1368 } 1369 1370 type_init(vmsvga_register_types) 1371