1 /* 2 * QEMU PCI VGA Emulator. 3 * 4 * see docs/specs/standard-vga.txt for virtual hardware specs. 5 * 6 * Copyright (c) 2003 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/pci/pci.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "vga_int.h" 32 #include "ui/pixel_ops.h" 33 #include "qemu/module.h" 34 #include "qemu/timer.h" 35 #include "hw/loader.h" 36 #include "hw/display/edid.h" 37 38 enum vga_pci_flags { 39 PCI_VGA_FLAG_ENABLE_MMIO = 1, 40 PCI_VGA_FLAG_ENABLE_QEXT = 2, 41 PCI_VGA_FLAG_ENABLE_EDID = 3, 42 }; 43 44 typedef struct PCIVGAState { 45 PCIDevice dev; 46 VGACommonState vga; 47 uint32_t flags; 48 qemu_edid_info edid_info; 49 MemoryRegion mmio; 50 MemoryRegion mrs[4]; 51 uint8_t edid[256]; 52 } PCIVGAState; 53 54 #define TYPE_PCI_VGA "pci-vga" 55 #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA) 56 57 static const VMStateDescription vmstate_vga_pci = { 58 .name = "vga", 59 .version_id = 2, 60 .minimum_version_id = 2, 61 .fields = (VMStateField[]) { 62 VMSTATE_PCI_DEVICE(dev, PCIVGAState), 63 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState), 64 VMSTATE_END_OF_LIST() 65 } 66 }; 67 68 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, 69 unsigned size) 70 { 71 VGACommonState *s = ptr; 72 uint64_t ret = 0; 73 74 switch (size) { 75 case 1: 76 ret = vga_ioport_read(s, addr + 0x3c0); 77 break; 78 case 2: 79 ret = vga_ioport_read(s, addr + 0x3c0); 80 ret |= vga_ioport_read(s, addr + 0x3c1) << 8; 81 break; 82 } 83 return ret; 84 } 85 86 static void pci_vga_ioport_write(void *ptr, hwaddr addr, 87 uint64_t val, unsigned size) 88 { 89 VGACommonState *s = ptr; 90 91 switch (size) { 92 case 1: 93 vga_ioport_write(s, addr + 0x3c0, val); 94 break; 95 case 2: 96 /* 97 * Update bytes in little endian order. Allows to update 98 * indexed registers with a single word write because the 99 * index byte is updated first. 100 */ 101 vga_ioport_write(s, addr + 0x3c0, val & 0xff); 102 vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff); 103 break; 104 } 105 } 106 107 static const MemoryRegionOps pci_vga_ioport_ops = { 108 .read = pci_vga_ioport_read, 109 .write = pci_vga_ioport_write, 110 .valid.min_access_size = 1, 111 .valid.max_access_size = 4, 112 .impl.min_access_size = 1, 113 .impl.max_access_size = 2, 114 .endianness = DEVICE_LITTLE_ENDIAN, 115 }; 116 117 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, 118 unsigned size) 119 { 120 VGACommonState *s = ptr; 121 int index = addr >> 1; 122 123 vbe_ioport_write_index(s, 0, index); 124 return vbe_ioport_read_data(s, 0); 125 } 126 127 static void pci_vga_bochs_write(void *ptr, hwaddr addr, 128 uint64_t val, unsigned size) 129 { 130 VGACommonState *s = ptr; 131 int index = addr >> 1; 132 133 vbe_ioport_write_index(s, 0, index); 134 vbe_ioport_write_data(s, 0, val); 135 } 136 137 static const MemoryRegionOps pci_vga_bochs_ops = { 138 .read = pci_vga_bochs_read, 139 .write = pci_vga_bochs_write, 140 .valid.min_access_size = 1, 141 .valid.max_access_size = 4, 142 .impl.min_access_size = 2, 143 .impl.max_access_size = 2, 144 .endianness = DEVICE_LITTLE_ENDIAN, 145 }; 146 147 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) 148 { 149 VGACommonState *s = ptr; 150 151 switch (addr) { 152 case PCI_VGA_QEXT_REG_SIZE: 153 return PCI_VGA_QEXT_SIZE; 154 case PCI_VGA_QEXT_REG_BYTEORDER: 155 return s->big_endian_fb ? 156 PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN; 157 default: 158 return 0; 159 } 160 } 161 162 static void pci_vga_qext_write(void *ptr, hwaddr addr, 163 uint64_t val, unsigned size) 164 { 165 VGACommonState *s = ptr; 166 167 switch (addr) { 168 case PCI_VGA_QEXT_REG_BYTEORDER: 169 if (val == PCI_VGA_QEXT_BIG_ENDIAN) { 170 s->big_endian_fb = true; 171 } 172 if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) { 173 s->big_endian_fb = false; 174 } 175 break; 176 } 177 } 178 179 static bool vga_get_big_endian_fb(Object *obj, Error **errp) 180 { 181 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); 182 183 return d->vga.big_endian_fb; 184 } 185 186 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp) 187 { 188 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); 189 190 d->vga.big_endian_fb = value; 191 } 192 193 static const MemoryRegionOps pci_vga_qext_ops = { 194 .read = pci_vga_qext_read, 195 .write = pci_vga_qext_write, 196 .valid.min_access_size = 4, 197 .valid.max_access_size = 4, 198 .endianness = DEVICE_LITTLE_ENDIAN, 199 }; 200 201 void pci_std_vga_mmio_region_init(VGACommonState *s, 202 Object *owner, 203 MemoryRegion *parent, 204 MemoryRegion *subs, 205 bool qext, bool edid) 206 { 207 PCIVGAState *d = container_of(s, PCIVGAState, vga); 208 209 memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s, 210 "vga ioports remapped", PCI_VGA_IOPORT_SIZE); 211 memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET, 212 &subs[0]); 213 214 memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s, 215 "bochs dispi interface", PCI_VGA_BOCHS_SIZE); 216 memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET, 217 &subs[1]); 218 219 if (qext) { 220 memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s, 221 "qemu extended regs", PCI_VGA_QEXT_SIZE); 222 memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET, 223 &subs[2]); 224 } 225 226 if (edid) { 227 qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info); 228 qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid)); 229 memory_region_add_subregion(parent, 0, &subs[3]); 230 } 231 } 232 233 static void pci_std_vga_realize(PCIDevice *dev, Error **errp) 234 { 235 PCIVGAState *d = PCI_VGA(dev); 236 VGACommonState *s = &d->vga; 237 bool qext = false; 238 bool edid = false; 239 240 /* vga + console init */ 241 vga_common_init(s, OBJECT(dev)); 242 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev), 243 true); 244 245 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 246 247 /* XXX: VGA_RAM_SIZE must be a power of two */ 248 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 249 250 /* mmio bar for vga register access */ 251 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) { 252 memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL, 253 "vga.mmio", PCI_VGA_MMIO_SIZE); 254 255 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 256 qext = true; 257 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); 258 } 259 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { 260 edid = true; 261 } 262 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, 263 qext, edid); 264 265 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 266 } 267 } 268 269 static void pci_std_vga_init(Object *obj) 270 { 271 /* Expose framebuffer byteorder via QOM */ 272 object_property_add_bool(obj, "big-endian-framebuffer", 273 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); 274 } 275 276 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) 277 { 278 PCIVGAState *d = PCI_VGA(dev); 279 VGACommonState *s = &d->vga; 280 bool qext = false; 281 bool edid = false; 282 283 /* vga + console init */ 284 vga_common_init(s, OBJECT(dev)); 285 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 286 287 /* mmio bar */ 288 memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL, 289 "vga.mmio", PCI_VGA_MMIO_SIZE); 290 291 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 292 qext = true; 293 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); 294 } 295 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { 296 edid = true; 297 } 298 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid); 299 300 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 301 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 302 } 303 304 static void pci_secondary_vga_exit(PCIDevice *dev) 305 { 306 PCIVGAState *d = PCI_VGA(dev); 307 VGACommonState *s = &d->vga; 308 309 graphic_console_close(s->con); 310 memory_region_del_subregion(&d->mmio, &d->mrs[0]); 311 memory_region_del_subregion(&d->mmio, &d->mrs[1]); 312 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 313 memory_region_del_subregion(&d->mmio, &d->mrs[2]); 314 } 315 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { 316 memory_region_del_subregion(&d->mmio, &d->mrs[3]); 317 } 318 } 319 320 static void pci_secondary_vga_init(Object *obj) 321 { 322 /* Expose framebuffer byteorder via QOM */ 323 object_property_add_bool(obj, "big-endian-framebuffer", 324 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); 325 } 326 327 static void pci_secondary_vga_reset(DeviceState *dev) 328 { 329 PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev)); 330 vga_common_reset(&d->vga); 331 } 332 333 static Property vga_pci_properties[] = { 334 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 335 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true), 336 DEFINE_PROP_BIT("qemu-extended-regs", 337 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), 338 DEFINE_PROP_BIT("edid", 339 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), 340 DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), 341 DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false), 342 DEFINE_PROP_END_OF_LIST(), 343 }; 344 345 static Property secondary_pci_properties[] = { 346 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 347 DEFINE_PROP_BIT("qemu-extended-regs", 348 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), 349 DEFINE_PROP_BIT("edid", 350 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), 351 DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), 352 DEFINE_PROP_END_OF_LIST(), 353 }; 354 355 static void vga_pci_class_init(ObjectClass *klass, void *data) 356 { 357 DeviceClass *dc = DEVICE_CLASS(klass); 358 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 359 360 k->vendor_id = PCI_VENDOR_ID_QEMU; 361 k->device_id = PCI_DEVICE_ID_QEMU_VGA; 362 dc->vmsd = &vmstate_vga_pci; 363 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 364 } 365 366 static const TypeInfo vga_pci_type_info = { 367 .name = TYPE_PCI_VGA, 368 .parent = TYPE_PCI_DEVICE, 369 .instance_size = sizeof(PCIVGAState), 370 .abstract = true, 371 .class_init = vga_pci_class_init, 372 .interfaces = (InterfaceInfo[]) { 373 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 374 { }, 375 }, 376 }; 377 378 static void vga_class_init(ObjectClass *klass, void *data) 379 { 380 DeviceClass *dc = DEVICE_CLASS(klass); 381 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 382 383 k->realize = pci_std_vga_realize; 384 k->romfile = "vgabios-stdvga.bin"; 385 k->class_id = PCI_CLASS_DISPLAY_VGA; 386 device_class_set_props(dc, vga_pci_properties); 387 dc->hotpluggable = false; 388 } 389 390 static void secondary_class_init(ObjectClass *klass, void *data) 391 { 392 DeviceClass *dc = DEVICE_CLASS(klass); 393 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 394 395 k->realize = pci_secondary_vga_realize; 396 k->exit = pci_secondary_vga_exit; 397 k->class_id = PCI_CLASS_DISPLAY_OTHER; 398 device_class_set_props(dc, secondary_pci_properties); 399 dc->reset = pci_secondary_vga_reset; 400 } 401 402 static const TypeInfo vga_info = { 403 .name = "VGA", 404 .parent = TYPE_PCI_VGA, 405 .instance_init = pci_std_vga_init, 406 .class_init = vga_class_init, 407 }; 408 409 static const TypeInfo secondary_info = { 410 .name = "secondary-vga", 411 .parent = TYPE_PCI_VGA, 412 .instance_init = pci_secondary_vga_init, 413 .class_init = secondary_class_init, 414 }; 415 416 static void vga_register_types(void) 417 { 418 type_register_static(&vga_pci_type_info); 419 type_register_static(&vga_info); 420 type_register_static(&secondary_info); 421 } 422 423 type_init(vga_register_types) 424