1 /* 2 * QEMU PCI VGA Emulator. 3 * 4 * see docs/specs/standard-vga.txt for virtual hardware specs. 5 * 6 * Copyright (c) 2003 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "hw/hw.h" 27 #include "ui/console.h" 28 #include "hw/pci/pci.h" 29 #include "vga_int.h" 30 #include "ui/pixel_ops.h" 31 #include "qemu/timer.h" 32 #include "hw/loader.h" 33 34 #define PCI_VGA_IOPORT_OFFSET 0x400 35 #define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0) 36 #define PCI_VGA_BOCHS_OFFSET 0x500 37 #define PCI_VGA_BOCHS_SIZE (0x0b * 2) 38 #define PCI_VGA_MMIO_SIZE 0x1000 39 40 enum vga_pci_flags { 41 PCI_VGA_FLAG_ENABLE_MMIO = 1, 42 }; 43 44 typedef struct PCIVGAState { 45 PCIDevice dev; 46 VGACommonState vga; 47 uint32_t flags; 48 MemoryRegion mmio; 49 MemoryRegion ioport; 50 MemoryRegion bochs; 51 } PCIVGAState; 52 53 static const VMStateDescription vmstate_vga_pci = { 54 .name = "vga", 55 .version_id = 2, 56 .minimum_version_id = 2, 57 .fields = (VMStateField[]) { 58 VMSTATE_PCI_DEVICE(dev, PCIVGAState), 59 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState), 60 VMSTATE_END_OF_LIST() 61 } 62 }; 63 64 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, 65 unsigned size) 66 { 67 PCIVGAState *d = ptr; 68 uint64_t ret = 0; 69 70 switch (size) { 71 case 1: 72 ret = vga_ioport_read(&d->vga, addr); 73 break; 74 case 2: 75 ret = vga_ioport_read(&d->vga, addr); 76 ret |= vga_ioport_read(&d->vga, addr+1) << 8; 77 break; 78 } 79 return ret; 80 } 81 82 static void pci_vga_ioport_write(void *ptr, hwaddr addr, 83 uint64_t val, unsigned size) 84 { 85 PCIVGAState *d = ptr; 86 87 switch (size) { 88 case 1: 89 vga_ioport_write(&d->vga, addr + 0x3c0, val); 90 break; 91 case 2: 92 /* 93 * Update bytes in little endian order. Allows to update 94 * indexed registers with a single word write because the 95 * index byte is updated first. 96 */ 97 vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff); 98 vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff); 99 break; 100 } 101 } 102 103 static const MemoryRegionOps pci_vga_ioport_ops = { 104 .read = pci_vga_ioport_read, 105 .write = pci_vga_ioport_write, 106 .valid.min_access_size = 1, 107 .valid.max_access_size = 4, 108 .impl.min_access_size = 1, 109 .impl.max_access_size = 2, 110 .endianness = DEVICE_LITTLE_ENDIAN, 111 }; 112 113 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, 114 unsigned size) 115 { 116 PCIVGAState *d = ptr; 117 int index = addr >> 1; 118 119 vbe_ioport_write_index(&d->vga, 0, index); 120 return vbe_ioport_read_data(&d->vga, 0); 121 } 122 123 static void pci_vga_bochs_write(void *ptr, hwaddr addr, 124 uint64_t val, unsigned size) 125 { 126 PCIVGAState *d = ptr; 127 int index = addr >> 1; 128 129 vbe_ioport_write_index(&d->vga, 0, index); 130 vbe_ioport_write_data(&d->vga, 0, val); 131 } 132 133 static const MemoryRegionOps pci_vga_bochs_ops = { 134 .read = pci_vga_bochs_read, 135 .write = pci_vga_bochs_write, 136 .valid.min_access_size = 1, 137 .valid.max_access_size = 4, 138 .impl.min_access_size = 2, 139 .impl.max_access_size = 2, 140 .endianness = DEVICE_LITTLE_ENDIAN, 141 }; 142 143 static int pci_std_vga_initfn(PCIDevice *dev) 144 { 145 PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev); 146 VGACommonState *s = &d->vga; 147 148 /* vga + console init */ 149 vga_common_init(s, OBJECT(dev), true); 150 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev), 151 true); 152 153 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 154 155 /* XXX: VGA_RAM_SIZE must be a power of two */ 156 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 157 158 /* mmio bar for vga register access */ 159 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) { 160 memory_region_init(&d->mmio, NULL, "vga.mmio", 4096); 161 memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d, 162 "vga ioports remapped", PCI_VGA_IOPORT_SIZE); 163 memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d, 164 "bochs dispi interface", PCI_VGA_BOCHS_SIZE); 165 166 memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET, 167 &d->ioport); 168 memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET, 169 &d->bochs); 170 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 171 } 172 173 if (!dev->rom_bar) { 174 /* compatibility with pc-0.13 and older */ 175 vga_init_vbe(s, OBJECT(dev), pci_address_space(dev)); 176 } 177 178 return 0; 179 } 180 181 static int pci_secondary_vga_initfn(PCIDevice *dev) 182 { 183 PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev); 184 VGACommonState *s = &d->vga; 185 186 /* vga + console init */ 187 vga_common_init(s, OBJECT(dev), false); 188 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 189 190 /* mmio bar */ 191 memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096); 192 memory_region_init_io(&d->ioport, OBJECT(dev), &pci_vga_ioport_ops, d, 193 "vga ioports remapped", PCI_VGA_IOPORT_SIZE); 194 memory_region_init_io(&d->bochs, OBJECT(dev), &pci_vga_bochs_ops, d, 195 "bochs dispi interface", PCI_VGA_BOCHS_SIZE); 196 197 memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET, 198 &d->ioport); 199 memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET, 200 &d->bochs); 201 202 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 203 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 204 205 return 0; 206 } 207 208 static void pci_secondary_vga_reset(DeviceState *dev) 209 { 210 PCIVGAState *d = DO_UPCAST(PCIVGAState, dev.qdev, dev); 211 212 vga_common_reset(&d->vga); 213 } 214 215 static Property vga_pci_properties[] = { 216 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 217 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true), 218 DEFINE_PROP_END_OF_LIST(), 219 }; 220 221 static Property secondary_pci_properties[] = { 222 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 223 DEFINE_PROP_END_OF_LIST(), 224 }; 225 226 static void vga_class_init(ObjectClass *klass, void *data) 227 { 228 DeviceClass *dc = DEVICE_CLASS(klass); 229 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 230 231 k->init = pci_std_vga_initfn; 232 k->romfile = "vgabios-stdvga.bin"; 233 k->vendor_id = PCI_VENDOR_ID_QEMU; 234 k->device_id = PCI_DEVICE_ID_QEMU_VGA; 235 k->class_id = PCI_CLASS_DISPLAY_VGA; 236 dc->vmsd = &vmstate_vga_pci; 237 dc->props = vga_pci_properties; 238 dc->hotpluggable = false; 239 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 240 } 241 242 static void secondary_class_init(ObjectClass *klass, void *data) 243 { 244 DeviceClass *dc = DEVICE_CLASS(klass); 245 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 246 247 k->init = pci_secondary_vga_initfn; 248 k->vendor_id = PCI_VENDOR_ID_QEMU; 249 k->device_id = PCI_DEVICE_ID_QEMU_VGA; 250 k->class_id = PCI_CLASS_DISPLAY_OTHER; 251 dc->vmsd = &vmstate_vga_pci; 252 dc->props = secondary_pci_properties; 253 dc->reset = pci_secondary_vga_reset; 254 } 255 256 static const TypeInfo vga_info = { 257 .name = "VGA", 258 .parent = TYPE_PCI_DEVICE, 259 .instance_size = sizeof(PCIVGAState), 260 .class_init = vga_class_init, 261 }; 262 263 static const TypeInfo secondary_info = { 264 .name = "secondary-vga", 265 .parent = TYPE_PCI_DEVICE, 266 .instance_size = sizeof(PCIVGAState), 267 .class_init = secondary_class_init, 268 }; 269 270 static void vga_register_types(void) 271 { 272 type_register_static(&vga_info); 273 type_register_static(&secondary_info); 274 } 275 276 type_init(vga_register_types) 277