1 /* 2 * QEMU PCI VGA Emulator. 3 * 4 * see docs/specs/standard-vga.txt for virtual hardware specs. 5 * 6 * Copyright (c) 2003 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "hw/hw.h" 27 #include "ui/console.h" 28 #include "hw/pci/pci.h" 29 #include "vga_int.h" 30 #include "ui/pixel_ops.h" 31 #include "qemu/timer.h" 32 #include "hw/loader.h" 33 34 #define PCI_VGA_IOPORT_OFFSET 0x400 35 #define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0) 36 #define PCI_VGA_BOCHS_OFFSET 0x500 37 #define PCI_VGA_BOCHS_SIZE (0x0b * 2) 38 #define PCI_VGA_QEXT_OFFSET 0x600 39 #define PCI_VGA_QEXT_SIZE (2 * 4) 40 #define PCI_VGA_MMIO_SIZE 0x1000 41 42 #define PCI_VGA_QEXT_REG_SIZE (0 * 4) 43 #define PCI_VGA_QEXT_REG_BYTEORDER (1 * 4) 44 #define PCI_VGA_QEXT_LITTLE_ENDIAN 0x1e1e1e1e 45 #define PCI_VGA_QEXT_BIG_ENDIAN 0xbebebebe 46 47 enum vga_pci_flags { 48 PCI_VGA_FLAG_ENABLE_MMIO = 1, 49 PCI_VGA_FLAG_ENABLE_QEXT = 2, 50 }; 51 52 typedef struct PCIVGAState { 53 PCIDevice dev; 54 VGACommonState vga; 55 uint32_t flags; 56 MemoryRegion mmio; 57 MemoryRegion ioport; 58 MemoryRegion bochs; 59 MemoryRegion qext; 60 } PCIVGAState; 61 62 static const VMStateDescription vmstate_vga_pci = { 63 .name = "vga", 64 .version_id = 2, 65 .minimum_version_id = 2, 66 .fields = (VMStateField[]) { 67 VMSTATE_PCI_DEVICE(dev, PCIVGAState), 68 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState), 69 VMSTATE_END_OF_LIST() 70 } 71 }; 72 73 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, 74 unsigned size) 75 { 76 PCIVGAState *d = ptr; 77 uint64_t ret = 0; 78 79 switch (size) { 80 case 1: 81 ret = vga_ioport_read(&d->vga, addr); 82 break; 83 case 2: 84 ret = vga_ioport_read(&d->vga, addr); 85 ret |= vga_ioport_read(&d->vga, addr+1) << 8; 86 break; 87 } 88 return ret; 89 } 90 91 static void pci_vga_ioport_write(void *ptr, hwaddr addr, 92 uint64_t val, unsigned size) 93 { 94 PCIVGAState *d = ptr; 95 96 switch (size) { 97 case 1: 98 vga_ioport_write(&d->vga, addr + 0x3c0, val); 99 break; 100 case 2: 101 /* 102 * Update bytes in little endian order. Allows to update 103 * indexed registers with a single word write because the 104 * index byte is updated first. 105 */ 106 vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff); 107 vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff); 108 break; 109 } 110 } 111 112 static const MemoryRegionOps pci_vga_ioport_ops = { 113 .read = pci_vga_ioport_read, 114 .write = pci_vga_ioport_write, 115 .valid.min_access_size = 1, 116 .valid.max_access_size = 4, 117 .impl.min_access_size = 1, 118 .impl.max_access_size = 2, 119 .endianness = DEVICE_LITTLE_ENDIAN, 120 }; 121 122 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, 123 unsigned size) 124 { 125 PCIVGAState *d = ptr; 126 int index = addr >> 1; 127 128 vbe_ioport_write_index(&d->vga, 0, index); 129 return vbe_ioport_read_data(&d->vga, 0); 130 } 131 132 static void pci_vga_bochs_write(void *ptr, hwaddr addr, 133 uint64_t val, unsigned size) 134 { 135 PCIVGAState *d = ptr; 136 int index = addr >> 1; 137 138 vbe_ioport_write_index(&d->vga, 0, index); 139 vbe_ioport_write_data(&d->vga, 0, val); 140 } 141 142 static const MemoryRegionOps pci_vga_bochs_ops = { 143 .read = pci_vga_bochs_read, 144 .write = pci_vga_bochs_write, 145 .valid.min_access_size = 1, 146 .valid.max_access_size = 4, 147 .impl.min_access_size = 2, 148 .impl.max_access_size = 2, 149 .endianness = DEVICE_LITTLE_ENDIAN, 150 }; 151 152 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) 153 { 154 PCIVGAState *d = ptr; 155 156 switch (addr) { 157 case PCI_VGA_QEXT_REG_SIZE: 158 return PCI_VGA_QEXT_SIZE; 159 case PCI_VGA_QEXT_REG_BYTEORDER: 160 return d->vga.big_endian_fb ? 161 PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN; 162 default: 163 return 0; 164 } 165 } 166 167 static void pci_vga_qext_write(void *ptr, hwaddr addr, 168 uint64_t val, unsigned size) 169 { 170 PCIVGAState *d = ptr; 171 172 switch (addr) { 173 case PCI_VGA_QEXT_REG_BYTEORDER: 174 if (val == PCI_VGA_QEXT_BIG_ENDIAN) { 175 d->vga.big_endian_fb = true; 176 } 177 if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) { 178 d->vga.big_endian_fb = false; 179 } 180 break; 181 } 182 } 183 184 static bool vga_get_big_endian_fb(Object *obj, Error **errp) 185 { 186 PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, PCI_DEVICE(obj)); 187 188 return d->vga.big_endian_fb; 189 } 190 191 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp) 192 { 193 PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, PCI_DEVICE(obj)); 194 195 d->vga.big_endian_fb = value; 196 } 197 198 static const MemoryRegionOps pci_vga_qext_ops = { 199 .read = pci_vga_qext_read, 200 .write = pci_vga_qext_write, 201 .valid.min_access_size = 4, 202 .valid.max_access_size = 4, 203 .endianness = DEVICE_LITTLE_ENDIAN, 204 }; 205 206 static void pci_std_vga_realize(PCIDevice *dev, Error **errp) 207 { 208 PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev); 209 VGACommonState *s = &d->vga; 210 211 /* vga + console init */ 212 vga_common_init(s, OBJECT(dev), true); 213 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev), 214 true); 215 216 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 217 218 /* XXX: VGA_RAM_SIZE must be a power of two */ 219 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 220 221 /* mmio bar for vga register access */ 222 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) { 223 memory_region_init(&d->mmio, NULL, "vga.mmio", 4096); 224 memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d, 225 "vga ioports remapped", PCI_VGA_IOPORT_SIZE); 226 memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d, 227 "bochs dispi interface", PCI_VGA_BOCHS_SIZE); 228 229 memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET, 230 &d->ioport); 231 memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET, 232 &d->bochs); 233 234 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 235 memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d, 236 "qemu extended regs", PCI_VGA_QEXT_SIZE); 237 memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET, 238 &d->qext); 239 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); 240 } 241 242 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 243 } 244 245 if (!dev->rom_bar) { 246 /* compatibility with pc-0.13 and older */ 247 vga_init_vbe(s, OBJECT(dev), pci_address_space(dev)); 248 } 249 } 250 251 static void pci_std_vga_init(Object *obj) 252 { 253 /* Expose framebuffer byteorder via QOM */ 254 object_property_add_bool(obj, "big-endian-framebuffer", 255 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); 256 } 257 258 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) 259 { 260 PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev); 261 VGACommonState *s = &d->vga; 262 263 /* vga + console init */ 264 vga_common_init(s, OBJECT(dev), false); 265 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 266 267 /* mmio bar */ 268 memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096); 269 memory_region_init_io(&d->ioport, OBJECT(dev), &pci_vga_ioport_ops, d, 270 "vga ioports remapped", PCI_VGA_IOPORT_SIZE); 271 memory_region_init_io(&d->bochs, OBJECT(dev), &pci_vga_bochs_ops, d, 272 "bochs dispi interface", PCI_VGA_BOCHS_SIZE); 273 274 memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET, 275 &d->ioport); 276 memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET, 277 &d->bochs); 278 279 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 280 memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d, 281 "qemu extended regs", PCI_VGA_QEXT_SIZE); 282 memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET, 283 &d->qext); 284 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); 285 } 286 287 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 288 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 289 } 290 291 static void pci_secondary_vga_init(Object *obj) 292 { 293 /* Expose framebuffer byteorder via QOM */ 294 object_property_add_bool(obj, "big-endian-framebuffer", 295 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); 296 } 297 298 static void pci_secondary_vga_reset(DeviceState *dev) 299 { 300 PCIVGAState *d = DO_UPCAST(PCIVGAState, dev.qdev, dev); 301 302 vga_common_reset(&d->vga); 303 } 304 305 static Property vga_pci_properties[] = { 306 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 307 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true), 308 DEFINE_PROP_BIT("qemu-extended-regs", 309 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), 310 DEFINE_PROP_END_OF_LIST(), 311 }; 312 313 static Property secondary_pci_properties[] = { 314 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 315 DEFINE_PROP_BIT("qemu-extended-regs", 316 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), 317 DEFINE_PROP_END_OF_LIST(), 318 }; 319 320 static void vga_class_init(ObjectClass *klass, void *data) 321 { 322 DeviceClass *dc = DEVICE_CLASS(klass); 323 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 324 325 k->realize = pci_std_vga_realize; 326 k->romfile = "vgabios-stdvga.bin"; 327 k->vendor_id = PCI_VENDOR_ID_QEMU; 328 k->device_id = PCI_DEVICE_ID_QEMU_VGA; 329 k->class_id = PCI_CLASS_DISPLAY_VGA; 330 dc->vmsd = &vmstate_vga_pci; 331 dc->props = vga_pci_properties; 332 dc->hotpluggable = false; 333 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 334 } 335 336 static void secondary_class_init(ObjectClass *klass, void *data) 337 { 338 DeviceClass *dc = DEVICE_CLASS(klass); 339 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 340 341 k->realize = pci_secondary_vga_realize; 342 k->vendor_id = PCI_VENDOR_ID_QEMU; 343 k->device_id = PCI_DEVICE_ID_QEMU_VGA; 344 k->class_id = PCI_CLASS_DISPLAY_OTHER; 345 dc->vmsd = &vmstate_vga_pci; 346 dc->props = secondary_pci_properties; 347 dc->reset = pci_secondary_vga_reset; 348 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 349 } 350 351 static const TypeInfo vga_info = { 352 .name = "VGA", 353 .parent = TYPE_PCI_DEVICE, 354 .instance_init = pci_std_vga_init, 355 .instance_size = sizeof(PCIVGAState), 356 .class_init = vga_class_init, 357 }; 358 359 static const TypeInfo secondary_info = { 360 .name = "secondary-vga", 361 .parent = TYPE_PCI_DEVICE, 362 .instance_init = pci_secondary_vga_init, 363 .instance_size = sizeof(PCIVGAState), 364 .class_init = secondary_class_init, 365 }; 366 367 static void vga_register_types(void) 368 { 369 type_register_static(&vga_info); 370 type_register_static(&secondary_info); 371 } 372 373 type_init(vga_register_types) 374