1 /* 2 * QEMU PCI VGA Emulator. 3 * 4 * see docs/specs/standard-vga.txt for virtual hardware specs. 5 * 6 * Copyright (c) 2003 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "vga_int.h" 31 #include "ui/pixel_ops.h" 32 #include "qemu/module.h" 33 #include "qemu/timer.h" 34 #include "hw/loader.h" 35 #include "hw/display/edid.h" 36 37 enum vga_pci_flags { 38 PCI_VGA_FLAG_ENABLE_MMIO = 1, 39 PCI_VGA_FLAG_ENABLE_QEXT = 2, 40 PCI_VGA_FLAG_ENABLE_EDID = 3, 41 }; 42 43 typedef struct PCIVGAState { 44 PCIDevice dev; 45 VGACommonState vga; 46 uint32_t flags; 47 qemu_edid_info edid_info; 48 MemoryRegion mmio; 49 MemoryRegion mrs[4]; 50 uint8_t edid[256]; 51 } PCIVGAState; 52 53 #define TYPE_PCI_VGA "pci-vga" 54 #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA) 55 56 static const VMStateDescription vmstate_vga_pci = { 57 .name = "vga", 58 .version_id = 2, 59 .minimum_version_id = 2, 60 .fields = (VMStateField[]) { 61 VMSTATE_PCI_DEVICE(dev, PCIVGAState), 62 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState), 63 VMSTATE_END_OF_LIST() 64 } 65 }; 66 67 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, 68 unsigned size) 69 { 70 VGACommonState *s = ptr; 71 uint64_t ret = 0; 72 73 switch (size) { 74 case 1: 75 ret = vga_ioport_read(s, addr + 0x3c0); 76 break; 77 case 2: 78 ret = vga_ioport_read(s, addr + 0x3c0); 79 ret |= vga_ioport_read(s, addr + 0x3c1) << 8; 80 break; 81 } 82 return ret; 83 } 84 85 static void pci_vga_ioport_write(void *ptr, hwaddr addr, 86 uint64_t val, unsigned size) 87 { 88 VGACommonState *s = ptr; 89 90 switch (size) { 91 case 1: 92 vga_ioport_write(s, addr + 0x3c0, val); 93 break; 94 case 2: 95 /* 96 * Update bytes in little endian order. Allows to update 97 * indexed registers with a single word write because the 98 * index byte is updated first. 99 */ 100 vga_ioport_write(s, addr + 0x3c0, val & 0xff); 101 vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff); 102 break; 103 } 104 } 105 106 static const MemoryRegionOps pci_vga_ioport_ops = { 107 .read = pci_vga_ioport_read, 108 .write = pci_vga_ioport_write, 109 .valid.min_access_size = 1, 110 .valid.max_access_size = 4, 111 .impl.min_access_size = 1, 112 .impl.max_access_size = 2, 113 .endianness = DEVICE_LITTLE_ENDIAN, 114 }; 115 116 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, 117 unsigned size) 118 { 119 VGACommonState *s = ptr; 120 int index = addr >> 1; 121 122 vbe_ioport_write_index(s, 0, index); 123 return vbe_ioport_read_data(s, 0); 124 } 125 126 static void pci_vga_bochs_write(void *ptr, hwaddr addr, 127 uint64_t val, unsigned size) 128 { 129 VGACommonState *s = ptr; 130 int index = addr >> 1; 131 132 vbe_ioport_write_index(s, 0, index); 133 vbe_ioport_write_data(s, 0, val); 134 } 135 136 static const MemoryRegionOps pci_vga_bochs_ops = { 137 .read = pci_vga_bochs_read, 138 .write = pci_vga_bochs_write, 139 .valid.min_access_size = 1, 140 .valid.max_access_size = 4, 141 .impl.min_access_size = 2, 142 .impl.max_access_size = 2, 143 .endianness = DEVICE_LITTLE_ENDIAN, 144 }; 145 146 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) 147 { 148 VGACommonState *s = ptr; 149 150 switch (addr) { 151 case PCI_VGA_QEXT_REG_SIZE: 152 return PCI_VGA_QEXT_SIZE; 153 case PCI_VGA_QEXT_REG_BYTEORDER: 154 return s->big_endian_fb ? 155 PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN; 156 default: 157 return 0; 158 } 159 } 160 161 static void pci_vga_qext_write(void *ptr, hwaddr addr, 162 uint64_t val, unsigned size) 163 { 164 VGACommonState *s = ptr; 165 166 switch (addr) { 167 case PCI_VGA_QEXT_REG_BYTEORDER: 168 if (val == PCI_VGA_QEXT_BIG_ENDIAN) { 169 s->big_endian_fb = true; 170 } 171 if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) { 172 s->big_endian_fb = false; 173 } 174 break; 175 } 176 } 177 178 static bool vga_get_big_endian_fb(Object *obj, Error **errp) 179 { 180 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); 181 182 return d->vga.big_endian_fb; 183 } 184 185 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp) 186 { 187 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); 188 189 d->vga.big_endian_fb = value; 190 } 191 192 static const MemoryRegionOps pci_vga_qext_ops = { 193 .read = pci_vga_qext_read, 194 .write = pci_vga_qext_write, 195 .valid.min_access_size = 4, 196 .valid.max_access_size = 4, 197 .endianness = DEVICE_LITTLE_ENDIAN, 198 }; 199 200 void pci_std_vga_mmio_region_init(VGACommonState *s, 201 Object *owner, 202 MemoryRegion *parent, 203 MemoryRegion *subs, 204 bool qext, bool edid) 205 { 206 PCIVGAState *d = container_of(s, PCIVGAState, vga); 207 208 memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s, 209 "vga ioports remapped", PCI_VGA_IOPORT_SIZE); 210 memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET, 211 &subs[0]); 212 213 memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s, 214 "bochs dispi interface", PCI_VGA_BOCHS_SIZE); 215 memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET, 216 &subs[1]); 217 218 if (qext) { 219 memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s, 220 "qemu extended regs", PCI_VGA_QEXT_SIZE); 221 memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET, 222 &subs[2]); 223 } 224 225 if (edid) { 226 qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info); 227 qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid)); 228 memory_region_add_subregion(parent, 0, &subs[3]); 229 } 230 } 231 232 static void pci_std_vga_realize(PCIDevice *dev, Error **errp) 233 { 234 PCIVGAState *d = PCI_VGA(dev); 235 VGACommonState *s = &d->vga; 236 bool qext = false; 237 bool edid = false; 238 239 /* vga + console init */ 240 vga_common_init(s, OBJECT(dev)); 241 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev), 242 true); 243 244 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 245 246 /* XXX: VGA_RAM_SIZE must be a power of two */ 247 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 248 249 /* mmio bar for vga register access */ 250 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) { 251 memory_region_init(&d->mmio, NULL, "vga.mmio", 252 PCI_VGA_MMIO_SIZE); 253 254 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 255 qext = true; 256 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); 257 } 258 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { 259 edid = true; 260 } 261 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, 262 qext, edid); 263 264 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 265 } 266 267 if (!dev->rom_bar) { 268 /* compatibility with pc-0.13 and older */ 269 vga_init_vbe(s, OBJECT(dev), pci_address_space(dev)); 270 } 271 } 272 273 static void pci_std_vga_init(Object *obj) 274 { 275 /* Expose framebuffer byteorder via QOM */ 276 object_property_add_bool(obj, "big-endian-framebuffer", 277 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); 278 } 279 280 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) 281 { 282 PCIVGAState *d = PCI_VGA(dev); 283 VGACommonState *s = &d->vga; 284 bool qext = false; 285 bool edid = false; 286 287 /* vga + console init */ 288 vga_common_init(s, OBJECT(dev)); 289 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 290 291 /* mmio bar */ 292 memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 293 PCI_VGA_MMIO_SIZE); 294 295 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 296 qext = true; 297 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); 298 } 299 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { 300 edid = true; 301 } 302 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid); 303 304 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 305 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 306 } 307 308 static void pci_secondary_vga_exit(PCIDevice *dev) 309 { 310 PCIVGAState *d = PCI_VGA(dev); 311 VGACommonState *s = &d->vga; 312 313 graphic_console_close(s->con); 314 memory_region_del_subregion(&d->mmio, &d->mrs[0]); 315 memory_region_del_subregion(&d->mmio, &d->mrs[1]); 316 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 317 memory_region_del_subregion(&d->mmio, &d->mrs[2]); 318 } 319 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { 320 memory_region_del_subregion(&d->mmio, &d->mrs[3]); 321 } 322 } 323 324 static void pci_secondary_vga_init(Object *obj) 325 { 326 /* Expose framebuffer byteorder via QOM */ 327 object_property_add_bool(obj, "big-endian-framebuffer", 328 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); 329 } 330 331 static void pci_secondary_vga_reset(DeviceState *dev) 332 { 333 PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev)); 334 vga_common_reset(&d->vga); 335 } 336 337 static Property vga_pci_properties[] = { 338 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 339 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true), 340 DEFINE_PROP_BIT("qemu-extended-regs", 341 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), 342 DEFINE_PROP_BIT("edid", 343 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), 344 DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), 345 DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false), 346 DEFINE_PROP_END_OF_LIST(), 347 }; 348 349 static Property secondary_pci_properties[] = { 350 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 351 DEFINE_PROP_BIT("qemu-extended-regs", 352 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), 353 DEFINE_PROP_BIT("edid", 354 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), 355 DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), 356 DEFINE_PROP_END_OF_LIST(), 357 }; 358 359 static void vga_pci_class_init(ObjectClass *klass, void *data) 360 { 361 DeviceClass *dc = DEVICE_CLASS(klass); 362 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 363 364 k->vendor_id = PCI_VENDOR_ID_QEMU; 365 k->device_id = PCI_DEVICE_ID_QEMU_VGA; 366 dc->vmsd = &vmstate_vga_pci; 367 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 368 } 369 370 static const TypeInfo vga_pci_type_info = { 371 .name = TYPE_PCI_VGA, 372 .parent = TYPE_PCI_DEVICE, 373 .instance_size = sizeof(PCIVGAState), 374 .abstract = true, 375 .class_init = vga_pci_class_init, 376 .interfaces = (InterfaceInfo[]) { 377 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 378 { }, 379 }, 380 }; 381 382 static void vga_class_init(ObjectClass *klass, void *data) 383 { 384 DeviceClass *dc = DEVICE_CLASS(klass); 385 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 386 387 k->realize = pci_std_vga_realize; 388 k->romfile = "vgabios-stdvga.bin"; 389 k->class_id = PCI_CLASS_DISPLAY_VGA; 390 dc->props = vga_pci_properties; 391 dc->hotpluggable = false; 392 } 393 394 static void secondary_class_init(ObjectClass *klass, void *data) 395 { 396 DeviceClass *dc = DEVICE_CLASS(klass); 397 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 398 399 k->realize = pci_secondary_vga_realize; 400 k->exit = pci_secondary_vga_exit; 401 k->class_id = PCI_CLASS_DISPLAY_OTHER; 402 dc->props = secondary_pci_properties; 403 dc->reset = pci_secondary_vga_reset; 404 } 405 406 static const TypeInfo vga_info = { 407 .name = "VGA", 408 .parent = TYPE_PCI_VGA, 409 .instance_init = pci_std_vga_init, 410 .class_init = vga_class_init, 411 }; 412 413 static const TypeInfo secondary_info = { 414 .name = "secondary-vga", 415 .parent = TYPE_PCI_VGA, 416 .instance_init = pci_secondary_vga_init, 417 .class_init = secondary_class_init, 418 }; 419 420 static void vga_register_types(void) 421 { 422 type_register_static(&vga_pci_type_info); 423 type_register_static(&vga_info); 424 type_register_static(&secondary_info); 425 } 426 427 type_init(vga_register_types) 428