1 /* 2 * QEMU PCI VGA Emulator. 3 * 4 * see docs/specs/standard-vga.txt for virtual hardware specs. 5 * 6 * Copyright (c) 2003 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/pci/pci.h" 29 #include "vga_int.h" 30 #include "ui/pixel_ops.h" 31 #include "qemu/timer.h" 32 #include "hw/loader.h" 33 34 enum vga_pci_flags { 35 PCI_VGA_FLAG_ENABLE_MMIO = 1, 36 PCI_VGA_FLAG_ENABLE_QEXT = 2, 37 }; 38 39 typedef struct PCIVGAState { 40 PCIDevice dev; 41 VGACommonState vga; 42 uint32_t flags; 43 MemoryRegion mmio; 44 MemoryRegion mrs[3]; 45 } PCIVGAState; 46 47 #define TYPE_PCI_VGA "pci-vga" 48 #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA) 49 50 static const VMStateDescription vmstate_vga_pci = { 51 .name = "vga", 52 .version_id = 2, 53 .minimum_version_id = 2, 54 .fields = (VMStateField[]) { 55 VMSTATE_PCI_DEVICE(dev, PCIVGAState), 56 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState), 57 VMSTATE_END_OF_LIST() 58 } 59 }; 60 61 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, 62 unsigned size) 63 { 64 VGACommonState *s = ptr; 65 uint64_t ret = 0; 66 67 switch (size) { 68 case 1: 69 ret = vga_ioport_read(s, addr + 0x3c0); 70 break; 71 case 2: 72 ret = vga_ioport_read(s, addr + 0x3c0); 73 ret |= vga_ioport_read(s, addr + 0x3c1) << 8; 74 break; 75 } 76 return ret; 77 } 78 79 static void pci_vga_ioport_write(void *ptr, hwaddr addr, 80 uint64_t val, unsigned size) 81 { 82 VGACommonState *s = ptr; 83 84 switch (size) { 85 case 1: 86 vga_ioport_write(s, addr + 0x3c0, val); 87 break; 88 case 2: 89 /* 90 * Update bytes in little endian order. Allows to update 91 * indexed registers with a single word write because the 92 * index byte is updated first. 93 */ 94 vga_ioport_write(s, addr + 0x3c0, val & 0xff); 95 vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff); 96 break; 97 } 98 } 99 100 static const MemoryRegionOps pci_vga_ioport_ops = { 101 .read = pci_vga_ioport_read, 102 .write = pci_vga_ioport_write, 103 .valid.min_access_size = 1, 104 .valid.max_access_size = 4, 105 .impl.min_access_size = 1, 106 .impl.max_access_size = 2, 107 .endianness = DEVICE_LITTLE_ENDIAN, 108 }; 109 110 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, 111 unsigned size) 112 { 113 VGACommonState *s = ptr; 114 int index = addr >> 1; 115 116 vbe_ioport_write_index(s, 0, index); 117 return vbe_ioport_read_data(s, 0); 118 } 119 120 static void pci_vga_bochs_write(void *ptr, hwaddr addr, 121 uint64_t val, unsigned size) 122 { 123 VGACommonState *s = ptr; 124 int index = addr >> 1; 125 126 vbe_ioport_write_index(s, 0, index); 127 vbe_ioport_write_data(s, 0, val); 128 } 129 130 static const MemoryRegionOps pci_vga_bochs_ops = { 131 .read = pci_vga_bochs_read, 132 .write = pci_vga_bochs_write, 133 .valid.min_access_size = 1, 134 .valid.max_access_size = 4, 135 .impl.min_access_size = 2, 136 .impl.max_access_size = 2, 137 .endianness = DEVICE_LITTLE_ENDIAN, 138 }; 139 140 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) 141 { 142 VGACommonState *s = ptr; 143 144 switch (addr) { 145 case PCI_VGA_QEXT_REG_SIZE: 146 return PCI_VGA_QEXT_SIZE; 147 case PCI_VGA_QEXT_REG_BYTEORDER: 148 return s->big_endian_fb ? 149 PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN; 150 default: 151 return 0; 152 } 153 } 154 155 static void pci_vga_qext_write(void *ptr, hwaddr addr, 156 uint64_t val, unsigned size) 157 { 158 VGACommonState *s = ptr; 159 160 switch (addr) { 161 case PCI_VGA_QEXT_REG_BYTEORDER: 162 if (val == PCI_VGA_QEXT_BIG_ENDIAN) { 163 s->big_endian_fb = true; 164 } 165 if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) { 166 s->big_endian_fb = false; 167 } 168 break; 169 } 170 } 171 172 static bool vga_get_big_endian_fb(Object *obj, Error **errp) 173 { 174 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); 175 176 return d->vga.big_endian_fb; 177 } 178 179 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp) 180 { 181 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); 182 183 d->vga.big_endian_fb = value; 184 } 185 186 static const MemoryRegionOps pci_vga_qext_ops = { 187 .read = pci_vga_qext_read, 188 .write = pci_vga_qext_write, 189 .valid.min_access_size = 4, 190 .valid.max_access_size = 4, 191 .endianness = DEVICE_LITTLE_ENDIAN, 192 }; 193 194 void pci_std_vga_mmio_region_init(VGACommonState *s, 195 MemoryRegion *parent, 196 MemoryRegion *subs, 197 bool qext) 198 { 199 memory_region_init_io(&subs[0], NULL, &pci_vga_ioport_ops, s, 200 "vga ioports remapped", PCI_VGA_IOPORT_SIZE); 201 memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET, 202 &subs[0]); 203 204 memory_region_init_io(&subs[1], NULL, &pci_vga_bochs_ops, s, 205 "bochs dispi interface", PCI_VGA_BOCHS_SIZE); 206 memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET, 207 &subs[1]); 208 209 if (qext) { 210 memory_region_init_io(&subs[2], NULL, &pci_vga_qext_ops, s, 211 "qemu extended regs", PCI_VGA_QEXT_SIZE); 212 memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET, 213 &subs[2]); 214 } 215 } 216 217 static void pci_std_vga_realize(PCIDevice *dev, Error **errp) 218 { 219 PCIVGAState *d = PCI_VGA(dev); 220 VGACommonState *s = &d->vga; 221 bool qext = false; 222 223 /* vga + console init */ 224 vga_common_init(s, OBJECT(dev), true); 225 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev), 226 true); 227 228 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 229 230 /* XXX: VGA_RAM_SIZE must be a power of two */ 231 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 232 233 /* mmio bar for vga register access */ 234 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) { 235 memory_region_init(&d->mmio, NULL, "vga.mmio", 236 PCI_VGA_MMIO_SIZE); 237 238 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 239 qext = true; 240 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); 241 } 242 pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext); 243 244 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 245 } 246 247 if (!dev->rom_bar) { 248 /* compatibility with pc-0.13 and older */ 249 vga_init_vbe(s, OBJECT(dev), pci_address_space(dev)); 250 } 251 } 252 253 static void pci_std_vga_init(Object *obj) 254 { 255 /* Expose framebuffer byteorder via QOM */ 256 object_property_add_bool(obj, "big-endian-framebuffer", 257 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); 258 } 259 260 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) 261 { 262 PCIVGAState *d = PCI_VGA(dev); 263 VGACommonState *s = &d->vga; 264 bool qext = false; 265 266 /* vga + console init */ 267 vga_common_init(s, OBJECT(dev), false); 268 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); 269 270 /* mmio bar */ 271 memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 272 PCI_VGA_MMIO_SIZE); 273 274 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { 275 qext = true; 276 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); 277 } 278 pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext); 279 280 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); 281 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 282 } 283 284 static void pci_secondary_vga_exit(PCIDevice *dev) 285 { 286 PCIVGAState *d = PCI_VGA(dev); 287 VGACommonState *s = &d->vga; 288 289 graphic_console_close(s->con); 290 } 291 292 static void pci_secondary_vga_init(Object *obj) 293 { 294 /* Expose framebuffer byteorder via QOM */ 295 object_property_add_bool(obj, "big-endian-framebuffer", 296 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); 297 } 298 299 static void pci_secondary_vga_reset(DeviceState *dev) 300 { 301 PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev)); 302 vga_common_reset(&d->vga); 303 } 304 305 static Property vga_pci_properties[] = { 306 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 307 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true), 308 DEFINE_PROP_BIT("qemu-extended-regs", 309 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), 310 DEFINE_PROP_END_OF_LIST(), 311 }; 312 313 static Property secondary_pci_properties[] = { 314 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), 315 DEFINE_PROP_BIT("qemu-extended-regs", 316 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), 317 DEFINE_PROP_END_OF_LIST(), 318 }; 319 320 static void vga_pci_class_init(ObjectClass *klass, void *data) 321 { 322 DeviceClass *dc = DEVICE_CLASS(klass); 323 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 324 325 k->vendor_id = PCI_VENDOR_ID_QEMU; 326 k->device_id = PCI_DEVICE_ID_QEMU_VGA; 327 dc->vmsd = &vmstate_vga_pci; 328 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 329 } 330 331 static const TypeInfo vga_pci_type_info = { 332 .name = TYPE_PCI_VGA, 333 .parent = TYPE_PCI_DEVICE, 334 .instance_size = sizeof(PCIVGAState), 335 .abstract = true, 336 .class_init = vga_pci_class_init, 337 .interfaces = (InterfaceInfo[]) { 338 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 339 { }, 340 }, 341 }; 342 343 static void vga_class_init(ObjectClass *klass, void *data) 344 { 345 DeviceClass *dc = DEVICE_CLASS(klass); 346 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 347 348 k->realize = pci_std_vga_realize; 349 k->romfile = "vgabios-stdvga.bin"; 350 k->class_id = PCI_CLASS_DISPLAY_VGA; 351 dc->props = vga_pci_properties; 352 dc->hotpluggable = false; 353 } 354 355 static void secondary_class_init(ObjectClass *klass, void *data) 356 { 357 DeviceClass *dc = DEVICE_CLASS(klass); 358 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 359 360 k->realize = pci_secondary_vga_realize; 361 k->exit = pci_secondary_vga_exit; 362 k->class_id = PCI_CLASS_DISPLAY_OTHER; 363 dc->props = secondary_pci_properties; 364 dc->reset = pci_secondary_vga_reset; 365 } 366 367 static const TypeInfo vga_info = { 368 .name = "VGA", 369 .parent = TYPE_PCI_VGA, 370 .instance_init = pci_std_vga_init, 371 .class_init = vga_class_init, 372 }; 373 374 static const TypeInfo secondary_info = { 375 .name = "secondary-vga", 376 .parent = TYPE_PCI_VGA, 377 .instance_init = pci_secondary_vga_init, 378 .class_init = secondary_class_init, 379 }; 380 381 static void vga_register_types(void) 382 { 383 type_register_static(&vga_pci_type_info); 384 type_register_static(&vga_info); 385 type_register_static(&secondary_info); 386 } 387 388 type_init(vga_register_types) 389