1# See docs/devel/tracing.txt for syntax documentation. 2 3# jazz_led.c 4jazz_led_read(uint64_t addr, uint8_t val) "read addr=0x%"PRIx64": 0x%x" 5jazz_led_write(uint64_t addr, uint8_t new) "write addr=0x%"PRIx64": 0x%x" 6 7# xenfb.c 8xenfb_mouse_event(void *opaque, int dx, int dy, int dz, int button_state, int abs_pointer_wanted) "%p x %d y %d z %d bs 0x%x abs %d" 9xenfb_key_event(void *opaque, int scancode, int button_state) "%p scancode %d bs 0x%x" 10xenfb_input_connected(void *xendev, int abs_pointer_wanted) "%p abs %d" 11 12# g364fb.c 13g364fb_read(uint64_t addr, uint32_t val) "read addr=0x%"PRIx64": 0x%x" 14g364fb_write(uint64_t addr, uint32_t new) "write addr=0x%"PRIx64": 0x%x" 15 16# milkymist-tmu2.c 17milkymist_tmu2_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" 18milkymist_tmu2_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" 19milkymist_tmu2_start(void) "Start TMU" 20milkymist_tmu2_pulse_irq(void) "Pulse IRQ" 21 22# milkymist-vgafb.c 23milkymist_vgafb_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" 24milkymist_vgafb_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" 25 26# vmware_vga.c 27vmware_value_read(uint32_t index, uint32_t value) "index %d, value 0x%x" 28vmware_value_write(uint32_t index, uint32_t value) "index %d, value 0x%x" 29vmware_palette_read(uint32_t index, uint32_t value) "index %d, value 0x%x" 30vmware_palette_write(uint32_t index, uint32_t value) "index %d, value 0x%x" 31vmware_scratch_read(uint32_t index, uint32_t value) "index %d, value 0x%x" 32vmware_scratch_write(uint32_t index, uint32_t value) "index %d, value 0x%x" 33vmware_setmode(uint32_t w, uint32_t h, uint32_t bpp) "%dx%d @ %d bpp" 34 35# virtio-gpu-base.c 36virtio_gpu_features(bool virgl) "virgl %d" 37 38# virtio-gpu-3d.c 39# virtio-gpu.c 40virtio_gpu_cmd_get_display_info(void) "" 41virtio_gpu_cmd_get_edid(uint32_t scanout) "scanout %d" 42virtio_gpu_cmd_set_scanout(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) "id %d, res 0x%x, w %d, h %d, x %d, y %d" 43virtio_gpu_cmd_res_create_2d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h) "res 0x%x, fmt 0x%x, w %d, h %d" 44virtio_gpu_cmd_res_create_3d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h, uint32_t d) "res 0x%x, fmt 0x%x, w %d, h %d, d %d" 45virtio_gpu_cmd_res_unref(uint32_t res) "res 0x%x" 46virtio_gpu_cmd_res_back_attach(uint32_t res) "res 0x%x" 47virtio_gpu_cmd_res_back_detach(uint32_t res) "res 0x%x" 48virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) "res 0x%x" 49virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) "res 0x%x" 50virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) "res 0x%x" 51virtio_gpu_cmd_res_flush(uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) "res 0x%x, w %d, h %d, x %d, y %d" 52virtio_gpu_cmd_ctx_create(uint32_t ctx, const char *name) "ctx 0x%x, name %s" 53virtio_gpu_cmd_ctx_destroy(uint32_t ctx) "ctx 0x%x" 54virtio_gpu_cmd_ctx_res_attach(uint32_t ctx, uint32_t res) "ctx 0x%x, res 0x%x" 55virtio_gpu_cmd_ctx_res_detach(uint32_t ctx, uint32_t res) "ctx 0x%x, res 0x%x" 56virtio_gpu_cmd_ctx_submit(uint32_t ctx, uint32_t size) "ctx 0x%x, size %d" 57virtio_gpu_update_cursor(uint32_t scanout, uint32_t x, uint32_t y, const char *type, uint32_t res) "scanout %d, x %d, y %d, %s, res 0x%x" 58virtio_gpu_fence_ctrl(uint64_t fence, uint32_t type) "fence 0x%" PRIx64 ", type 0x%x" 59virtio_gpu_fence_resp(uint64_t fence) "fence 0x%" PRIx64 60 61# qxl.c 62disable qxl_interface_set_mm_time(int qid, uint32_t mm_time) "%d %d" 63disable qxl_io_write_vga(int qid, const char *mode, uint32_t addr, uint32_t val) "%d %s addr=%u val=%u" 64qxl_create_guest_primary(int qid, uint32_t width, uint32_t height, uint64_t mem, uint32_t format, uint32_t position) "%d %ux%u mem=0x%" PRIx64 " %u,%u" 65qxl_create_guest_primary_rest(int qid, int32_t stride, uint32_t type, uint32_t flags) "%d %d,%d,%d" 66qxl_destroy_primary(int qid) "%d" 67qxl_enter_vga_mode(int qid) "%d" 68qxl_exit_vga_mode(int qid) "%d" 69qxl_hard_reset(int qid, int64_t loadvm) "%d loadvm=%"PRId64 70qxl_interface_async_complete_io(int qid, uint32_t current_async, void *cookie) "%d current=%d cookie=%p" 71qxl_interface_attach_worker(int qid) "%d" 72qxl_interface_get_init_info(int qid) "%d" 73qxl_interface_set_compression_level(int qid, int64_t level) "%d %"PRId64 74qxl_interface_update_area_complete(int qid, uint32_t surface_id, uint32_t dirty_left, uint32_t dirty_right, uint32_t dirty_top, uint32_t dirty_bottom) "%d surface=%d [%d,%d,%d,%d]" 75qxl_interface_update_area_complete_rest(int qid, uint32_t num_updated_rects) "%d #=%d" 76qxl_interface_update_area_complete_overflow(int qid, int max) "%d max=%d" 77qxl_interface_update_area_complete_schedule_bh(int qid, uint32_t num_dirty) "%d #dirty=%d" 78qxl_io_destroy_primary_ignored(int qid, const char *mode) "%d %s" 79qxl_io_log(int qid, const char *log_buf) "%d %s" 80qxl_io_read_unexpected(int qid) "%d" 81qxl_io_unexpected_vga_mode(int qid, uint64_t addr, uint64_t val, const char *desc) "%d 0x%"PRIx64"=%"PRIu64" (%s)" 82qxl_io_write(int qid, const char *mode, uint64_t addr, const char *aname, uint64_t val, unsigned size, int async) "%d %s addr=%"PRIu64 " (%s) val=%"PRIu64" size=%u async=%d" 83qxl_memslot_add_guest(int qid, uint32_t slot_id, uint64_t guest_start, uint64_t guest_end) "%d %u: guest phys 0x%"PRIx64 " - 0x%" PRIx64 84qxl_post_load(int qid, const char *mode) "%d %s" 85qxl_pre_load(int qid) "%d" 86qxl_pre_save(int qid) "%d" 87qxl_reset_surfaces(int qid) "%d" 88qxl_ring_command_check(int qid, const char *mode) "%d %s" 89qxl_ring_command_get(int qid, const char *mode) "%d %s" 90qxl_ring_command_req_notification(int qid) "%d" 91qxl_ring_cursor_check(int qid, const char *mode) "%d %s" 92qxl_ring_cursor_get(int qid, const char *mode) "%d %s" 93qxl_ring_cursor_req_notification(int qid) "%d" 94qxl_ring_res_push(int qid, const char *mode, uint32_t surface_count, uint32_t free_res, void *last_release, const char *notify) "%d %s s#=%d res#=%d last=%p notify=%s" 95qxl_ring_res_push_rest(int qid, uint32_t ring_has, uint32_t ring_size, uint32_t prod, uint32_t cons) "%d ring %d/%d [%d,%d]" 96qxl_ring_res_put(int qid, uint32_t free_res) "%d #res=%d" 97qxl_set_mode(int qid, int modenr, uint32_t x_res, uint32_t y_res, uint32_t bits, uint64_t devmem) "%d mode=%d [ x=%d y=%d @ bpp=%d devmem=0x%" PRIx64 " ]" 98qxl_soft_reset(int qid) "%d" 99qxl_spice_destroy_surfaces_complete(int qid) "%d" 100qxl_spice_destroy_surfaces(int qid, int async) "%d async=%d" 101qxl_spice_destroy_surface_wait_complete(int qid, uint32_t id) "%d sid=%d" 102qxl_spice_destroy_surface_wait(int qid, uint32_t id, int async) "%d sid=%d async=%d" 103qxl_spice_flush_surfaces_async(int qid, uint32_t surface_count, uint32_t num_free_res) "%d s#=%d, res#=%d" 104qxl_spice_monitors_config(int qid) "%d" 105qxl_spice_loadvm_commands(int qid, void *ext, uint32_t count) "%d ext=%p count=%d" 106qxl_spice_oom(int qid) "%d" 107qxl_spice_reset_cursor(int qid) "%d" 108qxl_spice_reset_image_cache(int qid) "%d" 109qxl_spice_reset_memslots(int qid) "%d" 110qxl_spice_update_area(int qid, uint32_t surface_id, uint32_t left, uint32_t right, uint32_t top, uint32_t bottom) "%d sid=%d [%d,%d,%d,%d]" 111qxl_spice_update_area_rest(int qid, uint32_t num_dirty_rects, uint32_t clear_dirty_region) "%d #d=%d clear=%d" 112qxl_surfaces_dirty(int qid, uint64_t offset, uint64_t size) "%d offset=0x%"PRIx64" size=0x%"PRIx64 113qxl_send_events(int qid, uint32_t events) "%d %d" 114qxl_send_events_vm_stopped(int qid, uint32_t events) "%d %d" 115qxl_set_guest_bug(int qid) "%d" 116qxl_interrupt_client_monitors_config(int qid, int num_heads, void *heads) "%d %d %p" 117qxl_client_monitors_config_unsupported_by_guest(int qid, uint32_t int_mask, void *client_monitors_config) "%d 0x%X %p" 118qxl_client_monitors_config_unsupported_by_device(int qid, int revision) "%d revision=%d" 119qxl_client_monitors_config_capped(int qid, int requested, int limit) "%d %d %d" 120qxl_client_monitors_config_crc(int qid, unsigned size, uint32_t crc32) "%d %u %u" 121qxl_set_client_capabilities_unsupported_by_revision(int qid, int revision) "%d revision=%d" 122 123# qxl-render.c 124qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom) "stride=%d [%d, %d, %d, %d]" 125qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp) "%dx%d, stride %d, bpp %d, depth %d" 126qxl_render_update_area_done(void *cookie) "%p" 127 128# vga.c 129vga_std_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" 130vga_std_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" 131vga_vbe_read(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" 132vga_vbe_write(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" 133 134# cirrus_vga.c 135vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" 136vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" 137vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x" 138vga_cirrus_write_gr(uint8_t index, uint8_t val) "GR addr 0x%02x, val 0x%02x" 139vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val) "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x" 140 141# sii9022.c 142sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x" 143sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x" 144sii9022_switch_mode(const char *mode) "mode: %s" 145 146# ati.c 147ati_mm_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s -> 0x%"PRIx64 148ati_mm_write(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s <- 0x%"PRIx64 149 150# artist.c 151artist_reg_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 "%s -> 0x%"PRIx64 152artist_reg_write(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 "%s <- 0x%"PRIx64 153artist_vram_read(unsigned int size, uint64_t addr, int posx, int posy, uint64_t val) "%u 0x%"PRIx64 " %ux%u-> 0x%"PRIx64 154artist_vram_write(unsigned int size, uint64_t addr, uint64_t val) "%u 0x%"PRIx64 " <- 0x%"PRIx64 155artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln) "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x" 156artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height) "source %ux%u -> dest %ux%u size %ux%u" 157artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y) "%ux%u %ux%u" 158 159# cg3.c 160cg3_read(uint32_t addr, uint32_t val, unsigned size) "read addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" 161cg3_write(uint32_t addr, uint32_t val, unsigned size) "write addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" 162 163# dpcd.c 164dpcd_read(uint32_t addr, uint8_t val) "read addr:0x%"PRIx32" val:0x%02x" 165dpcd_write(uint32_t addr, uint8_t val) "write addr:0x%"PRIx32" val:0x%02x" 166 167# sm501.c 168sm501_system_config_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 169sm501_system_config_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 170sm501_i2c_read(uint32_t addr, uint8_t val) "addr=0x%x, val=0x%x" 171sm501_i2c_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 172sm501_palette_read(uint32_t addr) "addr=0x%x" 173sm501_palette_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 174sm501_disp_ctrl_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 175sm501_disp_ctrl_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 176sm501_2d_engine_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 177sm501_2d_engine_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 178