1 /* 2 * QEMU TCX Frame buffer 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu-common.h" 26 #include "ui/console.h" 27 #include "ui/pixel_ops.h" 28 #include "hw/sysbus.h" 29 30 #define MAXX 1024 31 #define MAXY 768 32 #define TCX_DAC_NREGS 16 33 #define TCX_THC_NREGS_8 0x081c 34 #define TCX_THC_NREGS_24 0x1000 35 #define TCX_TEC_NREGS 0x1000 36 37 typedef struct TCXState { 38 SysBusDevice busdev; 39 QemuConsole *con; 40 uint8_t *vram; 41 uint32_t *vram24, *cplane; 42 MemoryRegion vram_mem; 43 MemoryRegion vram_8bit; 44 MemoryRegion vram_24bit; 45 MemoryRegion vram_cplane; 46 MemoryRegion dac; 47 MemoryRegion tec; 48 MemoryRegion thc24; 49 MemoryRegion thc8; 50 ram_addr_t vram24_offset, cplane_offset; 51 uint32_t vram_size; 52 uint32_t palette[256]; 53 uint8_t r[256], g[256], b[256]; 54 uint16_t width, height, depth; 55 uint8_t dac_index, dac_state; 56 } TCXState; 57 58 static void tcx_set_dirty(TCXState *s) 59 { 60 memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY); 61 } 62 63 static void tcx24_set_dirty(TCXState *s) 64 { 65 memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4); 66 memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4); 67 } 68 69 static void update_palette_entries(TCXState *s, int start, int end) 70 { 71 DisplaySurface *surface = qemu_console_surface(s->con); 72 int i; 73 74 for (i = start; i < end; i++) { 75 switch (surface_bits_per_pixel(surface)) { 76 default: 77 case 8: 78 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); 79 break; 80 case 15: 81 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); 82 break; 83 case 16: 84 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); 85 break; 86 case 32: 87 if (is_surface_bgr(surface)) { 88 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); 89 } else { 90 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); 91 } 92 break; 93 } 94 } 95 if (s->depth == 24) { 96 tcx24_set_dirty(s); 97 } else { 98 tcx_set_dirty(s); 99 } 100 } 101 102 static void tcx_draw_line32(TCXState *s1, uint8_t *d, 103 const uint8_t *s, int width) 104 { 105 int x; 106 uint8_t val; 107 uint32_t *p = (uint32_t *)d; 108 109 for(x = 0; x < width; x++) { 110 val = *s++; 111 *p++ = s1->palette[val]; 112 } 113 } 114 115 static void tcx_draw_line16(TCXState *s1, uint8_t *d, 116 const uint8_t *s, int width) 117 { 118 int x; 119 uint8_t val; 120 uint16_t *p = (uint16_t *)d; 121 122 for(x = 0; x < width; x++) { 123 val = *s++; 124 *p++ = s1->palette[val]; 125 } 126 } 127 128 static void tcx_draw_line8(TCXState *s1, uint8_t *d, 129 const uint8_t *s, int width) 130 { 131 int x; 132 uint8_t val; 133 134 for(x = 0; x < width; x++) { 135 val = *s++; 136 *d++ = s1->palette[val]; 137 } 138 } 139 140 /* 141 XXX Could be much more optimal: 142 * detect if line/page/whole screen is in 24 bit mode 143 * if destination is also BGR, use memcpy 144 */ 145 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, 146 const uint8_t *s, int width, 147 const uint32_t *cplane, 148 const uint32_t *s24) 149 { 150 DisplaySurface *surface = qemu_console_surface(s1->con); 151 int x, bgr, r, g, b; 152 uint8_t val, *p8; 153 uint32_t *p = (uint32_t *)d; 154 uint32_t dval; 155 156 bgr = is_surface_bgr(surface); 157 for(x = 0; x < width; x++, s++, s24++) { 158 if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { 159 // 24-bit direct, BGR order 160 p8 = (uint8_t *)s24; 161 p8++; 162 b = *p8++; 163 g = *p8++; 164 r = *p8; 165 if (bgr) 166 dval = rgb_to_pixel32bgr(r, g, b); 167 else 168 dval = rgb_to_pixel32(r, g, b); 169 } else { 170 val = *s; 171 dval = s1->palette[val]; 172 } 173 *p++ = dval; 174 } 175 } 176 177 static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24, 178 ram_addr_t cpage) 179 { 180 int ret; 181 182 ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE, 183 DIRTY_MEMORY_VGA); 184 ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4, 185 DIRTY_MEMORY_VGA); 186 ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4, 187 DIRTY_MEMORY_VGA); 188 return ret; 189 } 190 191 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, 192 ram_addr_t page_max, ram_addr_t page24, 193 ram_addr_t cpage) 194 { 195 memory_region_reset_dirty(&ts->vram_mem, 196 page_min, 197 (page_max - page_min) + TARGET_PAGE_SIZE, 198 DIRTY_MEMORY_VGA); 199 memory_region_reset_dirty(&ts->vram_mem, 200 page24 + page_min * 4, 201 (page_max - page_min) * 4 + TARGET_PAGE_SIZE, 202 DIRTY_MEMORY_VGA); 203 memory_region_reset_dirty(&ts->vram_mem, 204 cpage + page_min * 4, 205 (page_max - page_min) * 4 + TARGET_PAGE_SIZE, 206 DIRTY_MEMORY_VGA); 207 } 208 209 /* Fixed line length 1024 allows us to do nice tricks not possible on 210 VGA... */ 211 static void tcx_update_display(void *opaque) 212 { 213 TCXState *ts = opaque; 214 DisplaySurface *surface = qemu_console_surface(ts->con); 215 ram_addr_t page, page_min, page_max; 216 int y, y_start, dd, ds; 217 uint8_t *d, *s; 218 void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); 219 220 if (surface_bits_per_pixel(surface) == 0) { 221 return; 222 } 223 224 page = 0; 225 y_start = -1; 226 page_min = -1; 227 page_max = 0; 228 d = surface_data(surface); 229 s = ts->vram; 230 dd = surface_stride(surface); 231 ds = 1024; 232 233 switch (surface_bits_per_pixel(surface)) { 234 case 32: 235 f = tcx_draw_line32; 236 break; 237 case 15: 238 case 16: 239 f = tcx_draw_line16; 240 break; 241 default: 242 case 8: 243 f = tcx_draw_line8; 244 break; 245 case 0: 246 return; 247 } 248 249 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { 250 if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE, 251 DIRTY_MEMORY_VGA)) { 252 if (y_start < 0) 253 y_start = y; 254 if (page < page_min) 255 page_min = page; 256 if (page > page_max) 257 page_max = page; 258 f(ts, d, s, ts->width); 259 d += dd; 260 s += ds; 261 f(ts, d, s, ts->width); 262 d += dd; 263 s += ds; 264 f(ts, d, s, ts->width); 265 d += dd; 266 s += ds; 267 f(ts, d, s, ts->width); 268 d += dd; 269 s += ds; 270 } else { 271 if (y_start >= 0) { 272 /* flush to display */ 273 dpy_gfx_update(ts->con, 0, y_start, 274 ts->width, y - y_start); 275 y_start = -1; 276 } 277 d += dd * 4; 278 s += ds * 4; 279 } 280 } 281 if (y_start >= 0) { 282 /* flush to display */ 283 dpy_gfx_update(ts->con, 0, y_start, 284 ts->width, y - y_start); 285 } 286 /* reset modified pages */ 287 if (page_max >= page_min) { 288 memory_region_reset_dirty(&ts->vram_mem, 289 page_min, 290 (page_max - page_min) + TARGET_PAGE_SIZE, 291 DIRTY_MEMORY_VGA); 292 } 293 } 294 295 static void tcx24_update_display(void *opaque) 296 { 297 TCXState *ts = opaque; 298 DisplaySurface *surface = qemu_console_surface(ts->con); 299 ram_addr_t page, page_min, page_max, cpage, page24; 300 int y, y_start, dd, ds; 301 uint8_t *d, *s; 302 uint32_t *cptr, *s24; 303 304 if (surface_bits_per_pixel(surface) != 32) { 305 return; 306 } 307 308 page = 0; 309 page24 = ts->vram24_offset; 310 cpage = ts->cplane_offset; 311 y_start = -1; 312 page_min = -1; 313 page_max = 0; 314 d = surface_data(surface); 315 s = ts->vram; 316 s24 = ts->vram24; 317 cptr = ts->cplane; 318 dd = surface_stride(surface); 319 ds = 1024; 320 321 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, 322 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { 323 if (check_dirty(ts, page, page24, cpage)) { 324 if (y_start < 0) 325 y_start = y; 326 if (page < page_min) 327 page_min = page; 328 if (page > page_max) 329 page_max = page; 330 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 331 d += dd; 332 s += ds; 333 cptr += ds; 334 s24 += ds; 335 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 336 d += dd; 337 s += ds; 338 cptr += ds; 339 s24 += ds; 340 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 341 d += dd; 342 s += ds; 343 cptr += ds; 344 s24 += ds; 345 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 346 d += dd; 347 s += ds; 348 cptr += ds; 349 s24 += ds; 350 } else { 351 if (y_start >= 0) { 352 /* flush to display */ 353 dpy_gfx_update(ts->con, 0, y_start, 354 ts->width, y - y_start); 355 y_start = -1; 356 } 357 d += dd * 4; 358 s += ds * 4; 359 cptr += ds * 4; 360 s24 += ds * 4; 361 } 362 } 363 if (y_start >= 0) { 364 /* flush to display */ 365 dpy_gfx_update(ts->con, 0, y_start, 366 ts->width, y - y_start); 367 } 368 /* reset modified pages */ 369 if (page_max >= page_min) { 370 reset_dirty(ts, page_min, page_max, page24, cpage); 371 } 372 } 373 374 static void tcx_invalidate_display(void *opaque) 375 { 376 TCXState *s = opaque; 377 378 tcx_set_dirty(s); 379 qemu_console_resize(s->con, s->width, s->height); 380 } 381 382 static void tcx24_invalidate_display(void *opaque) 383 { 384 TCXState *s = opaque; 385 386 tcx_set_dirty(s); 387 tcx24_set_dirty(s); 388 qemu_console_resize(s->con, s->width, s->height); 389 } 390 391 static int vmstate_tcx_post_load(void *opaque, int version_id) 392 { 393 TCXState *s = opaque; 394 395 update_palette_entries(s, 0, 256); 396 if (s->depth == 24) { 397 tcx24_set_dirty(s); 398 } else { 399 tcx_set_dirty(s); 400 } 401 402 return 0; 403 } 404 405 static const VMStateDescription vmstate_tcx = { 406 .name ="tcx", 407 .version_id = 4, 408 .minimum_version_id = 4, 409 .minimum_version_id_old = 4, 410 .post_load = vmstate_tcx_post_load, 411 .fields = (VMStateField []) { 412 VMSTATE_UINT16(height, TCXState), 413 VMSTATE_UINT16(width, TCXState), 414 VMSTATE_UINT16(depth, TCXState), 415 VMSTATE_BUFFER(r, TCXState), 416 VMSTATE_BUFFER(g, TCXState), 417 VMSTATE_BUFFER(b, TCXState), 418 VMSTATE_UINT8(dac_index, TCXState), 419 VMSTATE_UINT8(dac_state, TCXState), 420 VMSTATE_END_OF_LIST() 421 } 422 }; 423 424 static void tcx_reset(DeviceState *d) 425 { 426 TCXState *s = container_of(d, TCXState, busdev.qdev); 427 428 /* Initialize palette */ 429 memset(s->r, 0, 256); 430 memset(s->g, 0, 256); 431 memset(s->b, 0, 256); 432 s->r[255] = s->g[255] = s->b[255] = 255; 433 update_palette_entries(s, 0, 256); 434 memset(s->vram, 0, MAXX*MAXY); 435 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), 436 DIRTY_MEMORY_VGA); 437 s->dac_index = 0; 438 s->dac_state = 0; 439 } 440 441 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, 442 unsigned size) 443 { 444 return 0; 445 } 446 447 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, 448 unsigned size) 449 { 450 TCXState *s = opaque; 451 452 switch (addr) { 453 case 0: 454 s->dac_index = val >> 24; 455 s->dac_state = 0; 456 break; 457 case 4: 458 switch (s->dac_state) { 459 case 0: 460 s->r[s->dac_index] = val >> 24; 461 update_palette_entries(s, s->dac_index, s->dac_index + 1); 462 s->dac_state++; 463 break; 464 case 1: 465 s->g[s->dac_index] = val >> 24; 466 update_palette_entries(s, s->dac_index, s->dac_index + 1); 467 s->dac_state++; 468 break; 469 case 2: 470 s->b[s->dac_index] = val >> 24; 471 update_palette_entries(s, s->dac_index, s->dac_index + 1); 472 s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement 473 default: 474 s->dac_state = 0; 475 break; 476 } 477 break; 478 default: 479 break; 480 } 481 } 482 483 static const MemoryRegionOps tcx_dac_ops = { 484 .read = tcx_dac_readl, 485 .write = tcx_dac_writel, 486 .endianness = DEVICE_NATIVE_ENDIAN, 487 .valid = { 488 .min_access_size = 4, 489 .max_access_size = 4, 490 }, 491 }; 492 493 static uint64_t dummy_readl(void *opaque, hwaddr addr, 494 unsigned size) 495 { 496 return 0; 497 } 498 499 static void dummy_writel(void *opaque, hwaddr addr, 500 uint64_t val, unsigned size) 501 { 502 } 503 504 static const MemoryRegionOps dummy_ops = { 505 .read = dummy_readl, 506 .write = dummy_writel, 507 .endianness = DEVICE_NATIVE_ENDIAN, 508 .valid = { 509 .min_access_size = 4, 510 .max_access_size = 4, 511 }, 512 }; 513 514 static const GraphicHwOps tcx_ops = { 515 .invalidate = tcx_invalidate_display, 516 .gfx_update = tcx_update_display, 517 }; 518 519 static const GraphicHwOps tcx24_ops = { 520 .invalidate = tcx24_invalidate_display, 521 .gfx_update = tcx24_update_display, 522 }; 523 524 static int tcx_init1(SysBusDevice *dev) 525 { 526 TCXState *s = FROM_SYSBUS(TCXState, dev); 527 ram_addr_t vram_offset = 0; 528 int size; 529 uint8_t *vram_base; 530 531 memory_region_init_ram(&s->vram_mem, "tcx.vram", 532 s->vram_size * (1 + 4 + 4)); 533 vmstate_register_ram_global(&s->vram_mem); 534 vram_base = memory_region_get_ram_ptr(&s->vram_mem); 535 536 /* 8-bit plane */ 537 s->vram = vram_base; 538 size = s->vram_size; 539 memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit", 540 &s->vram_mem, vram_offset, size); 541 sysbus_init_mmio(dev, &s->vram_8bit); 542 vram_offset += size; 543 vram_base += size; 544 545 /* DAC */ 546 memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS); 547 sysbus_init_mmio(dev, &s->dac); 548 549 /* TEC (dummy) */ 550 memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS); 551 sysbus_init_mmio(dev, &s->tec); 552 /* THC: NetBSD writes here even with 8-bit display: dummy */ 553 memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24", 554 TCX_THC_NREGS_24); 555 sysbus_init_mmio(dev, &s->thc24); 556 557 if (s->depth == 24) { 558 /* 24-bit plane */ 559 size = s->vram_size * 4; 560 s->vram24 = (uint32_t *)vram_base; 561 s->vram24_offset = vram_offset; 562 memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit", 563 &s->vram_mem, vram_offset, size); 564 sysbus_init_mmio(dev, &s->vram_24bit); 565 vram_offset += size; 566 vram_base += size; 567 568 /* Control plane */ 569 size = s->vram_size * 4; 570 s->cplane = (uint32_t *)vram_base; 571 s->cplane_offset = vram_offset; 572 memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane", 573 &s->vram_mem, vram_offset, size); 574 sysbus_init_mmio(dev, &s->vram_cplane); 575 576 s->con = graphic_console_init(DEVICE(dev), &tcx24_ops, s); 577 } else { 578 /* THC 8 bit (dummy) */ 579 memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8", 580 TCX_THC_NREGS_8); 581 sysbus_init_mmio(dev, &s->thc8); 582 583 s->con = graphic_console_init(DEVICE(dev), &tcx_ops, s); 584 } 585 586 qemu_console_resize(s->con, s->width, s->height); 587 return 0; 588 } 589 590 static Property tcx_properties[] = { 591 DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), 592 DEFINE_PROP_UINT16("width", TCXState, width, -1), 593 DEFINE_PROP_UINT16("height", TCXState, height, -1), 594 DEFINE_PROP_UINT16("depth", TCXState, depth, -1), 595 DEFINE_PROP_END_OF_LIST(), 596 }; 597 598 static void tcx_class_init(ObjectClass *klass, void *data) 599 { 600 DeviceClass *dc = DEVICE_CLASS(klass); 601 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 602 603 k->init = tcx_init1; 604 dc->reset = tcx_reset; 605 dc->vmsd = &vmstate_tcx; 606 dc->props = tcx_properties; 607 } 608 609 static const TypeInfo tcx_info = { 610 .name = "SUNW,tcx", 611 .parent = TYPE_SYS_BUS_DEVICE, 612 .instance_size = sizeof(TCXState), 613 .class_init = tcx_class_init, 614 }; 615 616 static void tcx_register_types(void) 617 { 618 type_register_static(&tcx_info); 619 } 620 621 type_init(tcx_register_types) 622