1 /* 2 * QEMU TCX Frame buffer 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu-common.h" 26 #include "ui/console.h" 27 #include "ui/pixel_ops.h" 28 #include "hw/sysbus.h" 29 30 #define MAXX 1024 31 #define MAXY 768 32 #define TCX_DAC_NREGS 16 33 #define TCX_THC_NREGS_8 0x081c 34 #define TCX_THC_NREGS_24 0x1000 35 #define TCX_TEC_NREGS 0x1000 36 37 typedef struct TCXState { 38 SysBusDevice busdev; 39 QemuConsole *con; 40 uint8_t *vram; 41 uint32_t *vram24, *cplane; 42 MemoryRegion vram_mem; 43 MemoryRegion vram_8bit; 44 MemoryRegion vram_24bit; 45 MemoryRegion vram_cplane; 46 MemoryRegion dac; 47 MemoryRegion tec; 48 MemoryRegion thc24; 49 MemoryRegion thc8; 50 ram_addr_t vram24_offset, cplane_offset; 51 uint32_t vram_size; 52 uint32_t palette[256]; 53 uint8_t r[256], g[256], b[256]; 54 uint16_t width, height, depth; 55 uint8_t dac_index, dac_state; 56 } TCXState; 57 58 static void tcx_set_dirty(TCXState *s) 59 { 60 memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY); 61 } 62 63 static void tcx24_set_dirty(TCXState *s) 64 { 65 memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4); 66 memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4); 67 } 68 69 static void update_palette_entries(TCXState *s, int start, int end) 70 { 71 DisplaySurface *surface = qemu_console_surface(s->con); 72 int i; 73 74 for (i = start; i < end; i++) { 75 switch (surface_bits_per_pixel(surface)) { 76 default: 77 case 8: 78 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); 79 break; 80 case 15: 81 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); 82 break; 83 case 16: 84 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); 85 break; 86 case 32: 87 if (is_surface_bgr(surface)) { 88 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); 89 } else { 90 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); 91 } 92 break; 93 } 94 } 95 if (s->depth == 24) { 96 tcx24_set_dirty(s); 97 } else { 98 tcx_set_dirty(s); 99 } 100 } 101 102 static void tcx_draw_line32(TCXState *s1, uint8_t *d, 103 const uint8_t *s, int width) 104 { 105 int x; 106 uint8_t val; 107 uint32_t *p = (uint32_t *)d; 108 109 for(x = 0; x < width; x++) { 110 val = *s++; 111 *p++ = s1->palette[val]; 112 } 113 } 114 115 static void tcx_draw_line16(TCXState *s1, uint8_t *d, 116 const uint8_t *s, int width) 117 { 118 int x; 119 uint8_t val; 120 uint16_t *p = (uint16_t *)d; 121 122 for(x = 0; x < width; x++) { 123 val = *s++; 124 *p++ = s1->palette[val]; 125 } 126 } 127 128 static void tcx_draw_line8(TCXState *s1, uint8_t *d, 129 const uint8_t *s, int width) 130 { 131 int x; 132 uint8_t val; 133 134 for(x = 0; x < width; x++) { 135 val = *s++; 136 *d++ = s1->palette[val]; 137 } 138 } 139 140 /* 141 XXX Could be much more optimal: 142 * detect if line/page/whole screen is in 24 bit mode 143 * if destination is also BGR, use memcpy 144 */ 145 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, 146 const uint8_t *s, int width, 147 const uint32_t *cplane, 148 const uint32_t *s24) 149 { 150 DisplaySurface *surface = qemu_console_surface(s1->con); 151 int x, bgr, r, g, b; 152 uint8_t val, *p8; 153 uint32_t *p = (uint32_t *)d; 154 uint32_t dval; 155 156 bgr = is_surface_bgr(surface); 157 for(x = 0; x < width; x++, s++, s24++) { 158 if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { 159 // 24-bit direct, BGR order 160 p8 = (uint8_t *)s24; 161 p8++; 162 b = *p8++; 163 g = *p8++; 164 r = *p8; 165 if (bgr) 166 dval = rgb_to_pixel32bgr(r, g, b); 167 else 168 dval = rgb_to_pixel32(r, g, b); 169 } else { 170 val = *s; 171 dval = s1->palette[val]; 172 } 173 *p++ = dval; 174 } 175 } 176 177 static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24, 178 ram_addr_t cpage) 179 { 180 int ret; 181 182 ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE, 183 DIRTY_MEMORY_VGA); 184 ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4, 185 DIRTY_MEMORY_VGA); 186 ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4, 187 DIRTY_MEMORY_VGA); 188 return ret; 189 } 190 191 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, 192 ram_addr_t page_max, ram_addr_t page24, 193 ram_addr_t cpage) 194 { 195 memory_region_reset_dirty(&ts->vram_mem, 196 page_min, page_max + TARGET_PAGE_SIZE, 197 DIRTY_MEMORY_VGA); 198 memory_region_reset_dirty(&ts->vram_mem, 199 page24 + page_min * 4, 200 page24 + page_max * 4 + TARGET_PAGE_SIZE, 201 DIRTY_MEMORY_VGA); 202 memory_region_reset_dirty(&ts->vram_mem, 203 cpage + page_min * 4, 204 cpage + page_max * 4 + TARGET_PAGE_SIZE, 205 DIRTY_MEMORY_VGA); 206 } 207 208 /* Fixed line length 1024 allows us to do nice tricks not possible on 209 VGA... */ 210 static void tcx_update_display(void *opaque) 211 { 212 TCXState *ts = opaque; 213 DisplaySurface *surface = qemu_console_surface(ts->con); 214 ram_addr_t page, page_min, page_max; 215 int y, y_start, dd, ds; 216 uint8_t *d, *s; 217 void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); 218 219 if (surface_bits_per_pixel(surface) == 0) { 220 return; 221 } 222 223 page = 0; 224 y_start = -1; 225 page_min = -1; 226 page_max = 0; 227 d = surface_data(surface); 228 s = ts->vram; 229 dd = surface_stride(surface); 230 ds = 1024; 231 232 switch (surface_bits_per_pixel(surface)) { 233 case 32: 234 f = tcx_draw_line32; 235 break; 236 case 15: 237 case 16: 238 f = tcx_draw_line16; 239 break; 240 default: 241 case 8: 242 f = tcx_draw_line8; 243 break; 244 case 0: 245 return; 246 } 247 248 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { 249 if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE, 250 DIRTY_MEMORY_VGA)) { 251 if (y_start < 0) 252 y_start = y; 253 if (page < page_min) 254 page_min = page; 255 if (page > page_max) 256 page_max = page; 257 f(ts, d, s, ts->width); 258 d += dd; 259 s += ds; 260 f(ts, d, s, ts->width); 261 d += dd; 262 s += ds; 263 f(ts, d, s, ts->width); 264 d += dd; 265 s += ds; 266 f(ts, d, s, ts->width); 267 d += dd; 268 s += ds; 269 } else { 270 if (y_start >= 0) { 271 /* flush to display */ 272 dpy_gfx_update(ts->con, 0, y_start, 273 ts->width, y - y_start); 274 y_start = -1; 275 } 276 d += dd * 4; 277 s += ds * 4; 278 } 279 } 280 if (y_start >= 0) { 281 /* flush to display */ 282 dpy_gfx_update(ts->con, 0, y_start, 283 ts->width, y - y_start); 284 } 285 /* reset modified pages */ 286 if (page_max >= page_min) { 287 memory_region_reset_dirty(&ts->vram_mem, 288 page_min, page_max + TARGET_PAGE_SIZE, 289 DIRTY_MEMORY_VGA); 290 } 291 } 292 293 static void tcx24_update_display(void *opaque) 294 { 295 TCXState *ts = opaque; 296 DisplaySurface *surface = qemu_console_surface(ts->con); 297 ram_addr_t page, page_min, page_max, cpage, page24; 298 int y, y_start, dd, ds; 299 uint8_t *d, *s; 300 uint32_t *cptr, *s24; 301 302 if (surface_bits_per_pixel(surface) != 32) { 303 return; 304 } 305 306 page = 0; 307 page24 = ts->vram24_offset; 308 cpage = ts->cplane_offset; 309 y_start = -1; 310 page_min = -1; 311 page_max = 0; 312 d = surface_data(surface); 313 s = ts->vram; 314 s24 = ts->vram24; 315 cptr = ts->cplane; 316 dd = surface_stride(surface); 317 ds = 1024; 318 319 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, 320 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { 321 if (check_dirty(ts, page, page24, cpage)) { 322 if (y_start < 0) 323 y_start = y; 324 if (page < page_min) 325 page_min = page; 326 if (page > page_max) 327 page_max = page; 328 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 329 d += dd; 330 s += ds; 331 cptr += ds; 332 s24 += ds; 333 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 334 d += dd; 335 s += ds; 336 cptr += ds; 337 s24 += ds; 338 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 339 d += dd; 340 s += ds; 341 cptr += ds; 342 s24 += ds; 343 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 344 d += dd; 345 s += ds; 346 cptr += ds; 347 s24 += ds; 348 } else { 349 if (y_start >= 0) { 350 /* flush to display */ 351 dpy_gfx_update(ts->con, 0, y_start, 352 ts->width, y - y_start); 353 y_start = -1; 354 } 355 d += dd * 4; 356 s += ds * 4; 357 cptr += ds * 4; 358 s24 += ds * 4; 359 } 360 } 361 if (y_start >= 0) { 362 /* flush to display */ 363 dpy_gfx_update(ts->con, 0, y_start, 364 ts->width, y - y_start); 365 } 366 /* reset modified pages */ 367 if (page_max >= page_min) { 368 reset_dirty(ts, page_min, page_max, page24, cpage); 369 } 370 } 371 372 static void tcx_invalidate_display(void *opaque) 373 { 374 TCXState *s = opaque; 375 376 tcx_set_dirty(s); 377 qemu_console_resize(s->con, s->width, s->height); 378 } 379 380 static void tcx24_invalidate_display(void *opaque) 381 { 382 TCXState *s = opaque; 383 384 tcx_set_dirty(s); 385 tcx24_set_dirty(s); 386 qemu_console_resize(s->con, s->width, s->height); 387 } 388 389 static int vmstate_tcx_post_load(void *opaque, int version_id) 390 { 391 TCXState *s = opaque; 392 393 update_palette_entries(s, 0, 256); 394 if (s->depth == 24) { 395 tcx24_set_dirty(s); 396 } else { 397 tcx_set_dirty(s); 398 } 399 400 return 0; 401 } 402 403 static const VMStateDescription vmstate_tcx = { 404 .name ="tcx", 405 .version_id = 4, 406 .minimum_version_id = 4, 407 .minimum_version_id_old = 4, 408 .post_load = vmstate_tcx_post_load, 409 .fields = (VMStateField []) { 410 VMSTATE_UINT16(height, TCXState), 411 VMSTATE_UINT16(width, TCXState), 412 VMSTATE_UINT16(depth, TCXState), 413 VMSTATE_BUFFER(r, TCXState), 414 VMSTATE_BUFFER(g, TCXState), 415 VMSTATE_BUFFER(b, TCXState), 416 VMSTATE_UINT8(dac_index, TCXState), 417 VMSTATE_UINT8(dac_state, TCXState), 418 VMSTATE_END_OF_LIST() 419 } 420 }; 421 422 static void tcx_reset(DeviceState *d) 423 { 424 TCXState *s = container_of(d, TCXState, busdev.qdev); 425 426 /* Initialize palette */ 427 memset(s->r, 0, 256); 428 memset(s->g, 0, 256); 429 memset(s->b, 0, 256); 430 s->r[255] = s->g[255] = s->b[255] = 255; 431 update_palette_entries(s, 0, 256); 432 memset(s->vram, 0, MAXX*MAXY); 433 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), 434 DIRTY_MEMORY_VGA); 435 s->dac_index = 0; 436 s->dac_state = 0; 437 } 438 439 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, 440 unsigned size) 441 { 442 return 0; 443 } 444 445 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, 446 unsigned size) 447 { 448 TCXState *s = opaque; 449 450 switch (addr) { 451 case 0: 452 s->dac_index = val >> 24; 453 s->dac_state = 0; 454 break; 455 case 4: 456 switch (s->dac_state) { 457 case 0: 458 s->r[s->dac_index] = val >> 24; 459 update_palette_entries(s, s->dac_index, s->dac_index + 1); 460 s->dac_state++; 461 break; 462 case 1: 463 s->g[s->dac_index] = val >> 24; 464 update_palette_entries(s, s->dac_index, s->dac_index + 1); 465 s->dac_state++; 466 break; 467 case 2: 468 s->b[s->dac_index] = val >> 24; 469 update_palette_entries(s, s->dac_index, s->dac_index + 1); 470 s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement 471 default: 472 s->dac_state = 0; 473 break; 474 } 475 break; 476 default: 477 break; 478 } 479 } 480 481 static const MemoryRegionOps tcx_dac_ops = { 482 .read = tcx_dac_readl, 483 .write = tcx_dac_writel, 484 .endianness = DEVICE_NATIVE_ENDIAN, 485 .valid = { 486 .min_access_size = 4, 487 .max_access_size = 4, 488 }, 489 }; 490 491 static uint64_t dummy_readl(void *opaque, hwaddr addr, 492 unsigned size) 493 { 494 return 0; 495 } 496 497 static void dummy_writel(void *opaque, hwaddr addr, 498 uint64_t val, unsigned size) 499 { 500 } 501 502 static const MemoryRegionOps dummy_ops = { 503 .read = dummy_readl, 504 .write = dummy_writel, 505 .endianness = DEVICE_NATIVE_ENDIAN, 506 .valid = { 507 .min_access_size = 4, 508 .max_access_size = 4, 509 }, 510 }; 511 512 static const GraphicHwOps tcx_ops = { 513 .invalidate = tcx_invalidate_display, 514 .gfx_update = tcx_update_display, 515 }; 516 517 static const GraphicHwOps tcx24_ops = { 518 .invalidate = tcx24_invalidate_display, 519 .gfx_update = tcx24_update_display, 520 }; 521 522 static int tcx_init1(SysBusDevice *dev) 523 { 524 TCXState *s = FROM_SYSBUS(TCXState, dev); 525 ram_addr_t vram_offset = 0; 526 int size; 527 uint8_t *vram_base; 528 529 memory_region_init_ram(&s->vram_mem, "tcx.vram", 530 s->vram_size * (1 + 4 + 4)); 531 vmstate_register_ram_global(&s->vram_mem); 532 vram_base = memory_region_get_ram_ptr(&s->vram_mem); 533 534 /* 8-bit plane */ 535 s->vram = vram_base; 536 size = s->vram_size; 537 memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit", 538 &s->vram_mem, vram_offset, size); 539 sysbus_init_mmio(dev, &s->vram_8bit); 540 vram_offset += size; 541 vram_base += size; 542 543 /* DAC */ 544 memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS); 545 sysbus_init_mmio(dev, &s->dac); 546 547 /* TEC (dummy) */ 548 memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS); 549 sysbus_init_mmio(dev, &s->tec); 550 /* THC: NetBSD writes here even with 8-bit display: dummy */ 551 memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24", 552 TCX_THC_NREGS_24); 553 sysbus_init_mmio(dev, &s->thc24); 554 555 if (s->depth == 24) { 556 /* 24-bit plane */ 557 size = s->vram_size * 4; 558 s->vram24 = (uint32_t *)vram_base; 559 s->vram24_offset = vram_offset; 560 memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit", 561 &s->vram_mem, vram_offset, size); 562 sysbus_init_mmio(dev, &s->vram_24bit); 563 vram_offset += size; 564 vram_base += size; 565 566 /* Control plane */ 567 size = s->vram_size * 4; 568 s->cplane = (uint32_t *)vram_base; 569 s->cplane_offset = vram_offset; 570 memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane", 571 &s->vram_mem, vram_offset, size); 572 sysbus_init_mmio(dev, &s->vram_cplane); 573 574 s->con = graphic_console_init(DEVICE(dev), &tcx24_ops, s); 575 } else { 576 /* THC 8 bit (dummy) */ 577 memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8", 578 TCX_THC_NREGS_8); 579 sysbus_init_mmio(dev, &s->thc8); 580 581 s->con = graphic_console_init(DEVICE(dev), &tcx_ops, s); 582 } 583 584 qemu_console_resize(s->con, s->width, s->height); 585 return 0; 586 } 587 588 static Property tcx_properties[] = { 589 DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), 590 DEFINE_PROP_UINT16("width", TCXState, width, -1), 591 DEFINE_PROP_UINT16("height", TCXState, height, -1), 592 DEFINE_PROP_UINT16("depth", TCXState, depth, -1), 593 DEFINE_PROP_END_OF_LIST(), 594 }; 595 596 static void tcx_class_init(ObjectClass *klass, void *data) 597 { 598 DeviceClass *dc = DEVICE_CLASS(klass); 599 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 600 601 k->init = tcx_init1; 602 dc->reset = tcx_reset; 603 dc->vmsd = &vmstate_tcx; 604 dc->props = tcx_properties; 605 } 606 607 static const TypeInfo tcx_info = { 608 .name = "SUNW,tcx", 609 .parent = TYPE_SYS_BUS_DEVICE, 610 .instance_size = sizeof(TCXState), 611 .class_init = tcx_class_init, 612 }; 613 614 static void tcx_register_types(void) 615 { 616 type_register_static(&tcx_info); 617 } 618 619 type_init(tcx_register_types) 620