1 /* 2 * QEMU TCX Frame buffer 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu-common.h" 28 #include "ui/console.h" 29 #include "ui/pixel_ops.h" 30 #include "hw/loader.h" 31 #include "hw/sysbus.h" 32 #include "qemu/error-report.h" 33 34 #define TCX_ROM_FILE "QEMU,tcx.bin" 35 #define FCODE_MAX_ROM_SIZE 0x10000 36 37 #define MAXX 1024 38 #define MAXY 768 39 #define TCX_DAC_NREGS 16 40 #define TCX_THC_NREGS 0x1000 41 #define TCX_DHC_NREGS 0x4000 42 #define TCX_TEC_NREGS 0x1000 43 #define TCX_ALT_NREGS 0x8000 44 #define TCX_STIP_NREGS 0x800000 45 #define TCX_BLIT_NREGS 0x800000 46 #define TCX_RSTIP_NREGS 0x800000 47 #define TCX_RBLIT_NREGS 0x800000 48 49 #define TCX_THC_MISC 0x818 50 #define TCX_THC_CURSXY 0x8fc 51 #define TCX_THC_CURSMASK 0x900 52 #define TCX_THC_CURSBITS 0x980 53 54 #define TYPE_TCX "SUNW,tcx" 55 #define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX) 56 57 typedef struct TCXState { 58 SysBusDevice parent_obj; 59 60 QemuConsole *con; 61 qemu_irq irq; 62 uint8_t *vram; 63 uint32_t *vram24, *cplane; 64 hwaddr prom_addr; 65 MemoryRegion rom; 66 MemoryRegion vram_mem; 67 MemoryRegion vram_8bit; 68 MemoryRegion vram_24bit; 69 MemoryRegion stip; 70 MemoryRegion blit; 71 MemoryRegion vram_cplane; 72 MemoryRegion rstip; 73 MemoryRegion rblit; 74 MemoryRegion tec; 75 MemoryRegion dac; 76 MemoryRegion thc; 77 MemoryRegion dhc; 78 MemoryRegion alt; 79 MemoryRegion thc24; 80 81 ram_addr_t vram24_offset, cplane_offset; 82 uint32_t tmpblit; 83 uint32_t vram_size; 84 uint32_t palette[260]; 85 uint8_t r[260], g[260], b[260]; 86 uint16_t width, height, depth; 87 uint8_t dac_index, dac_state; 88 uint32_t thcmisc; 89 uint32_t cursmask[32]; 90 uint32_t cursbits[32]; 91 uint16_t cursx; 92 uint16_t cursy; 93 } TCXState; 94 95 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len) 96 { 97 memory_region_set_dirty(&s->vram_mem, addr, len); 98 99 if (s->depth == 24) { 100 memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4, 101 len * 4); 102 memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4, 103 len * 4); 104 } 105 } 106 107 static int tcx_check_dirty(TCXState *s, ram_addr_t addr, int len) 108 { 109 int ret; 110 111 ret = memory_region_get_dirty(&s->vram_mem, addr, len, DIRTY_MEMORY_VGA); 112 113 if (s->depth == 24) { 114 ret |= memory_region_get_dirty(&s->vram_mem, 115 s->vram24_offset + addr * 4, len * 4, 116 DIRTY_MEMORY_VGA); 117 ret |= memory_region_get_dirty(&s->vram_mem, 118 s->cplane_offset + addr * 4, len * 4, 119 DIRTY_MEMORY_VGA); 120 } 121 122 return ret; 123 } 124 125 static void tcx_reset_dirty(TCXState *s, ram_addr_t addr, int len) 126 { 127 memory_region_reset_dirty(&s->vram_mem, addr, len, DIRTY_MEMORY_VGA); 128 129 if (s->depth == 24) { 130 memory_region_reset_dirty(&s->vram_mem, s->vram24_offset + addr * 4, 131 len * 4, DIRTY_MEMORY_VGA); 132 memory_region_reset_dirty(&s->vram_mem, s->cplane_offset + addr * 4, 133 len * 4, DIRTY_MEMORY_VGA); 134 } 135 } 136 137 static void update_palette_entries(TCXState *s, int start, int end) 138 { 139 DisplaySurface *surface = qemu_console_surface(s->con); 140 int i; 141 142 for (i = start; i < end; i++) { 143 if (is_surface_bgr(surface)) { 144 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); 145 } else { 146 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); 147 } 148 } 149 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 150 } 151 152 static void tcx_draw_line32(TCXState *s1, uint8_t *d, 153 const uint8_t *s, int width) 154 { 155 int x; 156 uint8_t val; 157 uint32_t *p = (uint32_t *)d; 158 159 for (x = 0; x < width; x++) { 160 val = *s++; 161 *p++ = s1->palette[val]; 162 } 163 } 164 165 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d, 166 int y, int width) 167 { 168 int x, len; 169 uint32_t mask, bits; 170 uint32_t *p = (uint32_t *)d; 171 172 y = y - s1->cursy; 173 mask = s1->cursmask[y]; 174 bits = s1->cursbits[y]; 175 len = MIN(width - s1->cursx, 32); 176 p = &p[s1->cursx]; 177 for (x = 0; x < len; x++) { 178 if (mask & 0x80000000) { 179 if (bits & 0x80000000) { 180 *p = s1->palette[259]; 181 } else { 182 *p = s1->palette[258]; 183 } 184 } 185 p++; 186 mask <<= 1; 187 bits <<= 1; 188 } 189 } 190 191 /* 192 XXX Could be much more optimal: 193 * detect if line/page/whole screen is in 24 bit mode 194 * if destination is also BGR, use memcpy 195 */ 196 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, 197 const uint8_t *s, int width, 198 const uint32_t *cplane, 199 const uint32_t *s24) 200 { 201 DisplaySurface *surface = qemu_console_surface(s1->con); 202 int x, bgr, r, g, b; 203 uint8_t val, *p8; 204 uint32_t *p = (uint32_t *)d; 205 uint32_t dval; 206 bgr = is_surface_bgr(surface); 207 for(x = 0; x < width; x++, s++, s24++) { 208 if (be32_to_cpu(*cplane) & 0x03000000) { 209 /* 24-bit direct, BGR order */ 210 p8 = (uint8_t *)s24; 211 p8++; 212 b = *p8++; 213 g = *p8++; 214 r = *p8; 215 if (bgr) 216 dval = rgb_to_pixel32bgr(r, g, b); 217 else 218 dval = rgb_to_pixel32(r, g, b); 219 } else { 220 /* 8-bit pseudocolor */ 221 val = *s; 222 dval = s1->palette[val]; 223 } 224 *p++ = dval; 225 cplane++; 226 } 227 } 228 229 /* Fixed line length 1024 allows us to do nice tricks not possible on 230 VGA... */ 231 232 static void tcx_update_display(void *opaque) 233 { 234 TCXState *ts = opaque; 235 DisplaySurface *surface = qemu_console_surface(ts->con); 236 ram_addr_t page, page_min, page_max; 237 int y, y_start, dd, ds; 238 uint8_t *d, *s; 239 240 if (surface_bits_per_pixel(surface) != 32) { 241 return; 242 } 243 244 page = 0; 245 y_start = -1; 246 page_min = -1; 247 page_max = 0; 248 d = surface_data(surface); 249 s = ts->vram; 250 dd = surface_stride(surface); 251 ds = 1024; 252 253 memory_region_sync_dirty_bitmap(&ts->vram_mem); 254 for (y = 0; y < ts->height; y++, page += ds) { 255 if (tcx_check_dirty(ts, page, ds)) { 256 if (y_start < 0) 257 y_start = y; 258 if (page < page_min) 259 page_min = page; 260 if (page > page_max) 261 page_max = page; 262 263 tcx_draw_line32(ts, d, s, ts->width); 264 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { 265 tcx_draw_cursor32(ts, d, y, ts->width); 266 } 267 } else { 268 if (y_start >= 0) { 269 /* flush to display */ 270 dpy_gfx_update(ts->con, 0, y_start, 271 ts->width, y - y_start); 272 y_start = -1; 273 } 274 } 275 s += ds; 276 d += dd; 277 } 278 if (y_start >= 0) { 279 /* flush to display */ 280 dpy_gfx_update(ts->con, 0, y_start, 281 ts->width, y - y_start); 282 } 283 /* reset modified pages */ 284 if (page_max >= page_min) { 285 tcx_reset_dirty(ts, page_min, page_max - page_min); 286 } 287 } 288 289 static void tcx24_update_display(void *opaque) 290 { 291 TCXState *ts = opaque; 292 DisplaySurface *surface = qemu_console_surface(ts->con); 293 ram_addr_t page, page_min, page_max; 294 int y, y_start, dd, ds; 295 uint8_t *d, *s; 296 uint32_t *cptr, *s24; 297 298 if (surface_bits_per_pixel(surface) != 32) { 299 return; 300 } 301 302 page = 0; 303 y_start = -1; 304 page_min = -1; 305 page_max = 0; 306 d = surface_data(surface); 307 s = ts->vram; 308 s24 = ts->vram24; 309 cptr = ts->cplane; 310 dd = surface_stride(surface); 311 ds = 1024; 312 313 memory_region_sync_dirty_bitmap(&ts->vram_mem); 314 for (y = 0; y < ts->height; y++, page += ds) { 315 if (tcx_check_dirty(ts, page, ds)) { 316 if (y_start < 0) 317 y_start = y; 318 if (page < page_min) 319 page_min = page; 320 if (page > page_max) 321 page_max = page; 322 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 323 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { 324 tcx_draw_cursor32(ts, d, y, ts->width); 325 } 326 } else { 327 if (y_start >= 0) { 328 /* flush to display */ 329 dpy_gfx_update(ts->con, 0, y_start, 330 ts->width, y - y_start); 331 y_start = -1; 332 } 333 } 334 d += dd; 335 s += ds; 336 cptr += ds; 337 s24 += ds; 338 } 339 if (y_start >= 0) { 340 /* flush to display */ 341 dpy_gfx_update(ts->con, 0, y_start, 342 ts->width, y - y_start); 343 } 344 /* reset modified pages */ 345 if (page_max >= page_min) { 346 tcx_reset_dirty(ts, page_min, page_max - page_min); 347 } 348 } 349 350 static void tcx_invalidate_display(void *opaque) 351 { 352 TCXState *s = opaque; 353 354 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 355 qemu_console_resize(s->con, s->width, s->height); 356 } 357 358 static void tcx24_invalidate_display(void *opaque) 359 { 360 TCXState *s = opaque; 361 362 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 363 qemu_console_resize(s->con, s->width, s->height); 364 } 365 366 static int vmstate_tcx_post_load(void *opaque, int version_id) 367 { 368 TCXState *s = opaque; 369 370 update_palette_entries(s, 0, 256); 371 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 372 return 0; 373 } 374 375 static const VMStateDescription vmstate_tcx = { 376 .name ="tcx", 377 .version_id = 4, 378 .minimum_version_id = 4, 379 .post_load = vmstate_tcx_post_load, 380 .fields = (VMStateField[]) { 381 VMSTATE_UINT16(height, TCXState), 382 VMSTATE_UINT16(width, TCXState), 383 VMSTATE_UINT16(depth, TCXState), 384 VMSTATE_BUFFER(r, TCXState), 385 VMSTATE_BUFFER(g, TCXState), 386 VMSTATE_BUFFER(b, TCXState), 387 VMSTATE_UINT8(dac_index, TCXState), 388 VMSTATE_UINT8(dac_state, TCXState), 389 VMSTATE_END_OF_LIST() 390 } 391 }; 392 393 static void tcx_reset(DeviceState *d) 394 { 395 TCXState *s = TCX(d); 396 397 /* Initialize palette */ 398 memset(s->r, 0, 260); 399 memset(s->g, 0, 260); 400 memset(s->b, 0, 260); 401 s->r[255] = s->g[255] = s->b[255] = 255; 402 s->r[256] = s->g[256] = s->b[256] = 255; 403 s->r[258] = s->g[258] = s->b[258] = 255; 404 update_palette_entries(s, 0, 260); 405 memset(s->vram, 0, MAXX*MAXY); 406 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), 407 DIRTY_MEMORY_VGA); 408 s->dac_index = 0; 409 s->dac_state = 0; 410 s->cursx = 0xf000; /* Put cursor off screen */ 411 s->cursy = 0xf000; 412 } 413 414 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, 415 unsigned size) 416 { 417 TCXState *s = opaque; 418 uint32_t val = 0; 419 420 switch (s->dac_state) { 421 case 0: 422 val = s->r[s->dac_index] << 24; 423 s->dac_state++; 424 break; 425 case 1: 426 val = s->g[s->dac_index] << 24; 427 s->dac_state++; 428 break; 429 case 2: 430 val = s->b[s->dac_index] << 24; 431 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 432 default: 433 s->dac_state = 0; 434 break; 435 } 436 437 return val; 438 } 439 440 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, 441 unsigned size) 442 { 443 TCXState *s = opaque; 444 unsigned index; 445 446 switch (addr) { 447 case 0: /* Address */ 448 s->dac_index = val >> 24; 449 s->dac_state = 0; 450 break; 451 case 4: /* Pixel colours */ 452 case 12: /* Overlay (cursor) colours */ 453 if (addr & 8) { 454 index = (s->dac_index & 3) + 256; 455 } else { 456 index = s->dac_index; 457 } 458 switch (s->dac_state) { 459 case 0: 460 s->r[index] = val >> 24; 461 update_palette_entries(s, index, index + 1); 462 s->dac_state++; 463 break; 464 case 1: 465 s->g[index] = val >> 24; 466 update_palette_entries(s, index, index + 1); 467 s->dac_state++; 468 break; 469 case 2: 470 s->b[index] = val >> 24; 471 update_palette_entries(s, index, index + 1); 472 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 473 default: 474 s->dac_state = 0; 475 break; 476 } 477 break; 478 default: /* Control registers */ 479 break; 480 } 481 } 482 483 static const MemoryRegionOps tcx_dac_ops = { 484 .read = tcx_dac_readl, 485 .write = tcx_dac_writel, 486 .endianness = DEVICE_NATIVE_ENDIAN, 487 .valid = { 488 .min_access_size = 4, 489 .max_access_size = 4, 490 }, 491 }; 492 493 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr, 494 unsigned size) 495 { 496 return 0; 497 } 498 499 static void tcx_stip_writel(void *opaque, hwaddr addr, 500 uint64_t val, unsigned size) 501 { 502 TCXState *s = opaque; 503 int i; 504 uint32_t col; 505 506 if (!(addr & 4)) { 507 s->tmpblit = val; 508 } else { 509 addr = (addr >> 3) & 0xfffff; 510 col = cpu_to_be32(s->tmpblit); 511 if (s->depth == 24) { 512 for (i = 0; i < 32; i++) { 513 if (val & 0x80000000) { 514 s->vram[addr + i] = s->tmpblit; 515 s->vram24[addr + i] = col; 516 } 517 val <<= 1; 518 } 519 } else { 520 for (i = 0; i < 32; i++) { 521 if (val & 0x80000000) { 522 s->vram[addr + i] = s->tmpblit; 523 } 524 val <<= 1; 525 } 526 } 527 tcx_set_dirty(s, addr, 32); 528 } 529 } 530 531 static void tcx_rstip_writel(void *opaque, hwaddr addr, 532 uint64_t val, unsigned size) 533 { 534 TCXState *s = opaque; 535 int i; 536 uint32_t col; 537 538 if (!(addr & 4)) { 539 s->tmpblit = val; 540 } else { 541 addr = (addr >> 3) & 0xfffff; 542 col = cpu_to_be32(s->tmpblit); 543 if (s->depth == 24) { 544 for (i = 0; i < 32; i++) { 545 if (val & 0x80000000) { 546 s->vram[addr + i] = s->tmpblit; 547 s->vram24[addr + i] = col; 548 s->cplane[addr + i] = col; 549 } 550 val <<= 1; 551 } 552 } else { 553 for (i = 0; i < 32; i++) { 554 if (val & 0x80000000) { 555 s->vram[addr + i] = s->tmpblit; 556 } 557 val <<= 1; 558 } 559 } 560 tcx_set_dirty(s, addr, 32); 561 } 562 } 563 564 static const MemoryRegionOps tcx_stip_ops = { 565 .read = tcx_stip_readl, 566 .write = tcx_stip_writel, 567 .endianness = DEVICE_NATIVE_ENDIAN, 568 .valid = { 569 .min_access_size = 4, 570 .max_access_size = 4, 571 }, 572 }; 573 574 static const MemoryRegionOps tcx_rstip_ops = { 575 .read = tcx_stip_readl, 576 .write = tcx_rstip_writel, 577 .endianness = DEVICE_NATIVE_ENDIAN, 578 .valid = { 579 .min_access_size = 4, 580 .max_access_size = 4, 581 }, 582 }; 583 584 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr, 585 unsigned size) 586 { 587 return 0; 588 } 589 590 static void tcx_blit_writel(void *opaque, hwaddr addr, 591 uint64_t val, unsigned size) 592 { 593 TCXState *s = opaque; 594 uint32_t adsr, len; 595 int i; 596 597 if (!(addr & 4)) { 598 s->tmpblit = val; 599 } else { 600 addr = (addr >> 3) & 0xfffff; 601 adsr = val & 0xffffff; 602 len = ((val >> 24) & 0x1f) + 1; 603 if (adsr == 0xffffff) { 604 memset(&s->vram[addr], s->tmpblit, len); 605 if (s->depth == 24) { 606 val = s->tmpblit & 0xffffff; 607 val = cpu_to_be32(val); 608 for (i = 0; i < len; i++) { 609 s->vram24[addr + i] = val; 610 } 611 } 612 } else { 613 memcpy(&s->vram[addr], &s->vram[adsr], len); 614 if (s->depth == 24) { 615 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); 616 } 617 } 618 tcx_set_dirty(s, addr, len); 619 } 620 } 621 622 static void tcx_rblit_writel(void *opaque, hwaddr addr, 623 uint64_t val, unsigned size) 624 { 625 TCXState *s = opaque; 626 uint32_t adsr, len; 627 int i; 628 629 if (!(addr & 4)) { 630 s->tmpblit = val; 631 } else { 632 addr = (addr >> 3) & 0xfffff; 633 adsr = val & 0xffffff; 634 len = ((val >> 24) & 0x1f) + 1; 635 if (adsr == 0xffffff) { 636 memset(&s->vram[addr], s->tmpblit, len); 637 if (s->depth == 24) { 638 val = s->tmpblit & 0xffffff; 639 val = cpu_to_be32(val); 640 for (i = 0; i < len; i++) { 641 s->vram24[addr + i] = val; 642 s->cplane[addr + i] = val; 643 } 644 } 645 } else { 646 memcpy(&s->vram[addr], &s->vram[adsr], len); 647 if (s->depth == 24) { 648 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); 649 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4); 650 } 651 } 652 tcx_set_dirty(s, addr, len); 653 } 654 } 655 656 static const MemoryRegionOps tcx_blit_ops = { 657 .read = tcx_blit_readl, 658 .write = tcx_blit_writel, 659 .endianness = DEVICE_NATIVE_ENDIAN, 660 .valid = { 661 .min_access_size = 4, 662 .max_access_size = 4, 663 }, 664 }; 665 666 static const MemoryRegionOps tcx_rblit_ops = { 667 .read = tcx_blit_readl, 668 .write = tcx_rblit_writel, 669 .endianness = DEVICE_NATIVE_ENDIAN, 670 .valid = { 671 .min_access_size = 4, 672 .max_access_size = 4, 673 }, 674 }; 675 676 static void tcx_invalidate_cursor_position(TCXState *s) 677 { 678 int ymin, ymax, start, end; 679 680 /* invalidate only near the cursor */ 681 ymin = s->cursy; 682 if (ymin >= s->height) { 683 return; 684 } 685 ymax = MIN(s->height, ymin + 32); 686 start = ymin * 1024; 687 end = ymax * 1024; 688 689 tcx_set_dirty(s, start, end - start); 690 } 691 692 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr, 693 unsigned size) 694 { 695 TCXState *s = opaque; 696 uint64_t val; 697 698 if (addr == TCX_THC_MISC) { 699 val = s->thcmisc | 0x02000000; 700 } else { 701 val = 0; 702 } 703 return val; 704 } 705 706 static void tcx_thc_writel(void *opaque, hwaddr addr, 707 uint64_t val, unsigned size) 708 { 709 TCXState *s = opaque; 710 711 if (addr == TCX_THC_CURSXY) { 712 tcx_invalidate_cursor_position(s); 713 s->cursx = val >> 16; 714 s->cursy = val; 715 tcx_invalidate_cursor_position(s); 716 } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) { 717 s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val; 718 tcx_invalidate_cursor_position(s); 719 } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) { 720 s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val; 721 tcx_invalidate_cursor_position(s); 722 } else if (addr == TCX_THC_MISC) { 723 s->thcmisc = val; 724 } 725 726 } 727 728 static const MemoryRegionOps tcx_thc_ops = { 729 .read = tcx_thc_readl, 730 .write = tcx_thc_writel, 731 .endianness = DEVICE_NATIVE_ENDIAN, 732 .valid = { 733 .min_access_size = 4, 734 .max_access_size = 4, 735 }, 736 }; 737 738 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr, 739 unsigned size) 740 { 741 return 0; 742 } 743 744 static void tcx_dummy_writel(void *opaque, hwaddr addr, 745 uint64_t val, unsigned size) 746 { 747 return; 748 } 749 750 static const MemoryRegionOps tcx_dummy_ops = { 751 .read = tcx_dummy_readl, 752 .write = tcx_dummy_writel, 753 .endianness = DEVICE_NATIVE_ENDIAN, 754 .valid = { 755 .min_access_size = 4, 756 .max_access_size = 4, 757 }, 758 }; 759 760 static const GraphicHwOps tcx_ops = { 761 .invalidate = tcx_invalidate_display, 762 .gfx_update = tcx_update_display, 763 }; 764 765 static const GraphicHwOps tcx24_ops = { 766 .invalidate = tcx24_invalidate_display, 767 .gfx_update = tcx24_update_display, 768 }; 769 770 static void tcx_initfn(Object *obj) 771 { 772 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 773 TCXState *s = TCX(obj); 774 775 memory_region_init_ram(&s->rom, obj, "tcx.prom", FCODE_MAX_ROM_SIZE, 776 &error_fatal); 777 memory_region_set_readonly(&s->rom, true); 778 sysbus_init_mmio(sbd, &s->rom); 779 780 /* 2/STIP : Stippler */ 781 memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip", 782 TCX_STIP_NREGS); 783 sysbus_init_mmio(sbd, &s->stip); 784 785 /* 3/BLIT : Blitter */ 786 memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit", 787 TCX_BLIT_NREGS); 788 sysbus_init_mmio(sbd, &s->blit); 789 790 /* 5/RSTIP : Raw Stippler */ 791 memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip", 792 TCX_RSTIP_NREGS); 793 sysbus_init_mmio(sbd, &s->rstip); 794 795 /* 6/RBLIT : Raw Blitter */ 796 memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit", 797 TCX_RBLIT_NREGS); 798 sysbus_init_mmio(sbd, &s->rblit); 799 800 /* 7/TEC : ??? */ 801 memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec", 802 TCX_TEC_NREGS); 803 sysbus_init_mmio(sbd, &s->tec); 804 805 /* 8/CMAP : DAC */ 806 memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac", 807 TCX_DAC_NREGS); 808 sysbus_init_mmio(sbd, &s->dac); 809 810 /* 9/THC : Cursor */ 811 memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc", 812 TCX_THC_NREGS); 813 sysbus_init_mmio(sbd, &s->thc); 814 815 /* 11/DHC : ??? */ 816 memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc", 817 TCX_DHC_NREGS); 818 sysbus_init_mmio(sbd, &s->dhc); 819 820 /* 12/ALT : ??? */ 821 memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt", 822 TCX_ALT_NREGS); 823 sysbus_init_mmio(sbd, &s->alt); 824 } 825 826 static void tcx_realizefn(DeviceState *dev, Error **errp) 827 { 828 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 829 TCXState *s = TCX(dev); 830 ram_addr_t vram_offset = 0; 831 int size, ret; 832 uint8_t *vram_base; 833 char *fcode_filename; 834 835 memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram", 836 s->vram_size * (1 + 4 + 4), &error_fatal); 837 vmstate_register_ram_global(&s->vram_mem); 838 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 839 vram_base = memory_region_get_ram_ptr(&s->vram_mem); 840 841 /* 10/ROM : FCode ROM */ 842 vmstate_register_ram_global(&s->rom); 843 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE); 844 if (fcode_filename) { 845 ret = load_image_mr(fcode_filename, &s->rom); 846 g_free(fcode_filename); 847 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 848 error_report("tcx: could not load prom '%s'", TCX_ROM_FILE); 849 } 850 } 851 852 /* 0/DFB8 : 8-bit plane */ 853 s->vram = vram_base; 854 size = s->vram_size; 855 memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit", 856 &s->vram_mem, vram_offset, size); 857 sysbus_init_mmio(sbd, &s->vram_8bit); 858 vram_offset += size; 859 vram_base += size; 860 861 /* 1/DFB24 : 24bit plane */ 862 size = s->vram_size * 4; 863 s->vram24 = (uint32_t *)vram_base; 864 s->vram24_offset = vram_offset; 865 memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit", 866 &s->vram_mem, vram_offset, size); 867 sysbus_init_mmio(sbd, &s->vram_24bit); 868 vram_offset += size; 869 vram_base += size; 870 871 /* 4/RDFB32 : Raw Framebuffer */ 872 size = s->vram_size * 4; 873 s->cplane = (uint32_t *)vram_base; 874 s->cplane_offset = vram_offset; 875 memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane", 876 &s->vram_mem, vram_offset, size); 877 sysbus_init_mmio(sbd, &s->vram_cplane); 878 879 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 880 if (s->depth == 8) { 881 memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s, 882 "tcx.thc24", TCX_THC_NREGS); 883 sysbus_init_mmio(sbd, &s->thc24); 884 } 885 886 sysbus_init_irq(sbd, &s->irq); 887 888 if (s->depth == 8) { 889 s->con = graphic_console_init(DEVICE(dev), 0, &tcx_ops, s); 890 } else { 891 s->con = graphic_console_init(DEVICE(dev), 0, &tcx24_ops, s); 892 } 893 s->thcmisc = 0; 894 895 qemu_console_resize(s->con, s->width, s->height); 896 } 897 898 static Property tcx_properties[] = { 899 DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1), 900 DEFINE_PROP_UINT16("width", TCXState, width, -1), 901 DEFINE_PROP_UINT16("height", TCXState, height, -1), 902 DEFINE_PROP_UINT16("depth", TCXState, depth, -1), 903 DEFINE_PROP_END_OF_LIST(), 904 }; 905 906 static void tcx_class_init(ObjectClass *klass, void *data) 907 { 908 DeviceClass *dc = DEVICE_CLASS(klass); 909 910 dc->realize = tcx_realizefn; 911 dc->reset = tcx_reset; 912 dc->vmsd = &vmstate_tcx; 913 dc->props = tcx_properties; 914 } 915 916 static const TypeInfo tcx_info = { 917 .name = TYPE_TCX, 918 .parent = TYPE_SYS_BUS_DEVICE, 919 .instance_size = sizeof(TCXState), 920 .instance_init = tcx_initfn, 921 .class_init = tcx_class_init, 922 }; 923 924 static void tcx_register_types(void) 925 { 926 type_register_static(&tcx_info); 927 } 928 929 type_init(tcx_register_types) 930