1 /* 2 * Toshiba TC6393XB I/O Controller. 3 * Found in Sharp Zaurus SL-6000 (tosa) or some 4 * Toshiba e-Series PDAs. 5 * 6 * Most features are currently unsupported!!! 7 * 8 * This code is licensed under the GNU GPL v2. 9 * 10 * Contributions after 2012-01-13 are licensed under the terms of the 11 * GNU GPL, version 2 or (at your option) any later version. 12 */ 13 #include "qemu/osdep.h" 14 #include "qapi/error.h" 15 #include "qemu/host-utils.h" 16 #include "hw/hw.h" 17 #include "hw/devices.h" 18 #include "hw/block/flash.h" 19 #include "ui/console.h" 20 #include "ui/pixel_ops.h" 21 #include "sysemu/block-backend.h" 22 #include "sysemu/blockdev.h" 23 24 #define IRQ_TC6393_NAND 0 25 #define IRQ_TC6393_MMC 1 26 #define IRQ_TC6393_OHCI 2 27 #define IRQ_TC6393_SERIAL 3 28 #define IRQ_TC6393_FB 4 29 30 #define TC6393XB_NR_IRQS 8 31 32 #define TC6393XB_GPIOS 16 33 34 #define SCR_REVID 0x08 /* b Revision ID */ 35 #define SCR_ISR 0x50 /* b Interrupt Status */ 36 #define SCR_IMR 0x52 /* b Interrupt Mask */ 37 #define SCR_IRR 0x54 /* b Interrupt Routing */ 38 #define SCR_GPER 0x60 /* w GP Enable */ 39 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ 40 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ 41 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ 42 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ 43 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ 44 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ 45 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ 46 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ 47 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ 48 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ 49 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ 50 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ 51 #define SCR_CCR 0x98 /* w Clock Control */ 52 #define SCR_PLL2CR 0x9a /* w PLL2 Control */ 53 #define SCR_PLL1CR 0x9c /* l PLL1 Control */ 54 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ 55 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ 56 #define SCR_FER 0xe0 /* b Function Enable */ 57 #define SCR_MCR 0xe4 /* w Mode Control */ 58 #define SCR_CONFIG 0xfc /* b Configuration Control */ 59 #define SCR_DEBUG 0xff /* b Debug */ 60 61 #define NAND_CFG_COMMAND 0x04 /* w Command */ 62 #define NAND_CFG_BASE 0x10 /* l Control Base Address */ 63 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */ 64 #define NAND_CFG_INTE 0x48 /* b Int Enable */ 65 #define NAND_CFG_EC 0x4a /* b Event Control */ 66 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */ 67 #define NAND_CFG_ECCC 0x5b /* b ECC Control */ 68 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */ 69 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */ 70 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */ 71 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */ 72 73 #define NAND_DATA 0x00 /* l Data */ 74 #define NAND_MODE 0x04 /* b Mode */ 75 #define NAND_STATUS 0x05 /* b Status */ 76 #define NAND_ISR 0x06 /* b Interrupt Status */ 77 #define NAND_IMR 0x07 /* b Interrupt Mask */ 78 79 #define NAND_MODE_WP 0x80 80 #define NAND_MODE_CE 0x10 81 #define NAND_MODE_ALE 0x02 82 #define NAND_MODE_CLE 0x01 83 #define NAND_MODE_ECC_MASK 0x60 84 #define NAND_MODE_ECC_EN 0x20 85 #define NAND_MODE_ECC_READ 0x40 86 #define NAND_MODE_ECC_RST 0x60 87 88 struct TC6393xbState { 89 MemoryRegion iomem; 90 qemu_irq irq; 91 qemu_irq *sub_irqs; 92 struct { 93 uint8_t ISR; 94 uint8_t IMR; 95 uint8_t IRR; 96 uint16_t GPER; 97 uint8_t GPI_SR[3]; 98 uint8_t GPI_IMR[3]; 99 uint8_t GPI_EDER[3]; 100 uint8_t GPI_LIR[3]; 101 uint8_t GP_IARCR[3]; 102 uint8_t GP_IARLCR[3]; 103 uint8_t GPI_BCR[3]; 104 uint16_t GPA_IARCR; 105 uint16_t GPA_IARLCR; 106 uint16_t CCR; 107 uint16_t PLL2CR; 108 uint32_t PLL1CR; 109 uint8_t DIARCR; 110 uint8_t DBOCR; 111 uint8_t FER; 112 uint16_t MCR; 113 uint8_t CONFIG; 114 uint8_t DEBUG; 115 } scr; 116 uint32_t gpio_dir; 117 uint32_t gpio_level; 118 uint32_t prev_level; 119 qemu_irq handler[TC6393XB_GPIOS]; 120 qemu_irq *gpio_in; 121 122 struct { 123 uint8_t mode; 124 uint8_t isr; 125 uint8_t imr; 126 } nand; 127 int nand_enable; 128 uint32_t nand_phys; 129 DeviceState *flash; 130 ECCState ecc; 131 132 QemuConsole *con; 133 MemoryRegion vram; 134 uint16_t *vram_ptr; 135 uint32_t scr_width, scr_height; /* in pixels */ 136 qemu_irq l3v; 137 unsigned blank : 1, 138 blanked : 1; 139 }; 140 141 qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s) 142 { 143 return s->gpio_in; 144 } 145 146 static void tc6393xb_gpio_set(void *opaque, int line, int level) 147 { 148 // TC6393xbState *s = opaque; 149 150 if (line > TC6393XB_GPIOS) { 151 printf("%s: No GPIO pin %i\n", __func__, line); 152 return; 153 } 154 155 // FIXME: how does the chip reflect the GPIO input level change? 156 } 157 158 void tc6393xb_gpio_out_set(TC6393xbState *s, int line, 159 qemu_irq handler) 160 { 161 if (line >= TC6393XB_GPIOS) { 162 fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line); 163 return; 164 } 165 166 s->handler[line] = handler; 167 } 168 169 static void tc6393xb_gpio_handler_update(TC6393xbState *s) 170 { 171 uint32_t level, diff; 172 int bit; 173 174 level = s->gpio_level & s->gpio_dir; 175 level &= MAKE_64BIT_MASK(0, TC6393XB_GPIOS); 176 177 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 178 bit = ctz32(diff); 179 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 180 } 181 182 s->prev_level = level; 183 } 184 185 qemu_irq tc6393xb_l3v_get(TC6393xbState *s) 186 { 187 return s->l3v; 188 } 189 190 static void tc6393xb_l3v(void *opaque, int line, int level) 191 { 192 TC6393xbState *s = opaque; 193 s->blank = !level; 194 fprintf(stderr, "L3V: %d\n", level); 195 } 196 197 static void tc6393xb_sub_irq(void *opaque, int line, int level) { 198 TC6393xbState *s = opaque; 199 uint8_t isr = s->scr.ISR; 200 if (level) 201 isr |= 1 << line; 202 else 203 isr &= ~(1 << line); 204 s->scr.ISR = isr; 205 qemu_set_irq(s->irq, isr & s->scr.IMR); 206 } 207 208 #define SCR_REG_B(N) \ 209 case SCR_ ##N: return s->scr.N 210 #define SCR_REG_W(N) \ 211 case SCR_ ##N: return s->scr.N; \ 212 case SCR_ ##N + 1: return s->scr.N >> 8; 213 #define SCR_REG_L(N) \ 214 case SCR_ ##N: return s->scr.N; \ 215 case SCR_ ##N + 1: return s->scr.N >> 8; \ 216 case SCR_ ##N + 2: return s->scr.N >> 16; \ 217 case SCR_ ##N + 3: return s->scr.N >> 24; 218 #define SCR_REG_A(N) \ 219 case SCR_ ##N(0): return s->scr.N[0]; \ 220 case SCR_ ##N(1): return s->scr.N[1]; \ 221 case SCR_ ##N(2): return s->scr.N[2] 222 223 static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr) 224 { 225 switch (addr) { 226 case SCR_REVID: 227 return 3; 228 case SCR_REVID+1: 229 return 0; 230 SCR_REG_B(ISR); 231 SCR_REG_B(IMR); 232 SCR_REG_B(IRR); 233 SCR_REG_W(GPER); 234 SCR_REG_A(GPI_SR); 235 SCR_REG_A(GPI_IMR); 236 SCR_REG_A(GPI_EDER); 237 SCR_REG_A(GPI_LIR); 238 case SCR_GPO_DSR(0): 239 case SCR_GPO_DSR(1): 240 case SCR_GPO_DSR(2): 241 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff; 242 case SCR_GPO_DOECR(0): 243 case SCR_GPO_DOECR(1): 244 case SCR_GPO_DOECR(2): 245 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff; 246 SCR_REG_A(GP_IARCR); 247 SCR_REG_A(GP_IARLCR); 248 SCR_REG_A(GPI_BCR); 249 SCR_REG_W(GPA_IARCR); 250 SCR_REG_W(GPA_IARLCR); 251 SCR_REG_W(CCR); 252 SCR_REG_W(PLL2CR); 253 SCR_REG_L(PLL1CR); 254 SCR_REG_B(DIARCR); 255 SCR_REG_B(DBOCR); 256 SCR_REG_B(FER); 257 SCR_REG_W(MCR); 258 SCR_REG_B(CONFIG); 259 SCR_REG_B(DEBUG); 260 } 261 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr); 262 return 0; 263 } 264 #undef SCR_REG_B 265 #undef SCR_REG_W 266 #undef SCR_REG_L 267 #undef SCR_REG_A 268 269 #define SCR_REG_B(N) \ 270 case SCR_ ##N: s->scr.N = value; return; 271 #define SCR_REG_W(N) \ 272 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ 273 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return 274 #define SCR_REG_L(N) \ 275 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ 276 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \ 277 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \ 278 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return; 279 #define SCR_REG_A(N) \ 280 case SCR_ ##N(0): s->scr.N[0] = value; return; \ 281 case SCR_ ##N(1): s->scr.N[1] = value; return; \ 282 case SCR_ ##N(2): s->scr.N[2] = value; return 283 284 static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) 285 { 286 switch (addr) { 287 SCR_REG_B(ISR); 288 SCR_REG_B(IMR); 289 SCR_REG_B(IRR); 290 SCR_REG_W(GPER); 291 SCR_REG_A(GPI_SR); 292 SCR_REG_A(GPI_IMR); 293 SCR_REG_A(GPI_EDER); 294 SCR_REG_A(GPI_LIR); 295 case SCR_GPO_DSR(0): 296 case SCR_GPO_DSR(1): 297 case SCR_GPO_DSR(2): 298 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8)); 299 tc6393xb_gpio_handler_update(s); 300 return; 301 case SCR_GPO_DOECR(0): 302 case SCR_GPO_DOECR(1): 303 case SCR_GPO_DOECR(2): 304 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8)); 305 tc6393xb_gpio_handler_update(s); 306 return; 307 SCR_REG_A(GP_IARCR); 308 SCR_REG_A(GP_IARLCR); 309 SCR_REG_A(GPI_BCR); 310 SCR_REG_W(GPA_IARCR); 311 SCR_REG_W(GPA_IARLCR); 312 SCR_REG_W(CCR); 313 SCR_REG_W(PLL2CR); 314 SCR_REG_L(PLL1CR); 315 SCR_REG_B(DIARCR); 316 SCR_REG_B(DBOCR); 317 SCR_REG_B(FER); 318 SCR_REG_W(MCR); 319 SCR_REG_B(CONFIG); 320 SCR_REG_B(DEBUG); 321 } 322 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n", 323 (uint32_t) addr, value & 0xff); 324 } 325 #undef SCR_REG_B 326 #undef SCR_REG_W 327 #undef SCR_REG_L 328 #undef SCR_REG_A 329 330 static void tc6393xb_nand_irq(TC6393xbState *s) { 331 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], 332 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); 333 } 334 335 static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) { 336 switch (addr) { 337 case NAND_CFG_COMMAND: 338 return s->nand_enable ? 2 : 0; 339 case NAND_CFG_BASE: 340 case NAND_CFG_BASE + 1: 341 case NAND_CFG_BASE + 2: 342 case NAND_CFG_BASE + 3: 343 return s->nand_phys >> (addr - NAND_CFG_BASE); 344 } 345 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr); 346 return 0; 347 } 348 static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) { 349 switch (addr) { 350 case NAND_CFG_COMMAND: 351 s->nand_enable = (value & 0x2); 352 return; 353 case NAND_CFG_BASE: 354 case NAND_CFG_BASE + 1: 355 case NAND_CFG_BASE + 2: 356 case NAND_CFG_BASE + 3: 357 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8)); 358 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8); 359 return; 360 } 361 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n", 362 (uint32_t) addr, value & 0xff); 363 } 364 365 static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) { 366 switch (addr) { 367 case NAND_DATA + 0: 368 case NAND_DATA + 1: 369 case NAND_DATA + 2: 370 case NAND_DATA + 3: 371 return nand_getio(s->flash); 372 case NAND_MODE: 373 return s->nand.mode; 374 case NAND_STATUS: 375 return 0x14; 376 case NAND_ISR: 377 return s->nand.isr; 378 case NAND_IMR: 379 return s->nand.imr; 380 } 381 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr); 382 return 0; 383 } 384 static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) { 385 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n", 386 // (uint32_t) addr, value & 0xff); 387 switch (addr) { 388 case NAND_DATA + 0: 389 case NAND_DATA + 1: 390 case NAND_DATA + 2: 391 case NAND_DATA + 3: 392 nand_setio(s->flash, value); 393 s->nand.isr |= 1; 394 tc6393xb_nand_irq(s); 395 return; 396 case NAND_MODE: 397 s->nand.mode = value; 398 nand_setpins(s->flash, 399 value & NAND_MODE_CLE, 400 value & NAND_MODE_ALE, 401 !(value & NAND_MODE_CE), 402 value & NAND_MODE_WP, 403 0); // FIXME: gnd 404 switch (value & NAND_MODE_ECC_MASK) { 405 case NAND_MODE_ECC_RST: 406 ecc_reset(&s->ecc); 407 break; 408 case NAND_MODE_ECC_READ: 409 // FIXME 410 break; 411 case NAND_MODE_ECC_EN: 412 ecc_reset(&s->ecc); 413 } 414 return; 415 case NAND_ISR: 416 s->nand.isr = value; 417 tc6393xb_nand_irq(s); 418 return; 419 case NAND_IMR: 420 s->nand.imr = value; 421 tc6393xb_nand_irq(s); 422 return; 423 } 424 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n", 425 (uint32_t) addr, value & 0xff); 426 } 427 428 #define BITS 8 429 #include "tc6393xb_template.h" 430 #define BITS 15 431 #include "tc6393xb_template.h" 432 #define BITS 16 433 #include "tc6393xb_template.h" 434 #define BITS 24 435 #include "tc6393xb_template.h" 436 #define BITS 32 437 #include "tc6393xb_template.h" 438 439 static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) 440 { 441 DisplaySurface *surface = qemu_console_surface(s->con); 442 443 switch (surface_bits_per_pixel(surface)) { 444 case 8: 445 tc6393xb_draw_graphic8(s); 446 break; 447 case 15: 448 tc6393xb_draw_graphic15(s); 449 break; 450 case 16: 451 tc6393xb_draw_graphic16(s); 452 break; 453 case 24: 454 tc6393xb_draw_graphic24(s); 455 break; 456 case 32: 457 tc6393xb_draw_graphic32(s); 458 break; 459 default: 460 printf("tc6393xb: unknown depth %d\n", 461 surface_bits_per_pixel(surface)); 462 return; 463 } 464 465 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height); 466 } 467 468 static void tc6393xb_draw_blank(TC6393xbState *s, int full_update) 469 { 470 DisplaySurface *surface = qemu_console_surface(s->con); 471 int i, w; 472 uint8_t *d; 473 474 if (!full_update) 475 return; 476 477 w = s->scr_width * surface_bytes_per_pixel(surface); 478 d = surface_data(surface); 479 for(i = 0; i < s->scr_height; i++) { 480 memset(d, 0, w); 481 d += surface_stride(surface); 482 } 483 484 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height); 485 } 486 487 static void tc6393xb_update_display(void *opaque) 488 { 489 TC6393xbState *s = opaque; 490 DisplaySurface *surface = qemu_console_surface(s->con); 491 int full_update; 492 493 if (s->scr_width == 0 || s->scr_height == 0) 494 return; 495 496 full_update = 0; 497 if (s->blanked != s->blank) { 498 s->blanked = s->blank; 499 full_update = 1; 500 } 501 if (s->scr_width != surface_width(surface) || 502 s->scr_height != surface_height(surface)) { 503 qemu_console_resize(s->con, s->scr_width, s->scr_height); 504 full_update = 1; 505 } 506 if (s->blanked) 507 tc6393xb_draw_blank(s, full_update); 508 else 509 tc6393xb_draw_graphic(s, full_update); 510 } 511 512 513 static uint64_t tc6393xb_readb(void *opaque, hwaddr addr, 514 unsigned size) 515 { 516 TC6393xbState *s = opaque; 517 518 switch (addr >> 8) { 519 case 0: 520 return tc6393xb_scr_readb(s, addr & 0xff); 521 case 1: 522 return tc6393xb_nand_cfg_readb(s, addr & 0xff); 523 }; 524 525 if ((addr &~0xff) == s->nand_phys && s->nand_enable) { 526 // return tc6393xb_nand_readb(s, addr & 0xff); 527 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff); 528 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d); 529 return d; 530 } 531 532 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr); 533 return 0; 534 } 535 536 static void tc6393xb_writeb(void *opaque, hwaddr addr, 537 uint64_t value, unsigned size) { 538 TC6393xbState *s = opaque; 539 540 switch (addr >> 8) { 541 case 0: 542 tc6393xb_scr_writeb(s, addr & 0xff, value); 543 return; 544 case 1: 545 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value); 546 return; 547 }; 548 549 if ((addr &~0xff) == s->nand_phys && s->nand_enable) 550 tc6393xb_nand_writeb(s, addr & 0xff, value); 551 else 552 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n", 553 (uint32_t) addr, (int)value & 0xff); 554 } 555 556 static const GraphicHwOps tc6393xb_gfx_ops = { 557 .gfx_update = tc6393xb_update_display, 558 }; 559 560 TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) 561 { 562 TC6393xbState *s; 563 DriveInfo *nand; 564 static const MemoryRegionOps tc6393xb_ops = { 565 .read = tc6393xb_readb, 566 .write = tc6393xb_writeb, 567 .endianness = DEVICE_NATIVE_ENDIAN, 568 .impl = { 569 .min_access_size = 1, 570 .max_access_size = 1, 571 }, 572 }; 573 574 s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState)); 575 s->irq = irq; 576 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); 577 578 s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0); 579 s->blanked = 1; 580 581 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); 582 583 nand = drive_get(IF_MTD, 0, 0); 584 s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL, 585 NAND_MFR_TOSHIBA, 0x76); 586 587 memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000); 588 memory_region_add_subregion(sysmem, base, &s->iomem); 589 590 memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000, 591 &error_fatal); 592 s->vram_ptr = memory_region_get_ram_ptr(&s->vram); 593 memory_region_add_subregion(sysmem, base + 0x100000, &s->vram); 594 s->scr_width = 480; 595 s->scr_height = 640; 596 s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s); 597 598 return s; 599 } 600