1 /* 2 * Toshiba TC6393XB I/O Controller. 3 * Found in Sharp Zaurus SL-6000 (tosa) or some 4 * Toshiba e-Series PDAs. 5 * 6 * Most features are currently unsupported!!! 7 * 8 * This code is licensed under the GNU GPL v2. 9 * 10 * Contributions after 2012-01-13 are licensed under the terms of the 11 * GNU GPL, version 2 or (at your option) any later version. 12 */ 13 #include "qemu/osdep.h" 14 #include "qapi/error.h" 15 #include "qemu/host-utils.h" 16 #include "hw/hw.h" 17 #include "hw/devices.h" 18 #include "hw/block/flash.h" 19 #include "ui/console.h" 20 #include "ui/pixel_ops.h" 21 #include "sysemu/blockdev.h" 22 23 #define IRQ_TC6393_NAND 0 24 #define IRQ_TC6393_MMC 1 25 #define IRQ_TC6393_OHCI 2 26 #define IRQ_TC6393_SERIAL 3 27 #define IRQ_TC6393_FB 4 28 29 #define TC6393XB_NR_IRQS 8 30 31 #define TC6393XB_GPIOS 16 32 33 #define SCR_REVID 0x08 /* b Revision ID */ 34 #define SCR_ISR 0x50 /* b Interrupt Status */ 35 #define SCR_IMR 0x52 /* b Interrupt Mask */ 36 #define SCR_IRR 0x54 /* b Interrupt Routing */ 37 #define SCR_GPER 0x60 /* w GP Enable */ 38 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ 39 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ 40 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ 41 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ 42 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ 43 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ 44 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ 45 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ 46 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ 47 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ 48 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ 49 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ 50 #define SCR_CCR 0x98 /* w Clock Control */ 51 #define SCR_PLL2CR 0x9a /* w PLL2 Control */ 52 #define SCR_PLL1CR 0x9c /* l PLL1 Control */ 53 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ 54 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ 55 #define SCR_FER 0xe0 /* b Function Enable */ 56 #define SCR_MCR 0xe4 /* w Mode Control */ 57 #define SCR_CONFIG 0xfc /* b Configuration Control */ 58 #define SCR_DEBUG 0xff /* b Debug */ 59 60 #define NAND_CFG_COMMAND 0x04 /* w Command */ 61 #define NAND_CFG_BASE 0x10 /* l Control Base Address */ 62 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */ 63 #define NAND_CFG_INTE 0x48 /* b Int Enable */ 64 #define NAND_CFG_EC 0x4a /* b Event Control */ 65 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */ 66 #define NAND_CFG_ECCC 0x5b /* b ECC Control */ 67 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */ 68 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */ 69 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */ 70 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */ 71 72 #define NAND_DATA 0x00 /* l Data */ 73 #define NAND_MODE 0x04 /* b Mode */ 74 #define NAND_STATUS 0x05 /* b Status */ 75 #define NAND_ISR 0x06 /* b Interrupt Status */ 76 #define NAND_IMR 0x07 /* b Interrupt Mask */ 77 78 #define NAND_MODE_WP 0x80 79 #define NAND_MODE_CE 0x10 80 #define NAND_MODE_ALE 0x02 81 #define NAND_MODE_CLE 0x01 82 #define NAND_MODE_ECC_MASK 0x60 83 #define NAND_MODE_ECC_EN 0x20 84 #define NAND_MODE_ECC_READ 0x40 85 #define NAND_MODE_ECC_RST 0x60 86 87 struct TC6393xbState { 88 MemoryRegion iomem; 89 qemu_irq irq; 90 qemu_irq *sub_irqs; 91 struct { 92 uint8_t ISR; 93 uint8_t IMR; 94 uint8_t IRR; 95 uint16_t GPER; 96 uint8_t GPI_SR[3]; 97 uint8_t GPI_IMR[3]; 98 uint8_t GPI_EDER[3]; 99 uint8_t GPI_LIR[3]; 100 uint8_t GP_IARCR[3]; 101 uint8_t GP_IARLCR[3]; 102 uint8_t GPI_BCR[3]; 103 uint16_t GPA_IARCR; 104 uint16_t GPA_IARLCR; 105 uint16_t CCR; 106 uint16_t PLL2CR; 107 uint32_t PLL1CR; 108 uint8_t DIARCR; 109 uint8_t DBOCR; 110 uint8_t FER; 111 uint16_t MCR; 112 uint8_t CONFIG; 113 uint8_t DEBUG; 114 } scr; 115 uint32_t gpio_dir; 116 uint32_t gpio_level; 117 uint32_t prev_level; 118 qemu_irq handler[TC6393XB_GPIOS]; 119 qemu_irq *gpio_in; 120 121 struct { 122 uint8_t mode; 123 uint8_t isr; 124 uint8_t imr; 125 } nand; 126 int nand_enable; 127 uint32_t nand_phys; 128 DeviceState *flash; 129 ECCState ecc; 130 131 QemuConsole *con; 132 MemoryRegion vram; 133 uint16_t *vram_ptr; 134 uint32_t scr_width, scr_height; /* in pixels */ 135 qemu_irq l3v; 136 unsigned blank : 1, 137 blanked : 1; 138 }; 139 140 qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s) 141 { 142 return s->gpio_in; 143 } 144 145 static void tc6393xb_gpio_set(void *opaque, int line, int level) 146 { 147 // TC6393xbState *s = opaque; 148 149 if (line > TC6393XB_GPIOS) { 150 printf("%s: No GPIO pin %i\n", __func__, line); 151 return; 152 } 153 154 // FIXME: how does the chip reflect the GPIO input level change? 155 } 156 157 void tc6393xb_gpio_out_set(TC6393xbState *s, int line, 158 qemu_irq handler) 159 { 160 if (line >= TC6393XB_GPIOS) { 161 fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line); 162 return; 163 } 164 165 s->handler[line] = handler; 166 } 167 168 static void tc6393xb_gpio_handler_update(TC6393xbState *s) 169 { 170 uint32_t level, diff; 171 int bit; 172 173 level = s->gpio_level & s->gpio_dir; 174 level &= MAKE_64BIT_MASK(0, TC6393XB_GPIOS); 175 176 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 177 bit = ctz32(diff); 178 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 179 } 180 181 s->prev_level = level; 182 } 183 184 qemu_irq tc6393xb_l3v_get(TC6393xbState *s) 185 { 186 return s->l3v; 187 } 188 189 static void tc6393xb_l3v(void *opaque, int line, int level) 190 { 191 TC6393xbState *s = opaque; 192 s->blank = !level; 193 fprintf(stderr, "L3V: %d\n", level); 194 } 195 196 static void tc6393xb_sub_irq(void *opaque, int line, int level) { 197 TC6393xbState *s = opaque; 198 uint8_t isr = s->scr.ISR; 199 if (level) 200 isr |= 1 << line; 201 else 202 isr &= ~(1 << line); 203 s->scr.ISR = isr; 204 qemu_set_irq(s->irq, isr & s->scr.IMR); 205 } 206 207 #define SCR_REG_B(N) \ 208 case SCR_ ##N: return s->scr.N 209 #define SCR_REG_W(N) \ 210 case SCR_ ##N: return s->scr.N; \ 211 case SCR_ ##N + 1: return s->scr.N >> 8; 212 #define SCR_REG_L(N) \ 213 case SCR_ ##N: return s->scr.N; \ 214 case SCR_ ##N + 1: return s->scr.N >> 8; \ 215 case SCR_ ##N + 2: return s->scr.N >> 16; \ 216 case SCR_ ##N + 3: return s->scr.N >> 24; 217 #define SCR_REG_A(N) \ 218 case SCR_ ##N(0): return s->scr.N[0]; \ 219 case SCR_ ##N(1): return s->scr.N[1]; \ 220 case SCR_ ##N(2): return s->scr.N[2] 221 222 static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr) 223 { 224 switch (addr) { 225 case SCR_REVID: 226 return 3; 227 case SCR_REVID+1: 228 return 0; 229 SCR_REG_B(ISR); 230 SCR_REG_B(IMR); 231 SCR_REG_B(IRR); 232 SCR_REG_W(GPER); 233 SCR_REG_A(GPI_SR); 234 SCR_REG_A(GPI_IMR); 235 SCR_REG_A(GPI_EDER); 236 SCR_REG_A(GPI_LIR); 237 case SCR_GPO_DSR(0): 238 case SCR_GPO_DSR(1): 239 case SCR_GPO_DSR(2): 240 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff; 241 case SCR_GPO_DOECR(0): 242 case SCR_GPO_DOECR(1): 243 case SCR_GPO_DOECR(2): 244 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff; 245 SCR_REG_A(GP_IARCR); 246 SCR_REG_A(GP_IARLCR); 247 SCR_REG_A(GPI_BCR); 248 SCR_REG_W(GPA_IARCR); 249 SCR_REG_W(GPA_IARLCR); 250 SCR_REG_W(CCR); 251 SCR_REG_W(PLL2CR); 252 SCR_REG_L(PLL1CR); 253 SCR_REG_B(DIARCR); 254 SCR_REG_B(DBOCR); 255 SCR_REG_B(FER); 256 SCR_REG_W(MCR); 257 SCR_REG_B(CONFIG); 258 SCR_REG_B(DEBUG); 259 } 260 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr); 261 return 0; 262 } 263 #undef SCR_REG_B 264 #undef SCR_REG_W 265 #undef SCR_REG_L 266 #undef SCR_REG_A 267 268 #define SCR_REG_B(N) \ 269 case SCR_ ##N: s->scr.N = value; return; 270 #define SCR_REG_W(N) \ 271 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ 272 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return 273 #define SCR_REG_L(N) \ 274 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ 275 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \ 276 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \ 277 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return; 278 #define SCR_REG_A(N) \ 279 case SCR_ ##N(0): s->scr.N[0] = value; return; \ 280 case SCR_ ##N(1): s->scr.N[1] = value; return; \ 281 case SCR_ ##N(2): s->scr.N[2] = value; return 282 283 static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) 284 { 285 switch (addr) { 286 SCR_REG_B(ISR); 287 SCR_REG_B(IMR); 288 SCR_REG_B(IRR); 289 SCR_REG_W(GPER); 290 SCR_REG_A(GPI_SR); 291 SCR_REG_A(GPI_IMR); 292 SCR_REG_A(GPI_EDER); 293 SCR_REG_A(GPI_LIR); 294 case SCR_GPO_DSR(0): 295 case SCR_GPO_DSR(1): 296 case SCR_GPO_DSR(2): 297 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8)); 298 tc6393xb_gpio_handler_update(s); 299 return; 300 case SCR_GPO_DOECR(0): 301 case SCR_GPO_DOECR(1): 302 case SCR_GPO_DOECR(2): 303 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8)); 304 tc6393xb_gpio_handler_update(s); 305 return; 306 SCR_REG_A(GP_IARCR); 307 SCR_REG_A(GP_IARLCR); 308 SCR_REG_A(GPI_BCR); 309 SCR_REG_W(GPA_IARCR); 310 SCR_REG_W(GPA_IARLCR); 311 SCR_REG_W(CCR); 312 SCR_REG_W(PLL2CR); 313 SCR_REG_L(PLL1CR); 314 SCR_REG_B(DIARCR); 315 SCR_REG_B(DBOCR); 316 SCR_REG_B(FER); 317 SCR_REG_W(MCR); 318 SCR_REG_B(CONFIG); 319 SCR_REG_B(DEBUG); 320 } 321 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n", 322 (uint32_t) addr, value & 0xff); 323 } 324 #undef SCR_REG_B 325 #undef SCR_REG_W 326 #undef SCR_REG_L 327 #undef SCR_REG_A 328 329 static void tc6393xb_nand_irq(TC6393xbState *s) { 330 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], 331 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); 332 } 333 334 static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) { 335 switch (addr) { 336 case NAND_CFG_COMMAND: 337 return s->nand_enable ? 2 : 0; 338 case NAND_CFG_BASE: 339 case NAND_CFG_BASE + 1: 340 case NAND_CFG_BASE + 2: 341 case NAND_CFG_BASE + 3: 342 return s->nand_phys >> (addr - NAND_CFG_BASE); 343 } 344 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr); 345 return 0; 346 } 347 static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) { 348 switch (addr) { 349 case NAND_CFG_COMMAND: 350 s->nand_enable = (value & 0x2); 351 return; 352 case NAND_CFG_BASE: 353 case NAND_CFG_BASE + 1: 354 case NAND_CFG_BASE + 2: 355 case NAND_CFG_BASE + 3: 356 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8)); 357 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8); 358 return; 359 } 360 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n", 361 (uint32_t) addr, value & 0xff); 362 } 363 364 static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) { 365 switch (addr) { 366 case NAND_DATA + 0: 367 case NAND_DATA + 1: 368 case NAND_DATA + 2: 369 case NAND_DATA + 3: 370 return nand_getio(s->flash); 371 case NAND_MODE: 372 return s->nand.mode; 373 case NAND_STATUS: 374 return 0x14; 375 case NAND_ISR: 376 return s->nand.isr; 377 case NAND_IMR: 378 return s->nand.imr; 379 } 380 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr); 381 return 0; 382 } 383 static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) { 384 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n", 385 // (uint32_t) addr, value & 0xff); 386 switch (addr) { 387 case NAND_DATA + 0: 388 case NAND_DATA + 1: 389 case NAND_DATA + 2: 390 case NAND_DATA + 3: 391 nand_setio(s->flash, value); 392 s->nand.isr |= 1; 393 tc6393xb_nand_irq(s); 394 return; 395 case NAND_MODE: 396 s->nand.mode = value; 397 nand_setpins(s->flash, 398 value & NAND_MODE_CLE, 399 value & NAND_MODE_ALE, 400 !(value & NAND_MODE_CE), 401 value & NAND_MODE_WP, 402 0); // FIXME: gnd 403 switch (value & NAND_MODE_ECC_MASK) { 404 case NAND_MODE_ECC_RST: 405 ecc_reset(&s->ecc); 406 break; 407 case NAND_MODE_ECC_READ: 408 // FIXME 409 break; 410 case NAND_MODE_ECC_EN: 411 ecc_reset(&s->ecc); 412 } 413 return; 414 case NAND_ISR: 415 s->nand.isr = value; 416 tc6393xb_nand_irq(s); 417 return; 418 case NAND_IMR: 419 s->nand.imr = value; 420 tc6393xb_nand_irq(s); 421 return; 422 } 423 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n", 424 (uint32_t) addr, value & 0xff); 425 } 426 427 #define BITS 8 428 #include "tc6393xb_template.h" 429 #define BITS 15 430 #include "tc6393xb_template.h" 431 #define BITS 16 432 #include "tc6393xb_template.h" 433 #define BITS 24 434 #include "tc6393xb_template.h" 435 #define BITS 32 436 #include "tc6393xb_template.h" 437 438 static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) 439 { 440 DisplaySurface *surface = qemu_console_surface(s->con); 441 442 switch (surface_bits_per_pixel(surface)) { 443 case 8: 444 tc6393xb_draw_graphic8(s); 445 break; 446 case 15: 447 tc6393xb_draw_graphic15(s); 448 break; 449 case 16: 450 tc6393xb_draw_graphic16(s); 451 break; 452 case 24: 453 tc6393xb_draw_graphic24(s); 454 break; 455 case 32: 456 tc6393xb_draw_graphic32(s); 457 break; 458 default: 459 printf("tc6393xb: unknown depth %d\n", 460 surface_bits_per_pixel(surface)); 461 return; 462 } 463 464 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height); 465 } 466 467 static void tc6393xb_draw_blank(TC6393xbState *s, int full_update) 468 { 469 DisplaySurface *surface = qemu_console_surface(s->con); 470 int i, w; 471 uint8_t *d; 472 473 if (!full_update) 474 return; 475 476 w = s->scr_width * surface_bytes_per_pixel(surface); 477 d = surface_data(surface); 478 for(i = 0; i < s->scr_height; i++) { 479 memset(d, 0, w); 480 d += surface_stride(surface); 481 } 482 483 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height); 484 } 485 486 static void tc6393xb_update_display(void *opaque) 487 { 488 TC6393xbState *s = opaque; 489 DisplaySurface *surface = qemu_console_surface(s->con); 490 int full_update; 491 492 if (s->scr_width == 0 || s->scr_height == 0) 493 return; 494 495 full_update = 0; 496 if (s->blanked != s->blank) { 497 s->blanked = s->blank; 498 full_update = 1; 499 } 500 if (s->scr_width != surface_width(surface) || 501 s->scr_height != surface_height(surface)) { 502 qemu_console_resize(s->con, s->scr_width, s->scr_height); 503 full_update = 1; 504 } 505 if (s->blanked) 506 tc6393xb_draw_blank(s, full_update); 507 else 508 tc6393xb_draw_graphic(s, full_update); 509 } 510 511 512 static uint64_t tc6393xb_readb(void *opaque, hwaddr addr, 513 unsigned size) 514 { 515 TC6393xbState *s = opaque; 516 517 switch (addr >> 8) { 518 case 0: 519 return tc6393xb_scr_readb(s, addr & 0xff); 520 case 1: 521 return tc6393xb_nand_cfg_readb(s, addr & 0xff); 522 }; 523 524 if ((addr &~0xff) == s->nand_phys && s->nand_enable) { 525 // return tc6393xb_nand_readb(s, addr & 0xff); 526 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff); 527 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d); 528 return d; 529 } 530 531 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr); 532 return 0; 533 } 534 535 static void tc6393xb_writeb(void *opaque, hwaddr addr, 536 uint64_t value, unsigned size) { 537 TC6393xbState *s = opaque; 538 539 switch (addr >> 8) { 540 case 0: 541 tc6393xb_scr_writeb(s, addr & 0xff, value); 542 return; 543 case 1: 544 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value); 545 return; 546 }; 547 548 if ((addr &~0xff) == s->nand_phys && s->nand_enable) 549 tc6393xb_nand_writeb(s, addr & 0xff, value); 550 else 551 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n", 552 (uint32_t) addr, (int)value & 0xff); 553 } 554 555 static const GraphicHwOps tc6393xb_gfx_ops = { 556 .gfx_update = tc6393xb_update_display, 557 }; 558 559 TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) 560 { 561 TC6393xbState *s; 562 DriveInfo *nand; 563 static const MemoryRegionOps tc6393xb_ops = { 564 .read = tc6393xb_readb, 565 .write = tc6393xb_writeb, 566 .endianness = DEVICE_NATIVE_ENDIAN, 567 .impl = { 568 .min_access_size = 1, 569 .max_access_size = 1, 570 }, 571 }; 572 573 s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState)); 574 s->irq = irq; 575 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); 576 577 s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0); 578 s->blanked = 1; 579 580 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); 581 582 nand = drive_get(IF_MTD, 0, 0); 583 s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL, 584 NAND_MFR_TOSHIBA, 0x76); 585 586 memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000); 587 memory_region_add_subregion(sysmem, base, &s->iomem); 588 589 memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000, 590 &error_fatal); 591 s->vram_ptr = memory_region_get_ram_ptr(&s->vram); 592 memory_region_add_subregion(sysmem, base + 0x100000, &s->vram); 593 s->scr_width = 480; 594 s->scr_height = 640; 595 s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s); 596 597 return s; 598 } 599