1 /* 2 * Toshiba TC6393XB I/O Controller. 3 * Found in Sharp Zaurus SL-6000 (tosa) or some 4 * Toshiba e-Series PDAs. 5 * 6 * Most features are currently unsupported!!! 7 * 8 * This code is licensed under the GNU GPL v2. 9 * 10 * Contributions after 2012-01-13 are licensed under the terms of the 11 * GNU GPL, version 2 or (at your option) any later version. 12 */ 13 #include "hw/hw.h" 14 #include "hw/devices.h" 15 #include "hw/block/flash.h" 16 #include "ui/console.h" 17 #include "ui/pixel_ops.h" 18 #include "sysemu/blockdev.h" 19 20 #define IRQ_TC6393_NAND 0 21 #define IRQ_TC6393_MMC 1 22 #define IRQ_TC6393_OHCI 2 23 #define IRQ_TC6393_SERIAL 3 24 #define IRQ_TC6393_FB 4 25 26 #define TC6393XB_NR_IRQS 8 27 28 #define TC6393XB_GPIOS 16 29 30 #define SCR_REVID 0x08 /* b Revision ID */ 31 #define SCR_ISR 0x50 /* b Interrupt Status */ 32 #define SCR_IMR 0x52 /* b Interrupt Mask */ 33 #define SCR_IRR 0x54 /* b Interrupt Routing */ 34 #define SCR_GPER 0x60 /* w GP Enable */ 35 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ 36 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ 37 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ 38 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ 39 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ 40 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ 41 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ 42 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ 43 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ 44 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ 45 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ 46 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ 47 #define SCR_CCR 0x98 /* w Clock Control */ 48 #define SCR_PLL2CR 0x9a /* w PLL2 Control */ 49 #define SCR_PLL1CR 0x9c /* l PLL1 Control */ 50 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ 51 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ 52 #define SCR_FER 0xe0 /* b Function Enable */ 53 #define SCR_MCR 0xe4 /* w Mode Control */ 54 #define SCR_CONFIG 0xfc /* b Configuration Control */ 55 #define SCR_DEBUG 0xff /* b Debug */ 56 57 #define NAND_CFG_COMMAND 0x04 /* w Command */ 58 #define NAND_CFG_BASE 0x10 /* l Control Base Address */ 59 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */ 60 #define NAND_CFG_INTE 0x48 /* b Int Enable */ 61 #define NAND_CFG_EC 0x4a /* b Event Control */ 62 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */ 63 #define NAND_CFG_ECCC 0x5b /* b ECC Control */ 64 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */ 65 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */ 66 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */ 67 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */ 68 69 #define NAND_DATA 0x00 /* l Data */ 70 #define NAND_MODE 0x04 /* b Mode */ 71 #define NAND_STATUS 0x05 /* b Status */ 72 #define NAND_ISR 0x06 /* b Interrupt Status */ 73 #define NAND_IMR 0x07 /* b Interrupt Mask */ 74 75 #define NAND_MODE_WP 0x80 76 #define NAND_MODE_CE 0x10 77 #define NAND_MODE_ALE 0x02 78 #define NAND_MODE_CLE 0x01 79 #define NAND_MODE_ECC_MASK 0x60 80 #define NAND_MODE_ECC_EN 0x20 81 #define NAND_MODE_ECC_READ 0x40 82 #define NAND_MODE_ECC_RST 0x60 83 84 struct TC6393xbState { 85 MemoryRegion iomem; 86 qemu_irq irq; 87 qemu_irq *sub_irqs; 88 struct { 89 uint8_t ISR; 90 uint8_t IMR; 91 uint8_t IRR; 92 uint16_t GPER; 93 uint8_t GPI_SR[3]; 94 uint8_t GPI_IMR[3]; 95 uint8_t GPI_EDER[3]; 96 uint8_t GPI_LIR[3]; 97 uint8_t GP_IARCR[3]; 98 uint8_t GP_IARLCR[3]; 99 uint8_t GPI_BCR[3]; 100 uint16_t GPA_IARCR; 101 uint16_t GPA_IARLCR; 102 uint16_t CCR; 103 uint16_t PLL2CR; 104 uint32_t PLL1CR; 105 uint8_t DIARCR; 106 uint8_t DBOCR; 107 uint8_t FER; 108 uint16_t MCR; 109 uint8_t CONFIG; 110 uint8_t DEBUG; 111 } scr; 112 uint32_t gpio_dir; 113 uint32_t gpio_level; 114 uint32_t prev_level; 115 qemu_irq handler[TC6393XB_GPIOS]; 116 qemu_irq *gpio_in; 117 118 struct { 119 uint8_t mode; 120 uint8_t isr; 121 uint8_t imr; 122 } nand; 123 int nand_enable; 124 uint32_t nand_phys; 125 DeviceState *flash; 126 ECCState ecc; 127 128 QemuConsole *con; 129 MemoryRegion vram; 130 uint16_t *vram_ptr; 131 uint32_t scr_width, scr_height; /* in pixels */ 132 qemu_irq l3v; 133 unsigned blank : 1, 134 blanked : 1; 135 }; 136 137 qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s) 138 { 139 return s->gpio_in; 140 } 141 142 static void tc6393xb_gpio_set(void *opaque, int line, int level) 143 { 144 // TC6393xbState *s = opaque; 145 146 if (line > TC6393XB_GPIOS) { 147 printf("%s: No GPIO pin %i\n", __FUNCTION__, line); 148 return; 149 } 150 151 // FIXME: how does the chip reflect the GPIO input level change? 152 } 153 154 void tc6393xb_gpio_out_set(TC6393xbState *s, int line, 155 qemu_irq handler) 156 { 157 if (line >= TC6393XB_GPIOS) { 158 fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line); 159 return; 160 } 161 162 s->handler[line] = handler; 163 } 164 165 static void tc6393xb_gpio_handler_update(TC6393xbState *s) 166 { 167 uint32_t level, diff; 168 int bit; 169 170 level = s->gpio_level & s->gpio_dir; 171 172 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 173 bit = ffs(diff) - 1; 174 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 175 } 176 177 s->prev_level = level; 178 } 179 180 qemu_irq tc6393xb_l3v_get(TC6393xbState *s) 181 { 182 return s->l3v; 183 } 184 185 static void tc6393xb_l3v(void *opaque, int line, int level) 186 { 187 TC6393xbState *s = opaque; 188 s->blank = !level; 189 fprintf(stderr, "L3V: %d\n", level); 190 } 191 192 static void tc6393xb_sub_irq(void *opaque, int line, int level) { 193 TC6393xbState *s = opaque; 194 uint8_t isr = s->scr.ISR; 195 if (level) 196 isr |= 1 << line; 197 else 198 isr &= ~(1 << line); 199 s->scr.ISR = isr; 200 qemu_set_irq(s->irq, isr & s->scr.IMR); 201 } 202 203 #define SCR_REG_B(N) \ 204 case SCR_ ##N: return s->scr.N 205 #define SCR_REG_W(N) \ 206 case SCR_ ##N: return s->scr.N; \ 207 case SCR_ ##N + 1: return s->scr.N >> 8; 208 #define SCR_REG_L(N) \ 209 case SCR_ ##N: return s->scr.N; \ 210 case SCR_ ##N + 1: return s->scr.N >> 8; \ 211 case SCR_ ##N + 2: return s->scr.N >> 16; \ 212 case SCR_ ##N + 3: return s->scr.N >> 24; 213 #define SCR_REG_A(N) \ 214 case SCR_ ##N(0): return s->scr.N[0]; \ 215 case SCR_ ##N(1): return s->scr.N[1]; \ 216 case SCR_ ##N(2): return s->scr.N[2] 217 218 static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr) 219 { 220 switch (addr) { 221 case SCR_REVID: 222 return 3; 223 case SCR_REVID+1: 224 return 0; 225 SCR_REG_B(ISR); 226 SCR_REG_B(IMR); 227 SCR_REG_B(IRR); 228 SCR_REG_W(GPER); 229 SCR_REG_A(GPI_SR); 230 SCR_REG_A(GPI_IMR); 231 SCR_REG_A(GPI_EDER); 232 SCR_REG_A(GPI_LIR); 233 case SCR_GPO_DSR(0): 234 case SCR_GPO_DSR(1): 235 case SCR_GPO_DSR(2): 236 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff; 237 case SCR_GPO_DOECR(0): 238 case SCR_GPO_DOECR(1): 239 case SCR_GPO_DOECR(2): 240 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff; 241 SCR_REG_A(GP_IARCR); 242 SCR_REG_A(GP_IARLCR); 243 SCR_REG_A(GPI_BCR); 244 SCR_REG_W(GPA_IARCR); 245 SCR_REG_W(GPA_IARLCR); 246 SCR_REG_W(CCR); 247 SCR_REG_W(PLL2CR); 248 SCR_REG_L(PLL1CR); 249 SCR_REG_B(DIARCR); 250 SCR_REG_B(DBOCR); 251 SCR_REG_B(FER); 252 SCR_REG_W(MCR); 253 SCR_REG_B(CONFIG); 254 SCR_REG_B(DEBUG); 255 } 256 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr); 257 return 0; 258 } 259 #undef SCR_REG_B 260 #undef SCR_REG_W 261 #undef SCR_REG_L 262 #undef SCR_REG_A 263 264 #define SCR_REG_B(N) \ 265 case SCR_ ##N: s->scr.N = value; return; 266 #define SCR_REG_W(N) \ 267 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ 268 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return 269 #define SCR_REG_L(N) \ 270 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ 271 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \ 272 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \ 273 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return; 274 #define SCR_REG_A(N) \ 275 case SCR_ ##N(0): s->scr.N[0] = value; return; \ 276 case SCR_ ##N(1): s->scr.N[1] = value; return; \ 277 case SCR_ ##N(2): s->scr.N[2] = value; return 278 279 static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) 280 { 281 switch (addr) { 282 SCR_REG_B(ISR); 283 SCR_REG_B(IMR); 284 SCR_REG_B(IRR); 285 SCR_REG_W(GPER); 286 SCR_REG_A(GPI_SR); 287 SCR_REG_A(GPI_IMR); 288 SCR_REG_A(GPI_EDER); 289 SCR_REG_A(GPI_LIR); 290 case SCR_GPO_DSR(0): 291 case SCR_GPO_DSR(1): 292 case SCR_GPO_DSR(2): 293 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8)); 294 tc6393xb_gpio_handler_update(s); 295 return; 296 case SCR_GPO_DOECR(0): 297 case SCR_GPO_DOECR(1): 298 case SCR_GPO_DOECR(2): 299 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8)); 300 tc6393xb_gpio_handler_update(s); 301 return; 302 SCR_REG_A(GP_IARCR); 303 SCR_REG_A(GP_IARLCR); 304 SCR_REG_A(GPI_BCR); 305 SCR_REG_W(GPA_IARCR); 306 SCR_REG_W(GPA_IARLCR); 307 SCR_REG_W(CCR); 308 SCR_REG_W(PLL2CR); 309 SCR_REG_L(PLL1CR); 310 SCR_REG_B(DIARCR); 311 SCR_REG_B(DBOCR); 312 SCR_REG_B(FER); 313 SCR_REG_W(MCR); 314 SCR_REG_B(CONFIG); 315 SCR_REG_B(DEBUG); 316 } 317 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n", 318 (uint32_t) addr, value & 0xff); 319 } 320 #undef SCR_REG_B 321 #undef SCR_REG_W 322 #undef SCR_REG_L 323 #undef SCR_REG_A 324 325 static void tc6393xb_nand_irq(TC6393xbState *s) { 326 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], 327 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); 328 } 329 330 static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) { 331 switch (addr) { 332 case NAND_CFG_COMMAND: 333 return s->nand_enable ? 2 : 0; 334 case NAND_CFG_BASE: 335 case NAND_CFG_BASE + 1: 336 case NAND_CFG_BASE + 2: 337 case NAND_CFG_BASE + 3: 338 return s->nand_phys >> (addr - NAND_CFG_BASE); 339 } 340 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr); 341 return 0; 342 } 343 static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) { 344 switch (addr) { 345 case NAND_CFG_COMMAND: 346 s->nand_enable = (value & 0x2); 347 return; 348 case NAND_CFG_BASE: 349 case NAND_CFG_BASE + 1: 350 case NAND_CFG_BASE + 2: 351 case NAND_CFG_BASE + 3: 352 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8)); 353 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8); 354 return; 355 } 356 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n", 357 (uint32_t) addr, value & 0xff); 358 } 359 360 static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) { 361 switch (addr) { 362 case NAND_DATA + 0: 363 case NAND_DATA + 1: 364 case NAND_DATA + 2: 365 case NAND_DATA + 3: 366 return nand_getio(s->flash); 367 case NAND_MODE: 368 return s->nand.mode; 369 case NAND_STATUS: 370 return 0x14; 371 case NAND_ISR: 372 return s->nand.isr; 373 case NAND_IMR: 374 return s->nand.imr; 375 } 376 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr); 377 return 0; 378 } 379 static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) { 380 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n", 381 // (uint32_t) addr, value & 0xff); 382 switch (addr) { 383 case NAND_DATA + 0: 384 case NAND_DATA + 1: 385 case NAND_DATA + 2: 386 case NAND_DATA + 3: 387 nand_setio(s->flash, value); 388 s->nand.isr |= 1; 389 tc6393xb_nand_irq(s); 390 return; 391 case NAND_MODE: 392 s->nand.mode = value; 393 nand_setpins(s->flash, 394 value & NAND_MODE_CLE, 395 value & NAND_MODE_ALE, 396 !(value & NAND_MODE_CE), 397 value & NAND_MODE_WP, 398 0); // FIXME: gnd 399 switch (value & NAND_MODE_ECC_MASK) { 400 case NAND_MODE_ECC_RST: 401 ecc_reset(&s->ecc); 402 break; 403 case NAND_MODE_ECC_READ: 404 // FIXME 405 break; 406 case NAND_MODE_ECC_EN: 407 ecc_reset(&s->ecc); 408 } 409 return; 410 case NAND_ISR: 411 s->nand.isr = value; 412 tc6393xb_nand_irq(s); 413 return; 414 case NAND_IMR: 415 s->nand.imr = value; 416 tc6393xb_nand_irq(s); 417 return; 418 } 419 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n", 420 (uint32_t) addr, value & 0xff); 421 } 422 423 #define BITS 8 424 #include "tc6393xb_template.h" 425 #define BITS 15 426 #include "tc6393xb_template.h" 427 #define BITS 16 428 #include "tc6393xb_template.h" 429 #define BITS 24 430 #include "tc6393xb_template.h" 431 #define BITS 32 432 #include "tc6393xb_template.h" 433 434 static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) 435 { 436 DisplaySurface *surface = qemu_console_surface(s->con); 437 438 switch (surface_bits_per_pixel(surface)) { 439 case 8: 440 tc6393xb_draw_graphic8(s); 441 break; 442 case 15: 443 tc6393xb_draw_graphic15(s); 444 break; 445 case 16: 446 tc6393xb_draw_graphic16(s); 447 break; 448 case 24: 449 tc6393xb_draw_graphic24(s); 450 break; 451 case 32: 452 tc6393xb_draw_graphic32(s); 453 break; 454 default: 455 printf("tc6393xb: unknown depth %d\n", 456 surface_bits_per_pixel(surface)); 457 return; 458 } 459 460 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height); 461 } 462 463 static void tc6393xb_draw_blank(TC6393xbState *s, int full_update) 464 { 465 DisplaySurface *surface = qemu_console_surface(s->con); 466 int i, w; 467 uint8_t *d; 468 469 if (!full_update) 470 return; 471 472 w = s->scr_width * surface_bytes_per_pixel(surface); 473 d = surface_data(surface); 474 for(i = 0; i < s->scr_height; i++) { 475 memset(d, 0, w); 476 d += surface_stride(surface); 477 } 478 479 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height); 480 } 481 482 static void tc6393xb_update_display(void *opaque) 483 { 484 TC6393xbState *s = opaque; 485 DisplaySurface *surface = qemu_console_surface(s->con); 486 int full_update; 487 488 if (s->scr_width == 0 || s->scr_height == 0) 489 return; 490 491 full_update = 0; 492 if (s->blanked != s->blank) { 493 s->blanked = s->blank; 494 full_update = 1; 495 } 496 if (s->scr_width != surface_width(surface) || 497 s->scr_height != surface_height(surface)) { 498 qemu_console_resize(s->con, s->scr_width, s->scr_height); 499 full_update = 1; 500 } 501 if (s->blanked) 502 tc6393xb_draw_blank(s, full_update); 503 else 504 tc6393xb_draw_graphic(s, full_update); 505 } 506 507 508 static uint64_t tc6393xb_readb(void *opaque, hwaddr addr, 509 unsigned size) 510 { 511 TC6393xbState *s = opaque; 512 513 switch (addr >> 8) { 514 case 0: 515 return tc6393xb_scr_readb(s, addr & 0xff); 516 case 1: 517 return tc6393xb_nand_cfg_readb(s, addr & 0xff); 518 }; 519 520 if ((addr &~0xff) == s->nand_phys && s->nand_enable) { 521 // return tc6393xb_nand_readb(s, addr & 0xff); 522 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff); 523 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d); 524 return d; 525 } 526 527 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr); 528 return 0; 529 } 530 531 static void tc6393xb_writeb(void *opaque, hwaddr addr, 532 uint64_t value, unsigned size) { 533 TC6393xbState *s = opaque; 534 535 switch (addr >> 8) { 536 case 0: 537 tc6393xb_scr_writeb(s, addr & 0xff, value); 538 return; 539 case 1: 540 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value); 541 return; 542 }; 543 544 if ((addr &~0xff) == s->nand_phys && s->nand_enable) 545 tc6393xb_nand_writeb(s, addr & 0xff, value); 546 else 547 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n", 548 (uint32_t) addr, (int)value & 0xff); 549 } 550 551 static const GraphicHwOps tc6393xb_gfx_ops = { 552 .gfx_update = tc6393xb_update_display, 553 }; 554 555 TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) 556 { 557 TC6393xbState *s; 558 DriveInfo *nand; 559 static const MemoryRegionOps tc6393xb_ops = { 560 .read = tc6393xb_readb, 561 .write = tc6393xb_writeb, 562 .endianness = DEVICE_NATIVE_ENDIAN, 563 .impl = { 564 .min_access_size = 1, 565 .max_access_size = 1, 566 }, 567 }; 568 569 s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState)); 570 s->irq = irq; 571 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); 572 573 s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1); 574 s->blanked = 1; 575 576 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); 577 578 nand = drive_get(IF_MTD, 0, 0); 579 s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76); 580 581 memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000); 582 memory_region_add_subregion(sysmem, base, &s->iomem); 583 584 memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000, 585 &error_abort); 586 vmstate_register_ram_global(&s->vram); 587 s->vram_ptr = memory_region_get_ram_ptr(&s->vram); 588 memory_region_add_subregion(sysmem, base + 0x100000, &s->vram); 589 s->scr_width = 480; 590 s->scr_height = 640; 591 s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s); 592 593 return s; 594 } 595