1 /* 2 * QEMU SM501 Device 3 * 4 * Copyright (c) 2008 Shin-ichiro KAWASAKI 5 * Copyright (c) 2016-2020 BALATON Zoltan 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qapi/error.h" 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "qemu/module.h" 32 #include "hw/usb/hcd-ohci.h" 33 #include "hw/char/serial-mm.h" 34 #include "ui/console.h" 35 #include "hw/sysbus.h" 36 #include "migration/vmstate.h" 37 #include "hw/pci/pci_device.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/i2c/i2c.h" 40 #include "hw/display/i2c-ddc.h" 41 #include "qemu/range.h" 42 #include "ui/pixel_ops.h" 43 #include "qemu/bswap.h" 44 #include "trace.h" 45 #include "qom/object.h" 46 47 #define MMIO_BASE_OFFSET 0x3e00000 48 #define MMIO_SIZE 0x200000 49 #define DC_PALETTE_ENTRIES (0x400 * 3) 50 51 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ 52 53 /* System Configuration area */ 54 /* System config base */ 55 #define SM501_SYS_CONFIG 0x000000 56 57 /* config 1 */ 58 #define SM501_SYSTEM_CONTROL 0x000000 59 60 #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) 61 #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) 62 #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) 63 64 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) 65 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) 66 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) 67 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) 68 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) 69 70 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) 71 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) 72 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) 73 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) 74 75 /* miscellaneous control */ 76 77 #define SM501_MISC_CONTROL 0x000004 78 79 #define SM501_MISC_BUS_SH 0x0 80 #define SM501_MISC_BUS_PCI 0x1 81 #define SM501_MISC_BUS_XSCALE 0x2 82 #define SM501_MISC_BUS_NEC 0x6 83 #define SM501_MISC_BUS_MASK 0x7 84 85 #define SM501_MISC_VR_62MB (1 << 3) 86 #define SM501_MISC_CDR_RESET (1 << 7) 87 #define SM501_MISC_USB_LB (1 << 8) 88 #define SM501_MISC_USB_SLAVE (1 << 9) 89 #define SM501_MISC_BL_1 (1 << 10) 90 #define SM501_MISC_MC (1 << 11) 91 #define SM501_MISC_DAC_POWER (1 << 12) 92 #define SM501_MISC_IRQ_INVERT (1 << 16) 93 #define SM501_MISC_SH (1 << 17) 94 95 #define SM501_MISC_HOLD_EMPTY (0 << 18) 96 #define SM501_MISC_HOLD_8 (1 << 18) 97 #define SM501_MISC_HOLD_16 (2 << 18) 98 #define SM501_MISC_HOLD_24 (3 << 18) 99 #define SM501_MISC_HOLD_32 (4 << 18) 100 #define SM501_MISC_HOLD_MASK (7 << 18) 101 102 #define SM501_MISC_FREQ_12 (1 << 24) 103 #define SM501_MISC_PNL_24BIT (1 << 25) 104 #define SM501_MISC_8051_LE (1 << 26) 105 106 107 108 #define SM501_GPIO31_0_CONTROL 0x000008 109 #define SM501_GPIO63_32_CONTROL 0x00000C 110 #define SM501_DRAM_CONTROL 0x000010 111 112 /* command list */ 113 #define SM501_ARBTRTN_CONTROL 0x000014 114 115 /* command list */ 116 #define SM501_COMMAND_LIST_STATUS 0x000024 117 118 /* interrupt debug */ 119 #define SM501_RAW_IRQ_STATUS 0x000028 120 #define SM501_RAW_IRQ_CLEAR 0x000028 121 #define SM501_IRQ_STATUS 0x00002C 122 #define SM501_IRQ_MASK 0x000030 123 #define SM501_DEBUG_CONTROL 0x000034 124 125 /* power management */ 126 #define SM501_POWERMODE_P2X_SRC (1 << 29) 127 #define SM501_POWERMODE_V2X_SRC (1 << 20) 128 #define SM501_POWERMODE_M_SRC (1 << 12) 129 #define SM501_POWERMODE_M1_SRC (1 << 4) 130 131 #define SM501_CURRENT_GATE 0x000038 132 #define SM501_CURRENT_CLOCK 0x00003C 133 #define SM501_POWER_MODE_0_GATE 0x000040 134 #define SM501_POWER_MODE_0_CLOCK 0x000044 135 #define SM501_POWER_MODE_1_GATE 0x000048 136 #define SM501_POWER_MODE_1_CLOCK 0x00004C 137 #define SM501_SLEEP_MODE_GATE 0x000050 138 #define SM501_POWER_MODE_CONTROL 0x000054 139 140 /* power gates for units within the 501 */ 141 #define SM501_GATE_HOST 0 142 #define SM501_GATE_MEMORY 1 143 #define SM501_GATE_DISPLAY 2 144 #define SM501_GATE_2D_ENGINE 3 145 #define SM501_GATE_CSC 4 146 #define SM501_GATE_ZVPORT 5 147 #define SM501_GATE_GPIO 6 148 #define SM501_GATE_UART0 7 149 #define SM501_GATE_UART1 8 150 #define SM501_GATE_SSP 10 151 #define SM501_GATE_USB_HOST 11 152 #define SM501_GATE_USB_GADGET 12 153 #define SM501_GATE_UCONTROLLER 17 154 #define SM501_GATE_AC97 18 155 156 /* panel clock */ 157 #define SM501_CLOCK_P2XCLK 24 158 /* crt clock */ 159 #define SM501_CLOCK_V2XCLK 16 160 /* main clock */ 161 #define SM501_CLOCK_MCLK 8 162 /* SDRAM controller clock */ 163 #define SM501_CLOCK_M1XCLK 0 164 165 /* config 2 */ 166 #define SM501_PCI_MASTER_BASE 0x000058 167 #define SM501_ENDIAN_CONTROL 0x00005C 168 #define SM501_DEVICEID 0x000060 169 /* 0x050100A0 */ 170 171 #define SM501_DEVICEID_SM501 0x05010000 172 #define SM501_DEVICEID_IDMASK 0xffff0000 173 #define SM501_DEVICEID_REVMASK 0x000000ff 174 175 #define SM501_PLLCLOCK_COUNT 0x000064 176 #define SM501_MISC_TIMING 0x000068 177 #define SM501_CURRENT_SDRAM_CLOCK 0x00006C 178 179 #define SM501_PROGRAMMABLE_PLL_CONTROL 0x000074 180 181 /* GPIO base */ 182 #define SM501_GPIO 0x010000 183 #define SM501_GPIO_DATA_LOW 0x00 184 #define SM501_GPIO_DATA_HIGH 0x04 185 #define SM501_GPIO_DDR_LOW 0x08 186 #define SM501_GPIO_DDR_HIGH 0x0C 187 #define SM501_GPIO_IRQ_SETUP 0x10 188 #define SM501_GPIO_IRQ_STATUS 0x14 189 #define SM501_GPIO_IRQ_RESET 0x14 190 191 /* I2C controller base */ 192 #define SM501_I2C 0x010040 193 #define SM501_I2C_BYTE_COUNT 0x00 194 #define SM501_I2C_CONTROL 0x01 195 #define SM501_I2C_STATUS 0x02 196 #define SM501_I2C_RESET 0x02 197 #define SM501_I2C_SLAVE_ADDRESS 0x03 198 #define SM501_I2C_DATA 0x04 199 200 #define SM501_I2C_CONTROL_START (1 << 2) 201 #define SM501_I2C_CONTROL_ENABLE (1 << 0) 202 203 #define SM501_I2C_STATUS_COMPLETE (1 << 3) 204 #define SM501_I2C_STATUS_ERROR (1 << 2) 205 206 #define SM501_I2C_RESET_ERROR (1 << 2) 207 208 /* SSP base */ 209 #define SM501_SSP 0x020000 210 211 /* Uart 0 base */ 212 #define SM501_UART0 0x030000 213 214 /* Uart 1 base */ 215 #define SM501_UART1 0x030020 216 217 /* USB host port base */ 218 #define SM501_USB_HOST 0x040000 219 220 /* USB slave/gadget base */ 221 #define SM501_USB_GADGET 0x060000 222 223 /* USB slave/gadget data port base */ 224 #define SM501_USB_GADGET_DATA 0x070000 225 226 /* Display controller/video engine base */ 227 #define SM501_DC 0x080000 228 229 /* common defines for the SM501 address registers */ 230 #define SM501_ADDR_FLIP (1 << 31) 231 #define SM501_ADDR_EXT (1 << 27) 232 #define SM501_ADDR_CS1 (1 << 26) 233 #define SM501_ADDR_MASK (0x3f << 26) 234 235 #define SM501_FIFO_MASK (0x3 << 16) 236 #define SM501_FIFO_1 (0x0 << 16) 237 #define SM501_FIFO_3 (0x1 << 16) 238 #define SM501_FIFO_7 (0x2 << 16) 239 #define SM501_FIFO_11 (0x3 << 16) 240 241 /* common registers for panel and the crt */ 242 #define SM501_OFF_DC_H_TOT 0x000 243 #define SM501_OFF_DC_V_TOT 0x008 244 #define SM501_OFF_DC_H_SYNC 0x004 245 #define SM501_OFF_DC_V_SYNC 0x00C 246 247 #define SM501_DC_PANEL_CONTROL 0x000 248 249 #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) 250 #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) 251 #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) 252 #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) 253 #define SM501_DC_PANEL_CONTROL_DP (1 << 23) 254 255 #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) 256 #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) 257 #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) 258 259 #define SM501_DC_PANEL_CONTROL_DE (1 << 20) 260 261 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) 262 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) 263 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) 264 265 #define SM501_DC_PANEL_CONTROL_CP (1 << 14) 266 #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) 267 #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) 268 #define SM501_DC_PANEL_CONTROL_CK (1 << 9) 269 #define SM501_DC_PANEL_CONTROL_TE (1 << 8) 270 #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) 271 #define SM501_DC_PANEL_CONTROL_VP (1 << 6) 272 #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) 273 #define SM501_DC_PANEL_CONTROL_HP (1 << 4) 274 #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) 275 #define SM501_DC_PANEL_CONTROL_EN (1 << 2) 276 277 #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) 278 #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) 279 #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) 280 281 282 #define SM501_DC_PANEL_PANNING_CONTROL 0x004 283 #define SM501_DC_PANEL_COLOR_KEY 0x008 284 #define SM501_DC_PANEL_FB_ADDR 0x00C 285 #define SM501_DC_PANEL_FB_OFFSET 0x010 286 #define SM501_DC_PANEL_FB_WIDTH 0x014 287 #define SM501_DC_PANEL_FB_HEIGHT 0x018 288 #define SM501_DC_PANEL_TL_LOC 0x01C 289 #define SM501_DC_PANEL_BR_LOC 0x020 290 #define SM501_DC_PANEL_H_TOT 0x024 291 #define SM501_DC_PANEL_H_SYNC 0x028 292 #define SM501_DC_PANEL_V_TOT 0x02C 293 #define SM501_DC_PANEL_V_SYNC 0x030 294 #define SM501_DC_PANEL_CUR_LINE 0x034 295 296 #define SM501_DC_VIDEO_CONTROL 0x040 297 #define SM501_DC_VIDEO_FB0_ADDR 0x044 298 #define SM501_DC_VIDEO_FB_WIDTH 0x048 299 #define SM501_DC_VIDEO_FB0_LAST_ADDR 0x04C 300 #define SM501_DC_VIDEO_TL_LOC 0x050 301 #define SM501_DC_VIDEO_BR_LOC 0x054 302 #define SM501_DC_VIDEO_SCALE 0x058 303 #define SM501_DC_VIDEO_INIT_SCALE 0x05C 304 #define SM501_DC_VIDEO_YUV_CONSTANTS 0x060 305 #define SM501_DC_VIDEO_FB1_ADDR 0x064 306 #define SM501_DC_VIDEO_FB1_LAST_ADDR 0x068 307 308 #define SM501_DC_VIDEO_ALPHA_CONTROL 0x080 309 #define SM501_DC_VIDEO_ALPHA_FB_ADDR 0x084 310 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET 0x088 311 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR 0x08C 312 #define SM501_DC_VIDEO_ALPHA_TL_LOC 0x090 313 #define SM501_DC_VIDEO_ALPHA_BR_LOC 0x094 314 #define SM501_DC_VIDEO_ALPHA_SCALE 0x098 315 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE 0x09C 316 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY 0x0A0 317 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP 0x0A4 318 319 #define SM501_DC_PANEL_HWC_BASE 0x0F0 320 #define SM501_DC_PANEL_HWC_ADDR 0x0F0 321 #define SM501_DC_PANEL_HWC_LOC 0x0F4 322 #define SM501_DC_PANEL_HWC_COLOR_1_2 0x0F8 323 #define SM501_DC_PANEL_HWC_COLOR_3 0x0FC 324 325 #define SM501_HWC_EN (1 << 31) 326 327 #define SM501_OFF_HWC_ADDR 0x00 328 #define SM501_OFF_HWC_LOC 0x04 329 #define SM501_OFF_HWC_COLOR_1_2 0x08 330 #define SM501_OFF_HWC_COLOR_3 0x0C 331 332 #define SM501_DC_ALPHA_CONTROL 0x100 333 #define SM501_DC_ALPHA_FB_ADDR 0x104 334 #define SM501_DC_ALPHA_FB_OFFSET 0x108 335 #define SM501_DC_ALPHA_TL_LOC 0x10C 336 #define SM501_DC_ALPHA_BR_LOC 0x110 337 #define SM501_DC_ALPHA_CHROMA_KEY 0x114 338 #define SM501_DC_ALPHA_COLOR_LOOKUP 0x118 339 340 #define SM501_DC_CRT_CONTROL 0x200 341 342 #define SM501_DC_CRT_CONTROL_TVP (1 << 15) 343 #define SM501_DC_CRT_CONTROL_CP (1 << 14) 344 #define SM501_DC_CRT_CONTROL_VSP (1 << 13) 345 #define SM501_DC_CRT_CONTROL_HSP (1 << 12) 346 #define SM501_DC_CRT_CONTROL_VS (1 << 11) 347 #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) 348 #define SM501_DC_CRT_CONTROL_SEL (1 << 9) 349 #define SM501_DC_CRT_CONTROL_TE (1 << 8) 350 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) 351 #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) 352 #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) 353 354 #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) 355 #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) 356 #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) 357 358 #define SM501_DC_CRT_FB_ADDR 0x204 359 #define SM501_DC_CRT_FB_OFFSET 0x208 360 #define SM501_DC_CRT_H_TOT 0x20C 361 #define SM501_DC_CRT_H_SYNC 0x210 362 #define SM501_DC_CRT_V_TOT 0x214 363 #define SM501_DC_CRT_V_SYNC 0x218 364 #define SM501_DC_CRT_SIGNATURE_ANALYZER 0x21C 365 #define SM501_DC_CRT_CUR_LINE 0x220 366 #define SM501_DC_CRT_MONITOR_DETECT 0x224 367 368 #define SM501_DC_CRT_HWC_BASE 0x230 369 #define SM501_DC_CRT_HWC_ADDR 0x230 370 #define SM501_DC_CRT_HWC_LOC 0x234 371 #define SM501_DC_CRT_HWC_COLOR_1_2 0x238 372 #define SM501_DC_CRT_HWC_COLOR_3 0x23C 373 374 #define SM501_DC_PANEL_PALETTE 0x400 375 376 #define SM501_DC_VIDEO_PALETTE 0x800 377 378 #define SM501_DC_CRT_PALETTE 0xC00 379 380 /* Zoom Video port base */ 381 #define SM501_ZVPORT 0x090000 382 383 /* AC97/I2S base */ 384 #define SM501_AC97 0x0A0000 385 386 /* 8051 micro controller base */ 387 #define SM501_UCONTROLLER 0x0B0000 388 389 /* 8051 micro controller SRAM base */ 390 #define SM501_UCONTROLLER_SRAM 0x0C0000 391 392 /* DMA base */ 393 #define SM501_DMA 0x0D0000 394 395 /* 2d engine base */ 396 #define SM501_2D_ENGINE 0x100000 397 #define SM501_2D_SOURCE 0x00 398 #define SM501_2D_DESTINATION 0x04 399 #define SM501_2D_DIMENSION 0x08 400 #define SM501_2D_CONTROL 0x0C 401 #define SM501_2D_PITCH 0x10 402 #define SM501_2D_FOREGROUND 0x14 403 #define SM501_2D_BACKGROUND 0x18 404 #define SM501_2D_STRETCH 0x1C 405 #define SM501_2D_COLOR_COMPARE 0x20 406 #define SM501_2D_COLOR_COMPARE_MASK 0x24 407 #define SM501_2D_MASK 0x28 408 #define SM501_2D_CLIP_TL 0x2C 409 #define SM501_2D_CLIP_BR 0x30 410 #define SM501_2D_MONO_PATTERN_LOW 0x34 411 #define SM501_2D_MONO_PATTERN_HIGH 0x38 412 #define SM501_2D_WINDOW_WIDTH 0x3C 413 #define SM501_2D_SOURCE_BASE 0x40 414 #define SM501_2D_DESTINATION_BASE 0x44 415 #define SM501_2D_ALPHA 0x48 416 #define SM501_2D_WRAP 0x4C 417 #define SM501_2D_STATUS 0x50 418 419 #define SM501_CSC_Y_SOURCE_BASE 0xC8 420 #define SM501_CSC_CONSTANTS 0xCC 421 #define SM501_CSC_Y_SOURCE_X 0xD0 422 #define SM501_CSC_Y_SOURCE_Y 0xD4 423 #define SM501_CSC_U_SOURCE_BASE 0xD8 424 #define SM501_CSC_V_SOURCE_BASE 0xDC 425 #define SM501_CSC_SOURCE_DIMENSION 0xE0 426 #define SM501_CSC_SOURCE_PITCH 0xE4 427 #define SM501_CSC_DESTINATION 0xE8 428 #define SM501_CSC_DESTINATION_DIMENSION 0xEC 429 #define SM501_CSC_DESTINATION_PITCH 0xF0 430 #define SM501_CSC_SCALE_FACTOR 0xF4 431 #define SM501_CSC_DESTINATION_BASE 0xF8 432 #define SM501_CSC_CONTROL 0xFC 433 434 /* 2d engine data port base */ 435 #define SM501_2D_ENGINE_DATA 0x110000 436 437 /* end of register definitions */ 438 439 #define SM501_HWC_WIDTH 64 440 #define SM501_HWC_HEIGHT 64 441 442 #ifdef CONFIG_PIXMAN 443 #define DEFAULT_X_PIXMAN 7 444 #else 445 #define DEFAULT_X_PIXMAN 0 446 #endif 447 448 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ 449 static const uint32_t sm501_mem_local_size[] = { 450 [0] = 4 * MiB, 451 [1] = 8 * MiB, 452 [2] = 16 * MiB, 453 [3] = 32 * MiB, 454 [4] = 64 * MiB, 455 [5] = 2 * MiB, 456 }; 457 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] 458 459 typedef struct SM501State { 460 /* graphic console status */ 461 QemuConsole *con; 462 463 /* status & internal resources */ 464 uint32_t local_mem_size_index; 465 uint8_t *local_mem; 466 MemoryRegion local_mem_region; 467 MemoryRegion mmio_region; 468 MemoryRegion system_config_region; 469 MemoryRegion i2c_region; 470 MemoryRegion disp_ctrl_region; 471 MemoryRegion twoD_engine_region; 472 uint32_t last_width; 473 uint32_t last_height; 474 bool do_full_update; /* perform a full update next time */ 475 uint8_t use_pixman; 476 I2CBus *i2c_bus; 477 478 /* mmio registers */ 479 uint32_t system_control; 480 uint32_t misc_control; 481 uint32_t gpio_31_0_control; 482 uint32_t gpio_63_32_control; 483 uint32_t dram_control; 484 uint32_t arbitration_control; 485 uint32_t irq_mask; 486 uint32_t misc_timing; 487 uint32_t power_mode_control; 488 489 uint8_t i2c_byte_count; 490 uint8_t i2c_status; 491 uint8_t i2c_addr; 492 uint8_t i2c_data[16]; 493 494 uint32_t uart0_ier; 495 uint32_t uart0_lcr; 496 uint32_t uart0_mcr; 497 uint32_t uart0_scr; 498 499 uint8_t dc_palette[DC_PALETTE_ENTRIES]; 500 501 uint32_t dc_panel_control; 502 uint32_t dc_panel_panning_control; 503 uint32_t dc_panel_fb_addr; 504 uint32_t dc_panel_fb_offset; 505 uint32_t dc_panel_fb_width; 506 uint32_t dc_panel_fb_height; 507 uint32_t dc_panel_tl_location; 508 uint32_t dc_panel_br_location; 509 uint32_t dc_panel_h_total; 510 uint32_t dc_panel_h_sync; 511 uint32_t dc_panel_v_total; 512 uint32_t dc_panel_v_sync; 513 514 uint32_t dc_panel_hwc_addr; 515 uint32_t dc_panel_hwc_location; 516 uint32_t dc_panel_hwc_color_1_2; 517 uint32_t dc_panel_hwc_color_3; 518 519 uint32_t dc_video_control; 520 521 uint32_t dc_crt_control; 522 uint32_t dc_crt_fb_addr; 523 uint32_t dc_crt_fb_offset; 524 uint32_t dc_crt_h_total; 525 uint32_t dc_crt_h_sync; 526 uint32_t dc_crt_v_total; 527 uint32_t dc_crt_v_sync; 528 529 uint32_t dc_crt_hwc_addr; 530 uint32_t dc_crt_hwc_location; 531 uint32_t dc_crt_hwc_color_1_2; 532 uint32_t dc_crt_hwc_color_3; 533 534 uint32_t twoD_source; 535 uint32_t twoD_destination; 536 uint32_t twoD_dimension; 537 uint32_t twoD_control; 538 uint32_t twoD_pitch; 539 uint32_t twoD_foreground; 540 uint32_t twoD_background; 541 uint32_t twoD_stretch; 542 uint32_t twoD_color_compare; 543 uint32_t twoD_color_compare_mask; 544 uint32_t twoD_mask; 545 uint32_t twoD_clip_tl; 546 uint32_t twoD_clip_br; 547 uint32_t twoD_mono_pattern_low; 548 uint32_t twoD_mono_pattern_high; 549 uint32_t twoD_window_width; 550 uint32_t twoD_source_base; 551 uint32_t twoD_destination_base; 552 uint32_t twoD_alpha; 553 uint32_t twoD_wrap; 554 } SM501State; 555 556 static uint32_t get_local_mem_size_index(uint32_t size) 557 { 558 uint32_t norm_size = 0; 559 int i, index = 0; 560 561 for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { 562 uint32_t new_size = sm501_mem_local_size[i]; 563 if (new_size >= size) { 564 if (norm_size == 0 || norm_size > new_size) { 565 norm_size = new_size; 566 index = i; 567 } 568 } 569 } 570 571 return index; 572 } 573 574 static ram_addr_t get_fb_addr(SM501State *s, int crt) 575 { 576 return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0; 577 } 578 579 static inline int get_width(SM501State *s, int crt) 580 { 581 int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total; 582 return (width & 0x00000FFF) + 1; 583 } 584 585 static inline int get_height(SM501State *s, int crt) 586 { 587 int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total; 588 return (height & 0x00000FFF) + 1; 589 } 590 591 static inline int get_bpp(SM501State *s, int crt) 592 { 593 int bpp = crt ? s->dc_crt_control : s->dc_panel_control; 594 return 1 << (bpp & 3); 595 } 596 597 /** 598 * Check the availability of hardware cursor. 599 * @param crt 0 for PANEL, 1 for CRT. 600 */ 601 static inline int is_hwc_enabled(SM501State *state, int crt) 602 { 603 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; 604 return addr & SM501_HWC_EN; 605 } 606 607 /** 608 * Get the address which holds cursor pattern data. 609 * @param crt 0 for PANEL, 1 for CRT. 610 */ 611 static inline uint8_t *get_hwc_address(SM501State *state, int crt) 612 { 613 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; 614 return state->local_mem + (addr & 0x03FFFFF0); 615 } 616 617 /** 618 * Get the cursor position in y coordinate. 619 * @param crt 0 for PANEL, 1 for CRT. 620 */ 621 static inline uint32_t get_hwc_y(SM501State *state, int crt) 622 { 623 uint32_t location = crt ? state->dc_crt_hwc_location 624 : state->dc_panel_hwc_location; 625 return (location & 0x07FF0000) >> 16; 626 } 627 628 /** 629 * Get the cursor position in x coordinate. 630 * @param crt 0 for PANEL, 1 for CRT. 631 */ 632 static inline uint32_t get_hwc_x(SM501State *state, int crt) 633 { 634 uint32_t location = crt ? state->dc_crt_hwc_location 635 : state->dc_panel_hwc_location; 636 return location & 0x000007FF; 637 } 638 639 /** 640 * Get the hardware cursor palette. 641 * @param crt 0 for PANEL, 1 for CRT. 642 * @param palette pointer to a [3 * 3] array to store color values in 643 */ 644 static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette) 645 { 646 int i; 647 uint32_t color_reg; 648 uint16_t rgb565; 649 650 for (i = 0; i < 3; i++) { 651 if (i + 1 == 3) { 652 color_reg = crt ? state->dc_crt_hwc_color_3 653 : state->dc_panel_hwc_color_3; 654 } else { 655 color_reg = crt ? state->dc_crt_hwc_color_1_2 656 : state->dc_panel_hwc_color_1_2; 657 } 658 659 if (i + 1 == 2) { 660 rgb565 = (color_reg >> 16) & 0xFFFF; 661 } else { 662 rgb565 = color_reg & 0xFFFF; 663 } 664 palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */ 665 palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */ 666 palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */ 667 } 668 } 669 670 static inline void hwc_invalidate(SM501State *s, int crt) 671 { 672 int w = get_width(s, crt); 673 int h = get_height(s, crt); 674 int bpp = get_bpp(s, crt); 675 int start = get_hwc_y(s, crt); 676 int end = MIN(h, start + SM501_HWC_HEIGHT) + 1; 677 678 start *= w * bpp; 679 end *= w * bpp; 680 681 memory_region_set_dirty(&s->local_mem_region, 682 get_fb_addr(s, crt) + start, end - start); 683 } 684 685 static void sm501_2d_operation(SM501State *s) 686 { 687 int cmd = (s->twoD_control >> 16) & 0x1F; 688 int rtl = s->twoD_control & BIT(27); 689 int format = (s->twoD_stretch >> 20) & 3; 690 int bypp = 1 << format; /* bytes per pixel */ 691 int rop_mode = (s->twoD_control >> 15) & 1; /* 1 for rop2, else rop3 */ 692 /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */ 693 int rop2_source_is_pattern = (s->twoD_control >> 14) & 1; 694 int rop = s->twoD_control & 0xFF; 695 unsigned int dst_x = (s->twoD_destination >> 16) & 0x01FFF; 696 unsigned int dst_y = s->twoD_destination & 0xFFFF; 697 unsigned int width = (s->twoD_dimension >> 16) & 0x1FFF; 698 unsigned int height = s->twoD_dimension & 0xFFFF; 699 uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF; 700 unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF; 701 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; 702 int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt); 703 bool overlap = false, fallback = false; 704 705 if ((s->twoD_stretch >> 16) & 0xF) { 706 qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n"); 707 return; 708 } 709 710 if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) { 711 qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n"); 712 return; 713 } 714 715 if (!dst_pitch) { 716 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero dest pitch.\n"); 717 return; 718 } 719 720 if (!width || !height) { 721 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero size 2D op.\n"); 722 return; 723 } 724 725 if (rtl) { 726 dst_x -= width - 1; 727 dst_y -= height - 1; 728 } 729 730 if (dst_base >= get_local_mem_size(s) || 731 dst_base + (dst_x + width + (dst_y + height) * dst_pitch) * bypp >= 732 get_local_mem_size(s)) { 733 qemu_log_mask(LOG_GUEST_ERROR, "sm501: 2D op dest is outside vram.\n"); 734 return; 735 } 736 737 switch (cmd) { 738 case 0: /* BitBlt */ 739 { 740 unsigned int src_x = (s->twoD_source >> 16) & 0x01FFF; 741 unsigned int src_y = s->twoD_source & 0xFFFF; 742 uint32_t src_base = s->twoD_source_base & 0x03FFFFFF; 743 unsigned int src_pitch = s->twoD_pitch & 0x1FFF; 744 745 if (!src_pitch) { 746 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero src pitch.\n"); 747 return; 748 } 749 750 if (rtl) { 751 src_x -= width - 1; 752 src_y -= height - 1; 753 } 754 755 if (src_base >= get_local_mem_size(s) || 756 src_base + (src_x + width + (src_y + height) * src_pitch) * bypp >= 757 get_local_mem_size(s)) { 758 qemu_log_mask(LOG_GUEST_ERROR, 759 "sm501: 2D op src is outside vram.\n"); 760 return; 761 } 762 763 if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) { 764 /* DSTINVERT, is there a way to do this with pixman? */ 765 unsigned int x, y, i; 766 uint8_t *d = s->local_mem + dst_base; 767 768 for (y = 0; y < height; y++) { 769 i = (dst_x + (dst_y + y) * dst_pitch) * bypp; 770 for (x = 0; x < width; x++, i += bypp) { 771 stn_he_p(&d[i], bypp, ~ldn_he_p(&d[i], bypp)); 772 } 773 } 774 } else if (!rop_mode && rop == 0x99) { 775 /* DSxn, is there a way to do this with pixman? */ 776 unsigned int x, y, i, j; 777 uint8_t *sp = s->local_mem + src_base; 778 uint8_t *d = s->local_mem + dst_base; 779 780 for (y = 0; y < height; y++) { 781 i = (dst_x + (dst_y + y) * dst_pitch) * bypp; 782 j = (src_x + (src_y + y) * src_pitch) * bypp; 783 for (x = 0; x < width; x++, i += bypp, j += bypp) { 784 stn_he_p(&d[i], bypp, 785 ~(ldn_he_p(&sp[j], bypp) ^ ldn_he_p(&d[i], bypp))); 786 } 787 } 788 } else if (!rop_mode && rop == 0xee) { 789 /* SRCPAINT, is there a way to do this with pixman? */ 790 unsigned int x, y, i, j; 791 uint8_t *sp = s->local_mem + src_base; 792 uint8_t *d = s->local_mem + dst_base; 793 794 for (y = 0; y < height; y++) { 795 i = (dst_x + (dst_y + y) * dst_pitch) * bypp; 796 j = (src_x + (src_y + y) * src_pitch) * bypp; 797 for (x = 0; x < width; x++, i += bypp, j += bypp) { 798 stn_he_p(&d[i], bypp, 799 ldn_he_p(&sp[j], bypp) | ldn_he_p(&d[i], bypp)); 800 } 801 } 802 } else { 803 /* Do copy src for unimplemented ops, better than unpainted area */ 804 if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) || 805 (!rop_mode && rop != 0xcc)) { 806 qemu_log_mask(LOG_UNIMP, 807 "sm501: rop%d op %x%s not implemented\n", 808 (rop_mode ? 2 : 3), rop, 809 (rop2_source_is_pattern ? 810 " with pattern source" : "")); 811 } 812 /* Ignore no-op blits, some guests seem to do this */ 813 if (src_base == dst_base && src_pitch == dst_pitch && 814 src_x == dst_x && src_y == dst_y) { 815 break; 816 } 817 /* Some clients also do 1 pixel blits, avoid overhead for these */ 818 if (width == 1 && height == 1) { 819 unsigned int si = (src_x + src_y * src_pitch) * bypp; 820 unsigned int di = (dst_x + dst_y * dst_pitch) * bypp; 821 stn_he_p(&s->local_mem[dst_base + di], bypp, 822 ldn_he_p(&s->local_mem[src_base + si], bypp)); 823 break; 824 } 825 /* If reverse blit do simple check for overlaps */ 826 if (rtl && src_base == dst_base && src_pitch == dst_pitch) { 827 overlap = (src_x < dst_x + width && src_x + width > dst_x && 828 src_y < dst_y + height && src_y + height > dst_y); 829 } else if (rtl) { 830 unsigned int sb, se, db, de; 831 sb = src_base + (src_x + src_y * src_pitch) * bypp; 832 se = sb + (width + (height - 1) * src_pitch) * bypp; 833 db = dst_base + (dst_x + dst_y * dst_pitch) * bypp; 834 de = db + (width + (height - 1) * dst_pitch) * bypp; 835 overlap = (db < se && sb < de); 836 } 837 #ifdef CONFIG_PIXMAN 838 if (overlap && (s->use_pixman & BIT(2))) { 839 /* pixman can't do reverse blit: copy via temporary */ 840 int tmp_stride = DIV_ROUND_UP(width * bypp, sizeof(uint32_t)); 841 static uint32_t tmp_buf[16384]; 842 uint32_t *tmp = tmp_buf; 843 844 if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) { 845 tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height); 846 } 847 fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base], 848 tmp, 849 src_pitch * bypp / sizeof(uint32_t), 850 tmp_stride, 851 8 * bypp, 8 * bypp, 852 src_x, src_y, 0, 0, width, height); 853 if (!fallback) { 854 fallback = !pixman_blt(tmp, 855 (uint32_t *)&s->local_mem[dst_base], 856 tmp_stride, 857 dst_pitch * bypp / sizeof(uint32_t), 858 8 * bypp, 8 * bypp, 859 0, 0, dst_x, dst_y, width, height); 860 } 861 if (tmp != tmp_buf) { 862 g_free(tmp); 863 } 864 } else if (!overlap && (s->use_pixman & BIT(1))) { 865 fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base], 866 (uint32_t *)&s->local_mem[dst_base], 867 src_pitch * bypp / sizeof(uint32_t), 868 dst_pitch * bypp / sizeof(uint32_t), 869 8 * bypp, 8 * bypp, src_x, src_y, 870 dst_x, dst_y, width, height); 871 } else 872 #endif 873 { 874 fallback = true; 875 } 876 if (fallback) { 877 uint8_t *sp = s->local_mem + src_base; 878 uint8_t *d = s->local_mem + dst_base; 879 unsigned int y, i, j; 880 for (y = 0; y < height; y++) { 881 if (overlap) { /* overlap also means rtl */ 882 i = (dst_y + height - 1 - y) * dst_pitch; 883 i = (dst_x + i) * bypp; 884 j = (src_y + height - 1 - y) * src_pitch; 885 j = (src_x + j) * bypp; 886 memmove(&d[i], &sp[j], width * bypp); 887 } else { 888 i = (dst_x + (dst_y + y) * dst_pitch) * bypp; 889 j = (src_x + (src_y + y) * src_pitch) * bypp; 890 memcpy(&d[i], &sp[j], width * bypp); 891 } 892 } 893 } 894 } 895 break; 896 } 897 case 1: /* Rectangle Fill */ 898 { 899 uint32_t color = s->twoD_foreground; 900 901 if (format == 2) { 902 color = cpu_to_le32(color); 903 } else if (format == 1) { 904 color = cpu_to_le16(color); 905 } 906 907 #ifdef CONFIG_PIXMAN 908 if (!(s->use_pixman & BIT(0)) || (width == 1 && height == 1) || 909 !pixman_fill((uint32_t *)&s->local_mem[dst_base], 910 dst_pitch * bypp / sizeof(uint32_t), 8 * bypp, 911 dst_x, dst_y, width, height, color)) 912 #endif 913 { 914 /* fallback when pixman failed or we don't want to call it */ 915 uint8_t *d = s->local_mem + dst_base; 916 unsigned int x, y, i; 917 for (y = 0; y < height; y++) { 918 i = (dst_x + (dst_y + y) * dst_pitch) * bypp; 919 for (x = 0; x < width; x++, i += bypp) { 920 stn_he_p(&d[i], bypp, color); 921 } 922 } 923 } 924 break; 925 } 926 default: 927 qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n", 928 cmd); 929 return; 930 } 931 932 if (dst_base >= get_fb_addr(s, crt) && 933 dst_base <= get_fb_addr(s, crt) + fb_len) { 934 int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch + 935 dst_x + width) * bypp); 936 if (dst_len) { 937 memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len); 938 } 939 } 940 } 941 942 static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, 943 unsigned size) 944 { 945 SM501State *s = opaque; 946 uint32_t ret = 0; 947 948 switch (addr) { 949 case SM501_SYSTEM_CONTROL: 950 ret = s->system_control; 951 break; 952 case SM501_MISC_CONTROL: 953 ret = s->misc_control; 954 break; 955 case SM501_GPIO31_0_CONTROL: 956 ret = s->gpio_31_0_control; 957 break; 958 case SM501_GPIO63_32_CONTROL: 959 ret = s->gpio_63_32_control; 960 break; 961 case SM501_DEVICEID: 962 ret = 0x050100A0; 963 break; 964 case SM501_DRAM_CONTROL: 965 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; 966 break; 967 case SM501_ARBTRTN_CONTROL: 968 ret = s->arbitration_control; 969 break; 970 case SM501_COMMAND_LIST_STATUS: 971 ret = 0x00180002; /* FIFOs are empty, everything idle */ 972 break; 973 case SM501_IRQ_MASK: 974 ret = s->irq_mask; 975 break; 976 case SM501_MISC_TIMING: 977 /* TODO : simulate gate control */ 978 ret = s->misc_timing; 979 break; 980 case SM501_CURRENT_GATE: 981 /* TODO : simulate gate control */ 982 ret = 0x00021807; 983 break; 984 case SM501_CURRENT_CLOCK: 985 ret = 0x2A1A0A09; 986 break; 987 case SM501_POWER_MODE_CONTROL: 988 ret = s->power_mode_control; 989 break; 990 case SM501_ENDIAN_CONTROL: 991 ret = 0; /* Only default little endian mode is supported */ 992 break; 993 994 default: 995 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" 996 "register read. addr=%" HWADDR_PRIx "\n", addr); 997 } 998 trace_sm501_system_config_read(addr, ret); 999 return ret; 1000 } 1001 1002 static void sm501_system_config_write(void *opaque, hwaddr addr, 1003 uint64_t value, unsigned size) 1004 { 1005 SM501State *s = opaque; 1006 1007 trace_sm501_system_config_write((uint32_t)addr, (uint32_t)value); 1008 switch (addr) { 1009 case SM501_SYSTEM_CONTROL: 1010 s->system_control &= 0x10DB0000; 1011 s->system_control |= value & 0xEF00B8F7; 1012 break; 1013 case SM501_MISC_CONTROL: 1014 s->misc_control &= 0xEF; 1015 s->misc_control |= value & 0xFF7FFF10; 1016 break; 1017 case SM501_GPIO31_0_CONTROL: 1018 s->gpio_31_0_control = value; 1019 break; 1020 case SM501_GPIO63_32_CONTROL: 1021 s->gpio_63_32_control = value & 0xFF80FFFF; 1022 break; 1023 case SM501_DRAM_CONTROL: 1024 s->local_mem_size_index = (value >> 13) & 0x7; 1025 /* TODO : check validity of size change */ 1026 s->dram_control &= 0x80000000; 1027 s->dram_control |= value & 0x7FFFFFC3; 1028 break; 1029 case SM501_ARBTRTN_CONTROL: 1030 s->arbitration_control = value & 0x37777777; 1031 break; 1032 case SM501_IRQ_MASK: 1033 s->irq_mask = value & 0xFFDF3F5F; 1034 break; 1035 case SM501_MISC_TIMING: 1036 s->misc_timing = value & 0xF31F1FFF; 1037 break; 1038 case SM501_POWER_MODE_0_GATE: 1039 case SM501_POWER_MODE_1_GATE: 1040 case SM501_POWER_MODE_0_CLOCK: 1041 case SM501_POWER_MODE_1_CLOCK: 1042 /* TODO : simulate gate & clock control */ 1043 break; 1044 case SM501_POWER_MODE_CONTROL: 1045 s->power_mode_control = value & 0x00000003; 1046 break; 1047 case SM501_ENDIAN_CONTROL: 1048 if (value & 0x00000001) { 1049 qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not" 1050 " implemented.\n"); 1051 } 1052 break; 1053 1054 default: 1055 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" 1056 "register write. addr=%" HWADDR_PRIx 1057 ", val=%" PRIx64 "\n", addr, value); 1058 } 1059 } 1060 1061 static const MemoryRegionOps sm501_system_config_ops = { 1062 .read = sm501_system_config_read, 1063 .write = sm501_system_config_write, 1064 .valid = { 1065 .min_access_size = 4, 1066 .max_access_size = 4, 1067 }, 1068 .endianness = DEVICE_LITTLE_ENDIAN, 1069 }; 1070 1071 static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) 1072 { 1073 SM501State *s = opaque; 1074 uint8_t ret = 0; 1075 1076 switch (addr) { 1077 case SM501_I2C_BYTE_COUNT: 1078 ret = s->i2c_byte_count; 1079 break; 1080 case SM501_I2C_STATUS: 1081 ret = s->i2c_status; 1082 break; 1083 case SM501_I2C_SLAVE_ADDRESS: 1084 ret = s->i2c_addr; 1085 break; 1086 case SM501_I2C_DATA ... SM501_I2C_DATA + 15: 1087 ret = s->i2c_data[addr - SM501_I2C_DATA]; 1088 break; 1089 default: 1090 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." 1091 " addr=0x%" HWADDR_PRIx "\n", addr); 1092 } 1093 trace_sm501_i2c_read((uint32_t)addr, ret); 1094 return ret; 1095 } 1096 1097 static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value, 1098 unsigned size) 1099 { 1100 SM501State *s = opaque; 1101 1102 trace_sm501_i2c_write((uint32_t)addr, (uint32_t)value); 1103 switch (addr) { 1104 case SM501_I2C_BYTE_COUNT: 1105 s->i2c_byte_count = value & 0xf; 1106 break; 1107 case SM501_I2C_CONTROL: 1108 if (value & SM501_I2C_CONTROL_ENABLE) { 1109 if (value & SM501_I2C_CONTROL_START) { 1110 bool is_recv = s->i2c_addr & 1; 1111 int res = i2c_start_transfer(s->i2c_bus, 1112 s->i2c_addr >> 1, 1113 is_recv); 1114 if (res) { 1115 s->i2c_status |= SM501_I2C_STATUS_ERROR; 1116 } else { 1117 int i; 1118 for (i = 0; i <= s->i2c_byte_count; i++) { 1119 if (is_recv) { 1120 s->i2c_data[i] = i2c_recv(s->i2c_bus); 1121 } else if (i2c_send(s->i2c_bus, s->i2c_data[i]) < 0) { 1122 s->i2c_status |= SM501_I2C_STATUS_ERROR; 1123 return; 1124 } 1125 } 1126 if (i) { 1127 s->i2c_status = SM501_I2C_STATUS_COMPLETE; 1128 } 1129 } 1130 } else { 1131 i2c_end_transfer(s->i2c_bus); 1132 s->i2c_status &= ~SM501_I2C_STATUS_ERROR; 1133 } 1134 } 1135 break; 1136 case SM501_I2C_RESET: 1137 if ((value & SM501_I2C_RESET_ERROR) == 0) { 1138 s->i2c_status &= ~SM501_I2C_STATUS_ERROR; 1139 } 1140 break; 1141 case SM501_I2C_SLAVE_ADDRESS: 1142 s->i2c_addr = value & 0xff; 1143 break; 1144 case SM501_I2C_DATA ... SM501_I2C_DATA + 15: 1145 s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff; 1146 break; 1147 default: 1148 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. " 1149 "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value); 1150 } 1151 } 1152 1153 static const MemoryRegionOps sm501_i2c_ops = { 1154 .read = sm501_i2c_read, 1155 .write = sm501_i2c_write, 1156 .valid = { 1157 .min_access_size = 1, 1158 .max_access_size = 1, 1159 }, 1160 .impl = { 1161 .min_access_size = 1, 1162 .max_access_size = 1, 1163 }, 1164 .endianness = DEVICE_LITTLE_ENDIAN, 1165 }; 1166 1167 static uint32_t sm501_palette_read(void *opaque, hwaddr addr) 1168 { 1169 SM501State *s = opaque; 1170 1171 trace_sm501_palette_read((uint32_t)addr); 1172 1173 /* TODO : consider BYTE/WORD access */ 1174 /* TODO : consider endian */ 1175 1176 assert(range_covers_byte(0, 0x400 * 3, addr)); 1177 return *(uint32_t *)&s->dc_palette[addr]; 1178 } 1179 1180 static void sm501_palette_write(void *opaque, hwaddr addr, 1181 uint32_t value) 1182 { 1183 SM501State *s = opaque; 1184 1185 trace_sm501_palette_write((uint32_t)addr, value); 1186 1187 /* TODO : consider BYTE/WORD access */ 1188 /* TODO : consider endian */ 1189 1190 assert(range_covers_byte(0, 0x400 * 3, addr)); 1191 *(uint32_t *)&s->dc_palette[addr] = value; 1192 s->do_full_update = true; 1193 } 1194 1195 static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, 1196 unsigned size) 1197 { 1198 SM501State *s = opaque; 1199 uint32_t ret = 0; 1200 1201 switch (addr) { 1202 1203 case SM501_DC_PANEL_CONTROL: 1204 ret = s->dc_panel_control; 1205 break; 1206 case SM501_DC_PANEL_PANNING_CONTROL: 1207 ret = s->dc_panel_panning_control; 1208 break; 1209 case SM501_DC_PANEL_COLOR_KEY: 1210 /* Not implemented yet */ 1211 break; 1212 case SM501_DC_PANEL_FB_ADDR: 1213 ret = s->dc_panel_fb_addr; 1214 break; 1215 case SM501_DC_PANEL_FB_OFFSET: 1216 ret = s->dc_panel_fb_offset; 1217 break; 1218 case SM501_DC_PANEL_FB_WIDTH: 1219 ret = s->dc_panel_fb_width; 1220 break; 1221 case SM501_DC_PANEL_FB_HEIGHT: 1222 ret = s->dc_panel_fb_height; 1223 break; 1224 case SM501_DC_PANEL_TL_LOC: 1225 ret = s->dc_panel_tl_location; 1226 break; 1227 case SM501_DC_PANEL_BR_LOC: 1228 ret = s->dc_panel_br_location; 1229 break; 1230 1231 case SM501_DC_PANEL_H_TOT: 1232 ret = s->dc_panel_h_total; 1233 break; 1234 case SM501_DC_PANEL_H_SYNC: 1235 ret = s->dc_panel_h_sync; 1236 break; 1237 case SM501_DC_PANEL_V_TOT: 1238 ret = s->dc_panel_v_total; 1239 break; 1240 case SM501_DC_PANEL_V_SYNC: 1241 ret = s->dc_panel_v_sync; 1242 break; 1243 1244 case SM501_DC_PANEL_HWC_ADDR: 1245 ret = s->dc_panel_hwc_addr; 1246 break; 1247 case SM501_DC_PANEL_HWC_LOC: 1248 ret = s->dc_panel_hwc_location; 1249 break; 1250 case SM501_DC_PANEL_HWC_COLOR_1_2: 1251 ret = s->dc_panel_hwc_color_1_2; 1252 break; 1253 case SM501_DC_PANEL_HWC_COLOR_3: 1254 ret = s->dc_panel_hwc_color_3; 1255 break; 1256 1257 case SM501_DC_VIDEO_CONTROL: 1258 ret = s->dc_video_control; 1259 break; 1260 1261 case SM501_DC_CRT_CONTROL: 1262 ret = s->dc_crt_control; 1263 break; 1264 case SM501_DC_CRT_FB_ADDR: 1265 ret = s->dc_crt_fb_addr; 1266 break; 1267 case SM501_DC_CRT_FB_OFFSET: 1268 ret = s->dc_crt_fb_offset; 1269 break; 1270 case SM501_DC_CRT_H_TOT: 1271 ret = s->dc_crt_h_total; 1272 break; 1273 case SM501_DC_CRT_H_SYNC: 1274 ret = s->dc_crt_h_sync; 1275 break; 1276 case SM501_DC_CRT_V_TOT: 1277 ret = s->dc_crt_v_total; 1278 break; 1279 case SM501_DC_CRT_V_SYNC: 1280 ret = s->dc_crt_v_sync; 1281 break; 1282 1283 case SM501_DC_CRT_HWC_ADDR: 1284 ret = s->dc_crt_hwc_addr; 1285 break; 1286 case SM501_DC_CRT_HWC_LOC: 1287 ret = s->dc_crt_hwc_location; 1288 break; 1289 case SM501_DC_CRT_HWC_COLOR_1_2: 1290 ret = s->dc_crt_hwc_color_1_2; 1291 break; 1292 case SM501_DC_CRT_HWC_COLOR_3: 1293 ret = s->dc_crt_hwc_color_3; 1294 break; 1295 1296 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: 1297 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); 1298 break; 1299 1300 default: 1301 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " 1302 "read. addr=%" HWADDR_PRIx "\n", addr); 1303 } 1304 trace_sm501_disp_ctrl_read((uint32_t)addr, ret); 1305 return ret; 1306 } 1307 1308 static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, 1309 uint64_t value, unsigned size) 1310 { 1311 SM501State *s = opaque; 1312 1313 trace_sm501_disp_ctrl_write((uint32_t)addr, (uint32_t)value); 1314 switch (addr) { 1315 case SM501_DC_PANEL_CONTROL: 1316 s->dc_panel_control = value & 0x0FFF73FF; 1317 break; 1318 case SM501_DC_PANEL_PANNING_CONTROL: 1319 s->dc_panel_panning_control = value & 0xFF3FFF3F; 1320 break; 1321 case SM501_DC_PANEL_COLOR_KEY: 1322 /* Not implemented yet */ 1323 break; 1324 case SM501_DC_PANEL_FB_ADDR: 1325 s->dc_panel_fb_addr = value & 0x8FFFFFF0; 1326 if (value & 0x8000000) { 1327 qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n"); 1328 } 1329 s->do_full_update = true; 1330 break; 1331 case SM501_DC_PANEL_FB_OFFSET: 1332 s->dc_panel_fb_offset = value & 0x3FF03FF0; 1333 break; 1334 case SM501_DC_PANEL_FB_WIDTH: 1335 s->dc_panel_fb_width = value & 0x0FFF0FFF; 1336 break; 1337 case SM501_DC_PANEL_FB_HEIGHT: 1338 s->dc_panel_fb_height = value & 0x0FFF0FFF; 1339 break; 1340 case SM501_DC_PANEL_TL_LOC: 1341 s->dc_panel_tl_location = value & 0x07FF07FF; 1342 break; 1343 case SM501_DC_PANEL_BR_LOC: 1344 s->dc_panel_br_location = value & 0x07FF07FF; 1345 break; 1346 1347 case SM501_DC_PANEL_H_TOT: 1348 s->dc_panel_h_total = value & 0x0FFF0FFF; 1349 break; 1350 case SM501_DC_PANEL_H_SYNC: 1351 s->dc_panel_h_sync = value & 0x00FF0FFF; 1352 break; 1353 case SM501_DC_PANEL_V_TOT: 1354 s->dc_panel_v_total = value & 0x0FFF0FFF; 1355 break; 1356 case SM501_DC_PANEL_V_SYNC: 1357 s->dc_panel_v_sync = value & 0x003F0FFF; 1358 break; 1359 1360 case SM501_DC_PANEL_HWC_ADDR: 1361 value &= 0x8FFFFFF0; 1362 if (value != s->dc_panel_hwc_addr) { 1363 hwc_invalidate(s, 0); 1364 s->dc_panel_hwc_addr = value; 1365 } 1366 break; 1367 case SM501_DC_PANEL_HWC_LOC: 1368 value &= 0x0FFF0FFF; 1369 if (value != s->dc_panel_hwc_location) { 1370 hwc_invalidate(s, 0); 1371 s->dc_panel_hwc_location = value; 1372 } 1373 break; 1374 case SM501_DC_PANEL_HWC_COLOR_1_2: 1375 s->dc_panel_hwc_color_1_2 = value; 1376 break; 1377 case SM501_DC_PANEL_HWC_COLOR_3: 1378 s->dc_panel_hwc_color_3 = value & 0x0000FFFF; 1379 break; 1380 1381 case SM501_DC_VIDEO_CONTROL: 1382 s->dc_video_control = value & 0x00037FFF; 1383 break; 1384 1385 case SM501_DC_CRT_CONTROL: 1386 s->dc_crt_control = value & 0x0003FFFF; 1387 break; 1388 case SM501_DC_CRT_FB_ADDR: 1389 s->dc_crt_fb_addr = value & 0x8FFFFFF0; 1390 if (value & 0x8000000) { 1391 qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n"); 1392 } 1393 s->do_full_update = true; 1394 break; 1395 case SM501_DC_CRT_FB_OFFSET: 1396 s->dc_crt_fb_offset = value & 0x3FF03FF0; 1397 break; 1398 case SM501_DC_CRT_H_TOT: 1399 s->dc_crt_h_total = value & 0x0FFF0FFF; 1400 break; 1401 case SM501_DC_CRT_H_SYNC: 1402 s->dc_crt_h_sync = value & 0x00FF0FFF; 1403 break; 1404 case SM501_DC_CRT_V_TOT: 1405 s->dc_crt_v_total = value & 0x0FFF0FFF; 1406 break; 1407 case SM501_DC_CRT_V_SYNC: 1408 s->dc_crt_v_sync = value & 0x003F0FFF; 1409 break; 1410 1411 case SM501_DC_CRT_HWC_ADDR: 1412 value &= 0x8FFFFFF0; 1413 if (value != s->dc_crt_hwc_addr) { 1414 hwc_invalidate(s, 1); 1415 s->dc_crt_hwc_addr = value; 1416 } 1417 break; 1418 case SM501_DC_CRT_HWC_LOC: 1419 value &= 0x0FFF0FFF; 1420 if (value != s->dc_crt_hwc_location) { 1421 hwc_invalidate(s, 1); 1422 s->dc_crt_hwc_location = value; 1423 } 1424 break; 1425 case SM501_DC_CRT_HWC_COLOR_1_2: 1426 s->dc_crt_hwc_color_1_2 = value; 1427 break; 1428 case SM501_DC_CRT_HWC_COLOR_3: 1429 s->dc_crt_hwc_color_3 = value & 0x0000FFFF; 1430 break; 1431 1432 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: 1433 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); 1434 break; 1435 1436 default: 1437 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " 1438 "write. addr=%" HWADDR_PRIx 1439 ", val=%" PRIx64 "\n", addr, value); 1440 } 1441 } 1442 1443 static const MemoryRegionOps sm501_disp_ctrl_ops = { 1444 .read = sm501_disp_ctrl_read, 1445 .write = sm501_disp_ctrl_write, 1446 .valid = { 1447 .min_access_size = 4, 1448 .max_access_size = 4, 1449 }, 1450 .endianness = DEVICE_LITTLE_ENDIAN, 1451 }; 1452 1453 static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, 1454 unsigned size) 1455 { 1456 SM501State *s = opaque; 1457 uint32_t ret = 0; 1458 1459 switch (addr) { 1460 case SM501_2D_SOURCE: 1461 ret = s->twoD_source; 1462 break; 1463 case SM501_2D_DESTINATION: 1464 ret = s->twoD_destination; 1465 break; 1466 case SM501_2D_DIMENSION: 1467 ret = s->twoD_dimension; 1468 break; 1469 case SM501_2D_CONTROL: 1470 ret = s->twoD_control; 1471 break; 1472 case SM501_2D_PITCH: 1473 ret = s->twoD_pitch; 1474 break; 1475 case SM501_2D_FOREGROUND: 1476 ret = s->twoD_foreground; 1477 break; 1478 case SM501_2D_BACKGROUND: 1479 ret = s->twoD_background; 1480 break; 1481 case SM501_2D_STRETCH: 1482 ret = s->twoD_stretch; 1483 break; 1484 case SM501_2D_COLOR_COMPARE: 1485 ret = s->twoD_color_compare; 1486 break; 1487 case SM501_2D_COLOR_COMPARE_MASK: 1488 ret = s->twoD_color_compare_mask; 1489 break; 1490 case SM501_2D_MASK: 1491 ret = s->twoD_mask; 1492 break; 1493 case SM501_2D_CLIP_TL: 1494 ret = s->twoD_clip_tl; 1495 break; 1496 case SM501_2D_CLIP_BR: 1497 ret = s->twoD_clip_br; 1498 break; 1499 case SM501_2D_MONO_PATTERN_LOW: 1500 ret = s->twoD_mono_pattern_low; 1501 break; 1502 case SM501_2D_MONO_PATTERN_HIGH: 1503 ret = s->twoD_mono_pattern_high; 1504 break; 1505 case SM501_2D_WINDOW_WIDTH: 1506 ret = s->twoD_window_width; 1507 break; 1508 case SM501_2D_SOURCE_BASE: 1509 ret = s->twoD_source_base; 1510 break; 1511 case SM501_2D_DESTINATION_BASE: 1512 ret = s->twoD_destination_base; 1513 break; 1514 case SM501_2D_ALPHA: 1515 ret = s->twoD_alpha; 1516 break; 1517 case SM501_2D_WRAP: 1518 ret = s->twoD_wrap; 1519 break; 1520 case SM501_2D_STATUS: 1521 ret = 0; /* Should return interrupt status */ 1522 break; 1523 default: 1524 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " 1525 "read. addr=%" HWADDR_PRIx "\n", addr); 1526 } 1527 trace_sm501_2d_engine_read((uint32_t)addr, ret); 1528 return ret; 1529 } 1530 1531 static void sm501_2d_engine_write(void *opaque, hwaddr addr, 1532 uint64_t value, unsigned size) 1533 { 1534 SM501State *s = opaque; 1535 1536 trace_sm501_2d_engine_write((uint32_t)addr, (uint32_t)value); 1537 switch (addr) { 1538 case SM501_2D_SOURCE: 1539 s->twoD_source = value; 1540 break; 1541 case SM501_2D_DESTINATION: 1542 s->twoD_destination = value; 1543 break; 1544 case SM501_2D_DIMENSION: 1545 s->twoD_dimension = value; 1546 break; 1547 case SM501_2D_CONTROL: 1548 s->twoD_control = value; 1549 1550 /* do 2d operation if start flag is set. */ 1551 if (value & 0x80000000) { 1552 sm501_2d_operation(s); 1553 s->twoD_control &= ~0x80000000; /* start flag down */ 1554 } 1555 1556 break; 1557 case SM501_2D_PITCH: 1558 s->twoD_pitch = value; 1559 break; 1560 case SM501_2D_FOREGROUND: 1561 s->twoD_foreground = value; 1562 break; 1563 case SM501_2D_BACKGROUND: 1564 s->twoD_background = value; 1565 break; 1566 case SM501_2D_STRETCH: 1567 if (((value >> 20) & 3) == 3) { 1568 value &= ~BIT(20); 1569 } 1570 s->twoD_stretch = value; 1571 break; 1572 case SM501_2D_COLOR_COMPARE: 1573 s->twoD_color_compare = value; 1574 break; 1575 case SM501_2D_COLOR_COMPARE_MASK: 1576 s->twoD_color_compare_mask = value; 1577 break; 1578 case SM501_2D_MASK: 1579 s->twoD_mask = value; 1580 break; 1581 case SM501_2D_CLIP_TL: 1582 s->twoD_clip_tl = value; 1583 break; 1584 case SM501_2D_CLIP_BR: 1585 s->twoD_clip_br = value; 1586 break; 1587 case SM501_2D_MONO_PATTERN_LOW: 1588 s->twoD_mono_pattern_low = value; 1589 break; 1590 case SM501_2D_MONO_PATTERN_HIGH: 1591 s->twoD_mono_pattern_high = value; 1592 break; 1593 case SM501_2D_WINDOW_WIDTH: 1594 s->twoD_window_width = value; 1595 break; 1596 case SM501_2D_SOURCE_BASE: 1597 s->twoD_source_base = value; 1598 break; 1599 case SM501_2D_DESTINATION_BASE: 1600 s->twoD_destination_base = value; 1601 break; 1602 case SM501_2D_ALPHA: 1603 s->twoD_alpha = value; 1604 break; 1605 case SM501_2D_WRAP: 1606 s->twoD_wrap = value; 1607 break; 1608 case SM501_2D_STATUS: 1609 /* ignored, writing 0 should clear interrupt status */ 1610 break; 1611 default: 1612 qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register " 1613 "write. addr=%" HWADDR_PRIx 1614 ", val=%" PRIx64 "\n", addr, value); 1615 } 1616 } 1617 1618 static const MemoryRegionOps sm501_2d_engine_ops = { 1619 .read = sm501_2d_engine_read, 1620 .write = sm501_2d_engine_write, 1621 .valid = { 1622 .min_access_size = 4, 1623 .max_access_size = 4, 1624 }, 1625 .endianness = DEVICE_LITTLE_ENDIAN, 1626 }; 1627 1628 /* draw line functions for all console modes */ 1629 1630 typedef void draw_line_func(uint8_t *d, const uint8_t *s, 1631 int width, const uint32_t *pal); 1632 1633 typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s, 1634 int width, const uint8_t *palette, 1635 int c_x, int c_y); 1636 1637 static void draw_line8_32(uint8_t *d, const uint8_t *s, int width, 1638 const uint32_t *pal) 1639 { 1640 uint8_t v, r, g, b; 1641 do { 1642 v = ldub_p(s); 1643 r = (pal[v] >> 16) & 0xff; 1644 g = (pal[v] >> 8) & 0xff; 1645 b = (pal[v] >> 0) & 0xff; 1646 *(uint32_t *)d = rgb_to_pixel32(r, g, b); 1647 s++; 1648 d += 4; 1649 } while (--width != 0); 1650 } 1651 1652 static void draw_line16_32(uint8_t *d, const uint8_t *s, int width, 1653 const uint32_t *pal) 1654 { 1655 uint16_t rgb565; 1656 uint8_t r, g, b; 1657 1658 do { 1659 rgb565 = lduw_le_p(s); 1660 r = (rgb565 >> 8) & 0xf8; 1661 g = (rgb565 >> 3) & 0xfc; 1662 b = (rgb565 << 3) & 0xf8; 1663 *(uint32_t *)d = rgb_to_pixel32(r, g, b); 1664 s += 2; 1665 d += 4; 1666 } while (--width != 0); 1667 } 1668 1669 static void draw_line32_32(uint8_t *d, const uint8_t *s, int width, 1670 const uint32_t *pal) 1671 { 1672 uint8_t r, g, b; 1673 1674 do { 1675 r = s[2]; 1676 g = s[1]; 1677 b = s[0]; 1678 *(uint32_t *)d = rgb_to_pixel32(r, g, b); 1679 s += 4; 1680 d += 4; 1681 } while (--width != 0); 1682 } 1683 1684 /** 1685 * Draw hardware cursor image on the given line. 1686 */ 1687 static void draw_hwc_line_32(uint8_t *d, const uint8_t *s, int width, 1688 const uint8_t *palette, int c_x, int c_y) 1689 { 1690 int i; 1691 uint8_t r, g, b, v, bitset = 0; 1692 1693 /* get cursor position */ 1694 assert(0 <= c_y && c_y < SM501_HWC_HEIGHT); 1695 s += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */ 1696 d += c_x * 4; 1697 1698 for (i = 0; i < SM501_HWC_WIDTH && c_x + i < width; i++) { 1699 /* get pixel value */ 1700 if (i % 4 == 0) { 1701 bitset = ldub_p(s); 1702 s++; 1703 } 1704 v = bitset & 3; 1705 bitset >>= 2; 1706 1707 /* write pixel */ 1708 if (v) { 1709 v--; 1710 r = palette[v * 3 + 0]; 1711 g = palette[v * 3 + 1]; 1712 b = palette[v * 3 + 2]; 1713 *(uint32_t *)d = rgb_to_pixel32(r, g, b); 1714 } 1715 d += 4; 1716 } 1717 } 1718 1719 static void sm501_update_display(void *opaque) 1720 { 1721 SM501State *s = opaque; 1722 DisplaySurface *surface = qemu_console_surface(s->con); 1723 DirtyBitmapSnapshot *snap; 1724 int y, c_x = 0, c_y = 0; 1725 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; 1726 int width = get_width(s, crt); 1727 int height = get_height(s, crt); 1728 int src_bpp = get_bpp(s, crt); 1729 int dst_bpp = surface_bytes_per_pixel(surface); 1730 draw_line_func *draw_line = NULL; 1731 draw_hwc_line_func *draw_hwc_line = NULL; 1732 int full_update = 0; 1733 int y_start = -1; 1734 ram_addr_t offset; 1735 uint32_t *palette; 1736 uint8_t hwc_palette[3 * 3]; 1737 uint8_t *hwc_src = NULL; 1738 1739 assert(dst_bpp == 4); /* Output is always 32-bit RGB */ 1740 1741 if (!((crt ? s->dc_crt_control : s->dc_panel_control) 1742 & SM501_DC_CRT_CONTROL_ENABLE)) { 1743 return; 1744 } 1745 1746 palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - 1747 SM501_DC_PANEL_PALETTE] 1748 : &s->dc_palette[0]); 1749 1750 /* choose draw_line function */ 1751 switch (src_bpp) { 1752 case 1: 1753 draw_line = draw_line8_32; 1754 break; 1755 case 2: 1756 draw_line = draw_line16_32; 1757 break; 1758 case 4: 1759 draw_line = draw_line32_32; 1760 break; 1761 default: 1762 qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display" 1763 "invalid control register value.\n"); 1764 return; 1765 } 1766 1767 /* set up to draw hardware cursor */ 1768 if (is_hwc_enabled(s, crt)) { 1769 /* choose cursor draw line function */ 1770 draw_hwc_line = draw_hwc_line_32; 1771 hwc_src = get_hwc_address(s, crt); 1772 c_x = get_hwc_x(s, crt); 1773 c_y = get_hwc_y(s, crt); 1774 get_hwc_palette(s, crt, hwc_palette); 1775 } 1776 1777 /* adjust console size */ 1778 if (s->last_width != width || s->last_height != height) { 1779 qemu_console_resize(s->con, width, height); 1780 surface = qemu_console_surface(s->con); 1781 s->last_width = width; 1782 s->last_height = height; 1783 full_update = 1; 1784 } 1785 1786 /* someone else requested a full update */ 1787 if (s->do_full_update) { 1788 s->do_full_update = false; 1789 full_update = 1; 1790 } 1791 1792 /* draw each line according to conditions */ 1793 offset = get_fb_addr(s, crt); 1794 snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region, 1795 offset, width * height * src_bpp, DIRTY_MEMORY_VGA); 1796 for (y = 0; y < height; y++, offset += width * src_bpp) { 1797 int update, update_hwc; 1798 1799 /* check if hardware cursor is enabled and we're within its range */ 1800 update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT; 1801 update = full_update || update_hwc; 1802 /* check dirty flags for each line */ 1803 update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap, 1804 offset, width * src_bpp); 1805 1806 /* draw line and change status */ 1807 if (update) { 1808 uint8_t *d = surface_data(surface); 1809 d += y * width * dst_bpp; 1810 1811 /* draw graphics layer */ 1812 draw_line(d, s->local_mem + offset, width, palette); 1813 1814 /* draw hardware cursor */ 1815 if (update_hwc) { 1816 draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y); 1817 } 1818 1819 if (y_start < 0) { 1820 y_start = y; 1821 } 1822 } else { 1823 if (y_start >= 0) { 1824 /* flush to display */ 1825 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 1826 y_start = -1; 1827 } 1828 } 1829 } 1830 g_free(snap); 1831 1832 /* complete flush to display */ 1833 if (y_start >= 0) { 1834 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 1835 } 1836 } 1837 1838 static const GraphicHwOps sm501_ops = { 1839 .gfx_update = sm501_update_display, 1840 }; 1841 1842 static void sm501_reset(SM501State *s) 1843 { 1844 s->system_control = 0x00100000; /* 2D engine FIFO empty */ 1845 /* 1846 * Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed 1847 * to be determined at reset by GPIO lines which set config bits. 1848 * We hardwire them: 1849 * SH = 0 : Hitachi Ready Polarity == Active Low 1850 * CDR = 0 : do not reset clock divider 1851 * TEST = 0 : Normal mode (not testing the silicon) 1852 * BUS = 0 : Hitachi SH3/SH4 1853 */ 1854 s->misc_control = SM501_MISC_DAC_POWER; 1855 s->gpio_31_0_control = 0; 1856 s->gpio_63_32_control = 0; 1857 s->dram_control = 0; 1858 s->arbitration_control = 0x05146732; 1859 s->irq_mask = 0; 1860 s->misc_timing = 0; 1861 s->power_mode_control = 0; 1862 s->i2c_byte_count = 0; 1863 s->i2c_status = 0; 1864 s->i2c_addr = 0; 1865 memset(s->i2c_data, 0, 16); 1866 s->dc_panel_control = 0x00010000; /* FIFO level 3 */ 1867 s->dc_video_control = 0; 1868 s->dc_crt_control = 0x00010000; 1869 s->twoD_source = 0; 1870 s->twoD_destination = 0; 1871 s->twoD_dimension = 0; 1872 s->twoD_control = 0; 1873 s->twoD_pitch = 0; 1874 s->twoD_foreground = 0; 1875 s->twoD_background = 0; 1876 s->twoD_stretch = 0; 1877 s->twoD_color_compare = 0; 1878 s->twoD_color_compare_mask = 0; 1879 s->twoD_mask = 0; 1880 s->twoD_clip_tl = 0; 1881 s->twoD_clip_br = 0; 1882 s->twoD_mono_pattern_low = 0; 1883 s->twoD_mono_pattern_high = 0; 1884 s->twoD_window_width = 0; 1885 s->twoD_source_base = 0; 1886 s->twoD_destination_base = 0; 1887 s->twoD_alpha = 0; 1888 s->twoD_wrap = 0; 1889 } 1890 1891 static void sm501_init(SM501State *s, DeviceState *dev, 1892 uint32_t local_mem_bytes) 1893 { 1894 #ifndef CONFIG_PIXMAN 1895 if (s->use_pixman != 0) { 1896 warn_report("x-pixman != 0, not effective without PIXMAN"); 1897 } 1898 #endif 1899 1900 s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); 1901 1902 /* local memory */ 1903 memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local", 1904 get_local_mem_size(s), &error_fatal); 1905 memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); 1906 s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); 1907 1908 /* i2c */ 1909 s->i2c_bus = i2c_init_bus(dev, "sm501.i2c"); 1910 /* ddc */ 1911 I2CDDCState *ddc = I2CDDC(qdev_new(TYPE_I2CDDC)); 1912 i2c_slave_set_address(I2C_SLAVE(ddc), 0x50); 1913 qdev_realize_and_unref(DEVICE(ddc), BUS(s->i2c_bus), &error_abort); 1914 1915 /* mmio */ 1916 memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE); 1917 memory_region_init_io(&s->system_config_region, OBJECT(dev), 1918 &sm501_system_config_ops, s, 1919 "sm501-system-config", 0x6c); 1920 memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, 1921 &s->system_config_region); 1922 memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s, 1923 "sm501-i2c", 0x14); 1924 memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region); 1925 memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), 1926 &sm501_disp_ctrl_ops, s, 1927 "sm501-disp-ctrl", 0x1000); 1928 memory_region_add_subregion(&s->mmio_region, SM501_DC, 1929 &s->disp_ctrl_region); 1930 memory_region_init_io(&s->twoD_engine_region, OBJECT(dev), 1931 &sm501_2d_engine_ops, s, 1932 "sm501-2d-engine", 0x54); 1933 memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE, 1934 &s->twoD_engine_region); 1935 1936 /* create qemu graphic console */ 1937 s->con = graphic_console_init(dev, 0, &sm501_ops, s); 1938 } 1939 1940 static const VMStateDescription vmstate_sm501_state = { 1941 .name = "sm501-state", 1942 .version_id = 1, 1943 .minimum_version_id = 1, 1944 .fields = (const VMStateField[]) { 1945 VMSTATE_UINT32(local_mem_size_index, SM501State), 1946 VMSTATE_UINT32(system_control, SM501State), 1947 VMSTATE_UINT32(misc_control, SM501State), 1948 VMSTATE_UINT32(gpio_31_0_control, SM501State), 1949 VMSTATE_UINT32(gpio_63_32_control, SM501State), 1950 VMSTATE_UINT32(dram_control, SM501State), 1951 VMSTATE_UINT32(arbitration_control, SM501State), 1952 VMSTATE_UINT32(irq_mask, SM501State), 1953 VMSTATE_UINT32(misc_timing, SM501State), 1954 VMSTATE_UINT32(power_mode_control, SM501State), 1955 VMSTATE_UINT32(uart0_ier, SM501State), 1956 VMSTATE_UINT32(uart0_lcr, SM501State), 1957 VMSTATE_UINT32(uart0_mcr, SM501State), 1958 VMSTATE_UINT32(uart0_scr, SM501State), 1959 VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES), 1960 VMSTATE_UINT32(dc_panel_control, SM501State), 1961 VMSTATE_UINT32(dc_panel_panning_control, SM501State), 1962 VMSTATE_UINT32(dc_panel_fb_addr, SM501State), 1963 VMSTATE_UINT32(dc_panel_fb_offset, SM501State), 1964 VMSTATE_UINT32(dc_panel_fb_width, SM501State), 1965 VMSTATE_UINT32(dc_panel_fb_height, SM501State), 1966 VMSTATE_UINT32(dc_panel_tl_location, SM501State), 1967 VMSTATE_UINT32(dc_panel_br_location, SM501State), 1968 VMSTATE_UINT32(dc_panel_h_total, SM501State), 1969 VMSTATE_UINT32(dc_panel_h_sync, SM501State), 1970 VMSTATE_UINT32(dc_panel_v_total, SM501State), 1971 VMSTATE_UINT32(dc_panel_v_sync, SM501State), 1972 VMSTATE_UINT32(dc_panel_hwc_addr, SM501State), 1973 VMSTATE_UINT32(dc_panel_hwc_location, SM501State), 1974 VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State), 1975 VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State), 1976 VMSTATE_UINT32(dc_video_control, SM501State), 1977 VMSTATE_UINT32(dc_crt_control, SM501State), 1978 VMSTATE_UINT32(dc_crt_fb_addr, SM501State), 1979 VMSTATE_UINT32(dc_crt_fb_offset, SM501State), 1980 VMSTATE_UINT32(dc_crt_h_total, SM501State), 1981 VMSTATE_UINT32(dc_crt_h_sync, SM501State), 1982 VMSTATE_UINT32(dc_crt_v_total, SM501State), 1983 VMSTATE_UINT32(dc_crt_v_sync, SM501State), 1984 VMSTATE_UINT32(dc_crt_hwc_addr, SM501State), 1985 VMSTATE_UINT32(dc_crt_hwc_location, SM501State), 1986 VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State), 1987 VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State), 1988 VMSTATE_UINT32(twoD_source, SM501State), 1989 VMSTATE_UINT32(twoD_destination, SM501State), 1990 VMSTATE_UINT32(twoD_dimension, SM501State), 1991 VMSTATE_UINT32(twoD_control, SM501State), 1992 VMSTATE_UINT32(twoD_pitch, SM501State), 1993 VMSTATE_UINT32(twoD_foreground, SM501State), 1994 VMSTATE_UINT32(twoD_background, SM501State), 1995 VMSTATE_UINT32(twoD_stretch, SM501State), 1996 VMSTATE_UINT32(twoD_color_compare, SM501State), 1997 VMSTATE_UINT32(twoD_color_compare_mask, SM501State), 1998 VMSTATE_UINT32(twoD_mask, SM501State), 1999 VMSTATE_UINT32(twoD_clip_tl, SM501State), 2000 VMSTATE_UINT32(twoD_clip_br, SM501State), 2001 VMSTATE_UINT32(twoD_mono_pattern_low, SM501State), 2002 VMSTATE_UINT32(twoD_mono_pattern_high, SM501State), 2003 VMSTATE_UINT32(twoD_window_width, SM501State), 2004 VMSTATE_UINT32(twoD_source_base, SM501State), 2005 VMSTATE_UINT32(twoD_destination_base, SM501State), 2006 VMSTATE_UINT32(twoD_alpha, SM501State), 2007 VMSTATE_UINT32(twoD_wrap, SM501State), 2008 /* Added in version 2 */ 2009 VMSTATE_UINT8(i2c_byte_count, SM501State), 2010 VMSTATE_UINT8(i2c_status, SM501State), 2011 VMSTATE_UINT8(i2c_addr, SM501State), 2012 VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16), 2013 VMSTATE_END_OF_LIST() 2014 } 2015 }; 2016 2017 #define TYPE_SYSBUS_SM501 "sysbus-sm501" 2018 OBJECT_DECLARE_SIMPLE_TYPE(SM501SysBusState, SYSBUS_SM501) 2019 2020 struct SM501SysBusState { 2021 /*< private >*/ 2022 SysBusDevice parent_obj; 2023 /*< public >*/ 2024 SM501State state; 2025 uint32_t vram_size; 2026 SerialMM serial; 2027 OHCISysBusState ohci; 2028 }; 2029 2030 static void sm501_realize_sysbus(DeviceState *dev, Error **errp) 2031 { 2032 SM501SysBusState *s = SYSBUS_SM501(dev); 2033 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2034 MemoryRegion *mr; 2035 2036 sm501_init(&s->state, dev, s->vram_size); 2037 if (get_local_mem_size(&s->state) != s->vram_size) { 2038 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, 2039 get_local_mem_size(&s->state)); 2040 return; 2041 } 2042 sysbus_init_mmio(sbd, &s->state.local_mem_region); 2043 sysbus_init_mmio(sbd, &s->state.mmio_region); 2044 2045 /* bridge to usb host emulation module */ 2046 sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->ohci), &error_fatal); 2047 memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, 2048 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ohci), 0)); 2049 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->ohci)); 2050 2051 /* bridge to serial emulation module */ 2052 sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal); 2053 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0); 2054 memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr); 2055 /* TODO : chain irq to IRL */ 2056 } 2057 2058 static const Property sm501_sysbus_properties[] = { 2059 DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), 2060 /* this a debug option, prefer PROP_UINT over PROP_BIT for simplicity */ 2061 DEFINE_PROP_UINT8("x-pixman", SM501SysBusState, state.use_pixman, DEFAULT_X_PIXMAN), 2062 }; 2063 2064 static void sm501_reset_sysbus(DeviceState *dev) 2065 { 2066 SM501SysBusState *s = SYSBUS_SM501(dev); 2067 sm501_reset(&s->state); 2068 } 2069 2070 static const VMStateDescription vmstate_sm501_sysbus = { 2071 .name = TYPE_SYSBUS_SM501, 2072 .version_id = 2, 2073 .minimum_version_id = 2, 2074 .fields = (const VMStateField[]) { 2075 VMSTATE_STRUCT(state, SM501SysBusState, 1, 2076 vmstate_sm501_state, SM501State), 2077 VMSTATE_END_OF_LIST() 2078 } 2079 }; 2080 2081 static void sm501_sysbus_class_init(ObjectClass *klass, const void *data) 2082 { 2083 DeviceClass *dc = DEVICE_CLASS(klass); 2084 2085 dc->realize = sm501_realize_sysbus; 2086 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2087 dc->desc = "SM501 Multimedia Companion"; 2088 device_class_set_props(dc, sm501_sysbus_properties); 2089 device_class_set_legacy_reset(dc, sm501_reset_sysbus); 2090 dc->vmsd = &vmstate_sm501_sysbus; 2091 } 2092 2093 static void sm501_sysbus_init(Object *o) 2094 { 2095 SM501SysBusState *sm501 = SYSBUS_SM501(o); 2096 OHCISysBusState *ohci = &sm501->ohci; 2097 SerialMM *smm = &sm501->serial; 2098 2099 object_initialize_child(o, "ohci", ohci, TYPE_SYSBUS_OHCI); 2100 object_property_add_alias(o, "dma-offset", OBJECT(ohci), "dma-offset"); 2101 qdev_prop_set_uint32(DEVICE(ohci), "num-ports", 2); 2102 2103 object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM); 2104 qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); 2105 qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); 2106 qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); 2107 2108 object_property_add_alias(o, "chardev", OBJECT(smm), "chardev"); 2109 } 2110 2111 static const TypeInfo sm501_sysbus_info = { 2112 .name = TYPE_SYSBUS_SM501, 2113 .parent = TYPE_SYS_BUS_DEVICE, 2114 .instance_size = sizeof(SM501SysBusState), 2115 .class_init = sm501_sysbus_class_init, 2116 .instance_init = sm501_sysbus_init, 2117 }; 2118 2119 #define TYPE_PCI_SM501 "sm501" 2120 OBJECT_DECLARE_SIMPLE_TYPE(SM501PCIState, PCI_SM501) 2121 2122 struct SM501PCIState { 2123 /*< private >*/ 2124 PCIDevice parent_obj; 2125 /*< public >*/ 2126 SM501State state; 2127 uint32_t vram_size; 2128 }; 2129 2130 static void sm501_realize_pci(PCIDevice *dev, Error **errp) 2131 { 2132 SM501PCIState *s = PCI_SM501(dev); 2133 2134 sm501_init(&s->state, DEVICE(dev), s->vram_size); 2135 if (get_local_mem_size(&s->state) != s->vram_size) { 2136 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, 2137 get_local_mem_size(&s->state)); 2138 return; 2139 } 2140 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, 2141 &s->state.local_mem_region); 2142 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, 2143 &s->state.mmio_region); 2144 } 2145 2146 static const Property sm501_pci_properties[] = { 2147 DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), 2148 DEFINE_PROP_UINT8("x-pixman", SM501PCIState, state.use_pixman, DEFAULT_X_PIXMAN), 2149 }; 2150 2151 static void sm501_reset_pci(DeviceState *dev) 2152 { 2153 SM501PCIState *s = PCI_SM501(dev); 2154 sm501_reset(&s->state); 2155 /* Bits 2:0 of misc_control register is 001 for PCI */ 2156 s->state.misc_control |= 1; 2157 } 2158 2159 static const VMStateDescription vmstate_sm501_pci = { 2160 .name = TYPE_PCI_SM501, 2161 .version_id = 2, 2162 .minimum_version_id = 2, 2163 .fields = (const VMStateField[]) { 2164 VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState), 2165 VMSTATE_STRUCT(state, SM501PCIState, 1, 2166 vmstate_sm501_state, SM501State), 2167 VMSTATE_END_OF_LIST() 2168 } 2169 }; 2170 2171 static void sm501_pci_class_init(ObjectClass *klass, const void *data) 2172 { 2173 DeviceClass *dc = DEVICE_CLASS(klass); 2174 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2175 2176 k->realize = sm501_realize_pci; 2177 k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; 2178 k->device_id = PCI_DEVICE_ID_SM501; 2179 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2180 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2181 dc->desc = "SM501 Display Controller"; 2182 device_class_set_props(dc, sm501_pci_properties); 2183 device_class_set_legacy_reset(dc, sm501_reset_pci); 2184 dc->hotpluggable = false; 2185 dc->vmsd = &vmstate_sm501_pci; 2186 } 2187 2188 static void sm501_pci_init(Object *o) 2189 { 2190 object_property_set_description(o, "x-pixman", "Use pixman for: " 2191 "1: fill, 2: blit, 4: overlap blit"); 2192 } 2193 2194 static const TypeInfo sm501_pci_info = { 2195 .name = TYPE_PCI_SM501, 2196 .parent = TYPE_PCI_DEVICE, 2197 .instance_size = sizeof(SM501PCIState), 2198 .class_init = sm501_pci_class_init, 2199 .instance_init = sm501_pci_init, 2200 .interfaces = (const InterfaceInfo[]) { 2201 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2202 { }, 2203 }, 2204 }; 2205 2206 static void sm501_register_types(void) 2207 { 2208 type_register_static(&sm501_sysbus_info); 2209 type_register_static(&sm501_pci_info); 2210 } 2211 2212 type_init(sm501_register_types) 2213