1 /* 2 * QEMU SM501 Device 3 * 4 * Copyright (c) 2008 Shin-ichiro KAWASAKI 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include <stdio.h> 26 #include "hw/hw.h" 27 #include "hw/char/serial.h" 28 #include "ui/console.h" 29 #include "hw/devices.h" 30 #include "hw/sysbus.h" 31 #include "qemu/range.h" 32 #include "ui/pixel_ops.h" 33 #include "exec/address-spaces.h" 34 35 /* 36 * Status: 2010/05/07 37 * - Minimum implementation for Linux console : mmio regs and CRT layer. 38 * - 2D grapihcs acceleration partially supported : only fill rectangle. 39 * 40 * TODO: 41 * - Panel support 42 * - Touch panel support 43 * - USB support 44 * - UART support 45 * - More 2D graphics engine support 46 * - Performance tuning 47 */ 48 49 //#define DEBUG_SM501 50 //#define DEBUG_BITBLT 51 52 #ifdef DEBUG_SM501 53 #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) 54 #else 55 #define SM501_DPRINTF(fmt, ...) do {} while(0) 56 #endif 57 58 59 #define MMIO_BASE_OFFSET 0x3e00000 60 61 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ 62 63 /* System Configuration area */ 64 /* System config base */ 65 #define SM501_SYS_CONFIG (0x000000) 66 67 /* config 1 */ 68 #define SM501_SYSTEM_CONTROL (0x000000) 69 70 #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0) 71 #define SM501_SYSCTRL_MEM_TRISTATE (1<<1) 72 #define SM501_SYSCTRL_CRT_TRISTATE (1<<2) 73 74 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4) 75 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4) 76 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4) 77 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4) 78 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4) 79 80 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6) 81 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7) 82 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11) 83 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15) 84 85 /* miscellaneous control */ 86 87 #define SM501_MISC_CONTROL (0x000004) 88 89 #define SM501_MISC_BUS_SH (0x0) 90 #define SM501_MISC_BUS_PCI (0x1) 91 #define SM501_MISC_BUS_XSCALE (0x2) 92 #define SM501_MISC_BUS_NEC (0x6) 93 #define SM501_MISC_BUS_MASK (0x7) 94 95 #define SM501_MISC_VR_62MB (1<<3) 96 #define SM501_MISC_CDR_RESET (1<<7) 97 #define SM501_MISC_USB_LB (1<<8) 98 #define SM501_MISC_USB_SLAVE (1<<9) 99 #define SM501_MISC_BL_1 (1<<10) 100 #define SM501_MISC_MC (1<<11) 101 #define SM501_MISC_DAC_POWER (1<<12) 102 #define SM501_MISC_IRQ_INVERT (1<<16) 103 #define SM501_MISC_SH (1<<17) 104 105 #define SM501_MISC_HOLD_EMPTY (0<<18) 106 #define SM501_MISC_HOLD_8 (1<<18) 107 #define SM501_MISC_HOLD_16 (2<<18) 108 #define SM501_MISC_HOLD_24 (3<<18) 109 #define SM501_MISC_HOLD_32 (4<<18) 110 #define SM501_MISC_HOLD_MASK (7<<18) 111 112 #define SM501_MISC_FREQ_12 (1<<24) 113 #define SM501_MISC_PNL_24BIT (1<<25) 114 #define SM501_MISC_8051_LE (1<<26) 115 116 117 118 #define SM501_GPIO31_0_CONTROL (0x000008) 119 #define SM501_GPIO63_32_CONTROL (0x00000C) 120 #define SM501_DRAM_CONTROL (0x000010) 121 122 /* command list */ 123 #define SM501_ARBTRTN_CONTROL (0x000014) 124 125 /* command list */ 126 #define SM501_COMMAND_LIST_STATUS (0x000024) 127 128 /* interrupt debug */ 129 #define SM501_RAW_IRQ_STATUS (0x000028) 130 #define SM501_RAW_IRQ_CLEAR (0x000028) 131 #define SM501_IRQ_STATUS (0x00002C) 132 #define SM501_IRQ_MASK (0x000030) 133 #define SM501_DEBUG_CONTROL (0x000034) 134 135 /* power management */ 136 #define SM501_POWERMODE_P2X_SRC (1<<29) 137 #define SM501_POWERMODE_V2X_SRC (1<<20) 138 #define SM501_POWERMODE_M_SRC (1<<12) 139 #define SM501_POWERMODE_M1_SRC (1<<4) 140 141 #define SM501_CURRENT_GATE (0x000038) 142 #define SM501_CURRENT_CLOCK (0x00003C) 143 #define SM501_POWER_MODE_0_GATE (0x000040) 144 #define SM501_POWER_MODE_0_CLOCK (0x000044) 145 #define SM501_POWER_MODE_1_GATE (0x000048) 146 #define SM501_POWER_MODE_1_CLOCK (0x00004C) 147 #define SM501_SLEEP_MODE_GATE (0x000050) 148 #define SM501_POWER_MODE_CONTROL (0x000054) 149 150 /* power gates for units within the 501 */ 151 #define SM501_GATE_HOST (0) 152 #define SM501_GATE_MEMORY (1) 153 #define SM501_GATE_DISPLAY (2) 154 #define SM501_GATE_2D_ENGINE (3) 155 #define SM501_GATE_CSC (4) 156 #define SM501_GATE_ZVPORT (5) 157 #define SM501_GATE_GPIO (6) 158 #define SM501_GATE_UART0 (7) 159 #define SM501_GATE_UART1 (8) 160 #define SM501_GATE_SSP (10) 161 #define SM501_GATE_USB_HOST (11) 162 #define SM501_GATE_USB_GADGET (12) 163 #define SM501_GATE_UCONTROLLER (17) 164 #define SM501_GATE_AC97 (18) 165 166 /* panel clock */ 167 #define SM501_CLOCK_P2XCLK (24) 168 /* crt clock */ 169 #define SM501_CLOCK_V2XCLK (16) 170 /* main clock */ 171 #define SM501_CLOCK_MCLK (8) 172 /* SDRAM controller clock */ 173 #define SM501_CLOCK_M1XCLK (0) 174 175 /* config 2 */ 176 #define SM501_PCI_MASTER_BASE (0x000058) 177 #define SM501_ENDIAN_CONTROL (0x00005C) 178 #define SM501_DEVICEID (0x000060) 179 /* 0x050100A0 */ 180 181 #define SM501_DEVICEID_SM501 (0x05010000) 182 #define SM501_DEVICEID_IDMASK (0xffff0000) 183 #define SM501_DEVICEID_REVMASK (0x000000ff) 184 185 #define SM501_PLLCLOCK_COUNT (0x000064) 186 #define SM501_MISC_TIMING (0x000068) 187 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) 188 189 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) 190 191 /* GPIO base */ 192 #define SM501_GPIO (0x010000) 193 #define SM501_GPIO_DATA_LOW (0x00) 194 #define SM501_GPIO_DATA_HIGH (0x04) 195 #define SM501_GPIO_DDR_LOW (0x08) 196 #define SM501_GPIO_DDR_HIGH (0x0C) 197 #define SM501_GPIO_IRQ_SETUP (0x10) 198 #define SM501_GPIO_IRQ_STATUS (0x14) 199 #define SM501_GPIO_IRQ_RESET (0x14) 200 201 /* I2C controller base */ 202 #define SM501_I2C (0x010040) 203 #define SM501_I2C_BYTE_COUNT (0x00) 204 #define SM501_I2C_CONTROL (0x01) 205 #define SM501_I2C_STATUS (0x02) 206 #define SM501_I2C_RESET (0x02) 207 #define SM501_I2C_SLAVE_ADDRESS (0x03) 208 #define SM501_I2C_DATA (0x04) 209 210 /* SSP base */ 211 #define SM501_SSP (0x020000) 212 213 /* Uart 0 base */ 214 #define SM501_UART0 (0x030000) 215 216 /* Uart 1 base */ 217 #define SM501_UART1 (0x030020) 218 219 /* USB host port base */ 220 #define SM501_USB_HOST (0x040000) 221 222 /* USB slave/gadget base */ 223 #define SM501_USB_GADGET (0x060000) 224 225 /* USB slave/gadget data port base */ 226 #define SM501_USB_GADGET_DATA (0x070000) 227 228 /* Display controller/video engine base */ 229 #define SM501_DC (0x080000) 230 231 /* common defines for the SM501 address registers */ 232 #define SM501_ADDR_FLIP (1<<31) 233 #define SM501_ADDR_EXT (1<<27) 234 #define SM501_ADDR_CS1 (1<<26) 235 #define SM501_ADDR_MASK (0x3f << 26) 236 237 #define SM501_FIFO_MASK (0x3 << 16) 238 #define SM501_FIFO_1 (0x0 << 16) 239 #define SM501_FIFO_3 (0x1 << 16) 240 #define SM501_FIFO_7 (0x2 << 16) 241 #define SM501_FIFO_11 (0x3 << 16) 242 243 /* common registers for panel and the crt */ 244 #define SM501_OFF_DC_H_TOT (0x000) 245 #define SM501_OFF_DC_V_TOT (0x008) 246 #define SM501_OFF_DC_H_SYNC (0x004) 247 #define SM501_OFF_DC_V_SYNC (0x00C) 248 249 #define SM501_DC_PANEL_CONTROL (0x000) 250 251 #define SM501_DC_PANEL_CONTROL_FPEN (1<<27) 252 #define SM501_DC_PANEL_CONTROL_BIAS (1<<26) 253 #define SM501_DC_PANEL_CONTROL_DATA (1<<25) 254 #define SM501_DC_PANEL_CONTROL_VDD (1<<24) 255 #define SM501_DC_PANEL_CONTROL_DP (1<<23) 256 257 #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21) 258 #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21) 259 #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21) 260 261 #define SM501_DC_PANEL_CONTROL_DE (1<<20) 262 263 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18) 264 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18) 265 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18) 266 267 #define SM501_DC_PANEL_CONTROL_CP (1<<14) 268 #define SM501_DC_PANEL_CONTROL_VSP (1<<13) 269 #define SM501_DC_PANEL_CONTROL_HSP (1<<12) 270 #define SM501_DC_PANEL_CONTROL_CK (1<<9) 271 #define SM501_DC_PANEL_CONTROL_TE (1<<8) 272 #define SM501_DC_PANEL_CONTROL_VPD (1<<7) 273 #define SM501_DC_PANEL_CONTROL_VP (1<<6) 274 #define SM501_DC_PANEL_CONTROL_HPD (1<<5) 275 #define SM501_DC_PANEL_CONTROL_HP (1<<4) 276 #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3) 277 #define SM501_DC_PANEL_CONTROL_EN (1<<2) 278 279 #define SM501_DC_PANEL_CONTROL_8BPP (0<<0) 280 #define SM501_DC_PANEL_CONTROL_16BPP (1<<0) 281 #define SM501_DC_PANEL_CONTROL_32BPP (2<<0) 282 283 284 #define SM501_DC_PANEL_PANNING_CONTROL (0x004) 285 #define SM501_DC_PANEL_COLOR_KEY (0x008) 286 #define SM501_DC_PANEL_FB_ADDR (0x00C) 287 #define SM501_DC_PANEL_FB_OFFSET (0x010) 288 #define SM501_DC_PANEL_FB_WIDTH (0x014) 289 #define SM501_DC_PANEL_FB_HEIGHT (0x018) 290 #define SM501_DC_PANEL_TL_LOC (0x01C) 291 #define SM501_DC_PANEL_BR_LOC (0x020) 292 #define SM501_DC_PANEL_H_TOT (0x024) 293 #define SM501_DC_PANEL_H_SYNC (0x028) 294 #define SM501_DC_PANEL_V_TOT (0x02C) 295 #define SM501_DC_PANEL_V_SYNC (0x030) 296 #define SM501_DC_PANEL_CUR_LINE (0x034) 297 298 #define SM501_DC_VIDEO_CONTROL (0x040) 299 #define SM501_DC_VIDEO_FB0_ADDR (0x044) 300 #define SM501_DC_VIDEO_FB_WIDTH (0x048) 301 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) 302 #define SM501_DC_VIDEO_TL_LOC (0x050) 303 #define SM501_DC_VIDEO_BR_LOC (0x054) 304 #define SM501_DC_VIDEO_SCALE (0x058) 305 #define SM501_DC_VIDEO_INIT_SCALE (0x05C) 306 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) 307 #define SM501_DC_VIDEO_FB1_ADDR (0x064) 308 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) 309 310 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) 311 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) 312 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) 313 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) 314 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) 315 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) 316 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) 317 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) 318 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) 319 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) 320 321 #define SM501_DC_PANEL_HWC_BASE (0x0F0) 322 #define SM501_DC_PANEL_HWC_ADDR (0x0F0) 323 #define SM501_DC_PANEL_HWC_LOC (0x0F4) 324 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) 325 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) 326 327 #define SM501_HWC_EN (1<<31) 328 329 #define SM501_OFF_HWC_ADDR (0x00) 330 #define SM501_OFF_HWC_LOC (0x04) 331 #define SM501_OFF_HWC_COLOR_1_2 (0x08) 332 #define SM501_OFF_HWC_COLOR_3 (0x0C) 333 334 #define SM501_DC_ALPHA_CONTROL (0x100) 335 #define SM501_DC_ALPHA_FB_ADDR (0x104) 336 #define SM501_DC_ALPHA_FB_OFFSET (0x108) 337 #define SM501_DC_ALPHA_TL_LOC (0x10C) 338 #define SM501_DC_ALPHA_BR_LOC (0x110) 339 #define SM501_DC_ALPHA_CHROMA_KEY (0x114) 340 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) 341 342 #define SM501_DC_CRT_CONTROL (0x200) 343 344 #define SM501_DC_CRT_CONTROL_TVP (1<<15) 345 #define SM501_DC_CRT_CONTROL_CP (1<<14) 346 #define SM501_DC_CRT_CONTROL_VSP (1<<13) 347 #define SM501_DC_CRT_CONTROL_HSP (1<<12) 348 #define SM501_DC_CRT_CONTROL_VS (1<<11) 349 #define SM501_DC_CRT_CONTROL_BLANK (1<<10) 350 #define SM501_DC_CRT_CONTROL_SEL (1<<9) 351 #define SM501_DC_CRT_CONTROL_TE (1<<8) 352 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) 353 #define SM501_DC_CRT_CONTROL_GAMMA (1<<3) 354 #define SM501_DC_CRT_CONTROL_ENABLE (1<<2) 355 356 #define SM501_DC_CRT_CONTROL_8BPP (0<<0) 357 #define SM501_DC_CRT_CONTROL_16BPP (1<<0) 358 #define SM501_DC_CRT_CONTROL_32BPP (2<<0) 359 360 #define SM501_DC_CRT_FB_ADDR (0x204) 361 #define SM501_DC_CRT_FB_OFFSET (0x208) 362 #define SM501_DC_CRT_H_TOT (0x20C) 363 #define SM501_DC_CRT_H_SYNC (0x210) 364 #define SM501_DC_CRT_V_TOT (0x214) 365 #define SM501_DC_CRT_V_SYNC (0x218) 366 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) 367 #define SM501_DC_CRT_CUR_LINE (0x220) 368 #define SM501_DC_CRT_MONITOR_DETECT (0x224) 369 370 #define SM501_DC_CRT_HWC_BASE (0x230) 371 #define SM501_DC_CRT_HWC_ADDR (0x230) 372 #define SM501_DC_CRT_HWC_LOC (0x234) 373 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) 374 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) 375 376 #define SM501_DC_PANEL_PALETTE (0x400) 377 378 #define SM501_DC_VIDEO_PALETTE (0x800) 379 380 #define SM501_DC_CRT_PALETTE (0xC00) 381 382 /* Zoom Video port base */ 383 #define SM501_ZVPORT (0x090000) 384 385 /* AC97/I2S base */ 386 #define SM501_AC97 (0x0A0000) 387 388 /* 8051 micro controller base */ 389 #define SM501_UCONTROLLER (0x0B0000) 390 391 /* 8051 micro controller SRAM base */ 392 #define SM501_UCONTROLLER_SRAM (0x0C0000) 393 394 /* DMA base */ 395 #define SM501_DMA (0x0D0000) 396 397 /* 2d engine base */ 398 #define SM501_2D_ENGINE (0x100000) 399 #define SM501_2D_SOURCE (0x00) 400 #define SM501_2D_DESTINATION (0x04) 401 #define SM501_2D_DIMENSION (0x08) 402 #define SM501_2D_CONTROL (0x0C) 403 #define SM501_2D_PITCH (0x10) 404 #define SM501_2D_FOREGROUND (0x14) 405 #define SM501_2D_BACKGROUND (0x18) 406 #define SM501_2D_STRETCH (0x1C) 407 #define SM501_2D_COLOR_COMPARE (0x20) 408 #define SM501_2D_COLOR_COMPARE_MASK (0x24) 409 #define SM501_2D_MASK (0x28) 410 #define SM501_2D_CLIP_TL (0x2C) 411 #define SM501_2D_CLIP_BR (0x30) 412 #define SM501_2D_MONO_PATTERN_LOW (0x34) 413 #define SM501_2D_MONO_PATTERN_HIGH (0x38) 414 #define SM501_2D_WINDOW_WIDTH (0x3C) 415 #define SM501_2D_SOURCE_BASE (0x40) 416 #define SM501_2D_DESTINATION_BASE (0x44) 417 #define SM501_2D_ALPHA (0x48) 418 #define SM501_2D_WRAP (0x4C) 419 #define SM501_2D_STATUS (0x50) 420 421 #define SM501_CSC_Y_SOURCE_BASE (0xC8) 422 #define SM501_CSC_CONSTANTS (0xCC) 423 #define SM501_CSC_Y_SOURCE_X (0xD0) 424 #define SM501_CSC_Y_SOURCE_Y (0xD4) 425 #define SM501_CSC_U_SOURCE_BASE (0xD8) 426 #define SM501_CSC_V_SOURCE_BASE (0xDC) 427 #define SM501_CSC_SOURCE_DIMENSION (0xE0) 428 #define SM501_CSC_SOURCE_PITCH (0xE4) 429 #define SM501_CSC_DESTINATION (0xE8) 430 #define SM501_CSC_DESTINATION_DIMENSION (0xEC) 431 #define SM501_CSC_DESTINATION_PITCH (0xF0) 432 #define SM501_CSC_SCALE_FACTOR (0xF4) 433 #define SM501_CSC_DESTINATION_BASE (0xF8) 434 #define SM501_CSC_CONTROL (0xFC) 435 436 /* 2d engine data port base */ 437 #define SM501_2D_ENGINE_DATA (0x110000) 438 439 /* end of register definitions */ 440 441 #define SM501_HWC_WIDTH (64) 442 #define SM501_HWC_HEIGHT (64) 443 444 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ 445 static const uint32_t sm501_mem_local_size[] = { 446 [0] = 4*1024*1024, 447 [1] = 8*1024*1024, 448 [2] = 16*1024*1024, 449 [3] = 32*1024*1024, 450 [4] = 64*1024*1024, 451 [5] = 2*1024*1024, 452 }; 453 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] 454 455 typedef struct SM501State { 456 /* graphic console status */ 457 QemuConsole *con; 458 459 /* status & internal resources */ 460 hwaddr base; 461 uint32_t local_mem_size_index; 462 uint8_t * local_mem; 463 MemoryRegion local_mem_region; 464 uint32_t last_width; 465 uint32_t last_height; 466 467 /* mmio registers */ 468 uint32_t system_control; 469 uint32_t misc_control; 470 uint32_t gpio_31_0_control; 471 uint32_t gpio_63_32_control; 472 uint32_t dram_control; 473 uint32_t irq_mask; 474 uint32_t misc_timing; 475 uint32_t power_mode_control; 476 477 uint32_t uart0_ier; 478 uint32_t uart0_lcr; 479 uint32_t uart0_mcr; 480 uint32_t uart0_scr; 481 482 uint8_t dc_palette[0x400 * 3]; 483 484 uint32_t dc_panel_control; 485 uint32_t dc_panel_panning_control; 486 uint32_t dc_panel_fb_addr; 487 uint32_t dc_panel_fb_offset; 488 uint32_t dc_panel_fb_width; 489 uint32_t dc_panel_fb_height; 490 uint32_t dc_panel_tl_location; 491 uint32_t dc_panel_br_location; 492 uint32_t dc_panel_h_total; 493 uint32_t dc_panel_h_sync; 494 uint32_t dc_panel_v_total; 495 uint32_t dc_panel_v_sync; 496 497 uint32_t dc_panel_hwc_addr; 498 uint32_t dc_panel_hwc_location; 499 uint32_t dc_panel_hwc_color_1_2; 500 uint32_t dc_panel_hwc_color_3; 501 502 uint32_t dc_crt_control; 503 uint32_t dc_crt_fb_addr; 504 uint32_t dc_crt_fb_offset; 505 uint32_t dc_crt_h_total; 506 uint32_t dc_crt_h_sync; 507 uint32_t dc_crt_v_total; 508 uint32_t dc_crt_v_sync; 509 510 uint32_t dc_crt_hwc_addr; 511 uint32_t dc_crt_hwc_location; 512 uint32_t dc_crt_hwc_color_1_2; 513 uint32_t dc_crt_hwc_color_3; 514 515 uint32_t twoD_source; 516 uint32_t twoD_destination; 517 uint32_t twoD_dimension; 518 uint32_t twoD_control; 519 uint32_t twoD_pitch; 520 uint32_t twoD_foreground; 521 uint32_t twoD_stretch; 522 uint32_t twoD_color_compare_mask; 523 uint32_t twoD_mask; 524 uint32_t twoD_window_width; 525 uint32_t twoD_source_base; 526 uint32_t twoD_destination_base; 527 528 } SM501State; 529 530 static uint32_t get_local_mem_size_index(uint32_t size) 531 { 532 uint32_t norm_size = 0; 533 int i, index = 0; 534 535 for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { 536 uint32_t new_size = sm501_mem_local_size[i]; 537 if (new_size >= size) { 538 if (norm_size == 0 || norm_size > new_size) { 539 norm_size = new_size; 540 index = i; 541 } 542 } 543 } 544 545 return index; 546 } 547 548 /** 549 * Check the availability of hardware cursor. 550 * @param crt 0 for PANEL, 1 for CRT. 551 */ 552 static inline int is_hwc_enabled(SM501State *state, int crt) 553 { 554 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; 555 return addr & 0x80000000; 556 } 557 558 /** 559 * Get the address which holds cursor pattern data. 560 * @param crt 0 for PANEL, 1 for CRT. 561 */ 562 static inline uint32_t get_hwc_address(SM501State *state, int crt) 563 { 564 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; 565 return (addr & 0x03FFFFF0)/* >> 4*/; 566 } 567 568 /** 569 * Get the cursor position in y coordinate. 570 * @param crt 0 for PANEL, 1 for CRT. 571 */ 572 static inline uint32_t get_hwc_y(SM501State *state, int crt) 573 { 574 uint32_t location = crt ? state->dc_crt_hwc_location 575 : state->dc_panel_hwc_location; 576 return (location & 0x07FF0000) >> 16; 577 } 578 579 /** 580 * Get the cursor position in x coordinate. 581 * @param crt 0 for PANEL, 1 for CRT. 582 */ 583 static inline uint32_t get_hwc_x(SM501State *state, int crt) 584 { 585 uint32_t location = crt ? state->dc_crt_hwc_location 586 : state->dc_panel_hwc_location; 587 return location & 0x000007FF; 588 } 589 590 /** 591 * Get the cursor position in x coordinate. 592 * @param crt 0 for PANEL, 1 for CRT. 593 * @param index 0, 1, 2 or 3 which specifies color of corsor dot. 594 */ 595 static inline uint16_t get_hwc_color(SM501State *state, int crt, int index) 596 { 597 uint32_t color_reg = 0; 598 uint16_t color_565 = 0; 599 600 if (index == 0) { 601 return 0; 602 } 603 604 switch (index) { 605 case 1: 606 case 2: 607 color_reg = crt ? state->dc_crt_hwc_color_1_2 608 : state->dc_panel_hwc_color_1_2; 609 break; 610 case 3: 611 color_reg = crt ? state->dc_crt_hwc_color_3 612 : state->dc_panel_hwc_color_3; 613 break; 614 default: 615 printf("invalid hw cursor color.\n"); 616 abort(); 617 } 618 619 switch (index) { 620 case 1: 621 case 3: 622 color_565 = (uint16_t)(color_reg & 0xFFFF); 623 break; 624 case 2: 625 color_565 = (uint16_t)((color_reg >> 16) & 0xFFFF); 626 break; 627 } 628 return color_565; 629 } 630 631 static int within_hwc_y_range(SM501State *state, int y, int crt) 632 { 633 int hwc_y = get_hwc_y(state, crt); 634 return (hwc_y <= y && y < hwc_y + SM501_HWC_HEIGHT); 635 } 636 637 static void sm501_2d_operation(SM501State * s) 638 { 639 /* obtain operation parameters */ 640 int operation = (s->twoD_control >> 16) & 0x1f; 641 int rtl = s->twoD_control & 0x8000000; 642 int src_x = (s->twoD_source >> 16) & 0x01FFF; 643 int src_y = s->twoD_source & 0xFFFF; 644 int dst_x = (s->twoD_destination >> 16) & 0x01FFF; 645 int dst_y = s->twoD_destination & 0xFFFF; 646 int operation_width = (s->twoD_dimension >> 16) & 0x1FFF; 647 int operation_height = s->twoD_dimension & 0xFFFF; 648 uint32_t color = s->twoD_foreground; 649 int format_flags = (s->twoD_stretch >> 20) & 0x3; 650 int addressing = (s->twoD_stretch >> 16) & 0xF; 651 652 /* get frame buffer info */ 653 uint8_t * src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF); 654 uint8_t * dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF); 655 int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1; 656 int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1; 657 658 if (addressing != 0x0) { 659 printf("%s: only XY addressing is supported.\n", __func__); 660 abort(); 661 } 662 663 if ((s->twoD_source_base & 0x08000000) || 664 (s->twoD_destination_base & 0x08000000)) { 665 printf("%s: only local memory is supported.\n", __func__); 666 abort(); 667 } 668 669 switch (operation) { 670 case 0x00: /* copy area */ 671 #define COPY_AREA(_bpp, _pixel_type, rtl) { \ 672 int y, x, index_d, index_s; \ 673 for (y = 0; y < operation_height; y++) { \ 674 for (x = 0; x < operation_width; x++) { \ 675 if (rtl) { \ 676 index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \ 677 index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \ 678 } else { \ 679 index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \ 680 index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \ 681 } \ 682 *(_pixel_type*)&dst[index_d] = *(_pixel_type*)&src[index_s];\ 683 } \ 684 } \ 685 } 686 switch (format_flags) { 687 case 0: 688 COPY_AREA(1, uint8_t, rtl); 689 break; 690 case 1: 691 COPY_AREA(2, uint16_t, rtl); 692 break; 693 case 2: 694 COPY_AREA(4, uint32_t, rtl); 695 break; 696 } 697 break; 698 699 case 0x01: /* fill rectangle */ 700 #define FILL_RECT(_bpp, _pixel_type) { \ 701 int y, x; \ 702 for (y = 0; y < operation_height; y++) { \ 703 for (x = 0; x < operation_width; x++) { \ 704 int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \ 705 *(_pixel_type*)&dst[index] = (_pixel_type)color; \ 706 } \ 707 } \ 708 } 709 710 switch (format_flags) { 711 case 0: 712 FILL_RECT(1, uint8_t); 713 break; 714 case 1: 715 FILL_RECT(2, uint16_t); 716 break; 717 case 2: 718 FILL_RECT(4, uint32_t); 719 break; 720 } 721 break; 722 723 default: 724 printf("non-implemented SM501 2D operation. %d\n", operation); 725 abort(); 726 break; 727 } 728 } 729 730 static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, 731 unsigned size) 732 { 733 SM501State * s = (SM501State *)opaque; 734 uint32_t ret = 0; 735 SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr); 736 737 switch(addr) { 738 case SM501_SYSTEM_CONTROL: 739 ret = s->system_control; 740 break; 741 case SM501_MISC_CONTROL: 742 ret = s->misc_control; 743 break; 744 case SM501_GPIO31_0_CONTROL: 745 ret = s->gpio_31_0_control; 746 break; 747 case SM501_GPIO63_32_CONTROL: 748 ret = s->gpio_63_32_control; 749 break; 750 case SM501_DEVICEID: 751 ret = 0x050100A0; 752 break; 753 case SM501_DRAM_CONTROL: 754 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; 755 break; 756 case SM501_IRQ_MASK: 757 ret = s->irq_mask; 758 break; 759 case SM501_MISC_TIMING: 760 /* TODO : simulate gate control */ 761 ret = s->misc_timing; 762 break; 763 case SM501_CURRENT_GATE: 764 /* TODO : simulate gate control */ 765 ret = 0x00021807; 766 break; 767 case SM501_CURRENT_CLOCK: 768 ret = 0x2A1A0A09; 769 break; 770 case SM501_POWER_MODE_CONTROL: 771 ret = s->power_mode_control; 772 break; 773 774 default: 775 printf("sm501 system config : not implemented register read." 776 " addr=%x\n", (int)addr); 777 abort(); 778 } 779 780 return ret; 781 } 782 783 static void sm501_system_config_write(void *opaque, hwaddr addr, 784 uint64_t value, unsigned size) 785 { 786 SM501State * s = (SM501State *)opaque; 787 SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", 788 (uint32_t)addr, (uint32_t)value); 789 790 switch(addr) { 791 case SM501_SYSTEM_CONTROL: 792 s->system_control = value & 0xE300B8F7; 793 break; 794 case SM501_MISC_CONTROL: 795 s->misc_control = value & 0xFF7FFF20; 796 break; 797 case SM501_GPIO31_0_CONTROL: 798 s->gpio_31_0_control = value; 799 break; 800 case SM501_GPIO63_32_CONTROL: 801 s->gpio_63_32_control = value; 802 break; 803 case SM501_DRAM_CONTROL: 804 s->local_mem_size_index = (value >> 13) & 0x7; 805 /* rODO : check validity of size change */ 806 s->dram_control |= value & 0x7FFFFFC3; 807 break; 808 case SM501_IRQ_MASK: 809 s->irq_mask = value; 810 break; 811 case SM501_MISC_TIMING: 812 s->misc_timing = value & 0xF31F1FFF; 813 break; 814 case SM501_POWER_MODE_0_GATE: 815 case SM501_POWER_MODE_1_GATE: 816 case SM501_POWER_MODE_0_CLOCK: 817 case SM501_POWER_MODE_1_CLOCK: 818 /* TODO : simulate gate & clock control */ 819 break; 820 case SM501_POWER_MODE_CONTROL: 821 s->power_mode_control = value & 0x00000003; 822 break; 823 824 default: 825 printf("sm501 system config : not implemented register write." 826 " addr=%x, val=%x\n", (int)addr, (uint32_t)value); 827 abort(); 828 } 829 } 830 831 static const MemoryRegionOps sm501_system_config_ops = { 832 .read = sm501_system_config_read, 833 .write = sm501_system_config_write, 834 .valid = { 835 .min_access_size = 4, 836 .max_access_size = 4, 837 }, 838 .endianness = DEVICE_NATIVE_ENDIAN, 839 }; 840 841 static uint32_t sm501_palette_read(void *opaque, hwaddr addr) 842 { 843 SM501State * s = (SM501State *)opaque; 844 SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); 845 846 /* TODO : consider BYTE/WORD access */ 847 /* TODO : consider endian */ 848 849 assert(range_covers_byte(0, 0x400 * 3, addr)); 850 return *(uint32_t*)&s->dc_palette[addr]; 851 } 852 853 static void sm501_palette_write(void *opaque, 854 hwaddr addr, uint32_t value) 855 { 856 SM501State * s = (SM501State *)opaque; 857 SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", 858 (int)addr, value); 859 860 /* TODO : consider BYTE/WORD access */ 861 /* TODO : consider endian */ 862 863 assert(range_covers_byte(0, 0x400 * 3, addr)); 864 *(uint32_t*)&s->dc_palette[addr] = value; 865 } 866 867 static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, 868 unsigned size) 869 { 870 SM501State * s = (SM501State *)opaque; 871 uint32_t ret = 0; 872 SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr); 873 874 switch(addr) { 875 876 case SM501_DC_PANEL_CONTROL: 877 ret = s->dc_panel_control; 878 break; 879 case SM501_DC_PANEL_PANNING_CONTROL: 880 ret = s->dc_panel_panning_control; 881 break; 882 case SM501_DC_PANEL_FB_ADDR: 883 ret = s->dc_panel_fb_addr; 884 break; 885 case SM501_DC_PANEL_FB_OFFSET: 886 ret = s->dc_panel_fb_offset; 887 break; 888 case SM501_DC_PANEL_FB_WIDTH: 889 ret = s->dc_panel_fb_width; 890 break; 891 case SM501_DC_PANEL_FB_HEIGHT: 892 ret = s->dc_panel_fb_height; 893 break; 894 case SM501_DC_PANEL_TL_LOC: 895 ret = s->dc_panel_tl_location; 896 break; 897 case SM501_DC_PANEL_BR_LOC: 898 ret = s->dc_panel_br_location; 899 break; 900 901 case SM501_DC_PANEL_H_TOT: 902 ret = s->dc_panel_h_total; 903 break; 904 case SM501_DC_PANEL_H_SYNC: 905 ret = s->dc_panel_h_sync; 906 break; 907 case SM501_DC_PANEL_V_TOT: 908 ret = s->dc_panel_v_total; 909 break; 910 case SM501_DC_PANEL_V_SYNC: 911 ret = s->dc_panel_v_sync; 912 break; 913 914 case SM501_DC_CRT_CONTROL: 915 ret = s->dc_crt_control; 916 break; 917 case SM501_DC_CRT_FB_ADDR: 918 ret = s->dc_crt_fb_addr; 919 break; 920 case SM501_DC_CRT_FB_OFFSET: 921 ret = s->dc_crt_fb_offset; 922 break; 923 case SM501_DC_CRT_H_TOT: 924 ret = s->dc_crt_h_total; 925 break; 926 case SM501_DC_CRT_H_SYNC: 927 ret = s->dc_crt_h_sync; 928 break; 929 case SM501_DC_CRT_V_TOT: 930 ret = s->dc_crt_v_total; 931 break; 932 case SM501_DC_CRT_V_SYNC: 933 ret = s->dc_crt_v_sync; 934 break; 935 936 case SM501_DC_CRT_HWC_ADDR: 937 ret = s->dc_crt_hwc_addr; 938 break; 939 case SM501_DC_CRT_HWC_LOC: 940 ret = s->dc_crt_hwc_location; 941 break; 942 case SM501_DC_CRT_HWC_COLOR_1_2: 943 ret = s->dc_crt_hwc_color_1_2; 944 break; 945 case SM501_DC_CRT_HWC_COLOR_3: 946 ret = s->dc_crt_hwc_color_3; 947 break; 948 949 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: 950 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); 951 break; 952 953 default: 954 printf("sm501 disp ctrl : not implemented register read." 955 " addr=%x\n", (int)addr); 956 abort(); 957 } 958 959 return ret; 960 } 961 962 static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, 963 uint64_t value, unsigned size) 964 { 965 SM501State * s = (SM501State *)opaque; 966 SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n", 967 (unsigned)addr, (unsigned)value); 968 969 switch(addr) { 970 case SM501_DC_PANEL_CONTROL: 971 s->dc_panel_control = value & 0x0FFF73FF; 972 break; 973 case SM501_DC_PANEL_PANNING_CONTROL: 974 s->dc_panel_panning_control = value & 0xFF3FFF3F; 975 break; 976 case SM501_DC_PANEL_FB_ADDR: 977 s->dc_panel_fb_addr = value & 0x8FFFFFF0; 978 break; 979 case SM501_DC_PANEL_FB_OFFSET: 980 s->dc_panel_fb_offset = value & 0x3FF03FF0; 981 break; 982 case SM501_DC_PANEL_FB_WIDTH: 983 s->dc_panel_fb_width = value & 0x0FFF0FFF; 984 break; 985 case SM501_DC_PANEL_FB_HEIGHT: 986 s->dc_panel_fb_height = value & 0x0FFF0FFF; 987 break; 988 case SM501_DC_PANEL_TL_LOC: 989 s->dc_panel_tl_location = value & 0x07FF07FF; 990 break; 991 case SM501_DC_PANEL_BR_LOC: 992 s->dc_panel_br_location = value & 0x07FF07FF; 993 break; 994 995 case SM501_DC_PANEL_H_TOT: 996 s->dc_panel_h_total = value & 0x0FFF0FFF; 997 break; 998 case SM501_DC_PANEL_H_SYNC: 999 s->dc_panel_h_sync = value & 0x00FF0FFF; 1000 break; 1001 case SM501_DC_PANEL_V_TOT: 1002 s->dc_panel_v_total = value & 0x0FFF0FFF; 1003 break; 1004 case SM501_DC_PANEL_V_SYNC: 1005 s->dc_panel_v_sync = value & 0x003F0FFF; 1006 break; 1007 1008 case SM501_DC_PANEL_HWC_ADDR: 1009 s->dc_panel_hwc_addr = value & 0x8FFFFFF0; 1010 break; 1011 case SM501_DC_PANEL_HWC_LOC: 1012 s->dc_panel_hwc_location = value & 0x0FFF0FFF; 1013 break; 1014 case SM501_DC_PANEL_HWC_COLOR_1_2: 1015 s->dc_panel_hwc_color_1_2 = value; 1016 break; 1017 case SM501_DC_PANEL_HWC_COLOR_3: 1018 s->dc_panel_hwc_color_3 = value & 0x0000FFFF; 1019 break; 1020 1021 case SM501_DC_CRT_CONTROL: 1022 s->dc_crt_control = value & 0x0003FFFF; 1023 break; 1024 case SM501_DC_CRT_FB_ADDR: 1025 s->dc_crt_fb_addr = value & 0x8FFFFFF0; 1026 break; 1027 case SM501_DC_CRT_FB_OFFSET: 1028 s->dc_crt_fb_offset = value & 0x3FF03FF0; 1029 break; 1030 case SM501_DC_CRT_H_TOT: 1031 s->dc_crt_h_total = value & 0x0FFF0FFF; 1032 break; 1033 case SM501_DC_CRT_H_SYNC: 1034 s->dc_crt_h_sync = value & 0x00FF0FFF; 1035 break; 1036 case SM501_DC_CRT_V_TOT: 1037 s->dc_crt_v_total = value & 0x0FFF0FFF; 1038 break; 1039 case SM501_DC_CRT_V_SYNC: 1040 s->dc_crt_v_sync = value & 0x003F0FFF; 1041 break; 1042 1043 case SM501_DC_CRT_HWC_ADDR: 1044 s->dc_crt_hwc_addr = value & 0x8FFFFFF0; 1045 break; 1046 case SM501_DC_CRT_HWC_LOC: 1047 s->dc_crt_hwc_location = value & 0x0FFF0FFF; 1048 break; 1049 case SM501_DC_CRT_HWC_COLOR_1_2: 1050 s->dc_crt_hwc_color_1_2 = value; 1051 break; 1052 case SM501_DC_CRT_HWC_COLOR_3: 1053 s->dc_crt_hwc_color_3 = value & 0x0000FFFF; 1054 break; 1055 1056 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: 1057 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); 1058 break; 1059 1060 default: 1061 printf("sm501 disp ctrl : not implemented register write." 1062 " addr=%x, val=%x\n", (int)addr, (unsigned)value); 1063 abort(); 1064 } 1065 } 1066 1067 static const MemoryRegionOps sm501_disp_ctrl_ops = { 1068 .read = sm501_disp_ctrl_read, 1069 .write = sm501_disp_ctrl_write, 1070 .valid = { 1071 .min_access_size = 4, 1072 .max_access_size = 4, 1073 }, 1074 .endianness = DEVICE_NATIVE_ENDIAN, 1075 }; 1076 1077 static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, 1078 unsigned size) 1079 { 1080 SM501State * s = (SM501State *)opaque; 1081 uint32_t ret = 0; 1082 SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr); 1083 1084 switch(addr) { 1085 case SM501_2D_SOURCE_BASE: 1086 ret = s->twoD_source_base; 1087 break; 1088 default: 1089 printf("sm501 disp ctrl : not implemented register read." 1090 " addr=%x\n", (int)addr); 1091 abort(); 1092 } 1093 1094 return ret; 1095 } 1096 1097 static void sm501_2d_engine_write(void *opaque, hwaddr addr, 1098 uint64_t value, unsigned size) 1099 { 1100 SM501State * s = (SM501State *)opaque; 1101 SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n", 1102 (unsigned)addr, (unsigned)value); 1103 1104 switch(addr) { 1105 case SM501_2D_SOURCE: 1106 s->twoD_source = value; 1107 break; 1108 case SM501_2D_DESTINATION: 1109 s->twoD_destination = value; 1110 break; 1111 case SM501_2D_DIMENSION: 1112 s->twoD_dimension = value; 1113 break; 1114 case SM501_2D_CONTROL: 1115 s->twoD_control = value; 1116 1117 /* do 2d operation if start flag is set. */ 1118 if (value & 0x80000000) { 1119 sm501_2d_operation(s); 1120 s->twoD_control &= ~0x80000000; /* start flag down */ 1121 } 1122 1123 break; 1124 case SM501_2D_PITCH: 1125 s->twoD_pitch = value; 1126 break; 1127 case SM501_2D_FOREGROUND: 1128 s->twoD_foreground = value; 1129 break; 1130 case SM501_2D_STRETCH: 1131 s->twoD_stretch = value; 1132 break; 1133 case SM501_2D_COLOR_COMPARE_MASK: 1134 s->twoD_color_compare_mask = value; 1135 break; 1136 case SM501_2D_MASK: 1137 s->twoD_mask = value; 1138 break; 1139 case SM501_2D_WINDOW_WIDTH: 1140 s->twoD_window_width = value; 1141 break; 1142 case SM501_2D_SOURCE_BASE: 1143 s->twoD_source_base = value; 1144 break; 1145 case SM501_2D_DESTINATION_BASE: 1146 s->twoD_destination_base = value; 1147 break; 1148 default: 1149 printf("sm501 2d engine : not implemented register write." 1150 " addr=%x, val=%x\n", (int)addr, (unsigned)value); 1151 abort(); 1152 } 1153 } 1154 1155 static const MemoryRegionOps sm501_2d_engine_ops = { 1156 .read = sm501_2d_engine_read, 1157 .write = sm501_2d_engine_write, 1158 .valid = { 1159 .min_access_size = 4, 1160 .max_access_size = 4, 1161 }, 1162 .endianness = DEVICE_NATIVE_ENDIAN, 1163 }; 1164 1165 /* draw line functions for all console modes */ 1166 1167 typedef void draw_line_func(uint8_t *d, const uint8_t *s, 1168 int width, const uint32_t *pal); 1169 1170 typedef void draw_hwc_line_func(SM501State * s, int crt, uint8_t * palette, 1171 int c_y, uint8_t *d, int width); 1172 1173 #define DEPTH 8 1174 #include "sm501_template.h" 1175 1176 #define DEPTH 15 1177 #include "sm501_template.h" 1178 1179 #define BGR_FORMAT 1180 #define DEPTH 15 1181 #include "sm501_template.h" 1182 1183 #define DEPTH 16 1184 #include "sm501_template.h" 1185 1186 #define BGR_FORMAT 1187 #define DEPTH 16 1188 #include "sm501_template.h" 1189 1190 #define DEPTH 32 1191 #include "sm501_template.h" 1192 1193 #define BGR_FORMAT 1194 #define DEPTH 32 1195 #include "sm501_template.h" 1196 1197 static draw_line_func * draw_line8_funcs[] = { 1198 draw_line8_8, 1199 draw_line8_15, 1200 draw_line8_16, 1201 draw_line8_32, 1202 draw_line8_32bgr, 1203 draw_line8_15bgr, 1204 draw_line8_16bgr, 1205 }; 1206 1207 static draw_line_func * draw_line16_funcs[] = { 1208 draw_line16_8, 1209 draw_line16_15, 1210 draw_line16_16, 1211 draw_line16_32, 1212 draw_line16_32bgr, 1213 draw_line16_15bgr, 1214 draw_line16_16bgr, 1215 }; 1216 1217 static draw_line_func * draw_line32_funcs[] = { 1218 draw_line32_8, 1219 draw_line32_15, 1220 draw_line32_16, 1221 draw_line32_32, 1222 draw_line32_32bgr, 1223 draw_line32_15bgr, 1224 draw_line32_16bgr, 1225 }; 1226 1227 static draw_hwc_line_func * draw_hwc_line_funcs[] = { 1228 draw_hwc_line_8, 1229 draw_hwc_line_15, 1230 draw_hwc_line_16, 1231 draw_hwc_line_32, 1232 draw_hwc_line_32bgr, 1233 draw_hwc_line_15bgr, 1234 draw_hwc_line_16bgr, 1235 }; 1236 1237 static inline int get_depth_index(DisplaySurface *surface) 1238 { 1239 switch (surface_bits_per_pixel(surface)) { 1240 default: 1241 case 8: 1242 return 0; 1243 case 15: 1244 return 1; 1245 case 16: 1246 return 2; 1247 case 32: 1248 if (is_surface_bgr(surface)) { 1249 return 4; 1250 } else { 1251 return 3; 1252 } 1253 } 1254 } 1255 1256 static void sm501_draw_crt(SM501State * s) 1257 { 1258 DisplaySurface *surface = qemu_console_surface(s->con); 1259 int y; 1260 int width = (s->dc_crt_h_total & 0x00000FFF) + 1; 1261 int height = (s->dc_crt_v_total & 0x00000FFF) + 1; 1262 1263 uint8_t * src = s->local_mem; 1264 int src_bpp = 0; 1265 int dst_bpp = surface_bytes_per_pixel(surface); 1266 uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE 1267 - SM501_DC_PANEL_PALETTE]; 1268 uint8_t hwc_palette[3 * 3]; 1269 int ds_depth_index = get_depth_index(surface); 1270 draw_line_func * draw_line = NULL; 1271 draw_hwc_line_func * draw_hwc_line = NULL; 1272 int full_update = 0; 1273 int y_start = -1; 1274 ram_addr_t page_min = ~0l; 1275 ram_addr_t page_max = 0l; 1276 ram_addr_t offset = 0; 1277 1278 /* choose draw_line function */ 1279 switch (s->dc_crt_control & 3) { 1280 case SM501_DC_CRT_CONTROL_8BPP: 1281 src_bpp = 1; 1282 draw_line = draw_line8_funcs[ds_depth_index]; 1283 break; 1284 case SM501_DC_CRT_CONTROL_16BPP: 1285 src_bpp = 2; 1286 draw_line = draw_line16_funcs[ds_depth_index]; 1287 break; 1288 case SM501_DC_CRT_CONTROL_32BPP: 1289 src_bpp = 4; 1290 draw_line = draw_line32_funcs[ds_depth_index]; 1291 break; 1292 default: 1293 printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n", 1294 s->dc_crt_control); 1295 abort(); 1296 break; 1297 } 1298 1299 /* set up to draw hardware cursor */ 1300 if (is_hwc_enabled(s, 1)) { 1301 int i; 1302 1303 /* get cursor palette */ 1304 for (i = 0; i < 3; i++) { 1305 uint16_t rgb565 = get_hwc_color(s, 1, i + 1); 1306 hwc_palette[i * 3 + 0] = (rgb565 & 0xf800) >> 8; /* red */ 1307 hwc_palette[i * 3 + 1] = (rgb565 & 0x07e0) >> 3; /* green */ 1308 hwc_palette[i * 3 + 2] = (rgb565 & 0x001f) << 3; /* blue */ 1309 } 1310 1311 /* choose cursor draw line function */ 1312 draw_hwc_line = draw_hwc_line_funcs[ds_depth_index]; 1313 } 1314 1315 /* adjust console size */ 1316 if (s->last_width != width || s->last_height != height) { 1317 qemu_console_resize(s->con, width, height); 1318 surface = qemu_console_surface(s->con); 1319 s->last_width = width; 1320 s->last_height = height; 1321 full_update = 1; 1322 } 1323 1324 /* draw each line according to conditions */ 1325 memory_region_sync_dirty_bitmap(&s->local_mem_region); 1326 for (y = 0; y < height; y++) { 1327 int update_hwc = draw_hwc_line ? within_hwc_y_range(s, y, 1) : 0; 1328 int update = full_update || update_hwc; 1329 ram_addr_t page0 = offset; 1330 ram_addr_t page1 = offset + width * src_bpp - 1; 1331 1332 /* check dirty flags for each line */ 1333 update = memory_region_get_dirty(&s->local_mem_region, page0, 1334 page1 - page0, DIRTY_MEMORY_VGA); 1335 1336 /* draw line and change status */ 1337 if (update) { 1338 uint8_t *d = surface_data(surface); 1339 d += y * width * dst_bpp; 1340 1341 /* draw graphics layer */ 1342 draw_line(d, src, width, palette); 1343 1344 /* draw haredware cursor */ 1345 if (update_hwc) { 1346 draw_hwc_line(s, 1, hwc_palette, y - get_hwc_y(s, 1), d, width); 1347 } 1348 1349 if (y_start < 0) 1350 y_start = y; 1351 if (page0 < page_min) 1352 page_min = page0; 1353 if (page1 > page_max) 1354 page_max = page1; 1355 } else { 1356 if (y_start >= 0) { 1357 /* flush to display */ 1358 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 1359 y_start = -1; 1360 } 1361 } 1362 1363 src += width * src_bpp; 1364 offset += width * src_bpp; 1365 } 1366 1367 /* complete flush to display */ 1368 if (y_start >= 0) 1369 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 1370 1371 /* clear dirty flags */ 1372 if (page_min != ~0l) { 1373 memory_region_reset_dirty(&s->local_mem_region, 1374 page_min, page_max + TARGET_PAGE_SIZE, 1375 DIRTY_MEMORY_VGA); 1376 } 1377 } 1378 1379 static void sm501_update_display(void *opaque) 1380 { 1381 SM501State * s = (SM501State *)opaque; 1382 1383 if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) 1384 sm501_draw_crt(s); 1385 } 1386 1387 static const GraphicHwOps sm501_ops = { 1388 .gfx_update = sm501_update_display, 1389 }; 1390 1391 void sm501_init(MemoryRegion *address_space_mem, uint32_t base, 1392 uint32_t local_mem_bytes, qemu_irq irq, CharDriverState *chr) 1393 { 1394 SM501State * s; 1395 DeviceState *dev; 1396 MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1); 1397 MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1); 1398 MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1); 1399 1400 /* allocate management data region */ 1401 s = (SM501State *)g_malloc0(sizeof(SM501State)); 1402 s->base = base; 1403 s->local_mem_size_index 1404 = get_local_mem_size_index(local_mem_bytes); 1405 SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s), 1406 s->local_mem_size_index); 1407 s->system_control = 0x00100000; 1408 s->misc_control = 0x00001000; /* assumes SH, active=low */ 1409 s->dc_panel_control = 0x00010000; 1410 s->dc_crt_control = 0x00010000; 1411 1412 /* allocate local memory */ 1413 memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local", 1414 local_mem_bytes, &error_abort); 1415 vmstate_register_ram_global(&s->local_mem_region); 1416 memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); 1417 s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); 1418 memory_region_add_subregion(address_space_mem, base, &s->local_mem_region); 1419 1420 /* map mmio */ 1421 memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops, s, 1422 "sm501-system-config", 0x6c); 1423 memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET, 1424 sm501_system_config); 1425 memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s, 1426 "sm501-disp-ctrl", 0x1000); 1427 memory_region_add_subregion(address_space_mem, 1428 base + MMIO_BASE_OFFSET + SM501_DC, 1429 sm501_disp_ctrl); 1430 memory_region_init_io(sm501_2d_engine, NULL, &sm501_2d_engine_ops, s, 1431 "sm501-2d-engine", 0x54); 1432 memory_region_add_subregion(address_space_mem, 1433 base + MMIO_BASE_OFFSET + SM501_2D_ENGINE, 1434 sm501_2d_engine); 1435 1436 /* bridge to usb host emulation module */ 1437 dev = qdev_create(NULL, "sysbus-ohci"); 1438 qdev_prop_set_uint32(dev, "num-ports", 2); 1439 qdev_prop_set_uint64(dev, "dma-offset", base); 1440 qdev_init_nofail(dev); 1441 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1442 base + MMIO_BASE_OFFSET + SM501_USB_HOST); 1443 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 1444 1445 /* bridge to serial emulation module */ 1446 if (chr) { 1447 serial_mm_init(address_space_mem, 1448 base + MMIO_BASE_OFFSET + SM501_UART0, 2, 1449 NULL, /* TODO : chain irq to IRL */ 1450 115200, chr, DEVICE_NATIVE_ENDIAN); 1451 } 1452 1453 /* create qemu graphic console */ 1454 s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s); 1455 } 1456