1 /* 2 * QEMU SM501 Device 3 * 4 * Copyright (c) 2008 Shin-ichiro KAWASAKI 5 * Copyright (c) 2016 BALATON Zoltan 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qapi/error.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "cpu.h" 32 #include "hw/char/serial.h" 33 #include "ui/console.h" 34 #include "hw/sysbus.h" 35 #include "migration/vmstate.h" 36 #include "hw/pci/pci.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/i2c/i2c.h" 39 #include "hw/display/i2c-ddc.h" 40 #include "qemu/range.h" 41 #include "ui/pixel_ops.h" 42 #include "qemu/bswap.h" 43 44 /* 45 * Status: 2010/05/07 46 * - Minimum implementation for Linux console : mmio regs and CRT layer. 47 * - 2D graphics acceleration partially supported : only fill rectangle. 48 * 49 * Status: 2016/12/04 50 * - Misc fixes: endianness, hardware cursor 51 * - Panel support 52 * 53 * TODO: 54 * - Touch panel support 55 * - USB support 56 * - UART support 57 * - More 2D graphics engine support 58 * - Performance tuning 59 */ 60 61 /*#define DEBUG_SM501*/ 62 /*#define DEBUG_BITBLT*/ 63 64 #ifdef DEBUG_SM501 65 #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) 66 #else 67 #define SM501_DPRINTF(fmt, ...) do {} while (0) 68 #endif 69 70 #define MMIO_BASE_OFFSET 0x3e00000 71 #define MMIO_SIZE 0x200000 72 #define DC_PALETTE_ENTRIES (0x400 * 3) 73 74 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ 75 76 /* System Configuration area */ 77 /* System config base */ 78 #define SM501_SYS_CONFIG (0x000000) 79 80 /* config 1 */ 81 #define SM501_SYSTEM_CONTROL (0x000000) 82 83 #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) 84 #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) 85 #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) 86 87 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) 88 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) 89 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) 90 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) 91 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) 92 93 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) 94 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) 95 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) 96 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) 97 98 /* miscellaneous control */ 99 100 #define SM501_MISC_CONTROL (0x000004) 101 102 #define SM501_MISC_BUS_SH (0x0) 103 #define SM501_MISC_BUS_PCI (0x1) 104 #define SM501_MISC_BUS_XSCALE (0x2) 105 #define SM501_MISC_BUS_NEC (0x6) 106 #define SM501_MISC_BUS_MASK (0x7) 107 108 #define SM501_MISC_VR_62MB (1 << 3) 109 #define SM501_MISC_CDR_RESET (1 << 7) 110 #define SM501_MISC_USB_LB (1 << 8) 111 #define SM501_MISC_USB_SLAVE (1 << 9) 112 #define SM501_MISC_BL_1 (1 << 10) 113 #define SM501_MISC_MC (1 << 11) 114 #define SM501_MISC_DAC_POWER (1 << 12) 115 #define SM501_MISC_IRQ_INVERT (1 << 16) 116 #define SM501_MISC_SH (1 << 17) 117 118 #define SM501_MISC_HOLD_EMPTY (0 << 18) 119 #define SM501_MISC_HOLD_8 (1 << 18) 120 #define SM501_MISC_HOLD_16 (2 << 18) 121 #define SM501_MISC_HOLD_24 (3 << 18) 122 #define SM501_MISC_HOLD_32 (4 << 18) 123 #define SM501_MISC_HOLD_MASK (7 << 18) 124 125 #define SM501_MISC_FREQ_12 (1 << 24) 126 #define SM501_MISC_PNL_24BIT (1 << 25) 127 #define SM501_MISC_8051_LE (1 << 26) 128 129 130 131 #define SM501_GPIO31_0_CONTROL (0x000008) 132 #define SM501_GPIO63_32_CONTROL (0x00000C) 133 #define SM501_DRAM_CONTROL (0x000010) 134 135 /* command list */ 136 #define SM501_ARBTRTN_CONTROL (0x000014) 137 138 /* command list */ 139 #define SM501_COMMAND_LIST_STATUS (0x000024) 140 141 /* interrupt debug */ 142 #define SM501_RAW_IRQ_STATUS (0x000028) 143 #define SM501_RAW_IRQ_CLEAR (0x000028) 144 #define SM501_IRQ_STATUS (0x00002C) 145 #define SM501_IRQ_MASK (0x000030) 146 #define SM501_DEBUG_CONTROL (0x000034) 147 148 /* power management */ 149 #define SM501_POWERMODE_P2X_SRC (1 << 29) 150 #define SM501_POWERMODE_V2X_SRC (1 << 20) 151 #define SM501_POWERMODE_M_SRC (1 << 12) 152 #define SM501_POWERMODE_M1_SRC (1 << 4) 153 154 #define SM501_CURRENT_GATE (0x000038) 155 #define SM501_CURRENT_CLOCK (0x00003C) 156 #define SM501_POWER_MODE_0_GATE (0x000040) 157 #define SM501_POWER_MODE_0_CLOCK (0x000044) 158 #define SM501_POWER_MODE_1_GATE (0x000048) 159 #define SM501_POWER_MODE_1_CLOCK (0x00004C) 160 #define SM501_SLEEP_MODE_GATE (0x000050) 161 #define SM501_POWER_MODE_CONTROL (0x000054) 162 163 /* power gates for units within the 501 */ 164 #define SM501_GATE_HOST (0) 165 #define SM501_GATE_MEMORY (1) 166 #define SM501_GATE_DISPLAY (2) 167 #define SM501_GATE_2D_ENGINE (3) 168 #define SM501_GATE_CSC (4) 169 #define SM501_GATE_ZVPORT (5) 170 #define SM501_GATE_GPIO (6) 171 #define SM501_GATE_UART0 (7) 172 #define SM501_GATE_UART1 (8) 173 #define SM501_GATE_SSP (10) 174 #define SM501_GATE_USB_HOST (11) 175 #define SM501_GATE_USB_GADGET (12) 176 #define SM501_GATE_UCONTROLLER (17) 177 #define SM501_GATE_AC97 (18) 178 179 /* panel clock */ 180 #define SM501_CLOCK_P2XCLK (24) 181 /* crt clock */ 182 #define SM501_CLOCK_V2XCLK (16) 183 /* main clock */ 184 #define SM501_CLOCK_MCLK (8) 185 /* SDRAM controller clock */ 186 #define SM501_CLOCK_M1XCLK (0) 187 188 /* config 2 */ 189 #define SM501_PCI_MASTER_BASE (0x000058) 190 #define SM501_ENDIAN_CONTROL (0x00005C) 191 #define SM501_DEVICEID (0x000060) 192 /* 0x050100A0 */ 193 194 #define SM501_DEVICEID_SM501 (0x05010000) 195 #define SM501_DEVICEID_IDMASK (0xffff0000) 196 #define SM501_DEVICEID_REVMASK (0x000000ff) 197 198 #define SM501_PLLCLOCK_COUNT (0x000064) 199 #define SM501_MISC_TIMING (0x000068) 200 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) 201 202 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) 203 204 /* GPIO base */ 205 #define SM501_GPIO (0x010000) 206 #define SM501_GPIO_DATA_LOW (0x00) 207 #define SM501_GPIO_DATA_HIGH (0x04) 208 #define SM501_GPIO_DDR_LOW (0x08) 209 #define SM501_GPIO_DDR_HIGH (0x0C) 210 #define SM501_GPIO_IRQ_SETUP (0x10) 211 #define SM501_GPIO_IRQ_STATUS (0x14) 212 #define SM501_GPIO_IRQ_RESET (0x14) 213 214 /* I2C controller base */ 215 #define SM501_I2C (0x010040) 216 #define SM501_I2C_BYTE_COUNT (0x00) 217 #define SM501_I2C_CONTROL (0x01) 218 #define SM501_I2C_STATUS (0x02) 219 #define SM501_I2C_RESET (0x02) 220 #define SM501_I2C_SLAVE_ADDRESS (0x03) 221 #define SM501_I2C_DATA (0x04) 222 223 #define SM501_I2C_CONTROL_START (1 << 2) 224 #define SM501_I2C_CONTROL_ENABLE (1 << 0) 225 226 #define SM501_I2C_STATUS_COMPLETE (1 << 3) 227 #define SM501_I2C_STATUS_ERROR (1 << 2) 228 229 #define SM501_I2C_RESET_ERROR (1 << 2) 230 231 /* SSP base */ 232 #define SM501_SSP (0x020000) 233 234 /* Uart 0 base */ 235 #define SM501_UART0 (0x030000) 236 237 /* Uart 1 base */ 238 #define SM501_UART1 (0x030020) 239 240 /* USB host port base */ 241 #define SM501_USB_HOST (0x040000) 242 243 /* USB slave/gadget base */ 244 #define SM501_USB_GADGET (0x060000) 245 246 /* USB slave/gadget data port base */ 247 #define SM501_USB_GADGET_DATA (0x070000) 248 249 /* Display controller/video engine base */ 250 #define SM501_DC (0x080000) 251 252 /* common defines for the SM501 address registers */ 253 #define SM501_ADDR_FLIP (1 << 31) 254 #define SM501_ADDR_EXT (1 << 27) 255 #define SM501_ADDR_CS1 (1 << 26) 256 #define SM501_ADDR_MASK (0x3f << 26) 257 258 #define SM501_FIFO_MASK (0x3 << 16) 259 #define SM501_FIFO_1 (0x0 << 16) 260 #define SM501_FIFO_3 (0x1 << 16) 261 #define SM501_FIFO_7 (0x2 << 16) 262 #define SM501_FIFO_11 (0x3 << 16) 263 264 /* common registers for panel and the crt */ 265 #define SM501_OFF_DC_H_TOT (0x000) 266 #define SM501_OFF_DC_V_TOT (0x008) 267 #define SM501_OFF_DC_H_SYNC (0x004) 268 #define SM501_OFF_DC_V_SYNC (0x00C) 269 270 #define SM501_DC_PANEL_CONTROL (0x000) 271 272 #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) 273 #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) 274 #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) 275 #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) 276 #define SM501_DC_PANEL_CONTROL_DP (1 << 23) 277 278 #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) 279 #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) 280 #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) 281 282 #define SM501_DC_PANEL_CONTROL_DE (1 << 20) 283 284 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) 285 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) 286 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) 287 288 #define SM501_DC_PANEL_CONTROL_CP (1 << 14) 289 #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) 290 #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) 291 #define SM501_DC_PANEL_CONTROL_CK (1 << 9) 292 #define SM501_DC_PANEL_CONTROL_TE (1 << 8) 293 #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) 294 #define SM501_DC_PANEL_CONTROL_VP (1 << 6) 295 #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) 296 #define SM501_DC_PANEL_CONTROL_HP (1 << 4) 297 #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) 298 #define SM501_DC_PANEL_CONTROL_EN (1 << 2) 299 300 #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) 301 #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) 302 #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) 303 304 305 #define SM501_DC_PANEL_PANNING_CONTROL (0x004) 306 #define SM501_DC_PANEL_COLOR_KEY (0x008) 307 #define SM501_DC_PANEL_FB_ADDR (0x00C) 308 #define SM501_DC_PANEL_FB_OFFSET (0x010) 309 #define SM501_DC_PANEL_FB_WIDTH (0x014) 310 #define SM501_DC_PANEL_FB_HEIGHT (0x018) 311 #define SM501_DC_PANEL_TL_LOC (0x01C) 312 #define SM501_DC_PANEL_BR_LOC (0x020) 313 #define SM501_DC_PANEL_H_TOT (0x024) 314 #define SM501_DC_PANEL_H_SYNC (0x028) 315 #define SM501_DC_PANEL_V_TOT (0x02C) 316 #define SM501_DC_PANEL_V_SYNC (0x030) 317 #define SM501_DC_PANEL_CUR_LINE (0x034) 318 319 #define SM501_DC_VIDEO_CONTROL (0x040) 320 #define SM501_DC_VIDEO_FB0_ADDR (0x044) 321 #define SM501_DC_VIDEO_FB_WIDTH (0x048) 322 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) 323 #define SM501_DC_VIDEO_TL_LOC (0x050) 324 #define SM501_DC_VIDEO_BR_LOC (0x054) 325 #define SM501_DC_VIDEO_SCALE (0x058) 326 #define SM501_DC_VIDEO_INIT_SCALE (0x05C) 327 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) 328 #define SM501_DC_VIDEO_FB1_ADDR (0x064) 329 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) 330 331 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) 332 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) 333 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) 334 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) 335 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) 336 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) 337 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) 338 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) 339 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) 340 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) 341 342 #define SM501_DC_PANEL_HWC_BASE (0x0F0) 343 #define SM501_DC_PANEL_HWC_ADDR (0x0F0) 344 #define SM501_DC_PANEL_HWC_LOC (0x0F4) 345 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) 346 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) 347 348 #define SM501_HWC_EN (1 << 31) 349 350 #define SM501_OFF_HWC_ADDR (0x00) 351 #define SM501_OFF_HWC_LOC (0x04) 352 #define SM501_OFF_HWC_COLOR_1_2 (0x08) 353 #define SM501_OFF_HWC_COLOR_3 (0x0C) 354 355 #define SM501_DC_ALPHA_CONTROL (0x100) 356 #define SM501_DC_ALPHA_FB_ADDR (0x104) 357 #define SM501_DC_ALPHA_FB_OFFSET (0x108) 358 #define SM501_DC_ALPHA_TL_LOC (0x10C) 359 #define SM501_DC_ALPHA_BR_LOC (0x110) 360 #define SM501_DC_ALPHA_CHROMA_KEY (0x114) 361 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) 362 363 #define SM501_DC_CRT_CONTROL (0x200) 364 365 #define SM501_DC_CRT_CONTROL_TVP (1 << 15) 366 #define SM501_DC_CRT_CONTROL_CP (1 << 14) 367 #define SM501_DC_CRT_CONTROL_VSP (1 << 13) 368 #define SM501_DC_CRT_CONTROL_HSP (1 << 12) 369 #define SM501_DC_CRT_CONTROL_VS (1 << 11) 370 #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) 371 #define SM501_DC_CRT_CONTROL_SEL (1 << 9) 372 #define SM501_DC_CRT_CONTROL_TE (1 << 8) 373 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) 374 #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) 375 #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) 376 377 #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) 378 #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) 379 #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) 380 381 #define SM501_DC_CRT_FB_ADDR (0x204) 382 #define SM501_DC_CRT_FB_OFFSET (0x208) 383 #define SM501_DC_CRT_H_TOT (0x20C) 384 #define SM501_DC_CRT_H_SYNC (0x210) 385 #define SM501_DC_CRT_V_TOT (0x214) 386 #define SM501_DC_CRT_V_SYNC (0x218) 387 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) 388 #define SM501_DC_CRT_CUR_LINE (0x220) 389 #define SM501_DC_CRT_MONITOR_DETECT (0x224) 390 391 #define SM501_DC_CRT_HWC_BASE (0x230) 392 #define SM501_DC_CRT_HWC_ADDR (0x230) 393 #define SM501_DC_CRT_HWC_LOC (0x234) 394 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) 395 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) 396 397 #define SM501_DC_PANEL_PALETTE (0x400) 398 399 #define SM501_DC_VIDEO_PALETTE (0x800) 400 401 #define SM501_DC_CRT_PALETTE (0xC00) 402 403 /* Zoom Video port base */ 404 #define SM501_ZVPORT (0x090000) 405 406 /* AC97/I2S base */ 407 #define SM501_AC97 (0x0A0000) 408 409 /* 8051 micro controller base */ 410 #define SM501_UCONTROLLER (0x0B0000) 411 412 /* 8051 micro controller SRAM base */ 413 #define SM501_UCONTROLLER_SRAM (0x0C0000) 414 415 /* DMA base */ 416 #define SM501_DMA (0x0D0000) 417 418 /* 2d engine base */ 419 #define SM501_2D_ENGINE (0x100000) 420 #define SM501_2D_SOURCE (0x00) 421 #define SM501_2D_DESTINATION (0x04) 422 #define SM501_2D_DIMENSION (0x08) 423 #define SM501_2D_CONTROL (0x0C) 424 #define SM501_2D_PITCH (0x10) 425 #define SM501_2D_FOREGROUND (0x14) 426 #define SM501_2D_BACKGROUND (0x18) 427 #define SM501_2D_STRETCH (0x1C) 428 #define SM501_2D_COLOR_COMPARE (0x20) 429 #define SM501_2D_COLOR_COMPARE_MASK (0x24) 430 #define SM501_2D_MASK (0x28) 431 #define SM501_2D_CLIP_TL (0x2C) 432 #define SM501_2D_CLIP_BR (0x30) 433 #define SM501_2D_MONO_PATTERN_LOW (0x34) 434 #define SM501_2D_MONO_PATTERN_HIGH (0x38) 435 #define SM501_2D_WINDOW_WIDTH (0x3C) 436 #define SM501_2D_SOURCE_BASE (0x40) 437 #define SM501_2D_DESTINATION_BASE (0x44) 438 #define SM501_2D_ALPHA (0x48) 439 #define SM501_2D_WRAP (0x4C) 440 #define SM501_2D_STATUS (0x50) 441 442 #define SM501_CSC_Y_SOURCE_BASE (0xC8) 443 #define SM501_CSC_CONSTANTS (0xCC) 444 #define SM501_CSC_Y_SOURCE_X (0xD0) 445 #define SM501_CSC_Y_SOURCE_Y (0xD4) 446 #define SM501_CSC_U_SOURCE_BASE (0xD8) 447 #define SM501_CSC_V_SOURCE_BASE (0xDC) 448 #define SM501_CSC_SOURCE_DIMENSION (0xE0) 449 #define SM501_CSC_SOURCE_PITCH (0xE4) 450 #define SM501_CSC_DESTINATION (0xE8) 451 #define SM501_CSC_DESTINATION_DIMENSION (0xEC) 452 #define SM501_CSC_DESTINATION_PITCH (0xF0) 453 #define SM501_CSC_SCALE_FACTOR (0xF4) 454 #define SM501_CSC_DESTINATION_BASE (0xF8) 455 #define SM501_CSC_CONTROL (0xFC) 456 457 /* 2d engine data port base */ 458 #define SM501_2D_ENGINE_DATA (0x110000) 459 460 /* end of register definitions */ 461 462 #define SM501_HWC_WIDTH (64) 463 #define SM501_HWC_HEIGHT (64) 464 465 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ 466 static const uint32_t sm501_mem_local_size[] = { 467 [0] = 4 * MiB, 468 [1] = 8 * MiB, 469 [2] = 16 * MiB, 470 [3] = 32 * MiB, 471 [4] = 64 * MiB, 472 [5] = 2 * MiB, 473 }; 474 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] 475 476 typedef struct SM501State { 477 /* graphic console status */ 478 QemuConsole *con; 479 480 /* status & internal resources */ 481 uint32_t local_mem_size_index; 482 uint8_t *local_mem; 483 MemoryRegion local_mem_region; 484 MemoryRegion mmio_region; 485 MemoryRegion system_config_region; 486 MemoryRegion i2c_region; 487 MemoryRegion disp_ctrl_region; 488 MemoryRegion twoD_engine_region; 489 uint32_t last_width; 490 uint32_t last_height; 491 bool do_full_update; /* perform a full update next time */ 492 I2CBus *i2c_bus; 493 494 /* mmio registers */ 495 uint32_t system_control; 496 uint32_t misc_control; 497 uint32_t gpio_31_0_control; 498 uint32_t gpio_63_32_control; 499 uint32_t dram_control; 500 uint32_t arbitration_control; 501 uint32_t irq_mask; 502 uint32_t misc_timing; 503 uint32_t power_mode_control; 504 505 uint8_t i2c_byte_count; 506 uint8_t i2c_status; 507 uint8_t i2c_addr; 508 uint8_t i2c_data[16]; 509 510 uint32_t uart0_ier; 511 uint32_t uart0_lcr; 512 uint32_t uart0_mcr; 513 uint32_t uart0_scr; 514 515 uint8_t dc_palette[DC_PALETTE_ENTRIES]; 516 517 uint32_t dc_panel_control; 518 uint32_t dc_panel_panning_control; 519 uint32_t dc_panel_fb_addr; 520 uint32_t dc_panel_fb_offset; 521 uint32_t dc_panel_fb_width; 522 uint32_t dc_panel_fb_height; 523 uint32_t dc_panel_tl_location; 524 uint32_t dc_panel_br_location; 525 uint32_t dc_panel_h_total; 526 uint32_t dc_panel_h_sync; 527 uint32_t dc_panel_v_total; 528 uint32_t dc_panel_v_sync; 529 530 uint32_t dc_panel_hwc_addr; 531 uint32_t dc_panel_hwc_location; 532 uint32_t dc_panel_hwc_color_1_2; 533 uint32_t dc_panel_hwc_color_3; 534 535 uint32_t dc_video_control; 536 537 uint32_t dc_crt_control; 538 uint32_t dc_crt_fb_addr; 539 uint32_t dc_crt_fb_offset; 540 uint32_t dc_crt_h_total; 541 uint32_t dc_crt_h_sync; 542 uint32_t dc_crt_v_total; 543 uint32_t dc_crt_v_sync; 544 545 uint32_t dc_crt_hwc_addr; 546 uint32_t dc_crt_hwc_location; 547 uint32_t dc_crt_hwc_color_1_2; 548 uint32_t dc_crt_hwc_color_3; 549 550 uint32_t twoD_source; 551 uint32_t twoD_destination; 552 uint32_t twoD_dimension; 553 uint32_t twoD_control; 554 uint32_t twoD_pitch; 555 uint32_t twoD_foreground; 556 uint32_t twoD_background; 557 uint32_t twoD_stretch; 558 uint32_t twoD_color_compare; 559 uint32_t twoD_color_compare_mask; 560 uint32_t twoD_mask; 561 uint32_t twoD_clip_tl; 562 uint32_t twoD_clip_br; 563 uint32_t twoD_mono_pattern_low; 564 uint32_t twoD_mono_pattern_high; 565 uint32_t twoD_window_width; 566 uint32_t twoD_source_base; 567 uint32_t twoD_destination_base; 568 uint32_t twoD_alpha; 569 uint32_t twoD_wrap; 570 } SM501State; 571 572 static uint32_t get_local_mem_size_index(uint32_t size) 573 { 574 uint32_t norm_size = 0; 575 int i, index = 0; 576 577 for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { 578 uint32_t new_size = sm501_mem_local_size[i]; 579 if (new_size >= size) { 580 if (norm_size == 0 || norm_size > new_size) { 581 norm_size = new_size; 582 index = i; 583 } 584 } 585 } 586 587 return index; 588 } 589 590 static ram_addr_t get_fb_addr(SM501State *s, int crt) 591 { 592 return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0; 593 } 594 595 static inline int get_width(SM501State *s, int crt) 596 { 597 int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total; 598 return (width & 0x00000FFF) + 1; 599 } 600 601 static inline int get_height(SM501State *s, int crt) 602 { 603 int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total; 604 return (height & 0x00000FFF) + 1; 605 } 606 607 static inline int get_bpp(SM501State *s, int crt) 608 { 609 int bpp = crt ? s->dc_crt_control : s->dc_panel_control; 610 return 1 << (bpp & 3); 611 } 612 613 /** 614 * Check the availability of hardware cursor. 615 * @param crt 0 for PANEL, 1 for CRT. 616 */ 617 static inline int is_hwc_enabled(SM501State *state, int crt) 618 { 619 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; 620 return addr & SM501_HWC_EN; 621 } 622 623 /** 624 * Get the address which holds cursor pattern data. 625 * @param crt 0 for PANEL, 1 for CRT. 626 */ 627 static inline uint8_t *get_hwc_address(SM501State *state, int crt) 628 { 629 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; 630 return state->local_mem + (addr & 0x03FFFFF0); 631 } 632 633 /** 634 * Get the cursor position in y coordinate. 635 * @param crt 0 for PANEL, 1 for CRT. 636 */ 637 static inline uint32_t get_hwc_y(SM501State *state, int crt) 638 { 639 uint32_t location = crt ? state->dc_crt_hwc_location 640 : state->dc_panel_hwc_location; 641 return (location & 0x07FF0000) >> 16; 642 } 643 644 /** 645 * Get the cursor position in x coordinate. 646 * @param crt 0 for PANEL, 1 for CRT. 647 */ 648 static inline uint32_t get_hwc_x(SM501State *state, int crt) 649 { 650 uint32_t location = crt ? state->dc_crt_hwc_location 651 : state->dc_panel_hwc_location; 652 return location & 0x000007FF; 653 } 654 655 /** 656 * Get the hardware cursor palette. 657 * @param crt 0 for PANEL, 1 for CRT. 658 * @param palette pointer to a [3 * 3] array to store color values in 659 */ 660 static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette) 661 { 662 int i; 663 uint32_t color_reg; 664 uint16_t rgb565; 665 666 for (i = 0; i < 3; i++) { 667 if (i + 1 == 3) { 668 color_reg = crt ? state->dc_crt_hwc_color_3 669 : state->dc_panel_hwc_color_3; 670 } else { 671 color_reg = crt ? state->dc_crt_hwc_color_1_2 672 : state->dc_panel_hwc_color_1_2; 673 } 674 675 if (i + 1 == 2) { 676 rgb565 = (color_reg >> 16) & 0xFFFF; 677 } else { 678 rgb565 = color_reg & 0xFFFF; 679 } 680 palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */ 681 palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */ 682 palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */ 683 } 684 } 685 686 static inline void hwc_invalidate(SM501State *s, int crt) 687 { 688 int w = get_width(s, crt); 689 int h = get_height(s, crt); 690 int bpp = get_bpp(s, crt); 691 int start = get_hwc_y(s, crt); 692 int end = MIN(h, start + SM501_HWC_HEIGHT) + 1; 693 694 start *= w * bpp; 695 end *= w * bpp; 696 697 memory_region_set_dirty(&s->local_mem_region, 698 get_fb_addr(s, crt) + start, end - start); 699 } 700 701 static void sm501_2d_operation(SM501State *s) 702 { 703 /* obtain operation parameters */ 704 int operation = (s->twoD_control >> 16) & 0x1f; 705 int rtl = s->twoD_control & 0x8000000; 706 int src_x = (s->twoD_source >> 16) & 0x01FFF; 707 int src_y = s->twoD_source & 0xFFFF; 708 int dst_x = (s->twoD_destination >> 16) & 0x01FFF; 709 int dst_y = s->twoD_destination & 0xFFFF; 710 int operation_width = (s->twoD_dimension >> 16) & 0x1FFF; 711 int operation_height = s->twoD_dimension & 0xFFFF; 712 uint32_t color = s->twoD_foreground; 713 int format_flags = (s->twoD_stretch >> 20) & 0x3; 714 int addressing = (s->twoD_stretch >> 16) & 0xF; 715 int rop_mode = (s->twoD_control >> 15) & 0x1; /* 1 for rop2, else rop3 */ 716 /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */ 717 int rop2_source_is_pattern = (s->twoD_control >> 14) & 0x1; 718 int rop = s->twoD_control & 0xFF; 719 uint32_t src_base = s->twoD_source_base & 0x03FFFFFF; 720 uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF; 721 722 /* get frame buffer info */ 723 uint8_t *src = s->local_mem + src_base; 724 uint8_t *dst = s->local_mem + dst_base; 725 int src_width = s->twoD_pitch & 0x1FFF; 726 int dst_width = (s->twoD_pitch >> 16) & 0x1FFF; 727 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; 728 int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt); 729 730 if (addressing != 0x0) { 731 printf("%s: only XY addressing is supported.\n", __func__); 732 abort(); 733 } 734 735 if (rop_mode == 0) { 736 if (rop != 0xcc) { 737 /* Anything other than plain copies are not supported */ 738 qemu_log_mask(LOG_UNIMP, "sm501: rop3 mode with rop %x is not " 739 "supported.\n", rop); 740 } 741 } else { 742 if (rop2_source_is_pattern && rop != 0x5) { 743 /* For pattern source, we support only inverse dest */ 744 qemu_log_mask(LOG_UNIMP, "sm501: rop2 source being the pattern and " 745 "rop %x is not supported.\n", rop); 746 } else { 747 if (rop != 0x5 && rop != 0xc) { 748 /* Anything other than plain copies or inverse dest is not 749 * supported */ 750 qemu_log_mask(LOG_UNIMP, "sm501: rop mode %x is not " 751 "supported.\n", rop); 752 } 753 } 754 } 755 756 if ((s->twoD_source_base & 0x08000000) || 757 (s->twoD_destination_base & 0x08000000)) { 758 printf("%s: only local memory is supported.\n", __func__); 759 abort(); 760 } 761 762 switch (operation) { 763 case 0x00: /* copy area */ 764 #define COPY_AREA(_bpp, _pixel_type, rtl) { \ 765 int y, x, index_d, index_s; \ 766 for (y = 0; y < operation_height; y++) { \ 767 for (x = 0; x < operation_width; x++) { \ 768 _pixel_type val; \ 769 \ 770 if (rtl) { \ 771 index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \ 772 index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \ 773 } else { \ 774 index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \ 775 index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \ 776 } \ 777 if (rop_mode == 1 && rop == 5) { \ 778 /* Invert dest */ \ 779 val = ~*(_pixel_type *)&dst[index_d]; \ 780 } else { \ 781 val = *(_pixel_type *)&src[index_s]; \ 782 } \ 783 *(_pixel_type *)&dst[index_d] = val; \ 784 } \ 785 } \ 786 } 787 switch (format_flags) { 788 case 0: 789 COPY_AREA(1, uint8_t, rtl); 790 break; 791 case 1: 792 COPY_AREA(2, uint16_t, rtl); 793 break; 794 case 2: 795 COPY_AREA(4, uint32_t, rtl); 796 break; 797 } 798 break; 799 800 case 0x01: /* fill rectangle */ 801 #define FILL_RECT(_bpp, _pixel_type) { \ 802 int y, x; \ 803 for (y = 0; y < operation_height; y++) { \ 804 for (x = 0; x < operation_width; x++) { \ 805 int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \ 806 *(_pixel_type *)&dst[index] = (_pixel_type)color; \ 807 } \ 808 } \ 809 } 810 811 switch (format_flags) { 812 case 0: 813 FILL_RECT(1, uint8_t); 814 break; 815 case 1: 816 color = cpu_to_le16(color); 817 FILL_RECT(2, uint16_t); 818 break; 819 case 2: 820 color = cpu_to_le32(color); 821 FILL_RECT(4, uint32_t); 822 break; 823 } 824 break; 825 826 default: 827 printf("non-implemented SM501 2D operation. %d\n", operation); 828 abort(); 829 break; 830 } 831 832 if (dst_base >= get_fb_addr(s, crt) && 833 dst_base <= get_fb_addr(s, crt) + fb_len) { 834 int dst_len = MIN(fb_len, ((dst_y + operation_height - 1) * dst_width + 835 dst_x + operation_width) * (1 << format_flags)); 836 if (dst_len) { 837 memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len); 838 } 839 } 840 } 841 842 static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, 843 unsigned size) 844 { 845 SM501State *s = (SM501State *)opaque; 846 uint32_t ret = 0; 847 SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr); 848 849 switch (addr) { 850 case SM501_SYSTEM_CONTROL: 851 ret = s->system_control; 852 break; 853 case SM501_MISC_CONTROL: 854 ret = s->misc_control; 855 break; 856 case SM501_GPIO31_0_CONTROL: 857 ret = s->gpio_31_0_control; 858 break; 859 case SM501_GPIO63_32_CONTROL: 860 ret = s->gpio_63_32_control; 861 break; 862 case SM501_DEVICEID: 863 ret = 0x050100A0; 864 break; 865 case SM501_DRAM_CONTROL: 866 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; 867 break; 868 case SM501_ARBTRTN_CONTROL: 869 ret = s->arbitration_control; 870 break; 871 case SM501_COMMAND_LIST_STATUS: 872 ret = 0x00180002; /* FIFOs are empty, everything idle */ 873 break; 874 case SM501_IRQ_MASK: 875 ret = s->irq_mask; 876 break; 877 case SM501_MISC_TIMING: 878 /* TODO : simulate gate control */ 879 ret = s->misc_timing; 880 break; 881 case SM501_CURRENT_GATE: 882 /* TODO : simulate gate control */ 883 ret = 0x00021807; 884 break; 885 case SM501_CURRENT_CLOCK: 886 ret = 0x2A1A0A09; 887 break; 888 case SM501_POWER_MODE_CONTROL: 889 ret = s->power_mode_control; 890 break; 891 case SM501_ENDIAN_CONTROL: 892 ret = 0; /* Only default little endian mode is supported */ 893 break; 894 895 default: 896 printf("sm501 system config : not implemented register read." 897 " addr=%x\n", (int)addr); 898 abort(); 899 } 900 901 return ret; 902 } 903 904 static void sm501_system_config_write(void *opaque, hwaddr addr, 905 uint64_t value, unsigned size) 906 { 907 SM501State *s = (SM501State *)opaque; 908 SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", 909 (uint32_t)addr, (uint32_t)value); 910 911 switch (addr) { 912 case SM501_SYSTEM_CONTROL: 913 s->system_control &= 0x10DB0000; 914 s->system_control |= value & 0xEF00B8F7; 915 break; 916 case SM501_MISC_CONTROL: 917 s->misc_control &= 0xEF; 918 s->misc_control |= value & 0xFF7FFF10; 919 break; 920 case SM501_GPIO31_0_CONTROL: 921 s->gpio_31_0_control = value; 922 break; 923 case SM501_GPIO63_32_CONTROL: 924 s->gpio_63_32_control = value & 0xFF80FFFF; 925 break; 926 case SM501_DRAM_CONTROL: 927 s->local_mem_size_index = (value >> 13) & 0x7; 928 /* TODO : check validity of size change */ 929 s->dram_control &= 0x80000000; 930 s->dram_control |= value & 0x7FFFFFC3; 931 break; 932 case SM501_ARBTRTN_CONTROL: 933 s->arbitration_control = value & 0x37777777; 934 break; 935 case SM501_IRQ_MASK: 936 s->irq_mask = value & 0xFFDF3F5F; 937 break; 938 case SM501_MISC_TIMING: 939 s->misc_timing = value & 0xF31F1FFF; 940 break; 941 case SM501_POWER_MODE_0_GATE: 942 case SM501_POWER_MODE_1_GATE: 943 case SM501_POWER_MODE_0_CLOCK: 944 case SM501_POWER_MODE_1_CLOCK: 945 /* TODO : simulate gate & clock control */ 946 break; 947 case SM501_POWER_MODE_CONTROL: 948 s->power_mode_control = value & 0x00000003; 949 break; 950 case SM501_ENDIAN_CONTROL: 951 if (value & 0x00000001) { 952 printf("sm501 system config : big endian mode not implemented.\n"); 953 abort(); 954 } 955 break; 956 957 default: 958 printf("sm501 system config : not implemented register write." 959 " addr=%x, val=%x\n", (int)addr, (uint32_t)value); 960 abort(); 961 } 962 } 963 964 static const MemoryRegionOps sm501_system_config_ops = { 965 .read = sm501_system_config_read, 966 .write = sm501_system_config_write, 967 .valid = { 968 .min_access_size = 4, 969 .max_access_size = 4, 970 }, 971 .endianness = DEVICE_LITTLE_ENDIAN, 972 }; 973 974 static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) 975 { 976 SM501State *s = (SM501State *)opaque; 977 uint8_t ret = 0; 978 979 switch (addr) { 980 case SM501_I2C_BYTE_COUNT: 981 ret = s->i2c_byte_count; 982 break; 983 case SM501_I2C_STATUS: 984 ret = s->i2c_status; 985 break; 986 case SM501_I2C_SLAVE_ADDRESS: 987 ret = s->i2c_addr; 988 break; 989 case SM501_I2C_DATA ... SM501_I2C_DATA + 15: 990 ret = s->i2c_data[addr - SM501_I2C_DATA]; 991 break; 992 default: 993 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." 994 " addr=0x%" HWADDR_PRIx "\n", addr); 995 } 996 997 SM501_DPRINTF("sm501 i2c regs : read addr=%" HWADDR_PRIx " val=%x\n", 998 addr, ret); 999 return ret; 1000 } 1001 1002 static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value, 1003 unsigned size) 1004 { 1005 SM501State *s = (SM501State *)opaque; 1006 SM501_DPRINTF("sm501 i2c regs : write addr=%" HWADDR_PRIx 1007 " val=%" PRIx64 "\n", addr, value); 1008 1009 switch (addr) { 1010 case SM501_I2C_BYTE_COUNT: 1011 s->i2c_byte_count = value & 0xf; 1012 break; 1013 case SM501_I2C_CONTROL: 1014 if (value & SM501_I2C_CONTROL_ENABLE) { 1015 if (value & SM501_I2C_CONTROL_START) { 1016 int res = i2c_start_transfer(s->i2c_bus, 1017 s->i2c_addr >> 1, 1018 s->i2c_addr & 1); 1019 s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0); 1020 if (!res) { 1021 int i; 1022 SM501_DPRINTF("sm501 i2c : transferring %d bytes to 0x%x\n", 1023 s->i2c_byte_count + 1, s->i2c_addr >> 1); 1024 for (i = 0; i <= s->i2c_byte_count; i++) { 1025 res = i2c_send_recv(s->i2c_bus, &s->i2c_data[i], 1026 !(s->i2c_addr & 1)); 1027 if (res) { 1028 SM501_DPRINTF("sm501 i2c : transfer failed" 1029 " i=%d, res=%d\n", i, res); 1030 s->i2c_status |= SM501_I2C_STATUS_ERROR; 1031 return; 1032 } 1033 } 1034 if (i) { 1035 SM501_DPRINTF("sm501 i2c : transferred %d bytes\n", i); 1036 s->i2c_status = SM501_I2C_STATUS_COMPLETE; 1037 } 1038 } 1039 } else { 1040 SM501_DPRINTF("sm501 i2c : end transfer\n"); 1041 i2c_end_transfer(s->i2c_bus); 1042 s->i2c_status &= ~SM501_I2C_STATUS_ERROR; 1043 } 1044 } 1045 break; 1046 case SM501_I2C_RESET: 1047 if ((value & SM501_I2C_RESET_ERROR) == 0) { 1048 s->i2c_status &= ~SM501_I2C_STATUS_ERROR; 1049 } 1050 break; 1051 case SM501_I2C_SLAVE_ADDRESS: 1052 s->i2c_addr = value & 0xff; 1053 break; 1054 case SM501_I2C_DATA ... SM501_I2C_DATA + 15: 1055 s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff; 1056 break; 1057 default: 1058 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. " 1059 "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value); 1060 } 1061 } 1062 1063 static const MemoryRegionOps sm501_i2c_ops = { 1064 .read = sm501_i2c_read, 1065 .write = sm501_i2c_write, 1066 .valid = { 1067 .min_access_size = 1, 1068 .max_access_size = 1, 1069 }, 1070 .impl = { 1071 .min_access_size = 1, 1072 .max_access_size = 1, 1073 }, 1074 .endianness = DEVICE_LITTLE_ENDIAN, 1075 }; 1076 1077 static uint32_t sm501_palette_read(void *opaque, hwaddr addr) 1078 { 1079 SM501State *s = (SM501State *)opaque; 1080 SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); 1081 1082 /* TODO : consider BYTE/WORD access */ 1083 /* TODO : consider endian */ 1084 1085 assert(range_covers_byte(0, 0x400 * 3, addr)); 1086 return *(uint32_t *)&s->dc_palette[addr]; 1087 } 1088 1089 static void sm501_palette_write(void *opaque, hwaddr addr, 1090 uint32_t value) 1091 { 1092 SM501State *s = (SM501State *)opaque; 1093 SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", 1094 (int)addr, value); 1095 1096 /* TODO : consider BYTE/WORD access */ 1097 /* TODO : consider endian */ 1098 1099 assert(range_covers_byte(0, 0x400 * 3, addr)); 1100 *(uint32_t *)&s->dc_palette[addr] = value; 1101 s->do_full_update = true; 1102 } 1103 1104 static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, 1105 unsigned size) 1106 { 1107 SM501State *s = (SM501State *)opaque; 1108 uint32_t ret = 0; 1109 SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr); 1110 1111 switch (addr) { 1112 1113 case SM501_DC_PANEL_CONTROL: 1114 ret = s->dc_panel_control; 1115 break; 1116 case SM501_DC_PANEL_PANNING_CONTROL: 1117 ret = s->dc_panel_panning_control; 1118 break; 1119 case SM501_DC_PANEL_COLOR_KEY: 1120 /* Not implemented yet */ 1121 break; 1122 case SM501_DC_PANEL_FB_ADDR: 1123 ret = s->dc_panel_fb_addr; 1124 break; 1125 case SM501_DC_PANEL_FB_OFFSET: 1126 ret = s->dc_panel_fb_offset; 1127 break; 1128 case SM501_DC_PANEL_FB_WIDTH: 1129 ret = s->dc_panel_fb_width; 1130 break; 1131 case SM501_DC_PANEL_FB_HEIGHT: 1132 ret = s->dc_panel_fb_height; 1133 break; 1134 case SM501_DC_PANEL_TL_LOC: 1135 ret = s->dc_panel_tl_location; 1136 break; 1137 case SM501_DC_PANEL_BR_LOC: 1138 ret = s->dc_panel_br_location; 1139 break; 1140 1141 case SM501_DC_PANEL_H_TOT: 1142 ret = s->dc_panel_h_total; 1143 break; 1144 case SM501_DC_PANEL_H_SYNC: 1145 ret = s->dc_panel_h_sync; 1146 break; 1147 case SM501_DC_PANEL_V_TOT: 1148 ret = s->dc_panel_v_total; 1149 break; 1150 case SM501_DC_PANEL_V_SYNC: 1151 ret = s->dc_panel_v_sync; 1152 break; 1153 1154 case SM501_DC_PANEL_HWC_ADDR: 1155 ret = s->dc_panel_hwc_addr; 1156 break; 1157 case SM501_DC_PANEL_HWC_LOC: 1158 ret = s->dc_panel_hwc_location; 1159 break; 1160 case SM501_DC_PANEL_HWC_COLOR_1_2: 1161 ret = s->dc_panel_hwc_color_1_2; 1162 break; 1163 case SM501_DC_PANEL_HWC_COLOR_3: 1164 ret = s->dc_panel_hwc_color_3; 1165 break; 1166 1167 case SM501_DC_VIDEO_CONTROL: 1168 ret = s->dc_video_control; 1169 break; 1170 1171 case SM501_DC_CRT_CONTROL: 1172 ret = s->dc_crt_control; 1173 break; 1174 case SM501_DC_CRT_FB_ADDR: 1175 ret = s->dc_crt_fb_addr; 1176 break; 1177 case SM501_DC_CRT_FB_OFFSET: 1178 ret = s->dc_crt_fb_offset; 1179 break; 1180 case SM501_DC_CRT_H_TOT: 1181 ret = s->dc_crt_h_total; 1182 break; 1183 case SM501_DC_CRT_H_SYNC: 1184 ret = s->dc_crt_h_sync; 1185 break; 1186 case SM501_DC_CRT_V_TOT: 1187 ret = s->dc_crt_v_total; 1188 break; 1189 case SM501_DC_CRT_V_SYNC: 1190 ret = s->dc_crt_v_sync; 1191 break; 1192 1193 case SM501_DC_CRT_HWC_ADDR: 1194 ret = s->dc_crt_hwc_addr; 1195 break; 1196 case SM501_DC_CRT_HWC_LOC: 1197 ret = s->dc_crt_hwc_location; 1198 break; 1199 case SM501_DC_CRT_HWC_COLOR_1_2: 1200 ret = s->dc_crt_hwc_color_1_2; 1201 break; 1202 case SM501_DC_CRT_HWC_COLOR_3: 1203 ret = s->dc_crt_hwc_color_3; 1204 break; 1205 1206 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: 1207 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); 1208 break; 1209 1210 default: 1211 printf("sm501 disp ctrl : not implemented register read." 1212 " addr=%x\n", (int)addr); 1213 abort(); 1214 } 1215 1216 return ret; 1217 } 1218 1219 static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, 1220 uint64_t value, unsigned size) 1221 { 1222 SM501State *s = (SM501State *)opaque; 1223 SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n", 1224 (unsigned)addr, (unsigned)value); 1225 1226 switch (addr) { 1227 case SM501_DC_PANEL_CONTROL: 1228 s->dc_panel_control = value & 0x0FFF73FF; 1229 break; 1230 case SM501_DC_PANEL_PANNING_CONTROL: 1231 s->dc_panel_panning_control = value & 0xFF3FFF3F; 1232 break; 1233 case SM501_DC_PANEL_COLOR_KEY: 1234 /* Not implemented yet */ 1235 break; 1236 case SM501_DC_PANEL_FB_ADDR: 1237 s->dc_panel_fb_addr = value & 0x8FFFFFF0; 1238 if (value & 0x8000000) { 1239 qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n"); 1240 } 1241 s->do_full_update = true; 1242 break; 1243 case SM501_DC_PANEL_FB_OFFSET: 1244 s->dc_panel_fb_offset = value & 0x3FF03FF0; 1245 break; 1246 case SM501_DC_PANEL_FB_WIDTH: 1247 s->dc_panel_fb_width = value & 0x0FFF0FFF; 1248 break; 1249 case SM501_DC_PANEL_FB_HEIGHT: 1250 s->dc_panel_fb_height = value & 0x0FFF0FFF; 1251 break; 1252 case SM501_DC_PANEL_TL_LOC: 1253 s->dc_panel_tl_location = value & 0x07FF07FF; 1254 break; 1255 case SM501_DC_PANEL_BR_LOC: 1256 s->dc_panel_br_location = value & 0x07FF07FF; 1257 break; 1258 1259 case SM501_DC_PANEL_H_TOT: 1260 s->dc_panel_h_total = value & 0x0FFF0FFF; 1261 break; 1262 case SM501_DC_PANEL_H_SYNC: 1263 s->dc_panel_h_sync = value & 0x00FF0FFF; 1264 break; 1265 case SM501_DC_PANEL_V_TOT: 1266 s->dc_panel_v_total = value & 0x0FFF0FFF; 1267 break; 1268 case SM501_DC_PANEL_V_SYNC: 1269 s->dc_panel_v_sync = value & 0x003F0FFF; 1270 break; 1271 1272 case SM501_DC_PANEL_HWC_ADDR: 1273 value &= 0x8FFFFFF0; 1274 if (value != s->dc_panel_hwc_addr) { 1275 hwc_invalidate(s, 0); 1276 s->dc_panel_hwc_addr = value; 1277 } 1278 break; 1279 case SM501_DC_PANEL_HWC_LOC: 1280 value &= 0x0FFF0FFF; 1281 if (value != s->dc_panel_hwc_location) { 1282 hwc_invalidate(s, 0); 1283 s->dc_panel_hwc_location = value; 1284 } 1285 break; 1286 case SM501_DC_PANEL_HWC_COLOR_1_2: 1287 s->dc_panel_hwc_color_1_2 = value; 1288 break; 1289 case SM501_DC_PANEL_HWC_COLOR_3: 1290 s->dc_panel_hwc_color_3 = value & 0x0000FFFF; 1291 break; 1292 1293 case SM501_DC_VIDEO_CONTROL: 1294 s->dc_video_control = value & 0x00037FFF; 1295 break; 1296 1297 case SM501_DC_CRT_CONTROL: 1298 s->dc_crt_control = value & 0x0003FFFF; 1299 break; 1300 case SM501_DC_CRT_FB_ADDR: 1301 s->dc_crt_fb_addr = value & 0x8FFFFFF0; 1302 if (value & 0x8000000) { 1303 qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n"); 1304 } 1305 s->do_full_update = true; 1306 break; 1307 case SM501_DC_CRT_FB_OFFSET: 1308 s->dc_crt_fb_offset = value & 0x3FF03FF0; 1309 break; 1310 case SM501_DC_CRT_H_TOT: 1311 s->dc_crt_h_total = value & 0x0FFF0FFF; 1312 break; 1313 case SM501_DC_CRT_H_SYNC: 1314 s->dc_crt_h_sync = value & 0x00FF0FFF; 1315 break; 1316 case SM501_DC_CRT_V_TOT: 1317 s->dc_crt_v_total = value & 0x0FFF0FFF; 1318 break; 1319 case SM501_DC_CRT_V_SYNC: 1320 s->dc_crt_v_sync = value & 0x003F0FFF; 1321 break; 1322 1323 case SM501_DC_CRT_HWC_ADDR: 1324 value &= 0x8FFFFFF0; 1325 if (value != s->dc_crt_hwc_addr) { 1326 hwc_invalidate(s, 1); 1327 s->dc_crt_hwc_addr = value; 1328 } 1329 break; 1330 case SM501_DC_CRT_HWC_LOC: 1331 value &= 0x0FFF0FFF; 1332 if (value != s->dc_crt_hwc_location) { 1333 hwc_invalidate(s, 1); 1334 s->dc_crt_hwc_location = value; 1335 } 1336 break; 1337 case SM501_DC_CRT_HWC_COLOR_1_2: 1338 s->dc_crt_hwc_color_1_2 = value; 1339 break; 1340 case SM501_DC_CRT_HWC_COLOR_3: 1341 s->dc_crt_hwc_color_3 = value & 0x0000FFFF; 1342 break; 1343 1344 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: 1345 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); 1346 break; 1347 1348 default: 1349 printf("sm501 disp ctrl : not implemented register write." 1350 " addr=%x, val=%x\n", (int)addr, (unsigned)value); 1351 abort(); 1352 } 1353 } 1354 1355 static const MemoryRegionOps sm501_disp_ctrl_ops = { 1356 .read = sm501_disp_ctrl_read, 1357 .write = sm501_disp_ctrl_write, 1358 .valid = { 1359 .min_access_size = 4, 1360 .max_access_size = 4, 1361 }, 1362 .endianness = DEVICE_LITTLE_ENDIAN, 1363 }; 1364 1365 static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, 1366 unsigned size) 1367 { 1368 SM501State *s = (SM501State *)opaque; 1369 uint32_t ret = 0; 1370 SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr); 1371 1372 switch (addr) { 1373 case SM501_2D_SOURCE: 1374 ret = s->twoD_source; 1375 break; 1376 case SM501_2D_DESTINATION: 1377 ret = s->twoD_destination; 1378 break; 1379 case SM501_2D_DIMENSION: 1380 ret = s->twoD_dimension; 1381 break; 1382 case SM501_2D_CONTROL: 1383 ret = s->twoD_control; 1384 break; 1385 case SM501_2D_PITCH: 1386 ret = s->twoD_pitch; 1387 break; 1388 case SM501_2D_FOREGROUND: 1389 ret = s->twoD_foreground; 1390 break; 1391 case SM501_2D_BACKGROUND: 1392 ret = s->twoD_background; 1393 break; 1394 case SM501_2D_STRETCH: 1395 ret = s->twoD_stretch; 1396 break; 1397 case SM501_2D_COLOR_COMPARE: 1398 ret = s->twoD_color_compare; 1399 break; 1400 case SM501_2D_COLOR_COMPARE_MASK: 1401 ret = s->twoD_color_compare_mask; 1402 break; 1403 case SM501_2D_MASK: 1404 ret = s->twoD_mask; 1405 break; 1406 case SM501_2D_CLIP_TL: 1407 ret = s->twoD_clip_tl; 1408 break; 1409 case SM501_2D_CLIP_BR: 1410 ret = s->twoD_clip_br; 1411 break; 1412 case SM501_2D_MONO_PATTERN_LOW: 1413 ret = s->twoD_mono_pattern_low; 1414 break; 1415 case SM501_2D_MONO_PATTERN_HIGH: 1416 ret = s->twoD_mono_pattern_high; 1417 break; 1418 case SM501_2D_WINDOW_WIDTH: 1419 ret = s->twoD_window_width; 1420 break; 1421 case SM501_2D_SOURCE_BASE: 1422 ret = s->twoD_source_base; 1423 break; 1424 case SM501_2D_DESTINATION_BASE: 1425 ret = s->twoD_destination_base; 1426 break; 1427 case SM501_2D_ALPHA: 1428 ret = s->twoD_alpha; 1429 break; 1430 case SM501_2D_WRAP: 1431 ret = s->twoD_wrap; 1432 break; 1433 case SM501_2D_STATUS: 1434 ret = 0; /* Should return interrupt status */ 1435 break; 1436 default: 1437 printf("sm501 disp ctrl : not implemented register read." 1438 " addr=%x\n", (int)addr); 1439 abort(); 1440 } 1441 1442 return ret; 1443 } 1444 1445 static void sm501_2d_engine_write(void *opaque, hwaddr addr, 1446 uint64_t value, unsigned size) 1447 { 1448 SM501State *s = (SM501State *)opaque; 1449 SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n", 1450 (unsigned)addr, (unsigned)value); 1451 1452 switch (addr) { 1453 case SM501_2D_SOURCE: 1454 s->twoD_source = value; 1455 break; 1456 case SM501_2D_DESTINATION: 1457 s->twoD_destination = value; 1458 break; 1459 case SM501_2D_DIMENSION: 1460 s->twoD_dimension = value; 1461 break; 1462 case SM501_2D_CONTROL: 1463 s->twoD_control = value; 1464 1465 /* do 2d operation if start flag is set. */ 1466 if (value & 0x80000000) { 1467 sm501_2d_operation(s); 1468 s->twoD_control &= ~0x80000000; /* start flag down */ 1469 } 1470 1471 break; 1472 case SM501_2D_PITCH: 1473 s->twoD_pitch = value; 1474 break; 1475 case SM501_2D_FOREGROUND: 1476 s->twoD_foreground = value; 1477 break; 1478 case SM501_2D_BACKGROUND: 1479 s->twoD_background = value; 1480 break; 1481 case SM501_2D_STRETCH: 1482 s->twoD_stretch = value; 1483 break; 1484 case SM501_2D_COLOR_COMPARE: 1485 s->twoD_color_compare = value; 1486 break; 1487 case SM501_2D_COLOR_COMPARE_MASK: 1488 s->twoD_color_compare_mask = value; 1489 break; 1490 case SM501_2D_MASK: 1491 s->twoD_mask = value; 1492 break; 1493 case SM501_2D_CLIP_TL: 1494 s->twoD_clip_tl = value; 1495 break; 1496 case SM501_2D_CLIP_BR: 1497 s->twoD_clip_br = value; 1498 break; 1499 case SM501_2D_MONO_PATTERN_LOW: 1500 s->twoD_mono_pattern_low = value; 1501 break; 1502 case SM501_2D_MONO_PATTERN_HIGH: 1503 s->twoD_mono_pattern_high = value; 1504 break; 1505 case SM501_2D_WINDOW_WIDTH: 1506 s->twoD_window_width = value; 1507 break; 1508 case SM501_2D_SOURCE_BASE: 1509 s->twoD_source_base = value; 1510 break; 1511 case SM501_2D_DESTINATION_BASE: 1512 s->twoD_destination_base = value; 1513 break; 1514 case SM501_2D_ALPHA: 1515 s->twoD_alpha = value; 1516 break; 1517 case SM501_2D_WRAP: 1518 s->twoD_wrap = value; 1519 break; 1520 case SM501_2D_STATUS: 1521 /* ignored, writing 0 should clear interrupt status */ 1522 break; 1523 default: 1524 printf("sm501 2d engine : not implemented register write." 1525 " addr=%x, val=%x\n", (int)addr, (unsigned)value); 1526 abort(); 1527 } 1528 } 1529 1530 static const MemoryRegionOps sm501_2d_engine_ops = { 1531 .read = sm501_2d_engine_read, 1532 .write = sm501_2d_engine_write, 1533 .valid = { 1534 .min_access_size = 4, 1535 .max_access_size = 4, 1536 }, 1537 .endianness = DEVICE_LITTLE_ENDIAN, 1538 }; 1539 1540 /* draw line functions for all console modes */ 1541 1542 typedef void draw_line_func(uint8_t *d, const uint8_t *s, 1543 int width, const uint32_t *pal); 1544 1545 typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s, 1546 int width, const uint8_t *palette, 1547 int c_x, int c_y); 1548 1549 #define DEPTH 8 1550 #include "sm501_template.h" 1551 1552 #define DEPTH 15 1553 #include "sm501_template.h" 1554 1555 #define BGR_FORMAT 1556 #define DEPTH 15 1557 #include "sm501_template.h" 1558 1559 #define DEPTH 16 1560 #include "sm501_template.h" 1561 1562 #define BGR_FORMAT 1563 #define DEPTH 16 1564 #include "sm501_template.h" 1565 1566 #define DEPTH 32 1567 #include "sm501_template.h" 1568 1569 #define BGR_FORMAT 1570 #define DEPTH 32 1571 #include "sm501_template.h" 1572 1573 static draw_line_func *draw_line8_funcs[] = { 1574 draw_line8_8, 1575 draw_line8_15, 1576 draw_line8_16, 1577 draw_line8_32, 1578 draw_line8_32bgr, 1579 draw_line8_15bgr, 1580 draw_line8_16bgr, 1581 }; 1582 1583 static draw_line_func *draw_line16_funcs[] = { 1584 draw_line16_8, 1585 draw_line16_15, 1586 draw_line16_16, 1587 draw_line16_32, 1588 draw_line16_32bgr, 1589 draw_line16_15bgr, 1590 draw_line16_16bgr, 1591 }; 1592 1593 static draw_line_func *draw_line32_funcs[] = { 1594 draw_line32_8, 1595 draw_line32_15, 1596 draw_line32_16, 1597 draw_line32_32, 1598 draw_line32_32bgr, 1599 draw_line32_15bgr, 1600 draw_line32_16bgr, 1601 }; 1602 1603 static draw_hwc_line_func *draw_hwc_line_funcs[] = { 1604 draw_hwc_line_8, 1605 draw_hwc_line_15, 1606 draw_hwc_line_16, 1607 draw_hwc_line_32, 1608 draw_hwc_line_32bgr, 1609 draw_hwc_line_15bgr, 1610 draw_hwc_line_16bgr, 1611 }; 1612 1613 static inline int get_depth_index(DisplaySurface *surface) 1614 { 1615 switch (surface_bits_per_pixel(surface)) { 1616 default: 1617 case 8: 1618 return 0; 1619 case 15: 1620 return 1; 1621 case 16: 1622 return 2; 1623 case 32: 1624 if (is_surface_bgr(surface)) { 1625 return 4; 1626 } else { 1627 return 3; 1628 } 1629 } 1630 } 1631 1632 static void sm501_update_display(void *opaque) 1633 { 1634 SM501State *s = (SM501State *)opaque; 1635 DisplaySurface *surface = qemu_console_surface(s->con); 1636 DirtyBitmapSnapshot *snap; 1637 int y, c_x = 0, c_y = 0; 1638 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; 1639 int width = get_width(s, crt); 1640 int height = get_height(s, crt); 1641 int src_bpp = get_bpp(s, crt); 1642 int dst_bpp = surface_bytes_per_pixel(surface); 1643 int dst_depth_index = get_depth_index(surface); 1644 draw_line_func *draw_line = NULL; 1645 draw_hwc_line_func *draw_hwc_line = NULL; 1646 int full_update = 0; 1647 int y_start = -1; 1648 ram_addr_t offset; 1649 uint32_t *palette; 1650 uint8_t hwc_palette[3 * 3]; 1651 uint8_t *hwc_src = NULL; 1652 1653 if (!((crt ? s->dc_crt_control : s->dc_panel_control) 1654 & SM501_DC_CRT_CONTROL_ENABLE)) { 1655 return; 1656 } 1657 1658 palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - 1659 SM501_DC_PANEL_PALETTE] 1660 : &s->dc_palette[0]); 1661 1662 /* choose draw_line function */ 1663 switch (src_bpp) { 1664 case 1: 1665 draw_line = draw_line8_funcs[dst_depth_index]; 1666 break; 1667 case 2: 1668 draw_line = draw_line16_funcs[dst_depth_index]; 1669 break; 1670 case 4: 1671 draw_line = draw_line32_funcs[dst_depth_index]; 1672 break; 1673 default: 1674 printf("sm501 update display : invalid control register value.\n"); 1675 abort(); 1676 break; 1677 } 1678 1679 /* set up to draw hardware cursor */ 1680 if (is_hwc_enabled(s, crt)) { 1681 /* choose cursor draw line function */ 1682 draw_hwc_line = draw_hwc_line_funcs[dst_depth_index]; 1683 hwc_src = get_hwc_address(s, crt); 1684 c_x = get_hwc_x(s, crt); 1685 c_y = get_hwc_y(s, crt); 1686 get_hwc_palette(s, crt, hwc_palette); 1687 } 1688 1689 /* adjust console size */ 1690 if (s->last_width != width || s->last_height != height) { 1691 qemu_console_resize(s->con, width, height); 1692 surface = qemu_console_surface(s->con); 1693 s->last_width = width; 1694 s->last_height = height; 1695 full_update = 1; 1696 } 1697 1698 /* someone else requested a full update */ 1699 if (s->do_full_update) { 1700 s->do_full_update = false; 1701 full_update = 1; 1702 } 1703 1704 /* draw each line according to conditions */ 1705 offset = get_fb_addr(s, crt); 1706 snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region, 1707 offset, width * height * src_bpp, DIRTY_MEMORY_VGA); 1708 for (y = 0; y < height; y++, offset += width * src_bpp) { 1709 int update, update_hwc; 1710 1711 /* check if hardware cursor is enabled and we're within its range */ 1712 update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT; 1713 update = full_update || update_hwc; 1714 /* check dirty flags for each line */ 1715 update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap, 1716 offset, width * src_bpp); 1717 1718 /* draw line and change status */ 1719 if (update) { 1720 uint8_t *d = surface_data(surface); 1721 d += y * width * dst_bpp; 1722 1723 /* draw graphics layer */ 1724 draw_line(d, s->local_mem + offset, width, palette); 1725 1726 /* draw hardware cursor */ 1727 if (update_hwc) { 1728 draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y); 1729 } 1730 1731 if (y_start < 0) { 1732 y_start = y; 1733 } 1734 } else { 1735 if (y_start >= 0) { 1736 /* flush to display */ 1737 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 1738 y_start = -1; 1739 } 1740 } 1741 } 1742 g_free(snap); 1743 1744 /* complete flush to display */ 1745 if (y_start >= 0) { 1746 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 1747 } 1748 } 1749 1750 static const GraphicHwOps sm501_ops = { 1751 .gfx_update = sm501_update_display, 1752 }; 1753 1754 static void sm501_reset(SM501State *s) 1755 { 1756 s->system_control = 0x00100000; /* 2D engine FIFO empty */ 1757 /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed 1758 * to be determined at reset by GPIO lines which set config bits. 1759 * We hardwire them: 1760 * SH = 0 : Hitachi Ready Polarity == Active Low 1761 * CDR = 0 : do not reset clock divider 1762 * TEST = 0 : Normal mode (not testing the silicon) 1763 * BUS = 0 : Hitachi SH3/SH4 1764 */ 1765 s->misc_control = SM501_MISC_DAC_POWER; 1766 s->gpio_31_0_control = 0; 1767 s->gpio_63_32_control = 0; 1768 s->dram_control = 0; 1769 s->arbitration_control = 0x05146732; 1770 s->irq_mask = 0; 1771 s->misc_timing = 0; 1772 s->power_mode_control = 0; 1773 s->i2c_byte_count = 0; 1774 s->i2c_status = 0; 1775 s->i2c_addr = 0; 1776 memset(s->i2c_data, 0, 16); 1777 s->dc_panel_control = 0x00010000; /* FIFO level 3 */ 1778 s->dc_video_control = 0; 1779 s->dc_crt_control = 0x00010000; 1780 s->twoD_source = 0; 1781 s->twoD_destination = 0; 1782 s->twoD_dimension = 0; 1783 s->twoD_control = 0; 1784 s->twoD_pitch = 0; 1785 s->twoD_foreground = 0; 1786 s->twoD_background = 0; 1787 s->twoD_stretch = 0; 1788 s->twoD_color_compare = 0; 1789 s->twoD_color_compare_mask = 0; 1790 s->twoD_mask = 0; 1791 s->twoD_clip_tl = 0; 1792 s->twoD_clip_br = 0; 1793 s->twoD_mono_pattern_low = 0; 1794 s->twoD_mono_pattern_high = 0; 1795 s->twoD_window_width = 0; 1796 s->twoD_source_base = 0; 1797 s->twoD_destination_base = 0; 1798 s->twoD_alpha = 0; 1799 s->twoD_wrap = 0; 1800 } 1801 1802 static void sm501_init(SM501State *s, DeviceState *dev, 1803 uint32_t local_mem_bytes) 1804 { 1805 s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); 1806 SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s), 1807 s->local_mem_size_index); 1808 1809 /* local memory */ 1810 memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local", 1811 get_local_mem_size(s), &error_fatal); 1812 memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); 1813 s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); 1814 1815 /* i2c */ 1816 s->i2c_bus = i2c_init_bus(dev, "sm501.i2c"); 1817 /* ddc */ 1818 I2CDDCState *ddc = I2CDDC(qdev_create(BUS(s->i2c_bus), TYPE_I2CDDC)); 1819 i2c_set_slave_address(I2C_SLAVE(ddc), 0x50); 1820 1821 /* mmio */ 1822 memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE); 1823 memory_region_init_io(&s->system_config_region, OBJECT(dev), 1824 &sm501_system_config_ops, s, 1825 "sm501-system-config", 0x6c); 1826 memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, 1827 &s->system_config_region); 1828 memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s, 1829 "sm501-i2c", 0x14); 1830 memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region); 1831 memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), 1832 &sm501_disp_ctrl_ops, s, 1833 "sm501-disp-ctrl", 0x1000); 1834 memory_region_add_subregion(&s->mmio_region, SM501_DC, 1835 &s->disp_ctrl_region); 1836 memory_region_init_io(&s->twoD_engine_region, OBJECT(dev), 1837 &sm501_2d_engine_ops, s, 1838 "sm501-2d-engine", 0x54); 1839 memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE, 1840 &s->twoD_engine_region); 1841 1842 /* create qemu graphic console */ 1843 s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s); 1844 } 1845 1846 static const VMStateDescription vmstate_sm501_state = { 1847 .name = "sm501-state", 1848 .version_id = 1, 1849 .minimum_version_id = 1, 1850 .fields = (VMStateField[]) { 1851 VMSTATE_UINT32(local_mem_size_index, SM501State), 1852 VMSTATE_UINT32(system_control, SM501State), 1853 VMSTATE_UINT32(misc_control, SM501State), 1854 VMSTATE_UINT32(gpio_31_0_control, SM501State), 1855 VMSTATE_UINT32(gpio_63_32_control, SM501State), 1856 VMSTATE_UINT32(dram_control, SM501State), 1857 VMSTATE_UINT32(arbitration_control, SM501State), 1858 VMSTATE_UINT32(irq_mask, SM501State), 1859 VMSTATE_UINT32(misc_timing, SM501State), 1860 VMSTATE_UINT32(power_mode_control, SM501State), 1861 VMSTATE_UINT32(uart0_ier, SM501State), 1862 VMSTATE_UINT32(uart0_lcr, SM501State), 1863 VMSTATE_UINT32(uart0_mcr, SM501State), 1864 VMSTATE_UINT32(uart0_scr, SM501State), 1865 VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES), 1866 VMSTATE_UINT32(dc_panel_control, SM501State), 1867 VMSTATE_UINT32(dc_panel_panning_control, SM501State), 1868 VMSTATE_UINT32(dc_panel_fb_addr, SM501State), 1869 VMSTATE_UINT32(dc_panel_fb_offset, SM501State), 1870 VMSTATE_UINT32(dc_panel_fb_width, SM501State), 1871 VMSTATE_UINT32(dc_panel_fb_height, SM501State), 1872 VMSTATE_UINT32(dc_panel_tl_location, SM501State), 1873 VMSTATE_UINT32(dc_panel_br_location, SM501State), 1874 VMSTATE_UINT32(dc_panel_h_total, SM501State), 1875 VMSTATE_UINT32(dc_panel_h_sync, SM501State), 1876 VMSTATE_UINT32(dc_panel_v_total, SM501State), 1877 VMSTATE_UINT32(dc_panel_v_sync, SM501State), 1878 VMSTATE_UINT32(dc_panel_hwc_addr, SM501State), 1879 VMSTATE_UINT32(dc_panel_hwc_location, SM501State), 1880 VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State), 1881 VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State), 1882 VMSTATE_UINT32(dc_video_control, SM501State), 1883 VMSTATE_UINT32(dc_crt_control, SM501State), 1884 VMSTATE_UINT32(dc_crt_fb_addr, SM501State), 1885 VMSTATE_UINT32(dc_crt_fb_offset, SM501State), 1886 VMSTATE_UINT32(dc_crt_h_total, SM501State), 1887 VMSTATE_UINT32(dc_crt_h_sync, SM501State), 1888 VMSTATE_UINT32(dc_crt_v_total, SM501State), 1889 VMSTATE_UINT32(dc_crt_v_sync, SM501State), 1890 VMSTATE_UINT32(dc_crt_hwc_addr, SM501State), 1891 VMSTATE_UINT32(dc_crt_hwc_location, SM501State), 1892 VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State), 1893 VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State), 1894 VMSTATE_UINT32(twoD_source, SM501State), 1895 VMSTATE_UINT32(twoD_destination, SM501State), 1896 VMSTATE_UINT32(twoD_dimension, SM501State), 1897 VMSTATE_UINT32(twoD_control, SM501State), 1898 VMSTATE_UINT32(twoD_pitch, SM501State), 1899 VMSTATE_UINT32(twoD_foreground, SM501State), 1900 VMSTATE_UINT32(twoD_background, SM501State), 1901 VMSTATE_UINT32(twoD_stretch, SM501State), 1902 VMSTATE_UINT32(twoD_color_compare, SM501State), 1903 VMSTATE_UINT32(twoD_color_compare_mask, SM501State), 1904 VMSTATE_UINT32(twoD_mask, SM501State), 1905 VMSTATE_UINT32(twoD_clip_tl, SM501State), 1906 VMSTATE_UINT32(twoD_clip_br, SM501State), 1907 VMSTATE_UINT32(twoD_mono_pattern_low, SM501State), 1908 VMSTATE_UINT32(twoD_mono_pattern_high, SM501State), 1909 VMSTATE_UINT32(twoD_window_width, SM501State), 1910 VMSTATE_UINT32(twoD_source_base, SM501State), 1911 VMSTATE_UINT32(twoD_destination_base, SM501State), 1912 VMSTATE_UINT32(twoD_alpha, SM501State), 1913 VMSTATE_UINT32(twoD_wrap, SM501State), 1914 /* Added in version 2 */ 1915 VMSTATE_UINT8(i2c_byte_count, SM501State), 1916 VMSTATE_UINT8(i2c_status, SM501State), 1917 VMSTATE_UINT8(i2c_addr, SM501State), 1918 VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16), 1919 VMSTATE_END_OF_LIST() 1920 } 1921 }; 1922 1923 #define TYPE_SYSBUS_SM501 "sysbus-sm501" 1924 #define SYSBUS_SM501(obj) \ 1925 OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501) 1926 1927 typedef struct { 1928 /*< private >*/ 1929 SysBusDevice parent_obj; 1930 /*< public >*/ 1931 SM501State state; 1932 uint32_t vram_size; 1933 uint32_t base; 1934 void *chr_state; 1935 } SM501SysBusState; 1936 1937 static void sm501_realize_sysbus(DeviceState *dev, Error **errp) 1938 { 1939 SM501SysBusState *s = SYSBUS_SM501(dev); 1940 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1941 DeviceState *usb_dev; 1942 1943 sm501_init(&s->state, dev, s->vram_size); 1944 if (get_local_mem_size(&s->state) != s->vram_size) { 1945 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, 1946 get_local_mem_size(&s->state)); 1947 return; 1948 } 1949 sysbus_init_mmio(sbd, &s->state.local_mem_region); 1950 sysbus_init_mmio(sbd, &s->state.mmio_region); 1951 1952 /* bridge to usb host emulation module */ 1953 usb_dev = qdev_create(NULL, "sysbus-ohci"); 1954 qdev_prop_set_uint32(usb_dev, "num-ports", 2); 1955 qdev_prop_set_uint64(usb_dev, "dma-offset", s->base); 1956 qdev_init_nofail(usb_dev); 1957 memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, 1958 sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0)); 1959 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev)); 1960 1961 /* bridge to serial emulation module */ 1962 if (s->chr_state) { 1963 serial_mm_init(&s->state.mmio_region, SM501_UART0, 2, 1964 NULL, /* TODO : chain irq to IRL */ 1965 115200, s->chr_state, DEVICE_LITTLE_ENDIAN); 1966 } 1967 } 1968 1969 static Property sm501_sysbus_properties[] = { 1970 DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), 1971 DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0), 1972 DEFINE_PROP_PTR("chr-state", SM501SysBusState, chr_state), 1973 DEFINE_PROP_END_OF_LIST(), 1974 }; 1975 1976 static void sm501_reset_sysbus(DeviceState *dev) 1977 { 1978 SM501SysBusState *s = SYSBUS_SM501(dev); 1979 sm501_reset(&s->state); 1980 } 1981 1982 static const VMStateDescription vmstate_sm501_sysbus = { 1983 .name = TYPE_SYSBUS_SM501, 1984 .version_id = 2, 1985 .minimum_version_id = 2, 1986 .fields = (VMStateField[]) { 1987 VMSTATE_STRUCT(state, SM501SysBusState, 1, 1988 vmstate_sm501_state, SM501State), 1989 VMSTATE_END_OF_LIST() 1990 } 1991 }; 1992 1993 static void sm501_sysbus_class_init(ObjectClass *klass, void *data) 1994 { 1995 DeviceClass *dc = DEVICE_CLASS(klass); 1996 1997 dc->realize = sm501_realize_sysbus; 1998 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1999 dc->desc = "SM501 Multimedia Companion"; 2000 dc->props = sm501_sysbus_properties; 2001 dc->reset = sm501_reset_sysbus; 2002 dc->vmsd = &vmstate_sm501_sysbus; 2003 /* Note: pointer property "chr-state" may remain null, thus 2004 * no need for dc->user_creatable = false; 2005 */ 2006 } 2007 2008 static const TypeInfo sm501_sysbus_info = { 2009 .name = TYPE_SYSBUS_SM501, 2010 .parent = TYPE_SYS_BUS_DEVICE, 2011 .instance_size = sizeof(SM501SysBusState), 2012 .class_init = sm501_sysbus_class_init, 2013 }; 2014 2015 #define TYPE_PCI_SM501 "sm501" 2016 #define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501) 2017 2018 typedef struct { 2019 /*< private >*/ 2020 PCIDevice parent_obj; 2021 /*< public >*/ 2022 SM501State state; 2023 uint32_t vram_size; 2024 } SM501PCIState; 2025 2026 static void sm501_realize_pci(PCIDevice *dev, Error **errp) 2027 { 2028 SM501PCIState *s = PCI_SM501(dev); 2029 2030 sm501_init(&s->state, DEVICE(dev), s->vram_size); 2031 if (get_local_mem_size(&s->state) != s->vram_size) { 2032 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, 2033 get_local_mem_size(&s->state)); 2034 return; 2035 } 2036 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, 2037 &s->state.local_mem_region); 2038 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, 2039 &s->state.mmio_region); 2040 } 2041 2042 static Property sm501_pci_properties[] = { 2043 DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), 2044 DEFINE_PROP_END_OF_LIST(), 2045 }; 2046 2047 static void sm501_reset_pci(DeviceState *dev) 2048 { 2049 SM501PCIState *s = PCI_SM501(dev); 2050 sm501_reset(&s->state); 2051 /* Bits 2:0 of misc_control register is 001 for PCI */ 2052 s->state.misc_control |= 1; 2053 } 2054 2055 static const VMStateDescription vmstate_sm501_pci = { 2056 .name = TYPE_PCI_SM501, 2057 .version_id = 2, 2058 .minimum_version_id = 2, 2059 .fields = (VMStateField[]) { 2060 VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState), 2061 VMSTATE_STRUCT(state, SM501PCIState, 1, 2062 vmstate_sm501_state, SM501State), 2063 VMSTATE_END_OF_LIST() 2064 } 2065 }; 2066 2067 static void sm501_pci_class_init(ObjectClass *klass, void *data) 2068 { 2069 DeviceClass *dc = DEVICE_CLASS(klass); 2070 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2071 2072 k->realize = sm501_realize_pci; 2073 k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; 2074 k->device_id = PCI_DEVICE_ID_SM501; 2075 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2076 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2077 dc->desc = "SM501 Display Controller"; 2078 dc->props = sm501_pci_properties; 2079 dc->reset = sm501_reset_pci; 2080 dc->hotpluggable = false; 2081 dc->vmsd = &vmstate_sm501_pci; 2082 } 2083 2084 static const TypeInfo sm501_pci_info = { 2085 .name = TYPE_PCI_SM501, 2086 .parent = TYPE_PCI_DEVICE, 2087 .instance_size = sizeof(SM501PCIState), 2088 .class_init = sm501_pci_class_init, 2089 .interfaces = (InterfaceInfo[]) { 2090 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2091 { }, 2092 }, 2093 }; 2094 2095 static void sm501_register_types(void) 2096 { 2097 type_register_static(&sm501_sysbus_info); 2098 type_register_static(&sm501_pci_info); 2099 } 2100 2101 type_init(sm501_register_types) 2102