xref: /openbmc/qemu/hw/display/sii9022.c (revision f0613160)
1a643bd77SLinus Walleij /*
2a643bd77SLinus Walleij  * Silicon Image SiI9022
3a643bd77SLinus Walleij  *
4a643bd77SLinus Walleij  * This is a pretty hollow emulation: all we do is acknowledge that we
5a643bd77SLinus Walleij  * exist (chip ID) and confirm that we get switched over into DDC mode
6a643bd77SLinus Walleij  * so the emulated host can proceed to read out EDID data. All subsequent
7a643bd77SLinus Walleij  * set-up of connectors etc will be acknowledged and ignored.
8a643bd77SLinus Walleij  *
9a643bd77SLinus Walleij  * Copyright (C) 2018 Linus Walleij
10a643bd77SLinus Walleij  *
11a643bd77SLinus Walleij  * This work is licensed under the terms of the GNU GPL, version 2 or later.
12a643bd77SLinus Walleij  * See the COPYING file in the top-level directory.
13a643bd77SLinus Walleij  * SPDX-License-Identifier: GPL-2.0-or-later
14a643bd77SLinus Walleij  */
15a643bd77SLinus Walleij 
16a643bd77SLinus Walleij #include "qemu/osdep.h"
170b8fa32fSMarkus Armbruster #include "qemu/module.h"
18a643bd77SLinus Walleij #include "hw/i2c/i2c.h"
19d6454270SMarkus Armbruster #include "migration/vmstate.h"
206306cae2SPaolo Bonzini #include "hw/display/i2c-ddc.h"
21a643bd77SLinus Walleij #include "trace.h"
22db1015e9SEduardo Habkost #include "qom/object.h"
23a643bd77SLinus Walleij 
24a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DATA 0x1a
25a643bd77SLinus Walleij #define SII9022_SYS_CTRL_PWR_DWN 0x10
26a643bd77SLinus Walleij #define SII9022_SYS_CTRL_AV_MUTE 0x08
27a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
28a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
29a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
30a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_HDMI 1
31a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_DVI 0
32a643bd77SLinus Walleij #define SII9022_REG_CHIPID 0x1b
33a643bd77SLinus Walleij #define SII9022_INT_ENABLE 0x3c
34a643bd77SLinus Walleij #define SII9022_INT_STATUS 0x3d
35a643bd77SLinus Walleij #define SII9022_INT_STATUS_HOTPLUG 0x01;
36a643bd77SLinus Walleij #define SII9022_INT_STATUS_PLUGGED 0x04;
37a643bd77SLinus Walleij 
38a643bd77SLinus Walleij #define TYPE_SII9022 "sii9022"
398063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(sii9022_state, SII9022)
40a643bd77SLinus Walleij 
41db1015e9SEduardo Habkost struct sii9022_state {
42a643bd77SLinus Walleij     I2CSlave parent_obj;
43a643bd77SLinus Walleij     uint8_t ptr;
44a643bd77SLinus Walleij     bool addr_byte;
45a643bd77SLinus Walleij     bool ddc_req;
46a643bd77SLinus Walleij     bool ddc_skip_finish;
47a643bd77SLinus Walleij     bool ddc;
48db1015e9SEduardo Habkost };
49a643bd77SLinus Walleij 
50a643bd77SLinus Walleij static const VMStateDescription vmstate_sii9022 = {
51a643bd77SLinus Walleij     .name = "sii9022",
52a643bd77SLinus Walleij     .version_id = 1,
53a643bd77SLinus Walleij     .minimum_version_id = 1,
54*f0613160SRichard Henderson     .fields = (const VMStateField[]) {
55a643bd77SLinus Walleij         VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
56a643bd77SLinus Walleij         VMSTATE_UINT8(ptr, sii9022_state),
57a643bd77SLinus Walleij         VMSTATE_BOOL(addr_byte, sii9022_state),
58a643bd77SLinus Walleij         VMSTATE_BOOL(ddc_req, sii9022_state),
59a643bd77SLinus Walleij         VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
60a643bd77SLinus Walleij         VMSTATE_BOOL(ddc, sii9022_state),
61a643bd77SLinus Walleij         VMSTATE_END_OF_LIST()
62a643bd77SLinus Walleij     }
63a643bd77SLinus Walleij };
64a643bd77SLinus Walleij 
sii9022_event(I2CSlave * i2c,enum i2c_event event)65a643bd77SLinus Walleij static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
66a643bd77SLinus Walleij {
67a643bd77SLinus Walleij     sii9022_state *s = SII9022(i2c);
68a643bd77SLinus Walleij 
69a643bd77SLinus Walleij     switch (event) {
70a643bd77SLinus Walleij     case I2C_START_SEND:
71a643bd77SLinus Walleij         s->addr_byte = true;
72a643bd77SLinus Walleij         break;
73a643bd77SLinus Walleij     case I2C_START_RECV:
74a643bd77SLinus Walleij         break;
75a643bd77SLinus Walleij     case I2C_FINISH:
76a643bd77SLinus Walleij         break;
77a643bd77SLinus Walleij     case I2C_NACK:
78a643bd77SLinus Walleij         break;
79a78e9839SKlaus Jensen     default:
80a78e9839SKlaus Jensen         return -1;
81a643bd77SLinus Walleij     }
82a643bd77SLinus Walleij 
83a643bd77SLinus Walleij     return 0;
84a643bd77SLinus Walleij }
85a643bd77SLinus Walleij 
sii9022_rx(I2CSlave * i2c)862ac4c5f4SCorey Minyard static uint8_t sii9022_rx(I2CSlave *i2c)
87a643bd77SLinus Walleij {
88a643bd77SLinus Walleij     sii9022_state *s = SII9022(i2c);
89a643bd77SLinus Walleij     uint8_t res = 0x00;
90a643bd77SLinus Walleij 
91a643bd77SLinus Walleij     switch (s->ptr) {
92a643bd77SLinus Walleij     case SII9022_SYS_CTRL_DATA:
93a643bd77SLinus Walleij         if (s->ddc_req) {
94a643bd77SLinus Walleij             /* Acknowledge DDC bus request */
95a643bd77SLinus Walleij             res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
96a643bd77SLinus Walleij         }
97a643bd77SLinus Walleij         break;
98a643bd77SLinus Walleij     case SII9022_REG_CHIPID:
99a643bd77SLinus Walleij         res = 0xb0;
100a643bd77SLinus Walleij         break;
101a643bd77SLinus Walleij     case SII9022_INT_STATUS:
102a643bd77SLinus Walleij         /* Something is cold-plugged in, no interrupts */
103a643bd77SLinus Walleij         res = SII9022_INT_STATUS_PLUGGED;
104a643bd77SLinus Walleij         break;
105a643bd77SLinus Walleij     default:
106a643bd77SLinus Walleij         break;
107a643bd77SLinus Walleij     }
108a643bd77SLinus Walleij 
109a643bd77SLinus Walleij     trace_sii9022_read_reg(s->ptr, res);
110a643bd77SLinus Walleij     s->ptr++;
111a643bd77SLinus Walleij 
112a643bd77SLinus Walleij     return res;
113a643bd77SLinus Walleij }
114a643bd77SLinus Walleij 
sii9022_tx(I2CSlave * i2c,uint8_t data)115a643bd77SLinus Walleij static int sii9022_tx(I2CSlave *i2c, uint8_t data)
116a643bd77SLinus Walleij {
117a643bd77SLinus Walleij     sii9022_state *s = SII9022(i2c);
118a643bd77SLinus Walleij 
119a643bd77SLinus Walleij     if (s->addr_byte) {
120a643bd77SLinus Walleij         s->ptr = data;
121a643bd77SLinus Walleij         s->addr_byte = false;
122a643bd77SLinus Walleij         return 0;
123a643bd77SLinus Walleij     }
124a643bd77SLinus Walleij 
125a643bd77SLinus Walleij     switch (s->ptr) {
126a643bd77SLinus Walleij     case SII9022_SYS_CTRL_DATA:
127a643bd77SLinus Walleij         if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
128a643bd77SLinus Walleij             s->ddc_req = true;
129a643bd77SLinus Walleij             if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
130a643bd77SLinus Walleij                 s->ddc = true;
131a643bd77SLinus Walleij                 /* Skip this finish since we just switched to DDC */
132a643bd77SLinus Walleij                 s->ddc_skip_finish = true;
133a643bd77SLinus Walleij                 trace_sii9022_switch_mode("DDC");
134a643bd77SLinus Walleij             }
135a643bd77SLinus Walleij         } else {
136a643bd77SLinus Walleij             s->ddc_req = false;
137a643bd77SLinus Walleij             s->ddc = false;
138a643bd77SLinus Walleij             trace_sii9022_switch_mode("normal");
139a643bd77SLinus Walleij         }
140a643bd77SLinus Walleij         break;
141a643bd77SLinus Walleij     default:
142a643bd77SLinus Walleij         break;
143a643bd77SLinus Walleij     }
144a643bd77SLinus Walleij 
145a643bd77SLinus Walleij     trace_sii9022_write_reg(s->ptr, data);
146a643bd77SLinus Walleij     s->ptr++;
147a643bd77SLinus Walleij 
148a643bd77SLinus Walleij     return 0;
149a643bd77SLinus Walleij }
150a643bd77SLinus Walleij 
sii9022_reset(DeviceState * dev)151a643bd77SLinus Walleij static void sii9022_reset(DeviceState *dev)
152a643bd77SLinus Walleij {
153a643bd77SLinus Walleij     sii9022_state *s = SII9022(dev);
154a643bd77SLinus Walleij 
155a643bd77SLinus Walleij     s->ptr = 0;
156a643bd77SLinus Walleij     s->addr_byte = false;
157a643bd77SLinus Walleij     s->ddc_req = false;
158a643bd77SLinus Walleij     s->ddc_skip_finish = false;
159a643bd77SLinus Walleij     s->ddc = false;
160a643bd77SLinus Walleij }
161a643bd77SLinus Walleij 
sii9022_realize(DeviceState * dev,Error ** errp)162a643bd77SLinus Walleij static void sii9022_realize(DeviceState *dev, Error **errp)
163a643bd77SLinus Walleij {
164a643bd77SLinus Walleij     I2CBus *bus;
165a643bd77SLinus Walleij 
166a643bd77SLinus Walleij     bus = I2C_BUS(qdev_get_parent_bus(dev));
1671373b15bSPhilippe Mathieu-Daudé     i2c_slave_create_simple(bus, TYPE_I2CDDC, 0x50);
168a643bd77SLinus Walleij }
169a643bd77SLinus Walleij 
sii9022_class_init(ObjectClass * klass,void * data)170a643bd77SLinus Walleij static void sii9022_class_init(ObjectClass *klass, void *data)
171a643bd77SLinus Walleij {
172a643bd77SLinus Walleij     DeviceClass *dc = DEVICE_CLASS(klass);
173a643bd77SLinus Walleij     I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
174a643bd77SLinus Walleij 
175a643bd77SLinus Walleij     k->event = sii9022_event;
176a643bd77SLinus Walleij     k->recv = sii9022_rx;
177a643bd77SLinus Walleij     k->send = sii9022_tx;
178a643bd77SLinus Walleij     dc->reset = sii9022_reset;
179a643bd77SLinus Walleij     dc->realize = sii9022_realize;
180a643bd77SLinus Walleij     dc->vmsd = &vmstate_sii9022;
181a643bd77SLinus Walleij }
182a643bd77SLinus Walleij 
183a643bd77SLinus Walleij static const TypeInfo sii9022_info = {
184a643bd77SLinus Walleij     .name          = TYPE_SII9022,
185a643bd77SLinus Walleij     .parent        = TYPE_I2C_SLAVE,
186a643bd77SLinus Walleij     .instance_size = sizeof(sii9022_state),
187a643bd77SLinus Walleij     .class_init    = sii9022_class_init,
188a643bd77SLinus Walleij };
189a643bd77SLinus Walleij 
sii9022_register_types(void)190a643bd77SLinus Walleij static void sii9022_register_types(void)
191a643bd77SLinus Walleij {
192a643bd77SLinus Walleij     type_register_static(&sii9022_info);
193a643bd77SLinus Walleij }
194a643bd77SLinus Walleij 
195a643bd77SLinus Walleij type_init(sii9022_register_types)
196