1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <zlib.h> 22 #include <stdint.h> 23 24 #include "qemu-common.h" 25 #include "qemu/timer.h" 26 #include "qemu/queue.h" 27 #include "qemu/atomic.h" 28 #include "monitor/monitor.h" 29 #include "sysemu/sysemu.h" 30 #include "trace.h" 31 32 #include "qxl.h" 33 34 /* 35 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as 36 * such can be changed by the guest, so to avoid a guest trigerrable 37 * abort we just qxl_set_guest_bug and set the return to NULL. Still 38 * it may happen as a result of emulator bug as well. 39 */ 40 #undef SPICE_RING_PROD_ITEM 41 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ 42 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ 43 if (prod >= ARRAY_SIZE((r)->items)) { \ 44 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ 45 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ 46 ret = NULL; \ 47 } else { \ 48 ret = &(r)->items[prod].el; \ 49 } \ 50 } 51 52 #undef SPICE_RING_CONS_ITEM 53 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 54 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 55 if (cons >= ARRAY_SIZE((r)->items)) { \ 56 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 57 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 58 ret = NULL; \ 59 } else { \ 60 ret = &(r)->items[cons].el; \ 61 } \ 62 } 63 64 #undef ALIGN 65 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 66 67 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 68 69 #define QXL_MODE(_x, _y, _b, _o) \ 70 { .x_res = _x, \ 71 .y_res = _y, \ 72 .bits = _b, \ 73 .stride = (_x) * (_b) / 8, \ 74 .x_mili = PIXEL_SIZE * (_x), \ 75 .y_mili = PIXEL_SIZE * (_y), \ 76 .orientation = _o, \ 77 } 78 79 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 80 QXL_MODE(x_res, y_res, 16, orientation), \ 81 QXL_MODE(x_res, y_res, 32, orientation) 82 83 #define QXL_MODE_EX(x_res, y_res) \ 84 QXL_MODE_16_32(x_res, y_res, 0), \ 85 QXL_MODE_16_32(x_res, y_res, 1) 86 87 static QXLMode qxl_modes[] = { 88 QXL_MODE_EX(640, 480), 89 QXL_MODE_EX(800, 480), 90 QXL_MODE_EX(800, 600), 91 QXL_MODE_EX(832, 624), 92 QXL_MODE_EX(960, 640), 93 QXL_MODE_EX(1024, 600), 94 QXL_MODE_EX(1024, 768), 95 QXL_MODE_EX(1152, 864), 96 QXL_MODE_EX(1152, 870), 97 QXL_MODE_EX(1280, 720), 98 QXL_MODE_EX(1280, 760), 99 QXL_MODE_EX(1280, 768), 100 QXL_MODE_EX(1280, 800), 101 QXL_MODE_EX(1280, 960), 102 QXL_MODE_EX(1280, 1024), 103 QXL_MODE_EX(1360, 768), 104 QXL_MODE_EX(1366, 768), 105 QXL_MODE_EX(1400, 1050), 106 QXL_MODE_EX(1440, 900), 107 QXL_MODE_EX(1600, 900), 108 QXL_MODE_EX(1600, 1200), 109 QXL_MODE_EX(1680, 1050), 110 QXL_MODE_EX(1920, 1080), 111 /* these modes need more than 8 MB video memory */ 112 QXL_MODE_EX(1920, 1200), 113 QXL_MODE_EX(1920, 1440), 114 QXL_MODE_EX(2000, 2000), 115 QXL_MODE_EX(2048, 1536), 116 QXL_MODE_EX(2048, 2048), 117 QXL_MODE_EX(2560, 1440), 118 QXL_MODE_EX(2560, 1600), 119 /* these modes need more than 16 MB video memory */ 120 QXL_MODE_EX(2560, 2048), 121 QXL_MODE_EX(2800, 2100), 122 QXL_MODE_EX(3200, 2400), 123 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 124 QXL_MODE_EX(4096, 2160), /* 4k */ 125 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 126 QXL_MODE_EX(8192, 4320), /* 8k */ 127 }; 128 129 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 130 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 131 static void qxl_reset_memslots(PCIQXLDevice *d); 132 static void qxl_reset_surfaces(PCIQXLDevice *d); 133 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 134 135 static void qxl_hw_update(void *opaque); 136 137 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 138 { 139 trace_qxl_set_guest_bug(qxl->id); 140 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 141 qxl->guest_bug = 1; 142 if (qxl->guestdebug) { 143 va_list ap; 144 va_start(ap, msg); 145 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 146 vfprintf(stderr, msg, ap); 147 fprintf(stderr, "\n"); 148 va_end(ap); 149 } 150 } 151 152 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 153 { 154 qxl->guest_bug = 0; 155 } 156 157 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 158 struct QXLRect *area, struct QXLRect *dirty_rects, 159 uint32_t num_dirty_rects, 160 uint32_t clear_dirty_region, 161 qxl_async_io async, struct QXLCookie *cookie) 162 { 163 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 164 area->top, area->bottom); 165 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 166 clear_dirty_region); 167 if (async == QXL_SYNC) { 168 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area, 169 dirty_rects, num_dirty_rects, clear_dirty_region); 170 } else { 171 assert(cookie != NULL); 172 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 173 clear_dirty_region, (uintptr_t)cookie); 174 } 175 } 176 177 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 178 uint32_t id) 179 { 180 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 181 qemu_mutex_lock(&qxl->track_lock); 182 qxl->guest_surfaces.cmds[id] = 0; 183 qxl->guest_surfaces.count--; 184 qemu_mutex_unlock(&qxl->track_lock); 185 } 186 187 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 188 qxl_async_io async) 189 { 190 QXLCookie *cookie; 191 192 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 193 if (async) { 194 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 195 QXL_IO_DESTROY_SURFACE_ASYNC); 196 cookie->u.surface_id = id; 197 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 198 } else { 199 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id); 200 qxl_spice_destroy_surface_wait_complete(qxl, id); 201 } 202 } 203 204 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 205 { 206 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 207 qxl->num_free_res); 208 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 209 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 210 QXL_IO_FLUSH_SURFACES_ASYNC)); 211 } 212 213 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 214 uint32_t count) 215 { 216 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 217 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count); 218 } 219 220 void qxl_spice_oom(PCIQXLDevice *qxl) 221 { 222 trace_qxl_spice_oom(qxl->id); 223 spice_qxl_oom(&qxl->ssd.qxl); 224 } 225 226 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 227 { 228 trace_qxl_spice_reset_memslots(qxl->id); 229 spice_qxl_reset_memslots(&qxl->ssd.qxl); 230 } 231 232 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 233 { 234 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 235 qemu_mutex_lock(&qxl->track_lock); 236 memset(qxl->guest_surfaces.cmds, 0, 237 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 238 qxl->guest_surfaces.count = 0; 239 qemu_mutex_unlock(&qxl->track_lock); 240 } 241 242 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 243 { 244 trace_qxl_spice_destroy_surfaces(qxl->id, async); 245 if (async) { 246 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 247 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 248 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 249 } else { 250 spice_qxl_destroy_surfaces(&qxl->ssd.qxl); 251 qxl_spice_destroy_surfaces_complete(qxl); 252 } 253 } 254 255 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 256 { 257 trace_qxl_spice_monitors_config(qxl->id); 258 if (replay) { 259 /* 260 * don't use QXL_COOKIE_TYPE_IO: 261 * - we are not running yet (post_load), we will assert 262 * in send_events 263 * - this is not a guest io, but a reply, so async_io isn't set. 264 */ 265 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 266 qxl->guest_monitors_config, 267 MEMSLOT_GROUP_GUEST, 268 (uintptr_t)qxl_cookie_new( 269 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 270 0)); 271 } else { 272 qxl->guest_monitors_config = qxl->ram->monitors_config; 273 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 274 qxl->ram->monitors_config, 275 MEMSLOT_GROUP_GUEST, 276 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 277 QXL_IO_MONITORS_CONFIG_ASYNC)); 278 } 279 } 280 281 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 282 { 283 trace_qxl_spice_reset_image_cache(qxl->id); 284 spice_qxl_reset_image_cache(&qxl->ssd.qxl); 285 } 286 287 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 288 { 289 trace_qxl_spice_reset_cursor(qxl->id); 290 spice_qxl_reset_cursor(&qxl->ssd.qxl); 291 qemu_mutex_lock(&qxl->track_lock); 292 qxl->guest_cursor = 0; 293 qemu_mutex_unlock(&qxl->track_lock); 294 if (qxl->ssd.cursor) { 295 cursor_put(qxl->ssd.cursor); 296 } 297 qxl->ssd.cursor = cursor_builtin_hidden(); 298 } 299 300 301 static inline uint32_t msb_mask(uint32_t val) 302 { 303 uint32_t mask; 304 305 do { 306 mask = ~(val - 1) & val; 307 val &= ~mask; 308 } while (mask < val); 309 310 return mask; 311 } 312 313 static ram_addr_t qxl_rom_size(void) 314 { 315 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) + 316 sizeof(qxl_modes); 317 uint32_t rom_size = 8192; /* two pages */ 318 319 QEMU_BUILD_BUG_ON(required_rom_size > rom_size); 320 return rom_size; 321 } 322 323 static void init_qxl_rom(PCIQXLDevice *d) 324 { 325 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 326 QXLModes *modes = (QXLModes *)(rom + 1); 327 uint32_t ram_header_size; 328 uint32_t surface0_area_size; 329 uint32_t num_pages; 330 uint32_t fb; 331 int i, n; 332 333 memset(rom, 0, d->rom_size); 334 335 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 336 rom->id = cpu_to_le32(d->id); 337 rom->log_level = cpu_to_le32(d->guestdebug); 338 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 339 340 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 341 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 342 rom->slots_start = 1; 343 rom->slots_end = NUM_MEMSLOTS - 1; 344 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 345 346 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 347 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 348 if (fb > d->vgamem_size) { 349 continue; 350 } 351 modes->modes[n].id = cpu_to_le32(i); 352 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 353 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 354 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 355 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 356 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 357 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 358 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 359 n++; 360 } 361 modes->n_modes = cpu_to_le32(n); 362 363 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 364 surface0_area_size = ALIGN(d->vgamem_size, 4096); 365 num_pages = d->vga.vram_size; 366 num_pages -= ram_header_size; 367 num_pages -= surface0_area_size; 368 num_pages = num_pages / QXL_PAGE_SIZE; 369 370 rom->draw_area_offset = cpu_to_le32(0); 371 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 372 rom->pages_offset = cpu_to_le32(surface0_area_size); 373 rom->num_pages = cpu_to_le32(num_pages); 374 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 375 376 d->shadow_rom = *rom; 377 d->rom = rom; 378 d->modes = modes; 379 } 380 381 static void init_qxl_ram(PCIQXLDevice *d) 382 { 383 uint8_t *buf; 384 uint64_t *item; 385 386 buf = d->vga.vram_ptr; 387 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 388 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 389 d->ram->int_pending = cpu_to_le32(0); 390 d->ram->int_mask = cpu_to_le32(0); 391 d->ram->update_surface = 0; 392 d->ram->monitors_config = 0; 393 SPICE_RING_INIT(&d->ram->cmd_ring); 394 SPICE_RING_INIT(&d->ram->cursor_ring); 395 SPICE_RING_INIT(&d->ram->release_ring); 396 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); 397 assert(item); 398 *item = 0; 399 qxl_ring_set_dirty(d); 400 } 401 402 /* can be called from spice server thread context */ 403 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 404 { 405 memory_region_set_dirty(mr, addr, end - addr); 406 } 407 408 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 409 { 410 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 411 } 412 413 /* called from spice server thread context only */ 414 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 415 { 416 void *base = qxl->vga.vram_ptr; 417 intptr_t offset; 418 419 offset = ptr - base; 420 assert(offset < qxl->vga.vram_size); 421 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3); 422 } 423 424 /* can be called from spice server thread context */ 425 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 426 { 427 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 428 ram_addr_t end = qxl->vga.vram_size; 429 qxl_set_dirty(&qxl->vga.vram, addr, end); 430 } 431 432 /* 433 * keep track of some command state, for savevm/loadvm. 434 * called from spice server thread context only 435 */ 436 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 437 { 438 switch (le32_to_cpu(ext->cmd.type)) { 439 case QXL_CMD_SURFACE: 440 { 441 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 442 443 if (!cmd) { 444 return 1; 445 } 446 uint32_t id = le32_to_cpu(cmd->surface_id); 447 448 if (id >= qxl->ssd.num_surfaces) { 449 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 450 qxl->ssd.num_surfaces); 451 return 1; 452 } 453 if (cmd->type == QXL_SURFACE_CMD_CREATE && 454 (cmd->u.surface_create.stride & 0x03) != 0) { 455 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 456 cmd->u.surface_create.stride); 457 return 1; 458 } 459 qemu_mutex_lock(&qxl->track_lock); 460 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 461 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 462 qxl->guest_surfaces.count++; 463 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) 464 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 465 } 466 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 467 qxl->guest_surfaces.cmds[id] = 0; 468 qxl->guest_surfaces.count--; 469 } 470 qemu_mutex_unlock(&qxl->track_lock); 471 break; 472 } 473 case QXL_CMD_CURSOR: 474 { 475 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 476 477 if (!cmd) { 478 return 1; 479 } 480 if (cmd->type == QXL_CURSOR_SET) { 481 qemu_mutex_lock(&qxl->track_lock); 482 qxl->guest_cursor = ext->cmd.data; 483 qemu_mutex_unlock(&qxl->track_lock); 484 } 485 break; 486 } 487 } 488 return 0; 489 } 490 491 /* spice display interface callbacks */ 492 493 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 494 { 495 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 496 497 trace_qxl_interface_attach_worker(qxl->id); 498 qxl->ssd.worker = qxl_worker; 499 } 500 501 static void interface_set_compression_level(QXLInstance *sin, int level) 502 { 503 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 504 505 trace_qxl_interface_set_compression_level(qxl->id, level); 506 qxl->shadow_rom.compression_level = cpu_to_le32(level); 507 qxl->rom->compression_level = cpu_to_le32(level); 508 qxl_rom_set_dirty(qxl); 509 } 510 511 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 512 { 513 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 514 515 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 516 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 517 qxl->rom->mm_clock = cpu_to_le32(mm_time); 518 qxl_rom_set_dirty(qxl); 519 } 520 521 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 522 { 523 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 524 525 trace_qxl_interface_get_init_info(qxl->id); 526 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 527 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 528 info->num_memslots = NUM_MEMSLOTS; 529 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 530 info->internal_groupslot_id = 0; 531 info->qxl_ram_size = 532 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS; 533 info->n_surfaces = qxl->ssd.num_surfaces; 534 } 535 536 static const char *qxl_mode_to_string(int mode) 537 { 538 switch (mode) { 539 case QXL_MODE_COMPAT: 540 return "compat"; 541 case QXL_MODE_NATIVE: 542 return "native"; 543 case QXL_MODE_UNDEFINED: 544 return "undefined"; 545 case QXL_MODE_VGA: 546 return "vga"; 547 } 548 return "INVALID"; 549 } 550 551 static const char *io_port_to_string(uint32_t io_port) 552 { 553 if (io_port >= QXL_IO_RANGE_SIZE) { 554 return "out of range"; 555 } 556 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 557 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 558 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 559 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 560 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 561 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 562 [QXL_IO_RESET] = "QXL_IO_RESET", 563 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 564 [QXL_IO_LOG] = "QXL_IO_LOG", 565 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 566 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 567 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 568 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 569 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 570 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 571 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 572 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 573 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 574 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 575 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 576 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 577 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 578 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 579 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 580 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 581 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 582 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 583 }; 584 return io_port_to_string[io_port]; 585 } 586 587 /* called from spice server thread context only */ 588 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 589 { 590 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 591 SimpleSpiceUpdate *update; 592 QXLCommandRing *ring; 593 QXLCommand *cmd; 594 int notify, ret; 595 596 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 597 598 switch (qxl->mode) { 599 case QXL_MODE_VGA: 600 ret = false; 601 qemu_mutex_lock(&qxl->ssd.lock); 602 update = QTAILQ_FIRST(&qxl->ssd.updates); 603 if (update != NULL) { 604 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 605 *ext = update->ext; 606 ret = true; 607 } 608 qemu_mutex_unlock(&qxl->ssd.lock); 609 if (ret) { 610 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 611 qxl_log_command(qxl, "vga", ext); 612 } 613 return ret; 614 case QXL_MODE_COMPAT: 615 case QXL_MODE_NATIVE: 616 case QXL_MODE_UNDEFINED: 617 ring = &qxl->ram->cmd_ring; 618 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 619 return false; 620 } 621 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 622 if (!cmd) { 623 return false; 624 } 625 ext->cmd = *cmd; 626 ext->group_id = MEMSLOT_GROUP_GUEST; 627 ext->flags = qxl->cmdflags; 628 SPICE_RING_POP(ring, notify); 629 qxl_ring_set_dirty(qxl); 630 if (notify) { 631 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 632 } 633 qxl->guest_primary.commands++; 634 qxl_track_command(qxl, ext); 635 qxl_log_command(qxl, "cmd", ext); 636 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 637 return true; 638 default: 639 return false; 640 } 641 } 642 643 /* called from spice server thread context only */ 644 static int interface_req_cmd_notification(QXLInstance *sin) 645 { 646 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 647 int wait = 1; 648 649 trace_qxl_ring_command_req_notification(qxl->id); 650 switch (qxl->mode) { 651 case QXL_MODE_COMPAT: 652 case QXL_MODE_NATIVE: 653 case QXL_MODE_UNDEFINED: 654 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 655 qxl_ring_set_dirty(qxl); 656 break; 657 default: 658 /* nothing */ 659 break; 660 } 661 return wait; 662 } 663 664 /* called from spice server thread context only */ 665 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 666 { 667 QXLReleaseRing *ring = &d->ram->release_ring; 668 uint64_t *item; 669 int notify; 670 671 #define QXL_FREE_BUNCH_SIZE 32 672 673 if (ring->prod - ring->cons + 1 == ring->num_items) { 674 /* ring full -- can't push */ 675 return; 676 } 677 if (!flush && d->oom_running) { 678 /* collect everything from oom handler before pushing */ 679 return; 680 } 681 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 682 /* collect a bit more before pushing */ 683 return; 684 } 685 686 SPICE_RING_PUSH(ring, notify); 687 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 688 d->guest_surfaces.count, d->num_free_res, 689 d->last_release, notify ? "yes" : "no"); 690 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 691 ring->num_items, ring->prod, ring->cons); 692 if (notify) { 693 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 694 } 695 SPICE_RING_PROD_ITEM(d, ring, item); 696 if (!item) { 697 return; 698 } 699 *item = 0; 700 d->num_free_res = 0; 701 d->last_release = NULL; 702 qxl_ring_set_dirty(d); 703 } 704 705 /* called from spice server thread context only */ 706 static void interface_release_resource(QXLInstance *sin, 707 struct QXLReleaseInfoExt ext) 708 { 709 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 710 QXLReleaseRing *ring; 711 uint64_t *item, id; 712 713 if (ext.group_id == MEMSLOT_GROUP_HOST) { 714 /* host group -> vga mode update request */ 715 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id); 716 SimpleSpiceUpdate *update; 717 g_assert(cmdext->cmd.type == QXL_CMD_DRAW); 718 update = container_of(cmdext, SimpleSpiceUpdate, ext); 719 qemu_spice_destroy_update(&qxl->ssd, update); 720 return; 721 } 722 723 /* 724 * ext->info points into guest-visible memory 725 * pci bar 0, $command.release_info 726 */ 727 ring = &qxl->ram->release_ring; 728 SPICE_RING_PROD_ITEM(qxl, ring, item); 729 if (!item) { 730 return; 731 } 732 if (*item == 0) { 733 /* stick head into the ring */ 734 id = ext.info->id; 735 ext.info->next = 0; 736 qxl_ram_set_dirty(qxl, &ext.info->next); 737 *item = id; 738 qxl_ring_set_dirty(qxl); 739 } else { 740 /* append item to the list */ 741 qxl->last_release->next = ext.info->id; 742 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 743 ext.info->next = 0; 744 qxl_ram_set_dirty(qxl, &ext.info->next); 745 } 746 qxl->last_release = ext.info; 747 qxl->num_free_res++; 748 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 749 qxl_push_free_res(qxl, 0); 750 } 751 752 /* called from spice server thread context only */ 753 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 754 { 755 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 756 QXLCursorRing *ring; 757 QXLCommand *cmd; 758 int notify; 759 760 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 761 762 switch (qxl->mode) { 763 case QXL_MODE_COMPAT: 764 case QXL_MODE_NATIVE: 765 case QXL_MODE_UNDEFINED: 766 ring = &qxl->ram->cursor_ring; 767 if (SPICE_RING_IS_EMPTY(ring)) { 768 return false; 769 } 770 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 771 if (!cmd) { 772 return false; 773 } 774 ext->cmd = *cmd; 775 ext->group_id = MEMSLOT_GROUP_GUEST; 776 ext->flags = qxl->cmdflags; 777 SPICE_RING_POP(ring, notify); 778 qxl_ring_set_dirty(qxl); 779 if (notify) { 780 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 781 } 782 qxl->guest_primary.commands++; 783 qxl_track_command(qxl, ext); 784 qxl_log_command(qxl, "csr", ext); 785 if (qxl->id == 0) { 786 qxl_render_cursor(qxl, ext); 787 } 788 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 789 return true; 790 default: 791 return false; 792 } 793 } 794 795 /* called from spice server thread context only */ 796 static int interface_req_cursor_notification(QXLInstance *sin) 797 { 798 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 799 int wait = 1; 800 801 trace_qxl_ring_cursor_req_notification(qxl->id); 802 switch (qxl->mode) { 803 case QXL_MODE_COMPAT: 804 case QXL_MODE_NATIVE: 805 case QXL_MODE_UNDEFINED: 806 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 807 qxl_ring_set_dirty(qxl); 808 break; 809 default: 810 /* nothing */ 811 break; 812 } 813 return wait; 814 } 815 816 /* called from spice server thread context */ 817 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 818 { 819 /* 820 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 821 * use by xf86-video-qxl and is defined out in the qxl windows driver. 822 * Probably was at some earlier version that is prior to git start (2009), 823 * and is still guest trigerrable. 824 */ 825 fprintf(stderr, "%s: deprecated\n", __func__); 826 } 827 828 /* called from spice server thread context only */ 829 static int interface_flush_resources(QXLInstance *sin) 830 { 831 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 832 int ret; 833 834 ret = qxl->num_free_res; 835 if (ret) { 836 qxl_push_free_res(qxl, 1); 837 } 838 return ret; 839 } 840 841 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 842 843 /* called from spice server thread context only */ 844 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 845 { 846 uint32_t current_async; 847 848 qemu_mutex_lock(&qxl->async_lock); 849 current_async = qxl->current_async; 850 qxl->current_async = QXL_UNDEFINED_IO; 851 qemu_mutex_unlock(&qxl->async_lock); 852 853 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 854 if (!cookie) { 855 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 856 return; 857 } 858 if (cookie && current_async != cookie->io) { 859 fprintf(stderr, 860 "qxl: %s: error: current_async = %d != %" 861 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 862 } 863 switch (current_async) { 864 case QXL_IO_MEMSLOT_ADD_ASYNC: 865 case QXL_IO_DESTROY_PRIMARY_ASYNC: 866 case QXL_IO_UPDATE_AREA_ASYNC: 867 case QXL_IO_FLUSH_SURFACES_ASYNC: 868 case QXL_IO_MONITORS_CONFIG_ASYNC: 869 break; 870 case QXL_IO_CREATE_PRIMARY_ASYNC: 871 qxl_create_guest_primary_complete(qxl); 872 break; 873 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 874 qxl_spice_destroy_surfaces_complete(qxl); 875 break; 876 case QXL_IO_DESTROY_SURFACE_ASYNC: 877 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 878 break; 879 default: 880 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 881 current_async); 882 } 883 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 884 } 885 886 /* called from spice server thread context only */ 887 static void interface_update_area_complete(QXLInstance *sin, 888 uint32_t surface_id, 889 QXLRect *dirty, uint32_t num_updated_rects) 890 { 891 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 892 int i; 893 int qxl_i; 894 895 qemu_mutex_lock(&qxl->ssd.lock); 896 if (surface_id != 0 || !qxl->render_update_cookie_num) { 897 qemu_mutex_unlock(&qxl->ssd.lock); 898 return; 899 } 900 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 901 dirty->right, dirty->top, dirty->bottom); 902 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 903 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 904 /* 905 * overflow - treat this as a full update. Not expected to be common. 906 */ 907 trace_qxl_interface_update_area_complete_overflow(qxl->id, 908 QXL_NUM_DIRTY_RECTS); 909 qxl->guest_primary.resized = 1; 910 } 911 if (qxl->guest_primary.resized) { 912 /* 913 * Don't bother copying or scheduling the bh since we will flip 914 * the whole area anyway on completion of the update_area async call 915 */ 916 qemu_mutex_unlock(&qxl->ssd.lock); 917 return; 918 } 919 qxl_i = qxl->num_dirty_rects; 920 for (i = 0; i < num_updated_rects; i++) { 921 qxl->dirty[qxl_i++] = dirty[i]; 922 } 923 qxl->num_dirty_rects += num_updated_rects; 924 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 925 qxl->num_dirty_rects); 926 qemu_bh_schedule(qxl->update_area_bh); 927 qemu_mutex_unlock(&qxl->ssd.lock); 928 } 929 930 /* called from spice server thread context only */ 931 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 932 { 933 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 934 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 935 936 switch (cookie->type) { 937 case QXL_COOKIE_TYPE_IO: 938 interface_async_complete_io(qxl, cookie); 939 g_free(cookie); 940 break; 941 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 942 qxl_render_update_area_done(qxl, cookie); 943 break; 944 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 945 break; 946 default: 947 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 948 __func__, cookie->type); 949 g_free(cookie); 950 } 951 } 952 953 /* called from spice server thread context only */ 954 static void interface_set_client_capabilities(QXLInstance *sin, 955 uint8_t client_present, 956 uint8_t caps[58]) 957 { 958 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 959 960 if (qxl->revision < 4) { 961 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 962 qxl->revision); 963 return; 964 } 965 966 if (runstate_check(RUN_STATE_INMIGRATE) || 967 runstate_check(RUN_STATE_POSTMIGRATE)) { 968 return; 969 } 970 971 qxl->shadow_rom.client_present = client_present; 972 memcpy(qxl->shadow_rom.client_capabilities, caps, 973 sizeof(qxl->shadow_rom.client_capabilities)); 974 qxl->rom->client_present = client_present; 975 memcpy(qxl->rom->client_capabilities, caps, 976 sizeof(qxl->rom->client_capabilities)); 977 qxl_rom_set_dirty(qxl); 978 979 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 980 } 981 982 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 983 { 984 /* 985 * zlib xors the seed with 0xffffffff, and xors the result 986 * again with 0xffffffff; Both are not done with linux's crc32, 987 * which we want to be compatible with, so undo that. 988 */ 989 return crc32(0xffffffff, p, len) ^ 0xffffffff; 990 } 991 992 /* called from main context only */ 993 static int interface_client_monitors_config(QXLInstance *sin, 994 VDAgentMonitorsConfig *monitors_config) 995 { 996 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 997 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 998 int i; 999 1000 if (qxl->revision < 4) { 1001 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 1002 qxl->revision); 1003 return 0; 1004 } 1005 /* 1006 * Older windows drivers set int_mask to 0 when their ISR is called, 1007 * then later set it to ~0. So it doesn't relate to the actual interrupts 1008 * handled. However, they are old, so clearly they don't support this 1009 * interrupt 1010 */ 1011 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1012 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1013 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1014 qxl->ram->int_mask, 1015 monitors_config); 1016 return 0; 1017 } 1018 if (!monitors_config) { 1019 return 1; 1020 } 1021 memset(&rom->client_monitors_config, 0, 1022 sizeof(rom->client_monitors_config)); 1023 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1024 /* monitors_config->flags ignored */ 1025 if (rom->client_monitors_config.count >= 1026 ARRAY_SIZE(rom->client_monitors_config.heads)) { 1027 trace_qxl_client_monitors_config_capped(qxl->id, 1028 monitors_config->num_of_monitors, 1029 ARRAY_SIZE(rom->client_monitors_config.heads)); 1030 rom->client_monitors_config.count = 1031 ARRAY_SIZE(rom->client_monitors_config.heads); 1032 } 1033 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1034 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1035 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1036 /* monitor->depth ignored */ 1037 rect->left = monitor->x; 1038 rect->top = monitor->y; 1039 rect->right = monitor->x + monitor->width; 1040 rect->bottom = monitor->y + monitor->height; 1041 } 1042 rom->client_monitors_config_crc = qxl_crc32( 1043 (const uint8_t *)&rom->client_monitors_config, 1044 sizeof(rom->client_monitors_config)); 1045 trace_qxl_client_monitors_config_crc(qxl->id, 1046 sizeof(rom->client_monitors_config), 1047 rom->client_monitors_config_crc); 1048 1049 trace_qxl_interrupt_client_monitors_config(qxl->id, 1050 rom->client_monitors_config.count, 1051 rom->client_monitors_config.heads); 1052 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1053 return 1; 1054 } 1055 1056 static const QXLInterface qxl_interface = { 1057 .base.type = SPICE_INTERFACE_QXL, 1058 .base.description = "qxl gpu", 1059 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1060 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1061 1062 .attache_worker = interface_attach_worker, 1063 .set_compression_level = interface_set_compression_level, 1064 .set_mm_time = interface_set_mm_time, 1065 .get_init_info = interface_get_init_info, 1066 1067 /* the callbacks below are called from spice server thread context */ 1068 .get_command = interface_get_command, 1069 .req_cmd_notification = interface_req_cmd_notification, 1070 .release_resource = interface_release_resource, 1071 .get_cursor_command = interface_get_cursor_command, 1072 .req_cursor_notification = interface_req_cursor_notification, 1073 .notify_update = interface_notify_update, 1074 .flush_resources = interface_flush_resources, 1075 .async_complete = interface_async_complete, 1076 .update_area_complete = interface_update_area_complete, 1077 .set_client_capabilities = interface_set_client_capabilities, 1078 .client_monitors_config = interface_client_monitors_config, 1079 }; 1080 1081 static const GraphicHwOps qxl_ops = { 1082 .gfx_update = qxl_hw_update, 1083 }; 1084 1085 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1086 { 1087 if (d->mode == QXL_MODE_VGA) { 1088 return; 1089 } 1090 trace_qxl_enter_vga_mode(d->id); 1091 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */ 1092 spice_qxl_driver_unload(&d->ssd.qxl); 1093 #endif 1094 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga); 1095 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT); 1096 qemu_spice_create_host_primary(&d->ssd); 1097 d->mode = QXL_MODE_VGA; 1098 vga_dirty_log_start(&d->vga); 1099 graphic_hw_update(d->vga.con); 1100 } 1101 1102 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1103 { 1104 if (d->mode != QXL_MODE_VGA) { 1105 return; 1106 } 1107 trace_qxl_exit_vga_mode(d->id); 1108 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d); 1109 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE); 1110 vga_dirty_log_stop(&d->vga); 1111 qxl_destroy_primary(d, QXL_SYNC); 1112 } 1113 1114 static void qxl_update_irq(PCIQXLDevice *d) 1115 { 1116 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1117 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1118 int level = !!(pending & mask); 1119 pci_set_irq(&d->pci, level); 1120 qxl_ring_set_dirty(d); 1121 } 1122 1123 static void qxl_check_state(PCIQXLDevice *d) 1124 { 1125 QXLRam *ram = d->ram; 1126 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1127 1128 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1129 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1130 } 1131 1132 static void qxl_reset_state(PCIQXLDevice *d) 1133 { 1134 QXLRom *rom = d->rom; 1135 1136 qxl_check_state(d); 1137 d->shadow_rom.update_id = cpu_to_le32(0); 1138 *rom = d->shadow_rom; 1139 qxl_rom_set_dirty(d); 1140 init_qxl_ram(d); 1141 d->num_free_res = 0; 1142 d->last_release = NULL; 1143 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1144 qxl_update_irq(d); 1145 } 1146 1147 static void qxl_soft_reset(PCIQXLDevice *d) 1148 { 1149 trace_qxl_soft_reset(d->id); 1150 qxl_check_state(d); 1151 qxl_clear_guest_bug(d); 1152 d->current_async = QXL_UNDEFINED_IO; 1153 1154 if (d->id == 0) { 1155 qxl_enter_vga_mode(d); 1156 } else { 1157 d->mode = QXL_MODE_UNDEFINED; 1158 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE); 1159 } 1160 } 1161 1162 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1163 { 1164 bool startstop = qemu_spice_display_is_running(&d->ssd); 1165 1166 trace_qxl_hard_reset(d->id, loadvm); 1167 1168 if (startstop) { 1169 qemu_spice_display_stop(); 1170 } 1171 1172 qxl_spice_reset_cursor(d); 1173 qxl_spice_reset_image_cache(d); 1174 qxl_reset_surfaces(d); 1175 qxl_reset_memslots(d); 1176 1177 /* pre loadvm reset must not touch QXLRam. This lives in 1178 * device memory, is migrated together with RAM and thus 1179 * already loaded at this point */ 1180 if (!loadvm) { 1181 qxl_reset_state(d); 1182 } 1183 qemu_spice_create_host_memslot(&d->ssd); 1184 qxl_soft_reset(d); 1185 1186 if (startstop) { 1187 qemu_spice_display_start(); 1188 } 1189 } 1190 1191 static void qxl_reset_handler(DeviceState *dev) 1192 { 1193 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); 1194 1195 qxl_hard_reset(d, 0); 1196 } 1197 1198 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1199 { 1200 VGACommonState *vga = opaque; 1201 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1202 1203 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1204 if (qxl->mode != QXL_MODE_VGA) { 1205 qxl_destroy_primary(qxl, QXL_SYNC); 1206 qxl_soft_reset(qxl); 1207 } 1208 vga_ioport_write(opaque, addr, val); 1209 } 1210 1211 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1212 { 0x04, 2, 1, .read = vga_ioport_read, 1213 .write = qxl_vga_ioport_write }, /* 3b4 */ 1214 { 0x0a, 1, 1, .read = vga_ioport_read, 1215 .write = qxl_vga_ioport_write }, /* 3ba */ 1216 { 0x10, 16, 1, .read = vga_ioport_read, 1217 .write = qxl_vga_ioport_write }, /* 3c0 */ 1218 { 0x24, 2, 1, .read = vga_ioport_read, 1219 .write = qxl_vga_ioport_write }, /* 3d4 */ 1220 { 0x2a, 1, 1, .read = vga_ioport_read, 1221 .write = qxl_vga_ioport_write }, /* 3da */ 1222 PORTIO_END_OF_LIST(), 1223 }; 1224 1225 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1226 qxl_async_io async) 1227 { 1228 static const int regions[] = { 1229 QXL_RAM_RANGE_INDEX, 1230 QXL_VRAM_RANGE_INDEX, 1231 QXL_VRAM64_RANGE_INDEX, 1232 }; 1233 uint64_t guest_start; 1234 uint64_t guest_end; 1235 int pci_region; 1236 pcibus_t pci_start; 1237 pcibus_t pci_end; 1238 intptr_t virt_start; 1239 QXLDevMemSlot memslot; 1240 int i; 1241 1242 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1243 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1244 1245 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1246 1247 if (slot_id >= NUM_MEMSLOTS) { 1248 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1249 slot_id, NUM_MEMSLOTS); 1250 return 1; 1251 } 1252 if (guest_start > guest_end) { 1253 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1254 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1255 return 1; 1256 } 1257 1258 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1259 pci_region = regions[i]; 1260 pci_start = d->pci.io_regions[pci_region].addr; 1261 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1262 /* mapped? */ 1263 if (pci_start == -1) { 1264 continue; 1265 } 1266 /* start address in range ? */ 1267 if (guest_start < pci_start || guest_start > pci_end) { 1268 continue; 1269 } 1270 /* end address in range ? */ 1271 if (guest_end > pci_end) { 1272 continue; 1273 } 1274 /* passed */ 1275 break; 1276 } 1277 if (i == ARRAY_SIZE(regions)) { 1278 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1279 return 1; 1280 } 1281 1282 switch (pci_region) { 1283 case QXL_RAM_RANGE_INDEX: 1284 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); 1285 break; 1286 case QXL_VRAM_RANGE_INDEX: 1287 case 4 /* vram 64bit */: 1288 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); 1289 break; 1290 default: 1291 /* should not happen */ 1292 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1293 return 1; 1294 } 1295 1296 memslot.slot_id = slot_id; 1297 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1298 memslot.virt_start = virt_start + (guest_start - pci_start); 1299 memslot.virt_end = virt_start + (guest_end - pci_start); 1300 memslot.addr_delta = memslot.virt_start - delta; 1301 memslot.generation = d->rom->slot_generation = 0; 1302 qxl_rom_set_dirty(d); 1303 1304 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1305 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; 1306 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1307 d->guest_slots[slot_id].delta = delta; 1308 d->guest_slots[slot_id].active = 1; 1309 return 0; 1310 } 1311 1312 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1313 { 1314 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1315 d->guest_slots[slot_id].active = 0; 1316 } 1317 1318 static void qxl_reset_memslots(PCIQXLDevice *d) 1319 { 1320 qxl_spice_reset_memslots(d); 1321 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1322 } 1323 1324 static void qxl_reset_surfaces(PCIQXLDevice *d) 1325 { 1326 trace_qxl_reset_surfaces(d->id); 1327 d->mode = QXL_MODE_UNDEFINED; 1328 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1329 } 1330 1331 /* can be also called from spice server thread context */ 1332 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1333 { 1334 uint64_t phys = le64_to_cpu(pqxl); 1335 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1336 uint64_t offset = phys & 0xffffffffffff; 1337 1338 switch (group_id) { 1339 case MEMSLOT_GROUP_HOST: 1340 return (void *)(intptr_t)offset; 1341 case MEMSLOT_GROUP_GUEST: 1342 if (slot >= NUM_MEMSLOTS) { 1343 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1344 NUM_MEMSLOTS); 1345 return NULL; 1346 } 1347 if (!qxl->guest_slots[slot].active) { 1348 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1349 return NULL; 1350 } 1351 if (offset < qxl->guest_slots[slot].delta) { 1352 qxl_set_guest_bug(qxl, 1353 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1354 slot, offset, qxl->guest_slots[slot].delta); 1355 return NULL; 1356 } 1357 offset -= qxl->guest_slots[slot].delta; 1358 if (offset > qxl->guest_slots[slot].size) { 1359 qxl_set_guest_bug(qxl, 1360 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1361 slot, offset, qxl->guest_slots[slot].size); 1362 return NULL; 1363 } 1364 return qxl->guest_slots[slot].ptr + offset; 1365 } 1366 return NULL; 1367 } 1368 1369 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1370 { 1371 /* for local rendering */ 1372 qxl_render_resize(qxl); 1373 } 1374 1375 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1376 qxl_async_io async) 1377 { 1378 QXLDevSurfaceCreate surface; 1379 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1380 uint32_t requested_height = le32_to_cpu(sc->height); 1381 int requested_stride = le32_to_cpu(sc->stride); 1382 1383 if (requested_stride == INT32_MIN || 1384 abs(requested_stride) * (uint64_t)requested_height 1385 > qxl->vgamem_size) { 1386 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer" 1387 " stride %d x height %" PRIu32 " > %" PRIu32, 1388 __func__, requested_stride, requested_height, 1389 qxl->vgamem_size); 1390 return; 1391 } 1392 1393 if (qxl->mode == QXL_MODE_NATIVE) { 1394 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1395 __func__); 1396 } 1397 qxl_exit_vga_mode(qxl); 1398 1399 surface.format = le32_to_cpu(sc->format); 1400 surface.height = le32_to_cpu(sc->height); 1401 surface.mem = le64_to_cpu(sc->mem); 1402 surface.position = le32_to_cpu(sc->position); 1403 surface.stride = le32_to_cpu(sc->stride); 1404 surface.width = le32_to_cpu(sc->width); 1405 surface.type = le32_to_cpu(sc->type); 1406 surface.flags = le32_to_cpu(sc->flags); 1407 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1408 sc->format, sc->position); 1409 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1410 sc->flags); 1411 1412 if ((surface.stride & 0x3) != 0) { 1413 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1414 surface.stride); 1415 return; 1416 } 1417 1418 surface.mouse_mode = true; 1419 surface.group_id = MEMSLOT_GROUP_GUEST; 1420 if (loadvm) { 1421 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1422 } 1423 1424 qxl->mode = QXL_MODE_NATIVE; 1425 qxl->cmdflags = 0; 1426 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1427 1428 if (async == QXL_SYNC) { 1429 qxl_create_guest_primary_complete(qxl); 1430 } 1431 } 1432 1433 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1434 * done (in QXL_SYNC case), 0 otherwise. */ 1435 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1436 { 1437 if (d->mode == QXL_MODE_UNDEFINED) { 1438 return 0; 1439 } 1440 trace_qxl_destroy_primary(d->id); 1441 d->mode = QXL_MODE_UNDEFINED; 1442 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1443 qxl_spice_reset_cursor(d); 1444 return 1; 1445 } 1446 1447 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm) 1448 { 1449 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1450 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1451 QXLMode *mode = d->modes->modes + modenr; 1452 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1453 QXLMemSlot slot = { 1454 .mem_start = start, 1455 .mem_end = end 1456 }; 1457 1458 if (modenr >= d->modes->n_modes) { 1459 qxl_set_guest_bug(d, "mode number out of range"); 1460 return; 1461 } 1462 1463 QXLSurfaceCreate surface = { 1464 .width = mode->x_res, 1465 .height = mode->y_res, 1466 .stride = -mode->x_res * 4, 1467 .format = SPICE_SURFACE_FMT_32_xRGB, 1468 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1469 .mouse_mode = true, 1470 .mem = devmem + d->shadow_rom.draw_area_offset, 1471 }; 1472 1473 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1474 devmem); 1475 if (!loadvm) { 1476 qxl_hard_reset(d, 0); 1477 } 1478 1479 d->guest_slots[0].slot = slot; 1480 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1481 1482 d->guest_primary.surface = surface; 1483 qxl_create_guest_primary(d, 0, QXL_SYNC); 1484 1485 d->mode = QXL_MODE_COMPAT; 1486 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1487 if (mode->bits == 16) { 1488 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1489 } 1490 d->shadow_rom.mode = cpu_to_le32(modenr); 1491 d->rom->mode = cpu_to_le32(modenr); 1492 qxl_rom_set_dirty(d); 1493 } 1494 1495 static void ioport_write(void *opaque, hwaddr addr, 1496 uint64_t val, unsigned size) 1497 { 1498 PCIQXLDevice *d = opaque; 1499 uint32_t io_port = addr; 1500 qxl_async_io async = QXL_SYNC; 1501 uint32_t orig_io_port = io_port; 1502 1503 if (d->guest_bug && io_port != QXL_IO_RESET) { 1504 return; 1505 } 1506 1507 if (d->revision <= QXL_REVISION_STABLE_V10 && 1508 io_port > QXL_IO_FLUSH_RELEASE) { 1509 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1510 io_port, d->revision); 1511 return; 1512 } 1513 1514 switch (io_port) { 1515 case QXL_IO_RESET: 1516 case QXL_IO_SET_MODE: 1517 case QXL_IO_MEMSLOT_ADD: 1518 case QXL_IO_MEMSLOT_DEL: 1519 case QXL_IO_CREATE_PRIMARY: 1520 case QXL_IO_UPDATE_IRQ: 1521 case QXL_IO_LOG: 1522 case QXL_IO_MEMSLOT_ADD_ASYNC: 1523 case QXL_IO_CREATE_PRIMARY_ASYNC: 1524 break; 1525 default: 1526 if (d->mode != QXL_MODE_VGA) { 1527 break; 1528 } 1529 trace_qxl_io_unexpected_vga_mode(d->id, 1530 addr, val, io_port_to_string(io_port)); 1531 /* be nice to buggy guest drivers */ 1532 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1533 io_port < QXL_IO_RANGE_SIZE) { 1534 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1535 } 1536 return; 1537 } 1538 1539 /* we change the io_port to avoid ifdeffery in the main switch */ 1540 orig_io_port = io_port; 1541 switch (io_port) { 1542 case QXL_IO_UPDATE_AREA_ASYNC: 1543 io_port = QXL_IO_UPDATE_AREA; 1544 goto async_common; 1545 case QXL_IO_MEMSLOT_ADD_ASYNC: 1546 io_port = QXL_IO_MEMSLOT_ADD; 1547 goto async_common; 1548 case QXL_IO_CREATE_PRIMARY_ASYNC: 1549 io_port = QXL_IO_CREATE_PRIMARY; 1550 goto async_common; 1551 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1552 io_port = QXL_IO_DESTROY_PRIMARY; 1553 goto async_common; 1554 case QXL_IO_DESTROY_SURFACE_ASYNC: 1555 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1556 goto async_common; 1557 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1558 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1559 goto async_common; 1560 case QXL_IO_FLUSH_SURFACES_ASYNC: 1561 case QXL_IO_MONITORS_CONFIG_ASYNC: 1562 async_common: 1563 async = QXL_ASYNC; 1564 qemu_mutex_lock(&d->async_lock); 1565 if (d->current_async != QXL_UNDEFINED_IO) { 1566 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1567 io_port, d->current_async); 1568 qemu_mutex_unlock(&d->async_lock); 1569 return; 1570 } 1571 d->current_async = orig_io_port; 1572 qemu_mutex_unlock(&d->async_lock); 1573 break; 1574 default: 1575 break; 1576 } 1577 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), 1578 addr, io_port_to_string(addr), 1579 val, size, async); 1580 1581 switch (io_port) { 1582 case QXL_IO_UPDATE_AREA: 1583 { 1584 QXLCookie *cookie = NULL; 1585 QXLRect update = d->ram->update_area; 1586 1587 if (d->ram->update_surface > d->ssd.num_surfaces) { 1588 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1589 d->ram->update_surface); 1590 break; 1591 } 1592 if (update.left >= update.right || update.top >= update.bottom || 1593 update.left < 0 || update.top < 0) { 1594 qxl_set_guest_bug(d, 1595 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1596 update.left, update.top, update.right, update.bottom); 1597 if (update.left == update.right || update.top == update.bottom) { 1598 /* old drivers may provide empty area, keep going */ 1599 qxl_clear_guest_bug(d); 1600 goto cancel_async; 1601 } 1602 break; 1603 } 1604 if (async == QXL_ASYNC) { 1605 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1606 QXL_IO_UPDATE_AREA_ASYNC); 1607 cookie->u.area = update; 1608 } 1609 qxl_spice_update_area(d, d->ram->update_surface, 1610 cookie ? &cookie->u.area : &update, 1611 NULL, 0, 0, async, cookie); 1612 break; 1613 } 1614 case QXL_IO_NOTIFY_CMD: 1615 qemu_spice_wakeup(&d->ssd); 1616 break; 1617 case QXL_IO_NOTIFY_CURSOR: 1618 qemu_spice_wakeup(&d->ssd); 1619 break; 1620 case QXL_IO_UPDATE_IRQ: 1621 qxl_update_irq(d); 1622 break; 1623 case QXL_IO_NOTIFY_OOM: 1624 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1625 break; 1626 } 1627 d->oom_running = 1; 1628 qxl_spice_oom(d); 1629 d->oom_running = 0; 1630 break; 1631 case QXL_IO_SET_MODE: 1632 qxl_set_mode(d, val, 0); 1633 break; 1634 case QXL_IO_LOG: 1635 trace_qxl_io_log(d->id, d->ram->log_buf); 1636 if (d->guestdebug) { 1637 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1638 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf); 1639 } 1640 break; 1641 case QXL_IO_RESET: 1642 qxl_hard_reset(d, 0); 1643 break; 1644 case QXL_IO_MEMSLOT_ADD: 1645 if (val >= NUM_MEMSLOTS) { 1646 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1647 break; 1648 } 1649 if (d->guest_slots[val].active) { 1650 qxl_set_guest_bug(d, 1651 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1652 break; 1653 } 1654 d->guest_slots[val].slot = d->ram->mem_slot; 1655 qxl_add_memslot(d, val, 0, async); 1656 break; 1657 case QXL_IO_MEMSLOT_DEL: 1658 if (val >= NUM_MEMSLOTS) { 1659 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1660 break; 1661 } 1662 qxl_del_memslot(d, val); 1663 break; 1664 case QXL_IO_CREATE_PRIMARY: 1665 if (val != 0) { 1666 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1667 async); 1668 goto cancel_async; 1669 } 1670 d->guest_primary.surface = d->ram->create_surface; 1671 qxl_create_guest_primary(d, 0, async); 1672 break; 1673 case QXL_IO_DESTROY_PRIMARY: 1674 if (val != 0) { 1675 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1676 async); 1677 goto cancel_async; 1678 } 1679 if (!qxl_destroy_primary(d, async)) { 1680 trace_qxl_io_destroy_primary_ignored(d->id, 1681 qxl_mode_to_string(d->mode)); 1682 goto cancel_async; 1683 } 1684 break; 1685 case QXL_IO_DESTROY_SURFACE_WAIT: 1686 if (val >= d->ssd.num_surfaces) { 1687 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1688 "%" PRIu64 " >= NUM_SURFACES", async, val); 1689 goto cancel_async; 1690 } 1691 qxl_spice_destroy_surface_wait(d, val, async); 1692 break; 1693 case QXL_IO_FLUSH_RELEASE: { 1694 QXLReleaseRing *ring = &d->ram->release_ring; 1695 if (ring->prod - ring->cons + 1 == ring->num_items) { 1696 fprintf(stderr, 1697 "ERROR: no flush, full release ring [p%d,%dc]\n", 1698 ring->prod, ring->cons); 1699 } 1700 qxl_push_free_res(d, 1 /* flush */); 1701 break; 1702 } 1703 case QXL_IO_FLUSH_SURFACES_ASYNC: 1704 qxl_spice_flush_surfaces_async(d); 1705 break; 1706 case QXL_IO_DESTROY_ALL_SURFACES: 1707 d->mode = QXL_MODE_UNDEFINED; 1708 qxl_spice_destroy_surfaces(d, async); 1709 break; 1710 case QXL_IO_MONITORS_CONFIG_ASYNC: 1711 qxl_spice_monitors_config_async(d, 0); 1712 break; 1713 default: 1714 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1715 } 1716 return; 1717 cancel_async: 1718 if (async) { 1719 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1720 qemu_mutex_lock(&d->async_lock); 1721 d->current_async = QXL_UNDEFINED_IO; 1722 qemu_mutex_unlock(&d->async_lock); 1723 } 1724 } 1725 1726 static uint64_t ioport_read(void *opaque, hwaddr addr, 1727 unsigned size) 1728 { 1729 PCIQXLDevice *qxl = opaque; 1730 1731 trace_qxl_io_read_unexpected(qxl->id); 1732 return 0xff; 1733 } 1734 1735 static const MemoryRegionOps qxl_io_ops = { 1736 .read = ioport_read, 1737 .write = ioport_write, 1738 .valid = { 1739 .min_access_size = 1, 1740 .max_access_size = 1, 1741 }, 1742 }; 1743 1744 static void qxl_update_irq_bh(void *opaque) 1745 { 1746 PCIQXLDevice *d = opaque; 1747 qxl_update_irq(d); 1748 } 1749 1750 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1751 { 1752 uint32_t old_pending; 1753 uint32_t le_events = cpu_to_le32(events); 1754 1755 trace_qxl_send_events(d->id, events); 1756 if (!qemu_spice_display_is_running(&d->ssd)) { 1757 /* spice-server tracks guest running state and should not do this */ 1758 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1759 __func__); 1760 trace_qxl_send_events_vm_stopped(d->id, events); 1761 return; 1762 } 1763 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events); 1764 if ((old_pending & le_events) == le_events) { 1765 return; 1766 } 1767 qemu_bh_schedule(d->update_irq); 1768 } 1769 1770 /* graphics console */ 1771 1772 static void qxl_hw_update(void *opaque) 1773 { 1774 PCIQXLDevice *qxl = opaque; 1775 1776 qxl_render_update(qxl); 1777 } 1778 1779 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1780 { 1781 uintptr_t vram_start; 1782 int i; 1783 1784 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1785 return; 1786 } 1787 1788 /* dirty the primary surface */ 1789 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, 1790 qxl->shadow_rom.surface0_area_size); 1791 1792 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); 1793 1794 /* dirty the off-screen surfaces */ 1795 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1796 QXLSurfaceCmd *cmd; 1797 intptr_t surface_offset; 1798 int surface_size; 1799 1800 if (qxl->guest_surfaces.cmds[i] == 0) { 1801 continue; 1802 } 1803 1804 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1805 MEMSLOT_GROUP_GUEST); 1806 assert(cmd); 1807 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1808 surface_offset = (intptr_t)qxl_phys2virt(qxl, 1809 cmd->u.surface_create.data, 1810 MEMSLOT_GROUP_GUEST); 1811 assert(surface_offset); 1812 surface_offset -= vram_start; 1813 surface_size = cmd->u.surface_create.height * 1814 abs(cmd->u.surface_create.stride); 1815 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); 1816 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); 1817 } 1818 } 1819 1820 static void qxl_vm_change_state_handler(void *opaque, int running, 1821 RunState state) 1822 { 1823 PCIQXLDevice *qxl = opaque; 1824 1825 if (running) { 1826 /* 1827 * if qxl_send_events was called from spice server context before 1828 * migration ended, qxl_update_irq for these events might not have been 1829 * called 1830 */ 1831 qxl_update_irq(qxl); 1832 } else { 1833 /* make sure surfaces are saved before migration */ 1834 qxl_dirty_surfaces(qxl); 1835 } 1836 } 1837 1838 /* display change listener */ 1839 1840 static void display_update(DisplayChangeListener *dcl, 1841 int x, int y, int w, int h) 1842 { 1843 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1844 1845 if (qxl->mode == QXL_MODE_VGA) { 1846 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 1847 } 1848 } 1849 1850 static void display_switch(DisplayChangeListener *dcl, 1851 struct DisplaySurface *surface) 1852 { 1853 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1854 1855 qxl->ssd.ds = surface; 1856 if (qxl->mode == QXL_MODE_VGA) { 1857 qemu_spice_display_switch(&qxl->ssd, surface); 1858 } 1859 } 1860 1861 static void display_refresh(DisplayChangeListener *dcl) 1862 { 1863 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1864 1865 if (qxl->mode == QXL_MODE_VGA) { 1866 qemu_spice_display_refresh(&qxl->ssd); 1867 } 1868 } 1869 1870 static DisplayChangeListenerOps display_listener_ops = { 1871 .dpy_name = "spice/qxl", 1872 .dpy_gfx_update = display_update, 1873 .dpy_gfx_switch = display_switch, 1874 .dpy_refresh = display_refresh, 1875 }; 1876 1877 static void qxl_init_ramsize(PCIQXLDevice *qxl) 1878 { 1879 /* vga mode framebuffer / primary surface (bar 0, first part) */ 1880 if (qxl->vgamem_size_mb < 8) { 1881 qxl->vgamem_size_mb = 8; 1882 } 1883 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; 1884 1885 /* vga ram (bar 0, total) */ 1886 if (qxl->ram_size_mb != -1) { 1887 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; 1888 } 1889 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 1890 qxl->vga.vram_size = qxl->vgamem_size * 2; 1891 } 1892 1893 /* vram32 (surfaces, 32bit, bar 1) */ 1894 if (qxl->vram32_size_mb != -1) { 1895 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; 1896 } 1897 if (qxl->vram32_size < 4096) { 1898 qxl->vram32_size = 4096; 1899 } 1900 1901 /* vram (surfaces, 64bit, bar 4+5) */ 1902 if (qxl->vram_size_mb != -1) { 1903 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; 1904 } 1905 if (qxl->vram_size < qxl->vram32_size) { 1906 qxl->vram_size = qxl->vram32_size; 1907 } 1908 1909 if (qxl->revision == 1) { 1910 qxl->vram32_size = 4096; 1911 qxl->vram_size = 4096; 1912 } 1913 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1); 1914 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); 1915 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); 1916 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); 1917 } 1918 1919 static int qxl_init_common(PCIQXLDevice *qxl) 1920 { 1921 uint8_t* config = qxl->pci.config; 1922 uint32_t pci_device_rev; 1923 uint32_t io_size; 1924 1925 qxl->mode = QXL_MODE_UNDEFINED; 1926 qxl->generation = 1; 1927 qxl->num_memslots = NUM_MEMSLOTS; 1928 qemu_mutex_init(&qxl->track_lock); 1929 qemu_mutex_init(&qxl->async_lock); 1930 qxl->current_async = QXL_UNDEFINED_IO; 1931 qxl->guest_bug = 0; 1932 1933 switch (qxl->revision) { 1934 case 1: /* spice 0.4 -- qxl-1 */ 1935 pci_device_rev = QXL_REVISION_STABLE_V04; 1936 io_size = 8; 1937 break; 1938 case 2: /* spice 0.6 -- qxl-2 */ 1939 pci_device_rev = QXL_REVISION_STABLE_V06; 1940 io_size = 16; 1941 break; 1942 case 3: /* qxl-3 */ 1943 pci_device_rev = QXL_REVISION_STABLE_V10; 1944 io_size = 32; /* PCI region size must be pow2 */ 1945 break; 1946 case 4: /* qxl-4 */ 1947 pci_device_rev = QXL_REVISION_STABLE_V12; 1948 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); 1949 break; 1950 default: 1951 error_report("Invalid revision %d for qxl device (max %d)", 1952 qxl->revision, QXL_DEFAULT_REVISION); 1953 return -1; 1954 } 1955 1956 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 1957 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 1958 1959 qxl->rom_size = qxl_rom_size(); 1960 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", 1961 qxl->rom_size, &error_abort); 1962 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); 1963 init_qxl_rom(qxl); 1964 init_qxl_ram(qxl); 1965 1966 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 1967 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", 1968 qxl->vram_size, &error_abort); 1969 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); 1970 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32", 1971 &qxl->vram_bar, 0, qxl->vram32_size); 1972 1973 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl, 1974 "qxl-ioports", io_size); 1975 if (qxl->id == 0) { 1976 vga_dirty_log_start(&qxl->vga); 1977 } 1978 memory_region_set_flush_coalesced(&qxl->io_bar); 1979 1980 1981 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 1982 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 1983 1984 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 1985 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 1986 1987 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 1988 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 1989 1990 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 1991 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 1992 1993 if (qxl->vram32_size < qxl->vram_size) { 1994 /* 1995 * Make the 64bit vram bar show up only in case it is 1996 * configured to be larger than the 32bit vram bar. 1997 */ 1998 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 1999 PCI_BASE_ADDRESS_SPACE_MEMORY | 2000 PCI_BASE_ADDRESS_MEM_TYPE_64 | 2001 PCI_BASE_ADDRESS_MEM_PREFETCH, 2002 &qxl->vram_bar); 2003 } 2004 2005 /* print pci bar details */ 2006 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", 2007 qxl->id == 0 ? "pri" : "sec", 2008 qxl->vga.vram_size / (1024*1024)); 2009 dprint(qxl, 1, "vram/32: %d MB [region 1]\n", 2010 qxl->vram32_size / (1024*1024)); 2011 dprint(qxl, 1, "vram/64: %d MB %s\n", 2012 qxl->vram_size / (1024*1024), 2013 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2014 2015 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2016 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) { 2017 error_report("qxl interface %d.%d not supported by spice-server", 2018 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2019 return -1; 2020 } 2021 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2022 2023 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl); 2024 qxl_reset_state(qxl); 2025 2026 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2027 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd); 2028 2029 return 0; 2030 } 2031 2032 static int qxl_init_primary(PCIDevice *dev) 2033 { 2034 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2035 VGACommonState *vga = &qxl->vga; 2036 int rc; 2037 2038 qxl->id = 0; 2039 qxl_init_ramsize(qxl); 2040 vga->vbe_size = qxl->vgamem_size; 2041 vga->vram_size_mb = qxl->vga.vram_size >> 20; 2042 vga_common_init(vga, OBJECT(dev), true); 2043 vga_init(vga, OBJECT(dev), 2044 pci_address_space(dev), pci_address_space_io(dev), false); 2045 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list, 2046 vga, "vga"); 2047 portio_list_set_flush_coalesced(&qxl->vga_port_list); 2048 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0); 2049 2050 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2051 qemu_spice_display_init_common(&qxl->ssd); 2052 2053 rc = qxl_init_common(qxl); 2054 if (rc != 0) { 2055 return rc; 2056 } 2057 2058 qxl->ssd.dcl.ops = &display_listener_ops; 2059 qxl->ssd.dcl.con = vga->con; 2060 register_displaychangelistener(&qxl->ssd.dcl); 2061 return rc; 2062 } 2063 2064 static int qxl_init_secondary(PCIDevice *dev) 2065 { 2066 static int device_id = 1; 2067 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2068 2069 qxl->id = device_id++; 2070 qxl_init_ramsize(qxl); 2071 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram", 2072 qxl->vga.vram_size, &error_abort); 2073 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); 2074 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2075 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2076 2077 return qxl_init_common(qxl); 2078 } 2079 2080 static void qxl_pre_save(void *opaque) 2081 { 2082 PCIQXLDevice* d = opaque; 2083 uint8_t *ram_start = d->vga.vram_ptr; 2084 2085 trace_qxl_pre_save(d->id); 2086 if (d->last_release == NULL) { 2087 d->last_release_offset = 0; 2088 } else { 2089 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2090 } 2091 assert(d->last_release_offset < d->vga.vram_size); 2092 } 2093 2094 static int qxl_pre_load(void *opaque) 2095 { 2096 PCIQXLDevice* d = opaque; 2097 2098 trace_qxl_pre_load(d->id); 2099 qxl_hard_reset(d, 1); 2100 qxl_exit_vga_mode(d); 2101 return 0; 2102 } 2103 2104 static void qxl_create_memslots(PCIQXLDevice *d) 2105 { 2106 int i; 2107 2108 for (i = 0; i < NUM_MEMSLOTS; i++) { 2109 if (!d->guest_slots[i].active) { 2110 continue; 2111 } 2112 qxl_add_memslot(d, i, 0, QXL_SYNC); 2113 } 2114 } 2115 2116 static int qxl_post_load(void *opaque, int version) 2117 { 2118 PCIQXLDevice* d = opaque; 2119 uint8_t *ram_start = d->vga.vram_ptr; 2120 QXLCommandExt *cmds; 2121 int in, out, newmode; 2122 2123 assert(d->last_release_offset < d->vga.vram_size); 2124 if (d->last_release_offset == 0) { 2125 d->last_release = NULL; 2126 } else { 2127 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2128 } 2129 2130 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2131 2132 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2133 newmode = d->mode; 2134 d->mode = QXL_MODE_UNDEFINED; 2135 2136 switch (newmode) { 2137 case QXL_MODE_UNDEFINED: 2138 qxl_create_memslots(d); 2139 break; 2140 case QXL_MODE_VGA: 2141 qxl_create_memslots(d); 2142 qxl_enter_vga_mode(d); 2143 break; 2144 case QXL_MODE_NATIVE: 2145 qxl_create_memslots(d); 2146 qxl_create_guest_primary(d, 1, QXL_SYNC); 2147 2148 /* replay surface-create and cursor-set commands */ 2149 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1)); 2150 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2151 if (d->guest_surfaces.cmds[in] == 0) { 2152 continue; 2153 } 2154 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2155 cmds[out].cmd.type = QXL_CMD_SURFACE; 2156 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2157 out++; 2158 } 2159 if (d->guest_cursor) { 2160 cmds[out].cmd.data = d->guest_cursor; 2161 cmds[out].cmd.type = QXL_CMD_CURSOR; 2162 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2163 out++; 2164 } 2165 qxl_spice_loadvm_commands(d, cmds, out); 2166 g_free(cmds); 2167 if (d->guest_monitors_config) { 2168 qxl_spice_monitors_config_async(d, 1); 2169 } 2170 break; 2171 case QXL_MODE_COMPAT: 2172 /* note: no need to call qxl_create_memslots, qxl_set_mode 2173 * creates the mem slot. */ 2174 qxl_set_mode(d, d->shadow_rom.mode, 1); 2175 break; 2176 } 2177 return 0; 2178 } 2179 2180 #define QXL_SAVE_VERSION 21 2181 2182 static bool qxl_monitors_config_needed(void *opaque) 2183 { 2184 PCIQXLDevice *qxl = opaque; 2185 2186 return qxl->guest_monitors_config != 0; 2187 } 2188 2189 2190 static VMStateDescription qxl_memslot = { 2191 .name = "qxl-memslot", 2192 .version_id = QXL_SAVE_VERSION, 2193 .minimum_version_id = QXL_SAVE_VERSION, 2194 .fields = (VMStateField[]) { 2195 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2196 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2197 VMSTATE_UINT32(active, struct guest_slots), 2198 VMSTATE_END_OF_LIST() 2199 } 2200 }; 2201 2202 static VMStateDescription qxl_surface = { 2203 .name = "qxl-surface", 2204 .version_id = QXL_SAVE_VERSION, 2205 .minimum_version_id = QXL_SAVE_VERSION, 2206 .fields = (VMStateField[]) { 2207 VMSTATE_UINT32(width, QXLSurfaceCreate), 2208 VMSTATE_UINT32(height, QXLSurfaceCreate), 2209 VMSTATE_INT32(stride, QXLSurfaceCreate), 2210 VMSTATE_UINT32(format, QXLSurfaceCreate), 2211 VMSTATE_UINT32(position, QXLSurfaceCreate), 2212 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2213 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2214 VMSTATE_UINT32(type, QXLSurfaceCreate), 2215 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2216 VMSTATE_END_OF_LIST() 2217 } 2218 }; 2219 2220 static VMStateDescription qxl_vmstate_monitors_config = { 2221 .name = "qxl/monitors-config", 2222 .version_id = 1, 2223 .minimum_version_id = 1, 2224 .fields = (VMStateField[]) { 2225 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2226 VMSTATE_END_OF_LIST() 2227 }, 2228 }; 2229 2230 static VMStateDescription qxl_vmstate = { 2231 .name = "qxl", 2232 .version_id = QXL_SAVE_VERSION, 2233 .minimum_version_id = QXL_SAVE_VERSION, 2234 .pre_save = qxl_pre_save, 2235 .pre_load = qxl_pre_load, 2236 .post_load = qxl_post_load, 2237 .fields = (VMStateField[]) { 2238 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2239 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2240 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2241 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2242 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2243 VMSTATE_UINT32(mode, PCIQXLDevice), 2244 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2245 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), 2246 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2247 qxl_memslot, struct guest_slots), 2248 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2249 qxl_surface, QXLSurfaceCreate), 2250 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), 2251 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2252 ssd.num_surfaces, 0, 2253 vmstate_info_uint64, uint64_t), 2254 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2255 VMSTATE_END_OF_LIST() 2256 }, 2257 .subsections = (VMStateSubsection[]) { 2258 { 2259 .vmsd = &qxl_vmstate_monitors_config, 2260 .needed = qxl_monitors_config_needed, 2261 }, { 2262 /* empty */ 2263 } 2264 } 2265 }; 2266 2267 static Property qxl_properties[] = { 2268 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 2269 64 * 1024 * 1024), 2270 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, 2271 64 * 1024 * 1024), 2272 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2273 QXL_DEFAULT_REVISION), 2274 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2275 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2276 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2277 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2278 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2279 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2280 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2281 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2282 DEFINE_PROP_END_OF_LIST(), 2283 }; 2284 2285 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2286 { 2287 DeviceClass *dc = DEVICE_CLASS(klass); 2288 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2289 2290 k->init = qxl_init_primary; 2291 k->romfile = "vgabios-qxl.bin"; 2292 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2293 k->device_id = QXL_DEVICE_ID_STABLE; 2294 k->class_id = PCI_CLASS_DISPLAY_VGA; 2295 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2296 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2297 dc->reset = qxl_reset_handler; 2298 dc->vmsd = &qxl_vmstate; 2299 dc->props = qxl_properties; 2300 dc->hotpluggable = false; 2301 } 2302 2303 static const TypeInfo qxl_primary_info = { 2304 .name = "qxl-vga", 2305 .parent = TYPE_PCI_DEVICE, 2306 .instance_size = sizeof(PCIQXLDevice), 2307 .class_init = qxl_primary_class_init, 2308 }; 2309 2310 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2311 { 2312 DeviceClass *dc = DEVICE_CLASS(klass); 2313 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2314 2315 k->init = qxl_init_secondary; 2316 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2317 k->device_id = QXL_DEVICE_ID_STABLE; 2318 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2319 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2320 dc->desc = "Spice QXL GPU (secondary)"; 2321 dc->reset = qxl_reset_handler; 2322 dc->vmsd = &qxl_vmstate; 2323 dc->props = qxl_properties; 2324 } 2325 2326 static const TypeInfo qxl_secondary_info = { 2327 .name = "qxl", 2328 .parent = TYPE_PCI_DEVICE, 2329 .instance_size = sizeof(PCIQXLDevice), 2330 .class_init = qxl_secondary_class_init, 2331 }; 2332 2333 static void qxl_register_types(void) 2334 { 2335 type_register_static(&qxl_primary_info); 2336 type_register_static(&qxl_secondary_info); 2337 } 2338 2339 type_init(qxl_register_types) 2340