xref: /openbmc/qemu/hw/display/qxl.c (revision db725815985654007ade0fd53590d613fd657208)
1 /*
2  * Copyright (C) 2010 Red Hat, Inc.
3  *
4  * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5  * maintained by Gerd Hoffmann <kraxel@redhat.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 or
10  * (at your option) version 3 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include <zlib.h>
24 
25 #include "qapi/error.h"
26 #include "qemu/timer.h"
27 #include "qemu/queue.h"
28 #include "qemu/atomic.h"
29 #include "qemu/main-loop.h"
30 #include "qemu/module.h"
31 #include "sysemu/sysemu.h"
32 #include "migration/blocker.h"
33 #include "migration/vmstate.h"
34 #include "trace.h"
35 
36 #include "qxl.h"
37 
38 #undef SPICE_RING_CONS_ITEM
39 #define SPICE_RING_CONS_ITEM(qxl, r, ret) {                             \
40         uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r);           \
41         if (cons >= ARRAY_SIZE((r)->items)) {                           \
42             qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
43                           "%u >= %zu", cons, ARRAY_SIZE((r)->items));   \
44             ret = NULL;                                                 \
45         } else {                                                        \
46             ret = &(r)->items[cons].el;                                 \
47         }                                                               \
48     }
49 
50 #undef ALIGN
51 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
52 
53 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
54 
55 #define QXL_MODE(_x, _y, _b, _o)                  \
56     {   .x_res = _x,                              \
57         .y_res = _y,                              \
58         .bits  = _b,                              \
59         .stride = (_x) * (_b) / 8,                \
60         .x_mili = PIXEL_SIZE * (_x),              \
61         .y_mili = PIXEL_SIZE * (_y),              \
62         .orientation = _o,                        \
63     }
64 
65 #define QXL_MODE_16_32(x_res, y_res, orientation) \
66     QXL_MODE(x_res, y_res, 16, orientation),      \
67     QXL_MODE(x_res, y_res, 32, orientation)
68 
69 #define QXL_MODE_EX(x_res, y_res)                 \
70     QXL_MODE_16_32(x_res, y_res, 0),              \
71     QXL_MODE_16_32(x_res, y_res, 1)
72 
73 static QXLMode qxl_modes[] = {
74     QXL_MODE_EX(640, 480),
75     QXL_MODE_EX(800, 480),
76     QXL_MODE_EX(800, 600),
77     QXL_MODE_EX(832, 624),
78     QXL_MODE_EX(960, 640),
79     QXL_MODE_EX(1024, 600),
80     QXL_MODE_EX(1024, 768),
81     QXL_MODE_EX(1152, 864),
82     QXL_MODE_EX(1152, 870),
83     QXL_MODE_EX(1280, 720),
84     QXL_MODE_EX(1280, 760),
85     QXL_MODE_EX(1280, 768),
86     QXL_MODE_EX(1280, 800),
87     QXL_MODE_EX(1280, 960),
88     QXL_MODE_EX(1280, 1024),
89     QXL_MODE_EX(1360, 768),
90     QXL_MODE_EX(1366, 768),
91     QXL_MODE_EX(1400, 1050),
92     QXL_MODE_EX(1440, 900),
93     QXL_MODE_EX(1600, 900),
94     QXL_MODE_EX(1600, 1200),
95     QXL_MODE_EX(1680, 1050),
96     QXL_MODE_EX(1920, 1080),
97     /* these modes need more than 8 MB video memory */
98     QXL_MODE_EX(1920, 1200),
99     QXL_MODE_EX(1920, 1440),
100     QXL_MODE_EX(2000, 2000),
101     QXL_MODE_EX(2048, 1536),
102     QXL_MODE_EX(2048, 2048),
103     QXL_MODE_EX(2560, 1440),
104     QXL_MODE_EX(2560, 1600),
105     /* these modes need more than 16 MB video memory */
106     QXL_MODE_EX(2560, 2048),
107     QXL_MODE_EX(2800, 2100),
108     QXL_MODE_EX(3200, 2400),
109     /* these modes need more than 32 MB video memory */
110     QXL_MODE_EX(3840, 2160), /* 4k mainstream */
111     QXL_MODE_EX(4096, 2160), /* 4k            */
112     /* these modes need more than 64 MB video memory */
113     QXL_MODE_EX(7680, 4320), /* 8k mainstream */
114     /* these modes need more than 128 MB video memory */
115     QXL_MODE_EX(8192, 4320), /* 8k            */
116 };
117 
118 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
119 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
120 static void qxl_reset_memslots(PCIQXLDevice *d);
121 static void qxl_reset_surfaces(PCIQXLDevice *d);
122 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
123 
124 static void qxl_hw_update(void *opaque);
125 
126 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
127 {
128     trace_qxl_set_guest_bug(qxl->id);
129     qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
130     qxl->guest_bug = 1;
131     if (qxl->guestdebug) {
132         va_list ap;
133         va_start(ap, msg);
134         fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
135         vfprintf(stderr, msg, ap);
136         fprintf(stderr, "\n");
137         va_end(ap);
138     }
139 }
140 
141 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
142 {
143     qxl->guest_bug = 0;
144 }
145 
146 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
147                            struct QXLRect *area, struct QXLRect *dirty_rects,
148                            uint32_t num_dirty_rects,
149                            uint32_t clear_dirty_region,
150                            qxl_async_io async, struct QXLCookie *cookie)
151 {
152     trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
153                                 area->top, area->bottom);
154     trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
155                                      clear_dirty_region);
156     if (async == QXL_SYNC) {
157         spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
158                         dirty_rects, num_dirty_rects, clear_dirty_region);
159     } else {
160         assert(cookie != NULL);
161         spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
162                                     clear_dirty_region, (uintptr_t)cookie);
163     }
164 }
165 
166 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
167                                                     uint32_t id)
168 {
169     trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
170     qemu_mutex_lock(&qxl->track_lock);
171     qxl->guest_surfaces.cmds[id] = 0;
172     qxl->guest_surfaces.count--;
173     qemu_mutex_unlock(&qxl->track_lock);
174 }
175 
176 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
177                                            qxl_async_io async)
178 {
179     QXLCookie *cookie;
180 
181     trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
182     if (async) {
183         cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
184                                 QXL_IO_DESTROY_SURFACE_ASYNC);
185         cookie->u.surface_id = id;
186         spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
187     } else {
188         spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
189         qxl_spice_destroy_surface_wait_complete(qxl, id);
190     }
191 }
192 
193 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
194 {
195     trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
196                                          qxl->num_free_res);
197     spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
198         (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
199                                   QXL_IO_FLUSH_SURFACES_ASYNC));
200 }
201 
202 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
203                                uint32_t count)
204 {
205     trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
206     spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
207 }
208 
209 void qxl_spice_oom(PCIQXLDevice *qxl)
210 {
211     trace_qxl_spice_oom(qxl->id);
212     spice_qxl_oom(&qxl->ssd.qxl);
213 }
214 
215 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
216 {
217     trace_qxl_spice_reset_memslots(qxl->id);
218     spice_qxl_reset_memslots(&qxl->ssd.qxl);
219 }
220 
221 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
222 {
223     trace_qxl_spice_destroy_surfaces_complete(qxl->id);
224     qemu_mutex_lock(&qxl->track_lock);
225     memset(qxl->guest_surfaces.cmds, 0,
226            sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
227     qxl->guest_surfaces.count = 0;
228     qemu_mutex_unlock(&qxl->track_lock);
229 }
230 
231 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
232 {
233     trace_qxl_spice_destroy_surfaces(qxl->id, async);
234     if (async) {
235         spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
236                 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
237                                           QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
238     } else {
239         spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
240         qxl_spice_destroy_surfaces_complete(qxl);
241     }
242 }
243 
244 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
245 {
246     QXLMonitorsConfig *cfg;
247 
248     trace_qxl_spice_monitors_config(qxl->id);
249     if (replay) {
250         /*
251          * don't use QXL_COOKIE_TYPE_IO:
252          *  - we are not running yet (post_load), we will assert
253          *    in send_events
254          *  - this is not a guest io, but a reply, so async_io isn't set.
255          */
256         spice_qxl_monitors_config_async(&qxl->ssd.qxl,
257                 qxl->guest_monitors_config,
258                 MEMSLOT_GROUP_GUEST,
259                 (uintptr_t)qxl_cookie_new(
260                     QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
261                     0));
262     } else {
263 /* >= release 0.12.6, < release 0.14.2 */
264 #if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02
265         if (qxl->max_outputs) {
266             spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
267         }
268 #endif
269         qxl->guest_monitors_config = qxl->ram->monitors_config;
270         spice_qxl_monitors_config_async(&qxl->ssd.qxl,
271                 qxl->ram->monitors_config,
272                 MEMSLOT_GROUP_GUEST,
273                 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
274                                           QXL_IO_MONITORS_CONFIG_ASYNC));
275     }
276 
277     cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST);
278     if (cfg != NULL && cfg->count == 1) {
279         qxl->guest_primary.resized = 1;
280         qxl->guest_head0_width  = cfg->heads[0].width;
281         qxl->guest_head0_height = cfg->heads[0].height;
282     } else {
283         qxl->guest_head0_width  = 0;
284         qxl->guest_head0_height = 0;
285     }
286 }
287 
288 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
289 {
290     trace_qxl_spice_reset_image_cache(qxl->id);
291     spice_qxl_reset_image_cache(&qxl->ssd.qxl);
292 }
293 
294 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
295 {
296     trace_qxl_spice_reset_cursor(qxl->id);
297     spice_qxl_reset_cursor(&qxl->ssd.qxl);
298     qemu_mutex_lock(&qxl->track_lock);
299     qxl->guest_cursor = 0;
300     qemu_mutex_unlock(&qxl->track_lock);
301     if (qxl->ssd.cursor) {
302         cursor_put(qxl->ssd.cursor);
303     }
304     qxl->ssd.cursor = cursor_builtin_hidden();
305 }
306 
307 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
308 {
309     /*
310      * zlib xors the seed with 0xffffffff, and xors the result
311      * again with 0xffffffff; Both are not done with linux's crc32,
312      * which we want to be compatible with, so undo that.
313      */
314     return crc32(0xffffffff, p, len) ^ 0xffffffff;
315 }
316 
317 static ram_addr_t qxl_rom_size(void)
318 {
319 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
320 #define QXL_ROM_SZ 8192
321 
322     QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
323     return QXL_ROM_SZ;
324 }
325 
326 static void init_qxl_rom(PCIQXLDevice *d)
327 {
328     QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
329     QXLModes *modes = (QXLModes *)(rom + 1);
330     uint32_t ram_header_size;
331     uint32_t surface0_area_size;
332     uint32_t num_pages;
333     uint32_t fb;
334     int i, n;
335 
336     memset(rom, 0, d->rom_size);
337 
338     rom->magic         = cpu_to_le32(QXL_ROM_MAGIC);
339     rom->id            = cpu_to_le32(d->id);
340     rom->log_level     = cpu_to_le32(d->guestdebug);
341     rom->modes_offset  = cpu_to_le32(sizeof(QXLRom));
342 
343     rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
344     rom->slot_id_bits  = MEMSLOT_SLOT_BITS;
345     rom->slots_start   = 1;
346     rom->slots_end     = NUM_MEMSLOTS - 1;
347     rom->n_surfaces    = cpu_to_le32(d->ssd.num_surfaces);
348 
349     for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
350         fb = qxl_modes[i].y_res * qxl_modes[i].stride;
351         if (fb > d->vgamem_size) {
352             continue;
353         }
354         modes->modes[n].id          = cpu_to_le32(i);
355         modes->modes[n].x_res       = cpu_to_le32(qxl_modes[i].x_res);
356         modes->modes[n].y_res       = cpu_to_le32(qxl_modes[i].y_res);
357         modes->modes[n].bits        = cpu_to_le32(qxl_modes[i].bits);
358         modes->modes[n].stride      = cpu_to_le32(qxl_modes[i].stride);
359         modes->modes[n].x_mili      = cpu_to_le32(qxl_modes[i].x_mili);
360         modes->modes[n].y_mili      = cpu_to_le32(qxl_modes[i].y_mili);
361         modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
362         n++;
363     }
364     modes->n_modes     = cpu_to_le32(n);
365 
366     ram_header_size    = ALIGN(sizeof(QXLRam), 4096);
367     surface0_area_size = ALIGN(d->vgamem_size, 4096);
368     num_pages          = d->vga.vram_size;
369     num_pages         -= ram_header_size;
370     num_pages         -= surface0_area_size;
371     num_pages          = num_pages / QXL_PAGE_SIZE;
372 
373     assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
374 
375     rom->draw_area_offset   = cpu_to_le32(0);
376     rom->surface0_area_size = cpu_to_le32(surface0_area_size);
377     rom->pages_offset       = cpu_to_le32(surface0_area_size);
378     rom->num_pages          = cpu_to_le32(num_pages);
379     rom->ram_header_offset  = cpu_to_le32(d->vga.vram_size - ram_header_size);
380 
381     if (d->xres && d->yres) {
382         /* needs linux kernel 4.12+ to work */
383         rom->client_monitors_config.count = 1;
384         rom->client_monitors_config.heads[0].left = 0;
385         rom->client_monitors_config.heads[0].top = 0;
386         rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
387         rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
388         rom->client_monitors_config_crc = qxl_crc32(
389             (const uint8_t *)&rom->client_monitors_config,
390             sizeof(rom->client_monitors_config));
391     }
392 
393     d->shadow_rom = *rom;
394     d->rom        = rom;
395     d->modes      = modes;
396 }
397 
398 static void init_qxl_ram(PCIQXLDevice *d)
399 {
400     uint8_t *buf;
401     uint32_t prod;
402     QXLReleaseRing *ring;
403 
404     buf = d->vga.vram_ptr;
405     d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
406     d->ram->magic       = cpu_to_le32(QXL_RAM_MAGIC);
407     d->ram->int_pending = cpu_to_le32(0);
408     d->ram->int_mask    = cpu_to_le32(0);
409     d->ram->update_surface = 0;
410     d->ram->monitors_config = 0;
411     SPICE_RING_INIT(&d->ram->cmd_ring);
412     SPICE_RING_INIT(&d->ram->cursor_ring);
413     SPICE_RING_INIT(&d->ram->release_ring);
414 
415     ring = &d->ram->release_ring;
416     prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
417     assert(prod < ARRAY_SIZE(ring->items));
418     ring->items[prod].el = 0;
419 
420     qxl_ring_set_dirty(d);
421 }
422 
423 /* can be called from spice server thread context */
424 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
425 {
426     memory_region_set_dirty(mr, addr, end - addr);
427 }
428 
429 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
430 {
431     qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
432 }
433 
434 /* called from spice server thread context only */
435 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
436 {
437     void *base = qxl->vga.vram_ptr;
438     intptr_t offset;
439 
440     offset = ptr - base;
441     assert(offset < qxl->vga.vram_size);
442     qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
443 }
444 
445 /* can be called from spice server thread context */
446 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
447 {
448     ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
449     ram_addr_t end  = qxl->vga.vram_size;
450     qxl_set_dirty(&qxl->vga.vram, addr, end);
451 }
452 
453 /*
454  * keep track of some command state, for savevm/loadvm.
455  * called from spice server thread context only
456  */
457 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
458 {
459     switch (le32_to_cpu(ext->cmd.type)) {
460     case QXL_CMD_SURFACE:
461     {
462         QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
463 
464         if (!cmd) {
465             return 1;
466         }
467         uint32_t id = le32_to_cpu(cmd->surface_id);
468 
469         if (id >= qxl->ssd.num_surfaces) {
470             qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
471                               qxl->ssd.num_surfaces);
472             return 1;
473         }
474         if (cmd->type == QXL_SURFACE_CMD_CREATE &&
475             (cmd->u.surface_create.stride & 0x03) != 0) {
476             qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
477                               cmd->u.surface_create.stride);
478             return 1;
479         }
480         qemu_mutex_lock(&qxl->track_lock);
481         if (cmd->type == QXL_SURFACE_CMD_CREATE) {
482             qxl->guest_surfaces.cmds[id] = ext->cmd.data;
483             qxl->guest_surfaces.count++;
484             if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
485                 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
486         }
487         if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
488             qxl->guest_surfaces.cmds[id] = 0;
489             qxl->guest_surfaces.count--;
490         }
491         qemu_mutex_unlock(&qxl->track_lock);
492         break;
493     }
494     case QXL_CMD_CURSOR:
495     {
496         QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
497 
498         if (!cmd) {
499             return 1;
500         }
501         if (cmd->type == QXL_CURSOR_SET) {
502             qemu_mutex_lock(&qxl->track_lock);
503             qxl->guest_cursor = ext->cmd.data;
504             qemu_mutex_unlock(&qxl->track_lock);
505         }
506         if (cmd->type == QXL_CURSOR_HIDE) {
507             qemu_mutex_lock(&qxl->track_lock);
508             qxl->guest_cursor = 0;
509             qemu_mutex_unlock(&qxl->track_lock);
510         }
511         break;
512     }
513     }
514     return 0;
515 }
516 
517 /* spice display interface callbacks */
518 
519 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
520 {
521     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
522 
523     trace_qxl_interface_attach_worker(qxl->id);
524 }
525 
526 static void interface_set_compression_level(QXLInstance *sin, int level)
527 {
528     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
529 
530     trace_qxl_interface_set_compression_level(qxl->id, level);
531     qxl->shadow_rom.compression_level = cpu_to_le32(level);
532     qxl->rom->compression_level = cpu_to_le32(level);
533     qxl_rom_set_dirty(qxl);
534 }
535 
536 #if SPICE_NEEDS_SET_MM_TIME
537 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
538 {
539     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
540 
541     if (!qemu_spice_display_is_running(&qxl->ssd)) {
542         return;
543     }
544 
545     trace_qxl_interface_set_mm_time(qxl->id, mm_time);
546     qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
547     qxl->rom->mm_clock = cpu_to_le32(mm_time);
548     qxl_rom_set_dirty(qxl);
549 }
550 #endif
551 
552 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
553 {
554     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
555 
556     trace_qxl_interface_get_init_info(qxl->id);
557     info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
558     info->memslot_id_bits = MEMSLOT_SLOT_BITS;
559     info->num_memslots = NUM_MEMSLOTS;
560     info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
561     info->internal_groupslot_id = 0;
562     info->qxl_ram_size =
563         le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
564     info->n_surfaces = qxl->ssd.num_surfaces;
565 }
566 
567 static const char *qxl_mode_to_string(int mode)
568 {
569     switch (mode) {
570     case QXL_MODE_COMPAT:
571         return "compat";
572     case QXL_MODE_NATIVE:
573         return "native";
574     case QXL_MODE_UNDEFINED:
575         return "undefined";
576     case QXL_MODE_VGA:
577         return "vga";
578     }
579     return "INVALID";
580 }
581 
582 static const char *io_port_to_string(uint32_t io_port)
583 {
584     if (io_port >= QXL_IO_RANGE_SIZE) {
585         return "out of range";
586     }
587     static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
588         [QXL_IO_NOTIFY_CMD]             = "QXL_IO_NOTIFY_CMD",
589         [QXL_IO_NOTIFY_CURSOR]          = "QXL_IO_NOTIFY_CURSOR",
590         [QXL_IO_UPDATE_AREA]            = "QXL_IO_UPDATE_AREA",
591         [QXL_IO_UPDATE_IRQ]             = "QXL_IO_UPDATE_IRQ",
592         [QXL_IO_NOTIFY_OOM]             = "QXL_IO_NOTIFY_OOM",
593         [QXL_IO_RESET]                  = "QXL_IO_RESET",
594         [QXL_IO_SET_MODE]               = "QXL_IO_SET_MODE",
595         [QXL_IO_LOG]                    = "QXL_IO_LOG",
596         [QXL_IO_MEMSLOT_ADD]            = "QXL_IO_MEMSLOT_ADD",
597         [QXL_IO_MEMSLOT_DEL]            = "QXL_IO_MEMSLOT_DEL",
598         [QXL_IO_DETACH_PRIMARY]         = "QXL_IO_DETACH_PRIMARY",
599         [QXL_IO_ATTACH_PRIMARY]         = "QXL_IO_ATTACH_PRIMARY",
600         [QXL_IO_CREATE_PRIMARY]         = "QXL_IO_CREATE_PRIMARY",
601         [QXL_IO_DESTROY_PRIMARY]        = "QXL_IO_DESTROY_PRIMARY",
602         [QXL_IO_DESTROY_SURFACE_WAIT]   = "QXL_IO_DESTROY_SURFACE_WAIT",
603         [QXL_IO_DESTROY_ALL_SURFACES]   = "QXL_IO_DESTROY_ALL_SURFACES",
604         [QXL_IO_UPDATE_AREA_ASYNC]      = "QXL_IO_UPDATE_AREA_ASYNC",
605         [QXL_IO_MEMSLOT_ADD_ASYNC]      = "QXL_IO_MEMSLOT_ADD_ASYNC",
606         [QXL_IO_CREATE_PRIMARY_ASYNC]   = "QXL_IO_CREATE_PRIMARY_ASYNC",
607         [QXL_IO_DESTROY_PRIMARY_ASYNC]  = "QXL_IO_DESTROY_PRIMARY_ASYNC",
608         [QXL_IO_DESTROY_SURFACE_ASYNC]  = "QXL_IO_DESTROY_SURFACE_ASYNC",
609         [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
610                                         = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
611         [QXL_IO_FLUSH_SURFACES_ASYNC]   = "QXL_IO_FLUSH_SURFACES_ASYNC",
612         [QXL_IO_FLUSH_RELEASE]          = "QXL_IO_FLUSH_RELEASE",
613         [QXL_IO_MONITORS_CONFIG_ASYNC]  = "QXL_IO_MONITORS_CONFIG_ASYNC",
614     };
615     return io_port_to_string[io_port];
616 }
617 
618 /* called from spice server thread context only */
619 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
620 {
621     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
622     SimpleSpiceUpdate *update;
623     QXLCommandRing *ring;
624     QXLCommand *cmd;
625     int notify, ret;
626 
627     trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
628 
629     switch (qxl->mode) {
630     case QXL_MODE_VGA:
631         ret = false;
632         qemu_mutex_lock(&qxl->ssd.lock);
633         update = QTAILQ_FIRST(&qxl->ssd.updates);
634         if (update != NULL) {
635             QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
636             *ext = update->ext;
637             ret = true;
638         }
639         qemu_mutex_unlock(&qxl->ssd.lock);
640         if (ret) {
641             trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
642             qxl_log_command(qxl, "vga", ext);
643         }
644         return ret;
645     case QXL_MODE_COMPAT:
646     case QXL_MODE_NATIVE:
647     case QXL_MODE_UNDEFINED:
648         ring = &qxl->ram->cmd_ring;
649         if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
650             return false;
651         }
652         SPICE_RING_CONS_ITEM(qxl, ring, cmd);
653         if (!cmd) {
654             return false;
655         }
656         ext->cmd      = *cmd;
657         ext->group_id = MEMSLOT_GROUP_GUEST;
658         ext->flags    = qxl->cmdflags;
659         SPICE_RING_POP(ring, notify);
660         qxl_ring_set_dirty(qxl);
661         if (notify) {
662             qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
663         }
664         qxl->guest_primary.commands++;
665         qxl_track_command(qxl, ext);
666         qxl_log_command(qxl, "cmd", ext);
667         {
668             /*
669              * Windows 8 drivers place qxl commands in the vram
670              * (instead of the ram) bar.  We can't live migrate such a
671              * guest, so add a migration blocker in case we detect
672              * this, to avoid triggering the assert in pre_save().
673              *
674              * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa
675              */
676             void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
677             if (msg != NULL && (
678                     msg < (void *)qxl->vga.vram_ptr ||
679                     msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) {
680                 if (!qxl->migration_blocker) {
681                     Error *local_err = NULL;
682                     error_setg(&qxl->migration_blocker,
683                                "qxl: guest bug: command not in ram bar");
684                     migrate_add_blocker(qxl->migration_blocker, &local_err);
685                     if (local_err) {
686                         error_report_err(local_err);
687                     }
688                 }
689             }
690         }
691         trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
692         return true;
693     default:
694         return false;
695     }
696 }
697 
698 /* called from spice server thread context only */
699 static int interface_req_cmd_notification(QXLInstance *sin)
700 {
701     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
702     int wait = 1;
703 
704     trace_qxl_ring_command_req_notification(qxl->id);
705     switch (qxl->mode) {
706     case QXL_MODE_COMPAT:
707     case QXL_MODE_NATIVE:
708     case QXL_MODE_UNDEFINED:
709         SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
710         qxl_ring_set_dirty(qxl);
711         break;
712     default:
713         /* nothing */
714         break;
715     }
716     return wait;
717 }
718 
719 /* called from spice server thread context only */
720 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
721 {
722     QXLReleaseRing *ring = &d->ram->release_ring;
723     uint32_t prod;
724     int notify;
725 
726 #define QXL_FREE_BUNCH_SIZE 32
727 
728     if (ring->prod - ring->cons + 1 == ring->num_items) {
729         /* ring full -- can't push */
730         return;
731     }
732     if (!flush && d->oom_running) {
733         /* collect everything from oom handler before pushing */
734         return;
735     }
736     if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
737         /* collect a bit more before pushing */
738         return;
739     }
740 
741     SPICE_RING_PUSH(ring, notify);
742     trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
743            d->guest_surfaces.count, d->num_free_res,
744            d->last_release, notify ? "yes" : "no");
745     trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
746            ring->num_items, ring->prod, ring->cons);
747     if (notify) {
748         qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
749     }
750 
751     ring = &d->ram->release_ring;
752     prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
753     if (prod >= ARRAY_SIZE(ring->items)) {
754         qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
755                           "%u >= %zu", prod, ARRAY_SIZE(ring->items));
756         return;
757     }
758     ring->items[prod].el = 0;
759     d->num_free_res = 0;
760     d->last_release = NULL;
761     qxl_ring_set_dirty(d);
762 }
763 
764 /* called from spice server thread context only */
765 static void interface_release_resource(QXLInstance *sin,
766                                        QXLReleaseInfoExt ext)
767 {
768     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
769     QXLReleaseRing *ring;
770     uint32_t prod;
771     uint64_t id;
772 
773     if (!ext.info) {
774         return;
775     }
776     if (ext.group_id == MEMSLOT_GROUP_HOST) {
777         /* host group -> vga mode update request */
778         QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
779         SimpleSpiceUpdate *update;
780         g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
781         update = container_of(cmdext, SimpleSpiceUpdate, ext);
782         qemu_spice_destroy_update(&qxl->ssd, update);
783         return;
784     }
785 
786     /*
787      * ext->info points into guest-visible memory
788      * pci bar 0, $command.release_info
789      */
790     ring = &qxl->ram->release_ring;
791     prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
792     if (prod >= ARRAY_SIZE(ring->items)) {
793         qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
794                           "%u >= %zu", prod, ARRAY_SIZE(ring->items));
795         return;
796     }
797     if (ring->items[prod].el == 0) {
798         /* stick head into the ring */
799         id = ext.info->id;
800         ext.info->next = 0;
801         qxl_ram_set_dirty(qxl, &ext.info->next);
802         ring->items[prod].el = id;
803         qxl_ring_set_dirty(qxl);
804     } else {
805         /* append item to the list */
806         qxl->last_release->next = ext.info->id;
807         qxl_ram_set_dirty(qxl, &qxl->last_release->next);
808         ext.info->next = 0;
809         qxl_ram_set_dirty(qxl, &ext.info->next);
810     }
811     qxl->last_release = ext.info;
812     qxl->num_free_res++;
813     trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
814     qxl_push_free_res(qxl, 0);
815 }
816 
817 /* called from spice server thread context only */
818 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
819 {
820     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
821     QXLCursorRing *ring;
822     QXLCommand *cmd;
823     int notify;
824 
825     trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
826 
827     switch (qxl->mode) {
828     case QXL_MODE_COMPAT:
829     case QXL_MODE_NATIVE:
830     case QXL_MODE_UNDEFINED:
831         ring = &qxl->ram->cursor_ring;
832         if (SPICE_RING_IS_EMPTY(ring)) {
833             return false;
834         }
835         SPICE_RING_CONS_ITEM(qxl, ring, cmd);
836         if (!cmd) {
837             return false;
838         }
839         ext->cmd      = *cmd;
840         ext->group_id = MEMSLOT_GROUP_GUEST;
841         ext->flags    = qxl->cmdflags;
842         SPICE_RING_POP(ring, notify);
843         qxl_ring_set_dirty(qxl);
844         if (notify) {
845             qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
846         }
847         qxl->guest_primary.commands++;
848         qxl_track_command(qxl, ext);
849         qxl_log_command(qxl, "csr", ext);
850         if (qxl->have_vga) {
851             qxl_render_cursor(qxl, ext);
852         }
853         trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
854         return true;
855     default:
856         return false;
857     }
858 }
859 
860 /* called from spice server thread context only */
861 static int interface_req_cursor_notification(QXLInstance *sin)
862 {
863     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
864     int wait = 1;
865 
866     trace_qxl_ring_cursor_req_notification(qxl->id);
867     switch (qxl->mode) {
868     case QXL_MODE_COMPAT:
869     case QXL_MODE_NATIVE:
870     case QXL_MODE_UNDEFINED:
871         SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
872         qxl_ring_set_dirty(qxl);
873         break;
874     default:
875         /* nothing */
876         break;
877     }
878     return wait;
879 }
880 
881 /* called from spice server thread context */
882 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
883 {
884     /*
885      * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
886      * use by xf86-video-qxl and is defined out in the qxl windows driver.
887      * Probably was at some earlier version that is prior to git start (2009),
888      * and is still guest trigerrable.
889      */
890     fprintf(stderr, "%s: deprecated\n", __func__);
891 }
892 
893 /* called from spice server thread context only */
894 static int interface_flush_resources(QXLInstance *sin)
895 {
896     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
897     int ret;
898 
899     ret = qxl->num_free_res;
900     if (ret) {
901         qxl_push_free_res(qxl, 1);
902     }
903     return ret;
904 }
905 
906 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
907 
908 /* called from spice server thread context only */
909 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
910 {
911     uint32_t current_async;
912 
913     qemu_mutex_lock(&qxl->async_lock);
914     current_async = qxl->current_async;
915     qxl->current_async = QXL_UNDEFINED_IO;
916     qemu_mutex_unlock(&qxl->async_lock);
917 
918     trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
919     if (!cookie) {
920         fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
921         return;
922     }
923     if (cookie && current_async != cookie->io) {
924         fprintf(stderr,
925                 "qxl: %s: error: current_async = %d != %"
926                 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
927     }
928     switch (current_async) {
929     case QXL_IO_MEMSLOT_ADD_ASYNC:
930     case QXL_IO_DESTROY_PRIMARY_ASYNC:
931     case QXL_IO_UPDATE_AREA_ASYNC:
932     case QXL_IO_FLUSH_SURFACES_ASYNC:
933     case QXL_IO_MONITORS_CONFIG_ASYNC:
934         break;
935     case QXL_IO_CREATE_PRIMARY_ASYNC:
936         qxl_create_guest_primary_complete(qxl);
937         break;
938     case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
939         qxl_spice_destroy_surfaces_complete(qxl);
940         break;
941     case QXL_IO_DESTROY_SURFACE_ASYNC:
942         qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
943         break;
944     default:
945         fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
946                 current_async);
947     }
948     qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
949 }
950 
951 /* called from spice server thread context only */
952 static void interface_update_area_complete(QXLInstance *sin,
953         uint32_t surface_id,
954         QXLRect *dirty, uint32_t num_updated_rects)
955 {
956     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
957     int i;
958     int qxl_i;
959 
960     qemu_mutex_lock(&qxl->ssd.lock);
961     if (surface_id != 0 || !num_updated_rects ||
962         !qxl->render_update_cookie_num) {
963         qemu_mutex_unlock(&qxl->ssd.lock);
964         return;
965     }
966     trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
967             dirty->right, dirty->top, dirty->bottom);
968     trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
969     if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
970         /*
971          * overflow - treat this as a full update. Not expected to be common.
972          */
973         trace_qxl_interface_update_area_complete_overflow(qxl->id,
974                                                           QXL_NUM_DIRTY_RECTS);
975         qxl->guest_primary.resized = 1;
976     }
977     if (qxl->guest_primary.resized) {
978         /*
979          * Don't bother copying or scheduling the bh since we will flip
980          * the whole area anyway on completion of the update_area async call
981          */
982         qemu_mutex_unlock(&qxl->ssd.lock);
983         return;
984     }
985     qxl_i = qxl->num_dirty_rects;
986     for (i = 0; i < num_updated_rects; i++) {
987         qxl->dirty[qxl_i++] = dirty[i];
988     }
989     qxl->num_dirty_rects += num_updated_rects;
990     trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
991                                                          qxl->num_dirty_rects);
992     qemu_bh_schedule(qxl->update_area_bh);
993     qemu_mutex_unlock(&qxl->ssd.lock);
994 }
995 
996 /* called from spice server thread context only */
997 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
998 {
999     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1000     QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
1001 
1002     switch (cookie->type) {
1003     case QXL_COOKIE_TYPE_IO:
1004         interface_async_complete_io(qxl, cookie);
1005         g_free(cookie);
1006         break;
1007     case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
1008         qxl_render_update_area_done(qxl, cookie);
1009         break;
1010     case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
1011         break;
1012     default:
1013         fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
1014                 __func__, cookie->type);
1015         g_free(cookie);
1016     }
1017 }
1018 
1019 /* called from spice server thread context only */
1020 static void interface_set_client_capabilities(QXLInstance *sin,
1021                                               uint8_t client_present,
1022                                               uint8_t caps[58])
1023 {
1024     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1025 
1026     if (qxl->revision < 4) {
1027         trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1028                                                               qxl->revision);
1029         return;
1030     }
1031 
1032     if (runstate_check(RUN_STATE_INMIGRATE) ||
1033         runstate_check(RUN_STATE_POSTMIGRATE)) {
1034         return;
1035     }
1036 
1037     qxl->shadow_rom.client_present = client_present;
1038     memcpy(qxl->shadow_rom.client_capabilities, caps,
1039            sizeof(qxl->shadow_rom.client_capabilities));
1040     qxl->rom->client_present = client_present;
1041     memcpy(qxl->rom->client_capabilities, caps,
1042            sizeof(qxl->rom->client_capabilities));
1043     qxl_rom_set_dirty(qxl);
1044 
1045     qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1046 }
1047 
1048 static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1049         VDAgentMonitorsConfig *monitors_config,
1050         unsigned int max_outputs)
1051 {
1052     int i;
1053     unsigned int monitors_count;
1054 
1055     monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1056 
1057     if (rom->client_monitors_config.count != monitors_count) {
1058         return true;
1059     }
1060 
1061     for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1062         VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1063         QXLURect *rect = &rom->client_monitors_config.heads[i];
1064         /* monitor->depth ignored */
1065         if ((rect->left != monitor->x) ||
1066             (rect->top != monitor->y)  ||
1067             (rect->right != monitor->x + monitor->width) ||
1068             (rect->bottom != monitor->y + monitor->height)) {
1069             return true;
1070         }
1071     }
1072 
1073     return false;
1074 }
1075 
1076 /* called from main context only */
1077 static int interface_client_monitors_config(QXLInstance *sin,
1078                                         VDAgentMonitorsConfig *monitors_config)
1079 {
1080     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1081     QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1082     int i;
1083     unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
1084     bool config_changed = false;
1085 
1086     if (qxl->revision < 4) {
1087         trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1088                                                                qxl->revision);
1089         return 0;
1090     }
1091     /*
1092      * Older windows drivers set int_mask to 0 when their ISR is called,
1093      * then later set it to ~0. So it doesn't relate to the actual interrupts
1094      * handled. However, they are old, so clearly they don't support this
1095      * interrupt
1096      */
1097     if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1098         !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1099         trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1100                                                             qxl->ram->int_mask,
1101                                                             monitors_config);
1102         return 0;
1103     }
1104     if (!monitors_config) {
1105         return 1;
1106     }
1107 
1108 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1109     /* limit number of outputs based on setting limit */
1110     if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1111         max_outputs = qxl->max_outputs;
1112     }
1113 #endif
1114 
1115     config_changed = qxl_rom_monitors_config_changed(rom,
1116                                                      monitors_config,
1117                                                      max_outputs);
1118 
1119     memset(&rom->client_monitors_config, 0,
1120            sizeof(rom->client_monitors_config));
1121     rom->client_monitors_config.count = monitors_config->num_of_monitors;
1122     /* monitors_config->flags ignored */
1123     if (rom->client_monitors_config.count >= max_outputs) {
1124         trace_qxl_client_monitors_config_capped(qxl->id,
1125                                 monitors_config->num_of_monitors,
1126                                 max_outputs);
1127         rom->client_monitors_config.count = max_outputs;
1128     }
1129     for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1130         VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1131         QXLURect *rect = &rom->client_monitors_config.heads[i];
1132         /* monitor->depth ignored */
1133         rect->left = monitor->x;
1134         rect->top = monitor->y;
1135         rect->right = monitor->x + monitor->width;
1136         rect->bottom = monitor->y + monitor->height;
1137     }
1138     rom->client_monitors_config_crc = qxl_crc32(
1139             (const uint8_t *)&rom->client_monitors_config,
1140             sizeof(rom->client_monitors_config));
1141     trace_qxl_client_monitors_config_crc(qxl->id,
1142             sizeof(rom->client_monitors_config),
1143             rom->client_monitors_config_crc);
1144 
1145     trace_qxl_interrupt_client_monitors_config(qxl->id,
1146                         rom->client_monitors_config.count,
1147                         rom->client_monitors_config.heads);
1148     if (config_changed) {
1149         qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1150     }
1151     return 1;
1152 }
1153 
1154 static const QXLInterface qxl_interface = {
1155     .base.type               = SPICE_INTERFACE_QXL,
1156     .base.description        = "qxl gpu",
1157     .base.major_version      = SPICE_INTERFACE_QXL_MAJOR,
1158     .base.minor_version      = SPICE_INTERFACE_QXL_MINOR,
1159 
1160     .attache_worker          = interface_attach_worker,
1161     .set_compression_level   = interface_set_compression_level,
1162 #if SPICE_NEEDS_SET_MM_TIME
1163     .set_mm_time             = interface_set_mm_time,
1164 #endif
1165     .get_init_info           = interface_get_init_info,
1166 
1167     /* the callbacks below are called from spice server thread context */
1168     .get_command             = interface_get_command,
1169     .req_cmd_notification    = interface_req_cmd_notification,
1170     .release_resource        = interface_release_resource,
1171     .get_cursor_command      = interface_get_cursor_command,
1172     .req_cursor_notification = interface_req_cursor_notification,
1173     .notify_update           = interface_notify_update,
1174     .flush_resources         = interface_flush_resources,
1175     .async_complete          = interface_async_complete,
1176     .update_area_complete    = interface_update_area_complete,
1177     .set_client_capabilities = interface_set_client_capabilities,
1178     .client_monitors_config = interface_client_monitors_config,
1179 };
1180 
1181 static const GraphicHwOps qxl_ops = {
1182     .gfx_update  = qxl_hw_update,
1183 };
1184 
1185 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1186 {
1187     if (d->mode == QXL_MODE_VGA) {
1188         return;
1189     }
1190     trace_qxl_enter_vga_mode(d->id);
1191     spice_qxl_driver_unload(&d->ssd.qxl);
1192     graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1193     update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
1194     qemu_spice_create_host_primary(&d->ssd);
1195     d->mode = QXL_MODE_VGA;
1196     qemu_spice_display_switch(&d->ssd, d->ssd.ds);
1197     vga_dirty_log_start(&d->vga);
1198     graphic_hw_update(d->vga.con);
1199 }
1200 
1201 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1202 {
1203     if (d->mode != QXL_MODE_VGA) {
1204         return;
1205     }
1206     trace_qxl_exit_vga_mode(d->id);
1207     graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1208     update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
1209     vga_dirty_log_stop(&d->vga);
1210     qxl_destroy_primary(d, QXL_SYNC);
1211 }
1212 
1213 static void qxl_update_irq(PCIQXLDevice *d)
1214 {
1215     uint32_t pending = le32_to_cpu(d->ram->int_pending);
1216     uint32_t mask    = le32_to_cpu(d->ram->int_mask);
1217     int level = !!(pending & mask);
1218     pci_set_irq(&d->pci, level);
1219     qxl_ring_set_dirty(d);
1220 }
1221 
1222 static void qxl_check_state(PCIQXLDevice *d)
1223 {
1224     QXLRam *ram = d->ram;
1225     int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1226 
1227     assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1228     assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1229 }
1230 
1231 static void qxl_reset_state(PCIQXLDevice *d)
1232 {
1233     QXLRom *rom = d->rom;
1234 
1235     qxl_check_state(d);
1236     d->shadow_rom.update_id = cpu_to_le32(0);
1237     *rom = d->shadow_rom;
1238     qxl_rom_set_dirty(d);
1239     init_qxl_ram(d);
1240     d->num_free_res = 0;
1241     d->last_release = NULL;
1242     memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1243     qxl_update_irq(d);
1244 }
1245 
1246 static void qxl_soft_reset(PCIQXLDevice *d)
1247 {
1248     trace_qxl_soft_reset(d->id);
1249     qxl_check_state(d);
1250     qxl_clear_guest_bug(d);
1251     qemu_mutex_lock(&d->async_lock);
1252     d->current_async = QXL_UNDEFINED_IO;
1253     qemu_mutex_unlock(&d->async_lock);
1254 
1255     if (d->have_vga) {
1256         qxl_enter_vga_mode(d);
1257     } else {
1258         d->mode = QXL_MODE_UNDEFINED;
1259     }
1260 }
1261 
1262 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1263 {
1264     bool startstop = qemu_spice_display_is_running(&d->ssd);
1265 
1266     trace_qxl_hard_reset(d->id, loadvm);
1267 
1268     if (startstop) {
1269         qemu_spice_display_stop();
1270     }
1271 
1272     qxl_spice_reset_cursor(d);
1273     qxl_spice_reset_image_cache(d);
1274     qxl_reset_surfaces(d);
1275     qxl_reset_memslots(d);
1276 
1277     /* pre loadvm reset must not touch QXLRam.  This lives in
1278      * device memory, is migrated together with RAM and thus
1279      * already loaded at this point */
1280     if (!loadvm) {
1281         qxl_reset_state(d);
1282     }
1283     qemu_spice_create_host_memslot(&d->ssd);
1284     qxl_soft_reset(d);
1285 
1286     if (d->migration_blocker) {
1287         migrate_del_blocker(d->migration_blocker);
1288         error_free(d->migration_blocker);
1289         d->migration_blocker = NULL;
1290     }
1291 
1292     if (startstop) {
1293         qemu_spice_display_start();
1294     }
1295 }
1296 
1297 static void qxl_reset_handler(DeviceState *dev)
1298 {
1299     PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
1300 
1301     qxl_hard_reset(d, 0);
1302 }
1303 
1304 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1305 {
1306     VGACommonState *vga = opaque;
1307     PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1308 
1309     trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1310     if (qxl->mode != QXL_MODE_VGA) {
1311         qxl_destroy_primary(qxl, QXL_SYNC);
1312         qxl_soft_reset(qxl);
1313     }
1314     vga_ioport_write(opaque, addr, val);
1315 }
1316 
1317 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1318     { 0x04,  2, 1, .read  = vga_ioport_read,
1319                    .write = qxl_vga_ioport_write }, /* 3b4 */
1320     { 0x0a,  1, 1, .read  = vga_ioport_read,
1321                    .write = qxl_vga_ioport_write }, /* 3ba */
1322     { 0x10, 16, 1, .read  = vga_ioport_read,
1323                    .write = qxl_vga_ioport_write }, /* 3c0 */
1324     { 0x24,  2, 1, .read  = vga_ioport_read,
1325                    .write = qxl_vga_ioport_write }, /* 3d4 */
1326     { 0x2a,  1, 1, .read  = vga_ioport_read,
1327                    .write = qxl_vga_ioport_write }, /* 3da */
1328     PORTIO_END_OF_LIST(),
1329 };
1330 
1331 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1332                            qxl_async_io async)
1333 {
1334     static const int regions[] = {
1335         QXL_RAM_RANGE_INDEX,
1336         QXL_VRAM_RANGE_INDEX,
1337         QXL_VRAM64_RANGE_INDEX,
1338     };
1339     uint64_t guest_start;
1340     uint64_t guest_end;
1341     int pci_region;
1342     pcibus_t pci_start;
1343     pcibus_t pci_end;
1344     MemoryRegion *mr;
1345     intptr_t virt_start;
1346     QXLDevMemSlot memslot;
1347     int i;
1348 
1349     guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1350     guest_end   = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1351 
1352     trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1353 
1354     if (slot_id >= NUM_MEMSLOTS) {
1355         qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1356                       slot_id, NUM_MEMSLOTS);
1357         return 1;
1358     }
1359     if (guest_start > guest_end) {
1360         qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1361                          " > 0x%" PRIx64, __func__, guest_start, guest_end);
1362         return 1;
1363     }
1364 
1365     for (i = 0; i < ARRAY_SIZE(regions); i++) {
1366         pci_region = regions[i];
1367         pci_start = d->pci.io_regions[pci_region].addr;
1368         pci_end = pci_start + d->pci.io_regions[pci_region].size;
1369         /* mapped? */
1370         if (pci_start == -1) {
1371             continue;
1372         }
1373         /* start address in range ? */
1374         if (guest_start < pci_start || guest_start > pci_end) {
1375             continue;
1376         }
1377         /* end address in range ? */
1378         if (guest_end > pci_end) {
1379             continue;
1380         }
1381         /* passed */
1382         break;
1383     }
1384     if (i == ARRAY_SIZE(regions)) {
1385         qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1386         return 1;
1387     }
1388 
1389     switch (pci_region) {
1390     case QXL_RAM_RANGE_INDEX:
1391         mr = &d->vga.vram;
1392         break;
1393     case QXL_VRAM_RANGE_INDEX:
1394     case 4 /* vram 64bit */:
1395         mr = &d->vram_bar;
1396         break;
1397     default:
1398         /* should not happen */
1399         qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1400         return 1;
1401     }
1402 
1403     virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
1404     memslot.slot_id = slot_id;
1405     memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1406     memslot.virt_start = virt_start + (guest_start - pci_start);
1407     memslot.virt_end   = virt_start + (guest_end   - pci_start);
1408     memslot.addr_delta = memslot.virt_start - delta;
1409     memslot.generation = d->rom->slot_generation = 0;
1410     qxl_rom_set_dirty(d);
1411 
1412     qemu_spice_add_memslot(&d->ssd, &memslot, async);
1413     d->guest_slots[slot_id].mr = mr;
1414     d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
1415     d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1416     d->guest_slots[slot_id].delta = delta;
1417     d->guest_slots[slot_id].active = 1;
1418     return 0;
1419 }
1420 
1421 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1422 {
1423     qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1424     d->guest_slots[slot_id].active = 0;
1425 }
1426 
1427 static void qxl_reset_memslots(PCIQXLDevice *d)
1428 {
1429     qxl_spice_reset_memslots(d);
1430     memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1431 }
1432 
1433 static void qxl_reset_surfaces(PCIQXLDevice *d)
1434 {
1435     trace_qxl_reset_surfaces(d->id);
1436     d->mode = QXL_MODE_UNDEFINED;
1437     qxl_spice_destroy_surfaces(d, QXL_SYNC);
1438 }
1439 
1440 /* can be also called from spice server thread context */
1441 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1442                                       uint32_t *s, uint64_t *o)
1443 {
1444     uint64_t phys   = le64_to_cpu(pqxl);
1445     uint32_t slot   = (phys >> (64 -  8)) & 0xff;
1446     uint64_t offset = phys & 0xffffffffffff;
1447 
1448     if (slot >= NUM_MEMSLOTS) {
1449         qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1450                           NUM_MEMSLOTS);
1451         return false;
1452     }
1453     if (!qxl->guest_slots[slot].active) {
1454         qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1455         return false;
1456     }
1457     if (offset < qxl->guest_slots[slot].delta) {
1458         qxl_set_guest_bug(qxl,
1459                           "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1460                           slot, offset, qxl->guest_slots[slot].delta);
1461         return false;
1462     }
1463     offset -= qxl->guest_slots[slot].delta;
1464     if (offset > qxl->guest_slots[slot].size) {
1465         qxl_set_guest_bug(qxl,
1466                           "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1467                           slot, offset, qxl->guest_slots[slot].size);
1468         return false;
1469     }
1470 
1471     *s = slot;
1472     *o = offset;
1473     return true;
1474 }
1475 
1476 /* can be also called from spice server thread context */
1477 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1478 {
1479     uint64_t offset;
1480     uint32_t slot;
1481     void *ptr;
1482 
1483     switch (group_id) {
1484     case MEMSLOT_GROUP_HOST:
1485         offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1486         return (void *)(intptr_t)offset;
1487     case MEMSLOT_GROUP_GUEST:
1488         if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
1489             return NULL;
1490         }
1491         ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1492         ptr += qxl->guest_slots[slot].offset;
1493         ptr += offset;
1494         return ptr;
1495     }
1496     return NULL;
1497 }
1498 
1499 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1500 {
1501     /* for local rendering */
1502     qxl_render_resize(qxl);
1503 }
1504 
1505 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1506                                      qxl_async_io async)
1507 {
1508     QXLDevSurfaceCreate surface;
1509     QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1510     uint32_t requested_height = le32_to_cpu(sc->height);
1511     int requested_stride = le32_to_cpu(sc->stride);
1512 
1513     if (requested_stride == INT32_MIN ||
1514         abs(requested_stride) * (uint64_t)requested_height
1515                                         > qxl->vgamem_size) {
1516         qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1517                                " stride %d x height %" PRIu32 " > %" PRIu32,
1518                                __func__, requested_stride, requested_height,
1519                                qxl->vgamem_size);
1520         return;
1521     }
1522 
1523     if (qxl->mode == QXL_MODE_NATIVE) {
1524         qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1525                       __func__);
1526     }
1527     qxl_exit_vga_mode(qxl);
1528 
1529     surface.format     = le32_to_cpu(sc->format);
1530     surface.height     = le32_to_cpu(sc->height);
1531     surface.mem        = le64_to_cpu(sc->mem);
1532     surface.position   = le32_to_cpu(sc->position);
1533     surface.stride     = le32_to_cpu(sc->stride);
1534     surface.width      = le32_to_cpu(sc->width);
1535     surface.type       = le32_to_cpu(sc->type);
1536     surface.flags      = le32_to_cpu(sc->flags);
1537     trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1538                                    sc->format, sc->position);
1539     trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1540                                         sc->flags);
1541 
1542     if ((surface.stride & 0x3) != 0) {
1543         qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1544                           surface.stride);
1545         return;
1546     }
1547 
1548     surface.mouse_mode = true;
1549     surface.group_id   = MEMSLOT_GROUP_GUEST;
1550     if (loadvm) {
1551         surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1552     }
1553 
1554     qxl->mode = QXL_MODE_NATIVE;
1555     qxl->cmdflags = 0;
1556     qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1557 
1558     if (async == QXL_SYNC) {
1559         qxl_create_guest_primary_complete(qxl);
1560     }
1561 }
1562 
1563 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1564  * done (in QXL_SYNC case), 0 otherwise. */
1565 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1566 {
1567     if (d->mode == QXL_MODE_UNDEFINED) {
1568         return 0;
1569     }
1570     trace_qxl_destroy_primary(d->id);
1571     d->mode = QXL_MODE_UNDEFINED;
1572     qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1573     qxl_spice_reset_cursor(d);
1574     return 1;
1575 }
1576 
1577 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1578 {
1579     pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1580     pcibus_t end   = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1581     QXLMode *mode = d->modes->modes + modenr;
1582     uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1583     QXLMemSlot slot = {
1584         .mem_start = start,
1585         .mem_end = end
1586     };
1587 
1588     if (modenr >= d->modes->n_modes) {
1589         qxl_set_guest_bug(d, "mode number out of range");
1590         return;
1591     }
1592 
1593     QXLSurfaceCreate surface = {
1594         .width      = mode->x_res,
1595         .height     = mode->y_res,
1596         .stride     = -mode->x_res * 4,
1597         .format     = SPICE_SURFACE_FMT_32_xRGB,
1598         .flags      = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1599         .mouse_mode = true,
1600         .mem        = devmem + d->shadow_rom.draw_area_offset,
1601     };
1602 
1603     trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1604                        devmem);
1605     if (!loadvm) {
1606         qxl_hard_reset(d, 0);
1607     }
1608 
1609     d->guest_slots[0].slot = slot;
1610     assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1611 
1612     d->guest_primary.surface = surface;
1613     qxl_create_guest_primary(d, 0, QXL_SYNC);
1614 
1615     d->mode = QXL_MODE_COMPAT;
1616     d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1617     if (mode->bits == 16) {
1618         d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1619     }
1620     d->shadow_rom.mode = cpu_to_le32(modenr);
1621     d->rom->mode = cpu_to_le32(modenr);
1622     qxl_rom_set_dirty(d);
1623 }
1624 
1625 static void ioport_write(void *opaque, hwaddr addr,
1626                          uint64_t val, unsigned size)
1627 {
1628     PCIQXLDevice *d = opaque;
1629     uint32_t io_port = addr;
1630     qxl_async_io async = QXL_SYNC;
1631     uint32_t orig_io_port = io_port;
1632 
1633     if (d->guest_bug && io_port != QXL_IO_RESET) {
1634         return;
1635     }
1636 
1637     if (d->revision <= QXL_REVISION_STABLE_V10 &&
1638         io_port > QXL_IO_FLUSH_RELEASE) {
1639         qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1640             io_port, d->revision);
1641         return;
1642     }
1643 
1644     switch (io_port) {
1645     case QXL_IO_RESET:
1646     case QXL_IO_SET_MODE:
1647     case QXL_IO_MEMSLOT_ADD:
1648     case QXL_IO_MEMSLOT_DEL:
1649     case QXL_IO_CREATE_PRIMARY:
1650     case QXL_IO_UPDATE_IRQ:
1651     case QXL_IO_LOG:
1652     case QXL_IO_MEMSLOT_ADD_ASYNC:
1653     case QXL_IO_CREATE_PRIMARY_ASYNC:
1654         break;
1655     default:
1656         if (d->mode != QXL_MODE_VGA) {
1657             break;
1658         }
1659         trace_qxl_io_unexpected_vga_mode(d->id,
1660             addr, val, io_port_to_string(io_port));
1661         /* be nice to buggy guest drivers */
1662         if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1663             io_port < QXL_IO_RANGE_SIZE) {
1664             qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1665         }
1666         return;
1667     }
1668 
1669     /* we change the io_port to avoid ifdeffery in the main switch */
1670     orig_io_port = io_port;
1671     switch (io_port) {
1672     case QXL_IO_UPDATE_AREA_ASYNC:
1673         io_port = QXL_IO_UPDATE_AREA;
1674         goto async_common;
1675     case QXL_IO_MEMSLOT_ADD_ASYNC:
1676         io_port = QXL_IO_MEMSLOT_ADD;
1677         goto async_common;
1678     case QXL_IO_CREATE_PRIMARY_ASYNC:
1679         io_port = QXL_IO_CREATE_PRIMARY;
1680         goto async_common;
1681     case QXL_IO_DESTROY_PRIMARY_ASYNC:
1682         io_port = QXL_IO_DESTROY_PRIMARY;
1683         goto async_common;
1684     case QXL_IO_DESTROY_SURFACE_ASYNC:
1685         io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1686         goto async_common;
1687     case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1688         io_port = QXL_IO_DESTROY_ALL_SURFACES;
1689         goto async_common;
1690     case QXL_IO_FLUSH_SURFACES_ASYNC:
1691     case QXL_IO_MONITORS_CONFIG_ASYNC:
1692 async_common:
1693         async = QXL_ASYNC;
1694         qemu_mutex_lock(&d->async_lock);
1695         if (d->current_async != QXL_UNDEFINED_IO) {
1696             qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1697                 io_port, d->current_async);
1698             qemu_mutex_unlock(&d->async_lock);
1699             return;
1700         }
1701         d->current_async = orig_io_port;
1702         qemu_mutex_unlock(&d->async_lock);
1703         break;
1704     default:
1705         break;
1706     }
1707     trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1708                        addr, io_port_to_string(addr),
1709                        val, size, async);
1710 
1711     switch (io_port) {
1712     case QXL_IO_UPDATE_AREA:
1713     {
1714         QXLCookie *cookie = NULL;
1715         QXLRect update = d->ram->update_area;
1716 
1717         if (d->ram->update_surface > d->ssd.num_surfaces) {
1718             qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1719                               d->ram->update_surface);
1720             break;
1721         }
1722         if (update.left >= update.right || update.top >= update.bottom ||
1723             update.left < 0 || update.top < 0) {
1724             qxl_set_guest_bug(d,
1725                     "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1726                     update.left, update.top, update.right, update.bottom);
1727             if (update.left == update.right || update.top == update.bottom) {
1728                 /* old drivers may provide empty area, keep going */
1729                 qxl_clear_guest_bug(d);
1730                 goto cancel_async;
1731             }
1732             break;
1733         }
1734         if (async == QXL_ASYNC) {
1735             cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1736                                     QXL_IO_UPDATE_AREA_ASYNC);
1737             cookie->u.area = update;
1738         }
1739         qxl_spice_update_area(d, d->ram->update_surface,
1740                               cookie ? &cookie->u.area : &update,
1741                               NULL, 0, 0, async, cookie);
1742         break;
1743     }
1744     case QXL_IO_NOTIFY_CMD:
1745         qemu_spice_wakeup(&d->ssd);
1746         break;
1747     case QXL_IO_NOTIFY_CURSOR:
1748         qemu_spice_wakeup(&d->ssd);
1749         break;
1750     case QXL_IO_UPDATE_IRQ:
1751         qxl_update_irq(d);
1752         break;
1753     case QXL_IO_NOTIFY_OOM:
1754         if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1755             break;
1756         }
1757         d->oom_running = 1;
1758         qxl_spice_oom(d);
1759         d->oom_running = 0;
1760         break;
1761     case QXL_IO_SET_MODE:
1762         qxl_set_mode(d, val, 0);
1763         break;
1764     case QXL_IO_LOG:
1765         if (TRACE_QXL_IO_LOG_ENABLED || d->guestdebug) {
1766             /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1767             char *log_buf = g_strndup((const char *)d->ram->log_buf,
1768                                       sizeof(d->ram->log_buf));
1769             trace_qxl_io_log(d->id, log_buf);
1770             if (d->guestdebug) {
1771                 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1772                         qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1773             }
1774             g_free(log_buf);
1775         }
1776         break;
1777     case QXL_IO_RESET:
1778         qxl_hard_reset(d, 0);
1779         break;
1780     case QXL_IO_MEMSLOT_ADD:
1781         if (val >= NUM_MEMSLOTS) {
1782             qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1783             break;
1784         }
1785         if (d->guest_slots[val].active) {
1786             qxl_set_guest_bug(d,
1787                         "QXL_IO_MEMSLOT_ADD: memory slot already active");
1788             break;
1789         }
1790         d->guest_slots[val].slot = d->ram->mem_slot;
1791         qxl_add_memslot(d, val, 0, async);
1792         break;
1793     case QXL_IO_MEMSLOT_DEL:
1794         if (val >= NUM_MEMSLOTS) {
1795             qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1796             break;
1797         }
1798         qxl_del_memslot(d, val);
1799         break;
1800     case QXL_IO_CREATE_PRIMARY:
1801         if (val != 0) {
1802             qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1803                           async);
1804             goto cancel_async;
1805         }
1806         d->guest_primary.surface = d->ram->create_surface;
1807         qxl_create_guest_primary(d, 0, async);
1808         break;
1809     case QXL_IO_DESTROY_PRIMARY:
1810         if (val != 0) {
1811             qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1812                           async);
1813             goto cancel_async;
1814         }
1815         if (!qxl_destroy_primary(d, async)) {
1816             trace_qxl_io_destroy_primary_ignored(d->id,
1817                                                  qxl_mode_to_string(d->mode));
1818             goto cancel_async;
1819         }
1820         break;
1821     case QXL_IO_DESTROY_SURFACE_WAIT:
1822         if (val >= d->ssd.num_surfaces) {
1823             qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1824                              "%" PRIu64 " >= NUM_SURFACES", async, val);
1825             goto cancel_async;
1826         }
1827         qxl_spice_destroy_surface_wait(d, val, async);
1828         break;
1829     case QXL_IO_FLUSH_RELEASE: {
1830         QXLReleaseRing *ring = &d->ram->release_ring;
1831         if (ring->prod - ring->cons + 1 == ring->num_items) {
1832             fprintf(stderr,
1833                 "ERROR: no flush, full release ring [p%d,%dc]\n",
1834                 ring->prod, ring->cons);
1835         }
1836         qxl_push_free_res(d, 1 /* flush */);
1837         break;
1838     }
1839     case QXL_IO_FLUSH_SURFACES_ASYNC:
1840         qxl_spice_flush_surfaces_async(d);
1841         break;
1842     case QXL_IO_DESTROY_ALL_SURFACES:
1843         d->mode = QXL_MODE_UNDEFINED;
1844         qxl_spice_destroy_surfaces(d, async);
1845         break;
1846     case QXL_IO_MONITORS_CONFIG_ASYNC:
1847         qxl_spice_monitors_config_async(d, 0);
1848         break;
1849     default:
1850         qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1851     }
1852     return;
1853 cancel_async:
1854     if (async) {
1855         qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1856         qemu_mutex_lock(&d->async_lock);
1857         d->current_async = QXL_UNDEFINED_IO;
1858         qemu_mutex_unlock(&d->async_lock);
1859     }
1860 }
1861 
1862 static uint64_t ioport_read(void *opaque, hwaddr addr,
1863                             unsigned size)
1864 {
1865     PCIQXLDevice *qxl = opaque;
1866 
1867     trace_qxl_io_read_unexpected(qxl->id);
1868     return 0xff;
1869 }
1870 
1871 static const MemoryRegionOps qxl_io_ops = {
1872     .read = ioport_read,
1873     .write = ioport_write,
1874     .valid = {
1875         .min_access_size = 1,
1876         .max_access_size = 1,
1877     },
1878 };
1879 
1880 static void qxl_update_irq_bh(void *opaque)
1881 {
1882     PCIQXLDevice *d = opaque;
1883     qxl_update_irq(d);
1884 }
1885 
1886 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1887 {
1888     uint32_t old_pending;
1889     uint32_t le_events = cpu_to_le32(events);
1890 
1891     trace_qxl_send_events(d->id, events);
1892     if (!qemu_spice_display_is_running(&d->ssd)) {
1893         /* spice-server tracks guest running state and should not do this */
1894         fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1895                 __func__);
1896         trace_qxl_send_events_vm_stopped(d->id, events);
1897         return;
1898     }
1899     /*
1900      * Older versions of Spice forgot to define the QXLRam struct
1901      * with the '__aligned__(4)' attribute. clang 7 and newer will
1902      * thus warn that atomic_fetch_or(&d->ram->int_pending, ...)
1903      * might be a misaligned atomic access, and will generate an
1904      * out-of-line call for it, which results in a link error since
1905      * we don't currently link against libatomic.
1906      *
1907      * In fact we set up d->ram in init_qxl_ram() so it always starts
1908      * at a 4K boundary, so we know that &d->ram->int_pending is
1909      * naturally aligned for a uint32_t. Newer Spice versions
1910      * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1911      * will fix the bug directly. To deal with older versions,
1912      * we tell the compiler to assume the address really is aligned.
1913      * Any compiler which cares about the misalignment will have
1914      * __builtin_assume_aligned.
1915      */
1916 #ifdef HAS_ASSUME_ALIGNED
1917 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1918 #else
1919 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1920 #endif
1921 
1922     old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1923                                   le_events);
1924     if ((old_pending & le_events) == le_events) {
1925         return;
1926     }
1927     qemu_bh_schedule(d->update_irq);
1928 }
1929 
1930 /* graphics console */
1931 
1932 static void qxl_hw_update(void *opaque)
1933 {
1934     PCIQXLDevice *qxl = opaque;
1935 
1936     qxl_render_update(qxl);
1937 }
1938 
1939 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1940                                   uint32_t height, int32_t stride)
1941 {
1942     uint64_t offset, size;
1943     uint32_t slot;
1944     bool rc;
1945 
1946     rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1947     assert(rc == true);
1948     size = (uint64_t)height * abs(stride);
1949     trace_qxl_surfaces_dirty(qxl->id, offset, size);
1950     qxl_set_dirty(qxl->guest_slots[slot].mr,
1951                   qxl->guest_slots[slot].offset + offset,
1952                   qxl->guest_slots[slot].offset + offset + size);
1953 }
1954 
1955 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1956 {
1957     int i;
1958 
1959     if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1960         return;
1961     }
1962 
1963     /* dirty the primary surface */
1964     qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1965                           qxl->guest_primary.surface.height,
1966                           qxl->guest_primary.surface.stride);
1967 
1968     /* dirty the off-screen surfaces */
1969     for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1970         QXLSurfaceCmd *cmd;
1971 
1972         if (qxl->guest_surfaces.cmds[i] == 0) {
1973             continue;
1974         }
1975 
1976         cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1977                             MEMSLOT_GROUP_GUEST);
1978         assert(cmd);
1979         assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1980         qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1981                               cmd->u.surface_create.height,
1982                               cmd->u.surface_create.stride);
1983     }
1984 }
1985 
1986 static void qxl_vm_change_state_handler(void *opaque, int running,
1987                                         RunState state)
1988 {
1989     PCIQXLDevice *qxl = opaque;
1990 
1991     if (running) {
1992         /*
1993          * if qxl_send_events was called from spice server context before
1994          * migration ended, qxl_update_irq for these events might not have been
1995          * called
1996          */
1997          qxl_update_irq(qxl);
1998     } else {
1999         /* make sure surfaces are saved before migration */
2000         qxl_dirty_surfaces(qxl);
2001     }
2002 }
2003 
2004 /* display change listener */
2005 
2006 static void display_update(DisplayChangeListener *dcl,
2007                            int x, int y, int w, int h)
2008 {
2009     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2010 
2011     if (qxl->mode == QXL_MODE_VGA) {
2012         qemu_spice_display_update(&qxl->ssd, x, y, w, h);
2013     }
2014 }
2015 
2016 static void display_switch(DisplayChangeListener *dcl,
2017                            struct DisplaySurface *surface)
2018 {
2019     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2020 
2021     qxl->ssd.ds = surface;
2022     if (qxl->mode == QXL_MODE_VGA) {
2023         qemu_spice_display_switch(&qxl->ssd, surface);
2024     }
2025 }
2026 
2027 static void display_refresh(DisplayChangeListener *dcl)
2028 {
2029     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2030 
2031     if (qxl->mode == QXL_MODE_VGA) {
2032         qemu_spice_display_refresh(&qxl->ssd);
2033     }
2034 }
2035 
2036 static DisplayChangeListenerOps display_listener_ops = {
2037     .dpy_name        = "spice/qxl",
2038     .dpy_gfx_update  = display_update,
2039     .dpy_gfx_switch  = display_switch,
2040     .dpy_refresh     = display_refresh,
2041 };
2042 
2043 static void qxl_init_ramsize(PCIQXLDevice *qxl)
2044 {
2045     /* vga mode framebuffer / primary surface (bar 0, first part) */
2046     if (qxl->vgamem_size_mb < 8) {
2047         qxl->vgamem_size_mb = 8;
2048     }
2049     /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2050      * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2051      */
2052     if (qxl->vgamem_size_mb > 256) {
2053         qxl->vgamem_size_mb = 256;
2054     }
2055     qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
2056 
2057     /* vga ram (bar 0, total) */
2058     if (qxl->ram_size_mb != -1) {
2059         qxl->vga.vram_size = qxl->ram_size_mb * MiB;
2060     }
2061     if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2062         qxl->vga.vram_size = qxl->vgamem_size * 2;
2063     }
2064 
2065     /* vram32 (surfaces, 32bit, bar 1) */
2066     if (qxl->vram32_size_mb != -1) {
2067         qxl->vram32_size = qxl->vram32_size_mb * MiB;
2068     }
2069     if (qxl->vram32_size < 4096) {
2070         qxl->vram32_size = 4096;
2071     }
2072 
2073     /* vram (surfaces, 64bit, bar 4+5) */
2074     if (qxl->vram_size_mb != -1) {
2075         qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
2076     }
2077     if (qxl->vram_size < qxl->vram32_size) {
2078         qxl->vram_size = qxl->vram32_size;
2079     }
2080 
2081     if (qxl->revision == 1) {
2082         qxl->vram32_size = 4096;
2083         qxl->vram_size = 4096;
2084     }
2085     qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2086     qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2087     qxl->vram32_size = pow2ceil(qxl->vram32_size);
2088     qxl->vram_size = pow2ceil(qxl->vram_size);
2089 }
2090 
2091 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
2092 {
2093     uint8_t* config = qxl->pci.config;
2094     uint32_t pci_device_rev;
2095     uint32_t io_size;
2096 
2097     qemu_spice_display_init_common(&qxl->ssd);
2098     qxl->mode = QXL_MODE_UNDEFINED;
2099     qxl->num_memslots = NUM_MEMSLOTS;
2100     qemu_mutex_init(&qxl->track_lock);
2101     qemu_mutex_init(&qxl->async_lock);
2102     qxl->current_async = QXL_UNDEFINED_IO;
2103     qxl->guest_bug = 0;
2104 
2105     switch (qxl->revision) {
2106     case 1: /* spice 0.4 -- qxl-1 */
2107         pci_device_rev = QXL_REVISION_STABLE_V04;
2108         io_size = 8;
2109         break;
2110     case 2: /* spice 0.6 -- qxl-2 */
2111         pci_device_rev = QXL_REVISION_STABLE_V06;
2112         io_size = 16;
2113         break;
2114     case 3: /* qxl-3 */
2115         pci_device_rev = QXL_REVISION_STABLE_V10;
2116         io_size = 32; /* PCI region size must be pow2 */
2117         break;
2118     case 4: /* qxl-4 */
2119         pci_device_rev = QXL_REVISION_STABLE_V12;
2120         io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2121         break;
2122     default:
2123         error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2124                    qxl->revision, QXL_DEFAULT_REVISION);
2125         return;
2126     }
2127 
2128     pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2129     pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2130 
2131     qxl->rom_size = qxl_rom_size();
2132     memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
2133                            qxl->rom_size, &error_fatal);
2134     init_qxl_rom(qxl);
2135     init_qxl_ram(qxl);
2136 
2137     qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2138     memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
2139                            qxl->vram_size, &error_fatal);
2140     memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2141                              &qxl->vram_bar, 0, qxl->vram32_size);
2142 
2143     memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
2144                           "qxl-ioports", io_size);
2145     if (qxl->have_vga) {
2146         vga_dirty_log_start(&qxl->vga);
2147     }
2148     memory_region_set_flush_coalesced(&qxl->io_bar);
2149 
2150 
2151     pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2152                      PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2153 
2154     pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2155                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2156 
2157     pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2158                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2159 
2160     pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2161                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2162 
2163     if (qxl->vram32_size < qxl->vram_size) {
2164         /*
2165          * Make the 64bit vram bar show up only in case it is
2166          * configured to be larger than the 32bit vram bar.
2167          */
2168         pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2169                          PCI_BASE_ADDRESS_SPACE_MEMORY |
2170                          PCI_BASE_ADDRESS_MEM_TYPE_64 |
2171                          PCI_BASE_ADDRESS_MEM_PREFETCH,
2172                          &qxl->vram_bar);
2173     }
2174 
2175     /* print pci bar details */
2176     dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
2177            qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
2178     dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2179            qxl->vram32_size / MiB);
2180     dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2181            qxl->vram_size / MiB,
2182            qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2183 
2184     qxl->ssd.qxl.base.sif = &qxl_interface.base;
2185     if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2186         error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2187                    SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2188         return;
2189     }
2190 
2191 #if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */
2192     char device_address[256] = "";
2193     if (qemu_spice_fill_device_address(qxl->vga.con, device_address, 256)) {
2194         spice_qxl_set_device_info(&qxl->ssd.qxl,
2195                                   device_address,
2196                                   0,
2197                                   qxl->max_outputs);
2198     }
2199 #endif
2200 
2201     qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2202 
2203     qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2204     qxl_reset_state(qxl);
2205 
2206     qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2207     qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
2208 }
2209 
2210 static void qxl_realize_primary(PCIDevice *dev, Error **errp)
2211 {
2212     PCIQXLDevice *qxl = PCI_QXL(dev);
2213     VGACommonState *vga = &qxl->vga;
2214     Error *local_err = NULL;
2215 
2216     qxl_init_ramsize(qxl);
2217     vga->vbe_size = qxl->vgamem_size;
2218     vga->vram_size_mb = qxl->vga.vram_size / MiB;
2219     vga_common_init(vga, OBJECT(dev));
2220     vga_init(vga, OBJECT(dev),
2221              pci_address_space(dev), pci_address_space_io(dev), false);
2222     portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2223                      vga, "vga");
2224     portio_list_set_flush_coalesced(&qxl->vga_port_list);
2225     portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2226     qxl->have_vga = true;
2227 
2228     vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2229     qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2230     if (qxl->id != 0) {
2231         error_setg(errp, "primary qxl-vga device must be console 0 "
2232                    "(first display device on the command line)");
2233         return;
2234     }
2235 
2236     qxl_realize_common(qxl, &local_err);
2237     if (local_err) {
2238         error_propagate(errp, local_err);
2239         return;
2240     }
2241 
2242     qxl->ssd.dcl.ops = &display_listener_ops;
2243     qxl->ssd.dcl.con = vga->con;
2244     register_displaychangelistener(&qxl->ssd.dcl);
2245 }
2246 
2247 static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
2248 {
2249     PCIQXLDevice *qxl = PCI_QXL(dev);
2250 
2251     qxl_init_ramsize(qxl);
2252     memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2253                            qxl->vga.vram_size, &error_fatal);
2254     qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2255     qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2256     qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
2257 
2258     qxl_realize_common(qxl, errp);
2259 }
2260 
2261 static int qxl_pre_save(void *opaque)
2262 {
2263     PCIQXLDevice* d = opaque;
2264     uint8_t *ram_start = d->vga.vram_ptr;
2265 
2266     trace_qxl_pre_save(d->id);
2267     if (d->last_release == NULL) {
2268         d->last_release_offset = 0;
2269     } else {
2270         d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2271     }
2272     assert(d->last_release_offset < d->vga.vram_size);
2273 
2274     return 0;
2275 }
2276 
2277 static int qxl_pre_load(void *opaque)
2278 {
2279     PCIQXLDevice* d = opaque;
2280 
2281     trace_qxl_pre_load(d->id);
2282     qxl_hard_reset(d, 1);
2283     qxl_exit_vga_mode(d);
2284     return 0;
2285 }
2286 
2287 static void qxl_create_memslots(PCIQXLDevice *d)
2288 {
2289     int i;
2290 
2291     for (i = 0; i < NUM_MEMSLOTS; i++) {
2292         if (!d->guest_slots[i].active) {
2293             continue;
2294         }
2295         qxl_add_memslot(d, i, 0, QXL_SYNC);
2296     }
2297 }
2298 
2299 static int qxl_post_load(void *opaque, int version)
2300 {
2301     PCIQXLDevice* d = opaque;
2302     uint8_t *ram_start = d->vga.vram_ptr;
2303     QXLCommandExt *cmds;
2304     int in, out, newmode;
2305 
2306     assert(d->last_release_offset < d->vga.vram_size);
2307     if (d->last_release_offset == 0) {
2308         d->last_release = NULL;
2309     } else {
2310         d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2311     }
2312 
2313     d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2314 
2315     trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2316     newmode = d->mode;
2317     d->mode = QXL_MODE_UNDEFINED;
2318 
2319     switch (newmode) {
2320     case QXL_MODE_UNDEFINED:
2321         qxl_create_memslots(d);
2322         break;
2323     case QXL_MODE_VGA:
2324         qxl_create_memslots(d);
2325         qxl_enter_vga_mode(d);
2326         break;
2327     case QXL_MODE_NATIVE:
2328         qxl_create_memslots(d);
2329         qxl_create_guest_primary(d, 1, QXL_SYNC);
2330 
2331         /* replay surface-create and cursor-set commands */
2332         cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
2333         for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2334             if (d->guest_surfaces.cmds[in] == 0) {
2335                 continue;
2336             }
2337             cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2338             cmds[out].cmd.type = QXL_CMD_SURFACE;
2339             cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2340             out++;
2341         }
2342         if (d->guest_cursor) {
2343             cmds[out].cmd.data = d->guest_cursor;
2344             cmds[out].cmd.type = QXL_CMD_CURSOR;
2345             cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2346             out++;
2347         }
2348         qxl_spice_loadvm_commands(d, cmds, out);
2349         g_free(cmds);
2350         if (d->guest_monitors_config) {
2351             qxl_spice_monitors_config_async(d, 1);
2352         }
2353         break;
2354     case QXL_MODE_COMPAT:
2355         /* note: no need to call qxl_create_memslots, qxl_set_mode
2356          * creates the mem slot. */
2357         qxl_set_mode(d, d->shadow_rom.mode, 1);
2358         break;
2359     }
2360     return 0;
2361 }
2362 
2363 #define QXL_SAVE_VERSION 21
2364 
2365 static bool qxl_monitors_config_needed(void *opaque)
2366 {
2367     PCIQXLDevice *qxl = opaque;
2368 
2369     return qxl->guest_monitors_config != 0;
2370 }
2371 
2372 
2373 static VMStateDescription qxl_memslot = {
2374     .name               = "qxl-memslot",
2375     .version_id         = QXL_SAVE_VERSION,
2376     .minimum_version_id = QXL_SAVE_VERSION,
2377     .fields = (VMStateField[]) {
2378         VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2379         VMSTATE_UINT64(slot.mem_end,   struct guest_slots),
2380         VMSTATE_UINT32(active,         struct guest_slots),
2381         VMSTATE_END_OF_LIST()
2382     }
2383 };
2384 
2385 static VMStateDescription qxl_surface = {
2386     .name               = "qxl-surface",
2387     .version_id         = QXL_SAVE_VERSION,
2388     .minimum_version_id = QXL_SAVE_VERSION,
2389     .fields = (VMStateField[]) {
2390         VMSTATE_UINT32(width,      QXLSurfaceCreate),
2391         VMSTATE_UINT32(height,     QXLSurfaceCreate),
2392         VMSTATE_INT32(stride,      QXLSurfaceCreate),
2393         VMSTATE_UINT32(format,     QXLSurfaceCreate),
2394         VMSTATE_UINT32(position,   QXLSurfaceCreate),
2395         VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2396         VMSTATE_UINT32(flags,      QXLSurfaceCreate),
2397         VMSTATE_UINT32(type,       QXLSurfaceCreate),
2398         VMSTATE_UINT64(mem,        QXLSurfaceCreate),
2399         VMSTATE_END_OF_LIST()
2400     }
2401 };
2402 
2403 static VMStateDescription qxl_vmstate_monitors_config = {
2404     .name               = "qxl/monitors-config",
2405     .version_id         = 1,
2406     .minimum_version_id = 1,
2407     .needed = qxl_monitors_config_needed,
2408     .fields = (VMStateField[]) {
2409         VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2410         VMSTATE_END_OF_LIST()
2411     },
2412 };
2413 
2414 static VMStateDescription qxl_vmstate = {
2415     .name               = "qxl",
2416     .version_id         = QXL_SAVE_VERSION,
2417     .minimum_version_id = QXL_SAVE_VERSION,
2418     .pre_save           = qxl_pre_save,
2419     .pre_load           = qxl_pre_load,
2420     .post_load          = qxl_post_load,
2421     .fields = (VMStateField[]) {
2422         VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2423         VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2424         VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2425         VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2426         VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2427         VMSTATE_UINT32(mode, PCIQXLDevice),
2428         VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2429         VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
2430         VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2431                              qxl_memslot, struct guest_slots),
2432         VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2433                        qxl_surface, QXLSurfaceCreate),
2434         VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
2435         VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2436                              ssd.num_surfaces, 0,
2437                              vmstate_info_uint64, uint64_t),
2438         VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2439         VMSTATE_END_OF_LIST()
2440     },
2441     .subsections = (const VMStateDescription*[]) {
2442         &qxl_vmstate_monitors_config,
2443         NULL
2444     }
2445 };
2446 
2447 static Property qxl_properties[] = {
2448         DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2449         DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
2450         DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2451                            QXL_DEFAULT_REVISION),
2452         DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2453         DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2454         DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2455         DEFINE_PROP_UINT32("ram_size_mb",  PCIQXLDevice, ram_size_mb, -1),
2456         DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2457         DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2458         DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2459         DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2460 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2461         DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2462 #endif
2463         DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2464         DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
2465         DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
2466         DEFINE_PROP_END_OF_LIST(),
2467 };
2468 
2469 static void qxl_pci_class_init(ObjectClass *klass, void *data)
2470 {
2471     DeviceClass *dc = DEVICE_CLASS(klass);
2472     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2473 
2474     k->vendor_id = REDHAT_PCI_VENDOR_ID;
2475     k->device_id = QXL_DEVICE_ID_STABLE;
2476     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2477     dc->reset = qxl_reset_handler;
2478     dc->vmsd = &qxl_vmstate;
2479     dc->props = qxl_properties;
2480 }
2481 
2482 static const TypeInfo qxl_pci_type_info = {
2483     .name = TYPE_PCI_QXL,
2484     .parent = TYPE_PCI_DEVICE,
2485     .instance_size = sizeof(PCIQXLDevice),
2486     .abstract = true,
2487     .class_init = qxl_pci_class_init,
2488     .interfaces = (InterfaceInfo[]) {
2489         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2490         { },
2491     },
2492 };
2493 
2494 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2495 {
2496     DeviceClass *dc = DEVICE_CLASS(klass);
2497     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2498 
2499     k->realize = qxl_realize_primary;
2500     k->romfile = "vgabios-qxl.bin";
2501     k->class_id = PCI_CLASS_DISPLAY_VGA;
2502     dc->desc = "Spice QXL GPU (primary, vga compatible)";
2503     dc->hotpluggable = false;
2504 }
2505 
2506 static const TypeInfo qxl_primary_info = {
2507     .name          = "qxl-vga",
2508     .parent        = TYPE_PCI_QXL,
2509     .class_init    = qxl_primary_class_init,
2510 };
2511 
2512 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2513 {
2514     DeviceClass *dc = DEVICE_CLASS(klass);
2515     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2516 
2517     k->realize = qxl_realize_secondary;
2518     k->class_id = PCI_CLASS_DISPLAY_OTHER;
2519     dc->desc = "Spice QXL GPU (secondary)";
2520 }
2521 
2522 static const TypeInfo qxl_secondary_info = {
2523     .name          = "qxl",
2524     .parent        = TYPE_PCI_QXL,
2525     .class_init    = qxl_secondary_class_init,
2526 };
2527 
2528 static void qxl_register_types(void)
2529 {
2530     type_register_static(&qxl_pci_type_info);
2531     type_register_static(&qxl_primary_info);
2532     type_register_static(&qxl_secondary_info);
2533 }
2534 
2535 type_init(qxl_register_types)
2536