xref: /openbmc/qemu/hw/display/qxl.c (revision 88f62c2b)
1 /*
2  * Copyright (C) 2010 Red Hat, Inc.
3  *
4  * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5  * maintained by Gerd Hoffmann <kraxel@redhat.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 or
10  * (at your option) version 3 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include <zlib.h>
22 
23 #include "qemu-common.h"
24 #include "qemu/timer.h"
25 #include "qemu/queue.h"
26 #include "monitor/monitor.h"
27 #include "sysemu/sysemu.h"
28 #include "trace.h"
29 
30 #include "qxl.h"
31 
32 /*
33  * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
34  * such can be changed by the guest, so to avoid a guest trigerrable
35  * abort we just qxl_set_guest_bug and set the return to NULL. Still
36  * it may happen as a result of emulator bug as well.
37  */
38 #undef SPICE_RING_PROD_ITEM
39 #define SPICE_RING_PROD_ITEM(qxl, r, ret) {                             \
40         uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r);           \
41         if (prod >= ARRAY_SIZE((r)->items)) {                           \
42             qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
43                           "%u >= %zu", prod, ARRAY_SIZE((r)->items));   \
44             ret = NULL;                                                 \
45         } else {                                                        \
46             ret = &(r)->items[prod].el;                                 \
47         }                                                               \
48     }
49 
50 #undef SPICE_RING_CONS_ITEM
51 #define SPICE_RING_CONS_ITEM(qxl, r, ret) {                             \
52         uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r);           \
53         if (cons >= ARRAY_SIZE((r)->items)) {                           \
54             qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
55                           "%u >= %zu", cons, ARRAY_SIZE((r)->items));   \
56             ret = NULL;                                                 \
57         } else {                                                        \
58             ret = &(r)->items[cons].el;                                 \
59         }                                                               \
60     }
61 
62 #undef ALIGN
63 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
64 
65 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
66 
67 #define QXL_MODE(_x, _y, _b, _o)                  \
68     {   .x_res = _x,                              \
69         .y_res = _y,                              \
70         .bits  = _b,                              \
71         .stride = (_x) * (_b) / 8,                \
72         .x_mili = PIXEL_SIZE * (_x),              \
73         .y_mili = PIXEL_SIZE * (_y),              \
74         .orientation = _o,                        \
75     }
76 
77 #define QXL_MODE_16_32(x_res, y_res, orientation) \
78     QXL_MODE(x_res, y_res, 16, orientation),      \
79     QXL_MODE(x_res, y_res, 32, orientation)
80 
81 #define QXL_MODE_EX(x_res, y_res)                 \
82     QXL_MODE_16_32(x_res, y_res, 0),              \
83     QXL_MODE_16_32(x_res, y_res, 1)
84 
85 static QXLMode qxl_modes[] = {
86     QXL_MODE_EX(640, 480),
87     QXL_MODE_EX(800, 480),
88     QXL_MODE_EX(800, 600),
89     QXL_MODE_EX(832, 624),
90     QXL_MODE_EX(960, 640),
91     QXL_MODE_EX(1024, 600),
92     QXL_MODE_EX(1024, 768),
93     QXL_MODE_EX(1152, 864),
94     QXL_MODE_EX(1152, 870),
95     QXL_MODE_EX(1280, 720),
96     QXL_MODE_EX(1280, 760),
97     QXL_MODE_EX(1280, 768),
98     QXL_MODE_EX(1280, 800),
99     QXL_MODE_EX(1280, 960),
100     QXL_MODE_EX(1280, 1024),
101     QXL_MODE_EX(1360, 768),
102     QXL_MODE_EX(1366, 768),
103     QXL_MODE_EX(1400, 1050),
104     QXL_MODE_EX(1440, 900),
105     QXL_MODE_EX(1600, 900),
106     QXL_MODE_EX(1600, 1200),
107     QXL_MODE_EX(1680, 1050),
108     QXL_MODE_EX(1920, 1080),
109     /* these modes need more than 8 MB video memory */
110     QXL_MODE_EX(1920, 1200),
111     QXL_MODE_EX(1920, 1440),
112     QXL_MODE_EX(2000, 2000),
113     QXL_MODE_EX(2048, 1536),
114     QXL_MODE_EX(2048, 2048),
115     QXL_MODE_EX(2560, 1440),
116     QXL_MODE_EX(2560, 1600),
117     /* these modes need more than 16 MB video memory */
118     QXL_MODE_EX(2560, 2048),
119     QXL_MODE_EX(2800, 2100),
120     QXL_MODE_EX(3200, 2400),
121     QXL_MODE_EX(3840, 2160), /* 4k mainstream */
122     QXL_MODE_EX(4096, 2160), /* 4k            */
123     QXL_MODE_EX(7680, 4320), /* 8k mainstream */
124     QXL_MODE_EX(8192, 4320), /* 8k            */
125 };
126 
127 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
128 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
129 static void qxl_reset_memslots(PCIQXLDevice *d);
130 static void qxl_reset_surfaces(PCIQXLDevice *d);
131 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
132 
133 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
134 {
135     trace_qxl_set_guest_bug(qxl->id);
136     qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
137     qxl->guest_bug = 1;
138     if (qxl->guestdebug) {
139         va_list ap;
140         va_start(ap, msg);
141         fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
142         vfprintf(stderr, msg, ap);
143         fprintf(stderr, "\n");
144         va_end(ap);
145     }
146 }
147 
148 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
149 {
150     qxl->guest_bug = 0;
151 }
152 
153 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
154                            struct QXLRect *area, struct QXLRect *dirty_rects,
155                            uint32_t num_dirty_rects,
156                            uint32_t clear_dirty_region,
157                            qxl_async_io async, struct QXLCookie *cookie)
158 {
159     trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
160                                 area->top, area->bottom);
161     trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
162                                      clear_dirty_region);
163     if (async == QXL_SYNC) {
164         qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
165                         dirty_rects, num_dirty_rects, clear_dirty_region);
166     } else {
167         assert(cookie != NULL);
168         spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
169                                     clear_dirty_region, (uintptr_t)cookie);
170     }
171 }
172 
173 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
174                                                     uint32_t id)
175 {
176     trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
177     qemu_mutex_lock(&qxl->track_lock);
178     qxl->guest_surfaces.cmds[id] = 0;
179     qxl->guest_surfaces.count--;
180     qemu_mutex_unlock(&qxl->track_lock);
181 }
182 
183 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
184                                            qxl_async_io async)
185 {
186     QXLCookie *cookie;
187 
188     trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
189     if (async) {
190         cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
191                                 QXL_IO_DESTROY_SURFACE_ASYNC);
192         cookie->u.surface_id = id;
193         spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
194     } else {
195         qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
196         qxl_spice_destroy_surface_wait_complete(qxl, id);
197     }
198 }
199 
200 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
201 {
202     trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
203                                          qxl->num_free_res);
204     spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
205         (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
206                                   QXL_IO_FLUSH_SURFACES_ASYNC));
207 }
208 
209 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
210                                uint32_t count)
211 {
212     trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
213     qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
214 }
215 
216 void qxl_spice_oom(PCIQXLDevice *qxl)
217 {
218     trace_qxl_spice_oom(qxl->id);
219     qxl->ssd.worker->oom(qxl->ssd.worker);
220 }
221 
222 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
223 {
224     trace_qxl_spice_reset_memslots(qxl->id);
225     qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
226 }
227 
228 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
229 {
230     trace_qxl_spice_destroy_surfaces_complete(qxl->id);
231     qemu_mutex_lock(&qxl->track_lock);
232     memset(qxl->guest_surfaces.cmds, 0,
233            sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
234     qxl->guest_surfaces.count = 0;
235     qemu_mutex_unlock(&qxl->track_lock);
236 }
237 
238 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
239 {
240     trace_qxl_spice_destroy_surfaces(qxl->id, async);
241     if (async) {
242         spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
243                 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
244                                           QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
245     } else {
246         qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
247         qxl_spice_destroy_surfaces_complete(qxl);
248     }
249 }
250 
251 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
252 {
253     trace_qxl_spice_monitors_config(qxl->id);
254     if (replay) {
255         /*
256          * don't use QXL_COOKIE_TYPE_IO:
257          *  - we are not running yet (post_load), we will assert
258          *    in send_events
259          *  - this is not a guest io, but a reply, so async_io isn't set.
260          */
261         spice_qxl_monitors_config_async(&qxl->ssd.qxl,
262                 qxl->guest_monitors_config,
263                 MEMSLOT_GROUP_GUEST,
264                 (uintptr_t)qxl_cookie_new(
265                     QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
266                     0));
267     } else {
268         qxl->guest_monitors_config = qxl->ram->monitors_config;
269         spice_qxl_monitors_config_async(&qxl->ssd.qxl,
270                 qxl->ram->monitors_config,
271                 MEMSLOT_GROUP_GUEST,
272                 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
273                                           QXL_IO_MONITORS_CONFIG_ASYNC));
274     }
275 }
276 
277 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
278 {
279     trace_qxl_spice_reset_image_cache(qxl->id);
280     qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
281 }
282 
283 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
284 {
285     trace_qxl_spice_reset_cursor(qxl->id);
286     qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
287     qemu_mutex_lock(&qxl->track_lock);
288     qxl->guest_cursor = 0;
289     qemu_mutex_unlock(&qxl->track_lock);
290     if (qxl->ssd.cursor) {
291         cursor_put(qxl->ssd.cursor);
292     }
293     qxl->ssd.cursor = cursor_builtin_hidden();
294 }
295 
296 
297 static inline uint32_t msb_mask(uint32_t val)
298 {
299     uint32_t mask;
300 
301     do {
302         mask = ~(val - 1) & val;
303         val &= ~mask;
304     } while (mask < val);
305 
306     return mask;
307 }
308 
309 static ram_addr_t qxl_rom_size(void)
310 {
311     uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
312                                  sizeof(qxl_modes);
313     uint32_t rom_size = 8192; /* two pages */
314 
315     required_rom_size = MAX(required_rom_size, TARGET_PAGE_SIZE);
316     required_rom_size = msb_mask(required_rom_size * 2 - 1);
317     assert(required_rom_size <= rom_size);
318     return rom_size;
319 }
320 
321 static void init_qxl_rom(PCIQXLDevice *d)
322 {
323     QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
324     QXLModes *modes = (QXLModes *)(rom + 1);
325     uint32_t ram_header_size;
326     uint32_t surface0_area_size;
327     uint32_t num_pages;
328     uint32_t fb;
329     int i, n;
330 
331     memset(rom, 0, d->rom_size);
332 
333     rom->magic         = cpu_to_le32(QXL_ROM_MAGIC);
334     rom->id            = cpu_to_le32(d->id);
335     rom->log_level     = cpu_to_le32(d->guestdebug);
336     rom->modes_offset  = cpu_to_le32(sizeof(QXLRom));
337 
338     rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
339     rom->slot_id_bits  = MEMSLOT_SLOT_BITS;
340     rom->slots_start   = 1;
341     rom->slots_end     = NUM_MEMSLOTS - 1;
342     rom->n_surfaces    = cpu_to_le32(d->ssd.num_surfaces);
343 
344     for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
345         fb = qxl_modes[i].y_res * qxl_modes[i].stride;
346         if (fb > d->vgamem_size) {
347             continue;
348         }
349         modes->modes[n].id          = cpu_to_le32(i);
350         modes->modes[n].x_res       = cpu_to_le32(qxl_modes[i].x_res);
351         modes->modes[n].y_res       = cpu_to_le32(qxl_modes[i].y_res);
352         modes->modes[n].bits        = cpu_to_le32(qxl_modes[i].bits);
353         modes->modes[n].stride      = cpu_to_le32(qxl_modes[i].stride);
354         modes->modes[n].x_mili      = cpu_to_le32(qxl_modes[i].x_mili);
355         modes->modes[n].y_mili      = cpu_to_le32(qxl_modes[i].y_mili);
356         modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
357         n++;
358     }
359     modes->n_modes     = cpu_to_le32(n);
360 
361     ram_header_size    = ALIGN(sizeof(QXLRam), 4096);
362     surface0_area_size = ALIGN(d->vgamem_size, 4096);
363     num_pages          = d->vga.vram_size;
364     num_pages         -= ram_header_size;
365     num_pages         -= surface0_area_size;
366     num_pages          = num_pages / TARGET_PAGE_SIZE;
367 
368     rom->draw_area_offset   = cpu_to_le32(0);
369     rom->surface0_area_size = cpu_to_le32(surface0_area_size);
370     rom->pages_offset       = cpu_to_le32(surface0_area_size);
371     rom->num_pages          = cpu_to_le32(num_pages);
372     rom->ram_header_offset  = cpu_to_le32(d->vga.vram_size - ram_header_size);
373 
374     d->shadow_rom = *rom;
375     d->rom        = rom;
376     d->modes      = modes;
377 }
378 
379 static void init_qxl_ram(PCIQXLDevice *d)
380 {
381     uint8_t *buf;
382     uint64_t *item;
383 
384     buf = d->vga.vram_ptr;
385     d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
386     d->ram->magic       = cpu_to_le32(QXL_RAM_MAGIC);
387     d->ram->int_pending = cpu_to_le32(0);
388     d->ram->int_mask    = cpu_to_le32(0);
389     d->ram->update_surface = 0;
390     SPICE_RING_INIT(&d->ram->cmd_ring);
391     SPICE_RING_INIT(&d->ram->cursor_ring);
392     SPICE_RING_INIT(&d->ram->release_ring);
393     SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
394     assert(item);
395     *item = 0;
396     qxl_ring_set_dirty(d);
397 }
398 
399 /* can be called from spice server thread context */
400 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
401 {
402     memory_region_set_dirty(mr, addr, end - addr);
403 }
404 
405 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
406 {
407     qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
408 }
409 
410 /* called from spice server thread context only */
411 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
412 {
413     void *base = qxl->vga.vram_ptr;
414     intptr_t offset;
415 
416     offset = ptr - base;
417     offset &= ~(TARGET_PAGE_SIZE-1);
418     assert(offset < qxl->vga.vram_size);
419     qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
420 }
421 
422 /* can be called from spice server thread context */
423 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
424 {
425     ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
426     ram_addr_t end  = qxl->vga.vram_size;
427     qxl_set_dirty(&qxl->vga.vram, addr, end);
428 }
429 
430 /*
431  * keep track of some command state, for savevm/loadvm.
432  * called from spice server thread context only
433  */
434 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
435 {
436     switch (le32_to_cpu(ext->cmd.type)) {
437     case QXL_CMD_SURFACE:
438     {
439         QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
440 
441         if (!cmd) {
442             return 1;
443         }
444         uint32_t id = le32_to_cpu(cmd->surface_id);
445 
446         if (id >= qxl->ssd.num_surfaces) {
447             qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
448                               qxl->ssd.num_surfaces);
449             return 1;
450         }
451         if (cmd->type == QXL_SURFACE_CMD_CREATE &&
452             (cmd->u.surface_create.stride & 0x03) != 0) {
453             qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
454                               cmd->u.surface_create.stride);
455             return 1;
456         }
457         qemu_mutex_lock(&qxl->track_lock);
458         if (cmd->type == QXL_SURFACE_CMD_CREATE) {
459             qxl->guest_surfaces.cmds[id] = ext->cmd.data;
460             qxl->guest_surfaces.count++;
461             if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
462                 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
463         }
464         if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
465             qxl->guest_surfaces.cmds[id] = 0;
466             qxl->guest_surfaces.count--;
467         }
468         qemu_mutex_unlock(&qxl->track_lock);
469         break;
470     }
471     case QXL_CMD_CURSOR:
472     {
473         QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
474 
475         if (!cmd) {
476             return 1;
477         }
478         if (cmd->type == QXL_CURSOR_SET) {
479             qemu_mutex_lock(&qxl->track_lock);
480             qxl->guest_cursor = ext->cmd.data;
481             qemu_mutex_unlock(&qxl->track_lock);
482         }
483         break;
484     }
485     }
486     return 0;
487 }
488 
489 /* spice display interface callbacks */
490 
491 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
492 {
493     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
494 
495     trace_qxl_interface_attach_worker(qxl->id);
496     qxl->ssd.worker = qxl_worker;
497 }
498 
499 static void interface_set_compression_level(QXLInstance *sin, int level)
500 {
501     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
502 
503     trace_qxl_interface_set_compression_level(qxl->id, level);
504     qxl->shadow_rom.compression_level = cpu_to_le32(level);
505     qxl->rom->compression_level = cpu_to_le32(level);
506     qxl_rom_set_dirty(qxl);
507 }
508 
509 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
510 {
511     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
512 
513     trace_qxl_interface_set_mm_time(qxl->id, mm_time);
514     qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
515     qxl->rom->mm_clock = cpu_to_le32(mm_time);
516     qxl_rom_set_dirty(qxl);
517 }
518 
519 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
520 {
521     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
522 
523     trace_qxl_interface_get_init_info(qxl->id);
524     info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
525     info->memslot_id_bits = MEMSLOT_SLOT_BITS;
526     info->num_memslots = NUM_MEMSLOTS;
527     info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
528     info->internal_groupslot_id = 0;
529     info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
530     info->n_surfaces = qxl->ssd.num_surfaces;
531 }
532 
533 static const char *qxl_mode_to_string(int mode)
534 {
535     switch (mode) {
536     case QXL_MODE_COMPAT:
537         return "compat";
538     case QXL_MODE_NATIVE:
539         return "native";
540     case QXL_MODE_UNDEFINED:
541         return "undefined";
542     case QXL_MODE_VGA:
543         return "vga";
544     }
545     return "INVALID";
546 }
547 
548 static const char *io_port_to_string(uint32_t io_port)
549 {
550     if (io_port >= QXL_IO_RANGE_SIZE) {
551         return "out of range";
552     }
553     static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
554         [QXL_IO_NOTIFY_CMD]             = "QXL_IO_NOTIFY_CMD",
555         [QXL_IO_NOTIFY_CURSOR]          = "QXL_IO_NOTIFY_CURSOR",
556         [QXL_IO_UPDATE_AREA]            = "QXL_IO_UPDATE_AREA",
557         [QXL_IO_UPDATE_IRQ]             = "QXL_IO_UPDATE_IRQ",
558         [QXL_IO_NOTIFY_OOM]             = "QXL_IO_NOTIFY_OOM",
559         [QXL_IO_RESET]                  = "QXL_IO_RESET",
560         [QXL_IO_SET_MODE]               = "QXL_IO_SET_MODE",
561         [QXL_IO_LOG]                    = "QXL_IO_LOG",
562         [QXL_IO_MEMSLOT_ADD]            = "QXL_IO_MEMSLOT_ADD",
563         [QXL_IO_MEMSLOT_DEL]            = "QXL_IO_MEMSLOT_DEL",
564         [QXL_IO_DETACH_PRIMARY]         = "QXL_IO_DETACH_PRIMARY",
565         [QXL_IO_ATTACH_PRIMARY]         = "QXL_IO_ATTACH_PRIMARY",
566         [QXL_IO_CREATE_PRIMARY]         = "QXL_IO_CREATE_PRIMARY",
567         [QXL_IO_DESTROY_PRIMARY]        = "QXL_IO_DESTROY_PRIMARY",
568         [QXL_IO_DESTROY_SURFACE_WAIT]   = "QXL_IO_DESTROY_SURFACE_WAIT",
569         [QXL_IO_DESTROY_ALL_SURFACES]   = "QXL_IO_DESTROY_ALL_SURFACES",
570         [QXL_IO_UPDATE_AREA_ASYNC]      = "QXL_IO_UPDATE_AREA_ASYNC",
571         [QXL_IO_MEMSLOT_ADD_ASYNC]      = "QXL_IO_MEMSLOT_ADD_ASYNC",
572         [QXL_IO_CREATE_PRIMARY_ASYNC]   = "QXL_IO_CREATE_PRIMARY_ASYNC",
573         [QXL_IO_DESTROY_PRIMARY_ASYNC]  = "QXL_IO_DESTROY_PRIMARY_ASYNC",
574         [QXL_IO_DESTROY_SURFACE_ASYNC]  = "QXL_IO_DESTROY_SURFACE_ASYNC",
575         [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
576                                         = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
577         [QXL_IO_FLUSH_SURFACES_ASYNC]   = "QXL_IO_FLUSH_SURFACES_ASYNC",
578         [QXL_IO_FLUSH_RELEASE]          = "QXL_IO_FLUSH_RELEASE",
579         [QXL_IO_MONITORS_CONFIG_ASYNC]  = "QXL_IO_MONITORS_CONFIG_ASYNC",
580     };
581     return io_port_to_string[io_port];
582 }
583 
584 /* called from spice server thread context only */
585 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
586 {
587     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
588     SimpleSpiceUpdate *update;
589     QXLCommandRing *ring;
590     QXLCommand *cmd;
591     int notify, ret;
592 
593     trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
594 
595     switch (qxl->mode) {
596     case QXL_MODE_VGA:
597         ret = false;
598         qemu_mutex_lock(&qxl->ssd.lock);
599         update = QTAILQ_FIRST(&qxl->ssd.updates);
600         if (update != NULL) {
601             QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
602             *ext = update->ext;
603             ret = true;
604         }
605         qemu_mutex_unlock(&qxl->ssd.lock);
606         if (ret) {
607             trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
608             qxl_log_command(qxl, "vga", ext);
609         }
610         return ret;
611     case QXL_MODE_COMPAT:
612     case QXL_MODE_NATIVE:
613     case QXL_MODE_UNDEFINED:
614         ring = &qxl->ram->cmd_ring;
615         if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
616             return false;
617         }
618         SPICE_RING_CONS_ITEM(qxl, ring, cmd);
619         if (!cmd) {
620             return false;
621         }
622         ext->cmd      = *cmd;
623         ext->group_id = MEMSLOT_GROUP_GUEST;
624         ext->flags    = qxl->cmdflags;
625         SPICE_RING_POP(ring, notify);
626         qxl_ring_set_dirty(qxl);
627         if (notify) {
628             qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
629         }
630         qxl->guest_primary.commands++;
631         qxl_track_command(qxl, ext);
632         qxl_log_command(qxl, "cmd", ext);
633         trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
634         return true;
635     default:
636         return false;
637     }
638 }
639 
640 /* called from spice server thread context only */
641 static int interface_req_cmd_notification(QXLInstance *sin)
642 {
643     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
644     int wait = 1;
645 
646     trace_qxl_ring_command_req_notification(qxl->id);
647     switch (qxl->mode) {
648     case QXL_MODE_COMPAT:
649     case QXL_MODE_NATIVE:
650     case QXL_MODE_UNDEFINED:
651         SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
652         qxl_ring_set_dirty(qxl);
653         break;
654     default:
655         /* nothing */
656         break;
657     }
658     return wait;
659 }
660 
661 /* called from spice server thread context only */
662 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
663 {
664     QXLReleaseRing *ring = &d->ram->release_ring;
665     uint64_t *item;
666     int notify;
667 
668 #define QXL_FREE_BUNCH_SIZE 32
669 
670     if (ring->prod - ring->cons + 1 == ring->num_items) {
671         /* ring full -- can't push */
672         return;
673     }
674     if (!flush && d->oom_running) {
675         /* collect everything from oom handler before pushing */
676         return;
677     }
678     if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
679         /* collect a bit more before pushing */
680         return;
681     }
682 
683     SPICE_RING_PUSH(ring, notify);
684     trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
685            d->guest_surfaces.count, d->num_free_res,
686            d->last_release, notify ? "yes" : "no");
687     trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
688            ring->num_items, ring->prod, ring->cons);
689     if (notify) {
690         qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
691     }
692     SPICE_RING_PROD_ITEM(d, ring, item);
693     if (!item) {
694         return;
695     }
696     *item = 0;
697     d->num_free_res = 0;
698     d->last_release = NULL;
699     qxl_ring_set_dirty(d);
700 }
701 
702 /* called from spice server thread context only */
703 static void interface_release_resource(QXLInstance *sin,
704                                        struct QXLReleaseInfoExt ext)
705 {
706     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
707     QXLReleaseRing *ring;
708     uint64_t *item, id;
709 
710     if (ext.group_id == MEMSLOT_GROUP_HOST) {
711         /* host group -> vga mode update request */
712         qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
713         return;
714     }
715 
716     /*
717      * ext->info points into guest-visible memory
718      * pci bar 0, $command.release_info
719      */
720     ring = &qxl->ram->release_ring;
721     SPICE_RING_PROD_ITEM(qxl, ring, item);
722     if (!item) {
723         return;
724     }
725     if (*item == 0) {
726         /* stick head into the ring */
727         id = ext.info->id;
728         ext.info->next = 0;
729         qxl_ram_set_dirty(qxl, &ext.info->next);
730         *item = id;
731         qxl_ring_set_dirty(qxl);
732     } else {
733         /* append item to the list */
734         qxl->last_release->next = ext.info->id;
735         qxl_ram_set_dirty(qxl, &qxl->last_release->next);
736         ext.info->next = 0;
737         qxl_ram_set_dirty(qxl, &ext.info->next);
738     }
739     qxl->last_release = ext.info;
740     qxl->num_free_res++;
741     trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
742     qxl_push_free_res(qxl, 0);
743 }
744 
745 /* called from spice server thread context only */
746 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
747 {
748     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
749     QXLCursorRing *ring;
750     QXLCommand *cmd;
751     int notify;
752 
753     trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
754 
755     switch (qxl->mode) {
756     case QXL_MODE_COMPAT:
757     case QXL_MODE_NATIVE:
758     case QXL_MODE_UNDEFINED:
759         ring = &qxl->ram->cursor_ring;
760         if (SPICE_RING_IS_EMPTY(ring)) {
761             return false;
762         }
763         SPICE_RING_CONS_ITEM(qxl, ring, cmd);
764         if (!cmd) {
765             return false;
766         }
767         ext->cmd      = *cmd;
768         ext->group_id = MEMSLOT_GROUP_GUEST;
769         ext->flags    = qxl->cmdflags;
770         SPICE_RING_POP(ring, notify);
771         qxl_ring_set_dirty(qxl);
772         if (notify) {
773             qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
774         }
775         qxl->guest_primary.commands++;
776         qxl_track_command(qxl, ext);
777         qxl_log_command(qxl, "csr", ext);
778         if (qxl->id == 0) {
779             qxl_render_cursor(qxl, ext);
780         }
781         trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
782         return true;
783     default:
784         return false;
785     }
786 }
787 
788 /* called from spice server thread context only */
789 static int interface_req_cursor_notification(QXLInstance *sin)
790 {
791     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
792     int wait = 1;
793 
794     trace_qxl_ring_cursor_req_notification(qxl->id);
795     switch (qxl->mode) {
796     case QXL_MODE_COMPAT:
797     case QXL_MODE_NATIVE:
798     case QXL_MODE_UNDEFINED:
799         SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
800         qxl_ring_set_dirty(qxl);
801         break;
802     default:
803         /* nothing */
804         break;
805     }
806     return wait;
807 }
808 
809 /* called from spice server thread context */
810 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
811 {
812     /*
813      * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
814      * use by xf86-video-qxl and is defined out in the qxl windows driver.
815      * Probably was at some earlier version that is prior to git start (2009),
816      * and is still guest trigerrable.
817      */
818     fprintf(stderr, "%s: deprecated\n", __func__);
819 }
820 
821 /* called from spice server thread context only */
822 static int interface_flush_resources(QXLInstance *sin)
823 {
824     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
825     int ret;
826 
827     ret = qxl->num_free_res;
828     if (ret) {
829         qxl_push_free_res(qxl, 1);
830     }
831     return ret;
832 }
833 
834 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
835 
836 /* called from spice server thread context only */
837 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
838 {
839     uint32_t current_async;
840 
841     qemu_mutex_lock(&qxl->async_lock);
842     current_async = qxl->current_async;
843     qxl->current_async = QXL_UNDEFINED_IO;
844     qemu_mutex_unlock(&qxl->async_lock);
845 
846     trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
847     if (!cookie) {
848         fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
849         return;
850     }
851     if (cookie && current_async != cookie->io) {
852         fprintf(stderr,
853                 "qxl: %s: error: current_async = %d != %"
854                 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
855     }
856     switch (current_async) {
857     case QXL_IO_MEMSLOT_ADD_ASYNC:
858     case QXL_IO_DESTROY_PRIMARY_ASYNC:
859     case QXL_IO_UPDATE_AREA_ASYNC:
860     case QXL_IO_FLUSH_SURFACES_ASYNC:
861     case QXL_IO_MONITORS_CONFIG_ASYNC:
862         break;
863     case QXL_IO_CREATE_PRIMARY_ASYNC:
864         qxl_create_guest_primary_complete(qxl);
865         break;
866     case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
867         qxl_spice_destroy_surfaces_complete(qxl);
868         break;
869     case QXL_IO_DESTROY_SURFACE_ASYNC:
870         qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
871         break;
872     default:
873         fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
874                 current_async);
875     }
876     qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
877 }
878 
879 /* called from spice server thread context only */
880 static void interface_update_area_complete(QXLInstance *sin,
881         uint32_t surface_id,
882         QXLRect *dirty, uint32_t num_updated_rects)
883 {
884     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
885     int i;
886     int qxl_i;
887 
888     qemu_mutex_lock(&qxl->ssd.lock);
889     if (surface_id != 0 || !qxl->render_update_cookie_num) {
890         qemu_mutex_unlock(&qxl->ssd.lock);
891         return;
892     }
893     trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
894             dirty->right, dirty->top, dirty->bottom);
895     trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
896     if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
897         /*
898          * overflow - treat this as a full update. Not expected to be common.
899          */
900         trace_qxl_interface_update_area_complete_overflow(qxl->id,
901                                                           QXL_NUM_DIRTY_RECTS);
902         qxl->guest_primary.resized = 1;
903     }
904     if (qxl->guest_primary.resized) {
905         /*
906          * Don't bother copying or scheduling the bh since we will flip
907          * the whole area anyway on completion of the update_area async call
908          */
909         qemu_mutex_unlock(&qxl->ssd.lock);
910         return;
911     }
912     qxl_i = qxl->num_dirty_rects;
913     for (i = 0; i < num_updated_rects; i++) {
914         qxl->dirty[qxl_i++] = dirty[i];
915     }
916     qxl->num_dirty_rects += num_updated_rects;
917     trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
918                                                          qxl->num_dirty_rects);
919     qemu_bh_schedule(qxl->update_area_bh);
920     qemu_mutex_unlock(&qxl->ssd.lock);
921 }
922 
923 /* called from spice server thread context only */
924 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
925 {
926     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
927     QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
928 
929     switch (cookie->type) {
930     case QXL_COOKIE_TYPE_IO:
931         interface_async_complete_io(qxl, cookie);
932         g_free(cookie);
933         break;
934     case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
935         qxl_render_update_area_done(qxl, cookie);
936         break;
937     case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
938         break;
939     default:
940         fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
941                 __func__, cookie->type);
942         g_free(cookie);
943     }
944 }
945 
946 /* called from spice server thread context only */
947 static void interface_set_client_capabilities(QXLInstance *sin,
948                                               uint8_t client_present,
949                                               uint8_t caps[58])
950 {
951     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
952 
953     if (qxl->revision < 4) {
954         trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
955                                                               qxl->revision);
956         return;
957     }
958 
959     if (runstate_check(RUN_STATE_INMIGRATE) ||
960         runstate_check(RUN_STATE_POSTMIGRATE)) {
961         return;
962     }
963 
964     qxl->shadow_rom.client_present = client_present;
965     memcpy(qxl->shadow_rom.client_capabilities, caps,
966            sizeof(qxl->shadow_rom.client_capabilities));
967     qxl->rom->client_present = client_present;
968     memcpy(qxl->rom->client_capabilities, caps,
969            sizeof(qxl->rom->client_capabilities));
970     qxl_rom_set_dirty(qxl);
971 
972     qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
973 }
974 
975 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
976 {
977     /*
978      * zlib xors the seed with 0xffffffff, and xors the result
979      * again with 0xffffffff; Both are not done with linux's crc32,
980      * which we want to be compatible with, so undo that.
981      */
982     return crc32(0xffffffff, p, len) ^ 0xffffffff;
983 }
984 
985 /* called from main context only */
986 static int interface_client_monitors_config(QXLInstance *sin,
987                                         VDAgentMonitorsConfig *monitors_config)
988 {
989     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
990     QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
991     int i;
992 
993     if (qxl->revision < 4) {
994         trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
995                                                                qxl->revision);
996         return 0;
997     }
998     /*
999      * Older windows drivers set int_mask to 0 when their ISR is called,
1000      * then later set it to ~0. So it doesn't relate to the actual interrupts
1001      * handled. However, they are old, so clearly they don't support this
1002      * interrupt
1003      */
1004     if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1005         !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1006         trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1007                                                             qxl->ram->int_mask,
1008                                                             monitors_config);
1009         return 0;
1010     }
1011     if (!monitors_config) {
1012         return 1;
1013     }
1014     memset(&rom->client_monitors_config, 0,
1015            sizeof(rom->client_monitors_config));
1016     rom->client_monitors_config.count = monitors_config->num_of_monitors;
1017     /* monitors_config->flags ignored */
1018     if (rom->client_monitors_config.count >=
1019             ARRAY_SIZE(rom->client_monitors_config.heads)) {
1020         trace_qxl_client_monitors_config_capped(qxl->id,
1021                                 monitors_config->num_of_monitors,
1022                                 ARRAY_SIZE(rom->client_monitors_config.heads));
1023         rom->client_monitors_config.count =
1024             ARRAY_SIZE(rom->client_monitors_config.heads);
1025     }
1026     for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1027         VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1028         QXLURect *rect = &rom->client_monitors_config.heads[i];
1029         /* monitor->depth ignored */
1030         rect->left = monitor->x;
1031         rect->top = monitor->y;
1032         rect->right = monitor->x + monitor->width;
1033         rect->bottom = monitor->y + monitor->height;
1034     }
1035     rom->client_monitors_config_crc = qxl_crc32(
1036             (const uint8_t *)&rom->client_monitors_config,
1037             sizeof(rom->client_monitors_config));
1038     trace_qxl_client_monitors_config_crc(qxl->id,
1039             sizeof(rom->client_monitors_config),
1040             rom->client_monitors_config_crc);
1041 
1042     trace_qxl_interrupt_client_monitors_config(qxl->id,
1043                         rom->client_monitors_config.count,
1044                         rom->client_monitors_config.heads);
1045     qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1046     return 1;
1047 }
1048 
1049 static const QXLInterface qxl_interface = {
1050     .base.type               = SPICE_INTERFACE_QXL,
1051     .base.description        = "qxl gpu",
1052     .base.major_version      = SPICE_INTERFACE_QXL_MAJOR,
1053     .base.minor_version      = SPICE_INTERFACE_QXL_MINOR,
1054 
1055     .attache_worker          = interface_attach_worker,
1056     .set_compression_level   = interface_set_compression_level,
1057     .set_mm_time             = interface_set_mm_time,
1058     .get_init_info           = interface_get_init_info,
1059 
1060     /* the callbacks below are called from spice server thread context */
1061     .get_command             = interface_get_command,
1062     .req_cmd_notification    = interface_req_cmd_notification,
1063     .release_resource        = interface_release_resource,
1064     .get_cursor_command      = interface_get_cursor_command,
1065     .req_cursor_notification = interface_req_cursor_notification,
1066     .notify_update           = interface_notify_update,
1067     .flush_resources         = interface_flush_resources,
1068     .async_complete          = interface_async_complete,
1069     .update_area_complete    = interface_update_area_complete,
1070     .set_client_capabilities = interface_set_client_capabilities,
1071     .client_monitors_config = interface_client_monitors_config,
1072 };
1073 
1074 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1075 {
1076     if (d->mode == QXL_MODE_VGA) {
1077         return;
1078     }
1079     trace_qxl_enter_vga_mode(d->id);
1080 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1081     spice_qxl_driver_unload(&d->ssd.qxl);
1082 #endif
1083     qemu_spice_create_host_primary(&d->ssd);
1084     d->mode = QXL_MODE_VGA;
1085     vga_dirty_log_start(&d->vga);
1086     graphic_hw_update(d->vga.con);
1087 }
1088 
1089 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1090 {
1091     if (d->mode != QXL_MODE_VGA) {
1092         return;
1093     }
1094     trace_qxl_exit_vga_mode(d->id);
1095     vga_dirty_log_stop(&d->vga);
1096     qxl_destroy_primary(d, QXL_SYNC);
1097 }
1098 
1099 static void qxl_update_irq(PCIQXLDevice *d)
1100 {
1101     uint32_t pending = le32_to_cpu(d->ram->int_pending);
1102     uint32_t mask    = le32_to_cpu(d->ram->int_mask);
1103     int level = !!(pending & mask);
1104     qemu_set_irq(d->pci.irq[0], level);
1105     qxl_ring_set_dirty(d);
1106 }
1107 
1108 static void qxl_check_state(PCIQXLDevice *d)
1109 {
1110     QXLRam *ram = d->ram;
1111     int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1112 
1113     assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1114     assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1115 }
1116 
1117 static void qxl_reset_state(PCIQXLDevice *d)
1118 {
1119     QXLRom *rom = d->rom;
1120 
1121     qxl_check_state(d);
1122     d->shadow_rom.update_id = cpu_to_le32(0);
1123     *rom = d->shadow_rom;
1124     qxl_rom_set_dirty(d);
1125     init_qxl_ram(d);
1126     d->num_free_res = 0;
1127     d->last_release = NULL;
1128     memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1129 }
1130 
1131 static void qxl_soft_reset(PCIQXLDevice *d)
1132 {
1133     trace_qxl_soft_reset(d->id);
1134     qxl_check_state(d);
1135     qxl_clear_guest_bug(d);
1136     d->current_async = QXL_UNDEFINED_IO;
1137 
1138     if (d->id == 0) {
1139         qxl_enter_vga_mode(d);
1140     } else {
1141         d->mode = QXL_MODE_UNDEFINED;
1142     }
1143 }
1144 
1145 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1146 {
1147     trace_qxl_hard_reset(d->id, loadvm);
1148 
1149     qxl_spice_reset_cursor(d);
1150     qxl_spice_reset_image_cache(d);
1151     qxl_reset_surfaces(d);
1152     qxl_reset_memslots(d);
1153 
1154     /* pre loadvm reset must not touch QXLRam.  This lives in
1155      * device memory, is migrated together with RAM and thus
1156      * already loaded at this point */
1157     if (!loadvm) {
1158         qxl_reset_state(d);
1159     }
1160     qemu_spice_create_host_memslot(&d->ssd);
1161     qxl_soft_reset(d);
1162 }
1163 
1164 static void qxl_reset_handler(DeviceState *dev)
1165 {
1166     PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
1167 
1168     qxl_hard_reset(d, 0);
1169 }
1170 
1171 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1172 {
1173     VGACommonState *vga = opaque;
1174     PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1175 
1176     trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1177     if (qxl->mode != QXL_MODE_VGA) {
1178         qxl_destroy_primary(qxl, QXL_SYNC);
1179         qxl_soft_reset(qxl);
1180     }
1181     vga_ioport_write(opaque, addr, val);
1182 }
1183 
1184 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1185     { 0x04,  2, 1, .read  = vga_ioport_read,
1186                    .write = qxl_vga_ioport_write }, /* 3b4 */
1187     { 0x0a,  1, 1, .read  = vga_ioport_read,
1188                    .write = qxl_vga_ioport_write }, /* 3ba */
1189     { 0x10, 16, 1, .read  = vga_ioport_read,
1190                    .write = qxl_vga_ioport_write }, /* 3c0 */
1191     { 0x24,  2, 1, .read  = vga_ioport_read,
1192                    .write = qxl_vga_ioport_write }, /* 3d4 */
1193     { 0x2a,  1, 1, .read  = vga_ioport_read,
1194                    .write = qxl_vga_ioport_write }, /* 3da */
1195     PORTIO_END_OF_LIST(),
1196 };
1197 
1198 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1199                            qxl_async_io async)
1200 {
1201     static const int regions[] = {
1202         QXL_RAM_RANGE_INDEX,
1203         QXL_VRAM_RANGE_INDEX,
1204         QXL_VRAM64_RANGE_INDEX,
1205     };
1206     uint64_t guest_start;
1207     uint64_t guest_end;
1208     int pci_region;
1209     pcibus_t pci_start;
1210     pcibus_t pci_end;
1211     intptr_t virt_start;
1212     QXLDevMemSlot memslot;
1213     int i;
1214 
1215     guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1216     guest_end   = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1217 
1218     trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1219 
1220     if (slot_id >= NUM_MEMSLOTS) {
1221         qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1222                       slot_id, NUM_MEMSLOTS);
1223         return 1;
1224     }
1225     if (guest_start > guest_end) {
1226         qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1227                          " > 0x%" PRIx64, __func__, guest_start, guest_end);
1228         return 1;
1229     }
1230 
1231     for (i = 0; i < ARRAY_SIZE(regions); i++) {
1232         pci_region = regions[i];
1233         pci_start = d->pci.io_regions[pci_region].addr;
1234         pci_end = pci_start + d->pci.io_regions[pci_region].size;
1235         /* mapped? */
1236         if (pci_start == -1) {
1237             continue;
1238         }
1239         /* start address in range ? */
1240         if (guest_start < pci_start || guest_start > pci_end) {
1241             continue;
1242         }
1243         /* end address in range ? */
1244         if (guest_end > pci_end) {
1245             continue;
1246         }
1247         /* passed */
1248         break;
1249     }
1250     if (i == ARRAY_SIZE(regions)) {
1251         qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1252         return 1;
1253     }
1254 
1255     switch (pci_region) {
1256     case QXL_RAM_RANGE_INDEX:
1257         virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1258         break;
1259     case QXL_VRAM_RANGE_INDEX:
1260     case 4 /* vram 64bit */:
1261         virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1262         break;
1263     default:
1264         /* should not happen */
1265         qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1266         return 1;
1267     }
1268 
1269     memslot.slot_id = slot_id;
1270     memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1271     memslot.virt_start = virt_start + (guest_start - pci_start);
1272     memslot.virt_end   = virt_start + (guest_end   - pci_start);
1273     memslot.addr_delta = memslot.virt_start - delta;
1274     memslot.generation = d->rom->slot_generation = 0;
1275     qxl_rom_set_dirty(d);
1276 
1277     qemu_spice_add_memslot(&d->ssd, &memslot, async);
1278     d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1279     d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1280     d->guest_slots[slot_id].delta = delta;
1281     d->guest_slots[slot_id].active = 1;
1282     return 0;
1283 }
1284 
1285 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1286 {
1287     qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1288     d->guest_slots[slot_id].active = 0;
1289 }
1290 
1291 static void qxl_reset_memslots(PCIQXLDevice *d)
1292 {
1293     qxl_spice_reset_memslots(d);
1294     memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1295 }
1296 
1297 static void qxl_reset_surfaces(PCIQXLDevice *d)
1298 {
1299     trace_qxl_reset_surfaces(d->id);
1300     d->mode = QXL_MODE_UNDEFINED;
1301     qxl_spice_destroy_surfaces(d, QXL_SYNC);
1302 }
1303 
1304 /* can be also called from spice server thread context */
1305 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1306 {
1307     uint64_t phys   = le64_to_cpu(pqxl);
1308     uint32_t slot   = (phys >> (64 -  8)) & 0xff;
1309     uint64_t offset = phys & 0xffffffffffff;
1310 
1311     switch (group_id) {
1312     case MEMSLOT_GROUP_HOST:
1313         return (void *)(intptr_t)offset;
1314     case MEMSLOT_GROUP_GUEST:
1315         if (slot >= NUM_MEMSLOTS) {
1316             qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1317                               NUM_MEMSLOTS);
1318             return NULL;
1319         }
1320         if (!qxl->guest_slots[slot].active) {
1321             qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1322             return NULL;
1323         }
1324         if (offset < qxl->guest_slots[slot].delta) {
1325             qxl_set_guest_bug(qxl,
1326                           "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1327                           slot, offset, qxl->guest_slots[slot].delta);
1328             return NULL;
1329         }
1330         offset -= qxl->guest_slots[slot].delta;
1331         if (offset > qxl->guest_slots[slot].size) {
1332             qxl_set_guest_bug(qxl,
1333                           "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1334                           slot, offset, qxl->guest_slots[slot].size);
1335             return NULL;
1336         }
1337         return qxl->guest_slots[slot].ptr + offset;
1338     }
1339     return NULL;
1340 }
1341 
1342 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1343 {
1344     /* for local rendering */
1345     qxl_render_resize(qxl);
1346 }
1347 
1348 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1349                                      qxl_async_io async)
1350 {
1351     QXLDevSurfaceCreate surface;
1352     QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1353     int size;
1354     int requested_height = le32_to_cpu(sc->height);
1355     int requested_stride = le32_to_cpu(sc->stride);
1356 
1357     size = abs(requested_stride) * requested_height;
1358     if (size > qxl->vgamem_size) {
1359         qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer"
1360                                " size", __func__);
1361         return;
1362     }
1363 
1364     if (qxl->mode == QXL_MODE_NATIVE) {
1365         qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1366                       __func__);
1367     }
1368     qxl_exit_vga_mode(qxl);
1369 
1370     surface.format     = le32_to_cpu(sc->format);
1371     surface.height     = le32_to_cpu(sc->height);
1372     surface.mem        = le64_to_cpu(sc->mem);
1373     surface.position   = le32_to_cpu(sc->position);
1374     surface.stride     = le32_to_cpu(sc->stride);
1375     surface.width      = le32_to_cpu(sc->width);
1376     surface.type       = le32_to_cpu(sc->type);
1377     surface.flags      = le32_to_cpu(sc->flags);
1378     trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1379                                    sc->format, sc->position);
1380     trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1381                                         sc->flags);
1382 
1383     if ((surface.stride & 0x3) != 0) {
1384         qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1385                           surface.stride);
1386         return;
1387     }
1388 
1389     surface.mouse_mode = true;
1390     surface.group_id   = MEMSLOT_GROUP_GUEST;
1391     if (loadvm) {
1392         surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1393     }
1394 
1395     qxl->mode = QXL_MODE_NATIVE;
1396     qxl->cmdflags = 0;
1397     qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1398 
1399     if (async == QXL_SYNC) {
1400         qxl_create_guest_primary_complete(qxl);
1401     }
1402 }
1403 
1404 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1405  * done (in QXL_SYNC case), 0 otherwise. */
1406 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1407 {
1408     if (d->mode == QXL_MODE_UNDEFINED) {
1409         return 0;
1410     }
1411     trace_qxl_destroy_primary(d->id);
1412     d->mode = QXL_MODE_UNDEFINED;
1413     qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1414     qxl_spice_reset_cursor(d);
1415     return 1;
1416 }
1417 
1418 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1419 {
1420     pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1421     pcibus_t end   = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1422     QXLMode *mode = d->modes->modes + modenr;
1423     uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1424     QXLMemSlot slot = {
1425         .mem_start = start,
1426         .mem_end = end
1427     };
1428     QXLSurfaceCreate surface = {
1429         .width      = mode->x_res,
1430         .height     = mode->y_res,
1431         .stride     = -mode->x_res * 4,
1432         .format     = SPICE_SURFACE_FMT_32_xRGB,
1433         .flags      = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1434         .mouse_mode = true,
1435         .mem        = devmem + d->shadow_rom.draw_area_offset,
1436     };
1437 
1438     trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1439                        devmem);
1440     if (!loadvm) {
1441         qxl_hard_reset(d, 0);
1442     }
1443 
1444     d->guest_slots[0].slot = slot;
1445     assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1446 
1447     d->guest_primary.surface = surface;
1448     qxl_create_guest_primary(d, 0, QXL_SYNC);
1449 
1450     d->mode = QXL_MODE_COMPAT;
1451     d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1452     if (mode->bits == 16) {
1453         d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1454     }
1455     d->shadow_rom.mode = cpu_to_le32(modenr);
1456     d->rom->mode = cpu_to_le32(modenr);
1457     qxl_rom_set_dirty(d);
1458 }
1459 
1460 static void ioport_write(void *opaque, hwaddr addr,
1461                          uint64_t val, unsigned size)
1462 {
1463     PCIQXLDevice *d = opaque;
1464     uint32_t io_port = addr;
1465     qxl_async_io async = QXL_SYNC;
1466     uint32_t orig_io_port = io_port;
1467 
1468     if (d->guest_bug && io_port != QXL_IO_RESET) {
1469         return;
1470     }
1471 
1472     if (d->revision <= QXL_REVISION_STABLE_V10 &&
1473         io_port > QXL_IO_FLUSH_RELEASE) {
1474         qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1475             io_port, d->revision);
1476         return;
1477     }
1478 
1479     switch (io_port) {
1480     case QXL_IO_RESET:
1481     case QXL_IO_SET_MODE:
1482     case QXL_IO_MEMSLOT_ADD:
1483     case QXL_IO_MEMSLOT_DEL:
1484     case QXL_IO_CREATE_PRIMARY:
1485     case QXL_IO_UPDATE_IRQ:
1486     case QXL_IO_LOG:
1487     case QXL_IO_MEMSLOT_ADD_ASYNC:
1488     case QXL_IO_CREATE_PRIMARY_ASYNC:
1489         break;
1490     default:
1491         if (d->mode != QXL_MODE_VGA) {
1492             break;
1493         }
1494         trace_qxl_io_unexpected_vga_mode(d->id,
1495             addr, val, io_port_to_string(io_port));
1496         /* be nice to buggy guest drivers */
1497         if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1498             io_port < QXL_IO_RANGE_SIZE) {
1499             qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1500         }
1501         return;
1502     }
1503 
1504     /* we change the io_port to avoid ifdeffery in the main switch */
1505     orig_io_port = io_port;
1506     switch (io_port) {
1507     case QXL_IO_UPDATE_AREA_ASYNC:
1508         io_port = QXL_IO_UPDATE_AREA;
1509         goto async_common;
1510     case QXL_IO_MEMSLOT_ADD_ASYNC:
1511         io_port = QXL_IO_MEMSLOT_ADD;
1512         goto async_common;
1513     case QXL_IO_CREATE_PRIMARY_ASYNC:
1514         io_port = QXL_IO_CREATE_PRIMARY;
1515         goto async_common;
1516     case QXL_IO_DESTROY_PRIMARY_ASYNC:
1517         io_port = QXL_IO_DESTROY_PRIMARY;
1518         goto async_common;
1519     case QXL_IO_DESTROY_SURFACE_ASYNC:
1520         io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1521         goto async_common;
1522     case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1523         io_port = QXL_IO_DESTROY_ALL_SURFACES;
1524         goto async_common;
1525     case QXL_IO_FLUSH_SURFACES_ASYNC:
1526     case QXL_IO_MONITORS_CONFIG_ASYNC:
1527 async_common:
1528         async = QXL_ASYNC;
1529         qemu_mutex_lock(&d->async_lock);
1530         if (d->current_async != QXL_UNDEFINED_IO) {
1531             qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1532                 io_port, d->current_async);
1533             qemu_mutex_unlock(&d->async_lock);
1534             return;
1535         }
1536         d->current_async = orig_io_port;
1537         qemu_mutex_unlock(&d->async_lock);
1538         break;
1539     default:
1540         break;
1541     }
1542     trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size,
1543                        async);
1544 
1545     switch (io_port) {
1546     case QXL_IO_UPDATE_AREA:
1547     {
1548         QXLCookie *cookie = NULL;
1549         QXLRect update = d->ram->update_area;
1550 
1551         if (d->ram->update_surface > d->ssd.num_surfaces) {
1552             qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1553                               d->ram->update_surface);
1554             break;
1555         }
1556         if (update.left >= update.right || update.top >= update.bottom ||
1557             update.left < 0 || update.top < 0) {
1558             qxl_set_guest_bug(d,
1559                     "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1560                     update.left, update.top, update.right, update.bottom);
1561             break;
1562         }
1563         if (async == QXL_ASYNC) {
1564             cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1565                                     QXL_IO_UPDATE_AREA_ASYNC);
1566             cookie->u.area = update;
1567         }
1568         qxl_spice_update_area(d, d->ram->update_surface,
1569                               cookie ? &cookie->u.area : &update,
1570                               NULL, 0, 0, async, cookie);
1571         break;
1572     }
1573     case QXL_IO_NOTIFY_CMD:
1574         qemu_spice_wakeup(&d->ssd);
1575         break;
1576     case QXL_IO_NOTIFY_CURSOR:
1577         qemu_spice_wakeup(&d->ssd);
1578         break;
1579     case QXL_IO_UPDATE_IRQ:
1580         qxl_update_irq(d);
1581         break;
1582     case QXL_IO_NOTIFY_OOM:
1583         if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1584             break;
1585         }
1586         d->oom_running = 1;
1587         qxl_spice_oom(d);
1588         d->oom_running = 0;
1589         break;
1590     case QXL_IO_SET_MODE:
1591         qxl_set_mode(d, val, 0);
1592         break;
1593     case QXL_IO_LOG:
1594         trace_qxl_io_log(d->id, d->ram->log_buf);
1595         if (d->guestdebug) {
1596             fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1597                     qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1598         }
1599         break;
1600     case QXL_IO_RESET:
1601         qxl_hard_reset(d, 0);
1602         break;
1603     case QXL_IO_MEMSLOT_ADD:
1604         if (val >= NUM_MEMSLOTS) {
1605             qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1606             break;
1607         }
1608         if (d->guest_slots[val].active) {
1609             qxl_set_guest_bug(d,
1610                         "QXL_IO_MEMSLOT_ADD: memory slot already active");
1611             break;
1612         }
1613         d->guest_slots[val].slot = d->ram->mem_slot;
1614         qxl_add_memslot(d, val, 0, async);
1615         break;
1616     case QXL_IO_MEMSLOT_DEL:
1617         if (val >= NUM_MEMSLOTS) {
1618             qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1619             break;
1620         }
1621         qxl_del_memslot(d, val);
1622         break;
1623     case QXL_IO_CREATE_PRIMARY:
1624         if (val != 0) {
1625             qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1626                           async);
1627             goto cancel_async;
1628         }
1629         d->guest_primary.surface = d->ram->create_surface;
1630         qxl_create_guest_primary(d, 0, async);
1631         break;
1632     case QXL_IO_DESTROY_PRIMARY:
1633         if (val != 0) {
1634             qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1635                           async);
1636             goto cancel_async;
1637         }
1638         if (!qxl_destroy_primary(d, async)) {
1639             trace_qxl_io_destroy_primary_ignored(d->id,
1640                                                  qxl_mode_to_string(d->mode));
1641             goto cancel_async;
1642         }
1643         break;
1644     case QXL_IO_DESTROY_SURFACE_WAIT:
1645         if (val >= d->ssd.num_surfaces) {
1646             qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1647                              "%" PRIu64 " >= NUM_SURFACES", async, val);
1648             goto cancel_async;
1649         }
1650         qxl_spice_destroy_surface_wait(d, val, async);
1651         break;
1652     case QXL_IO_FLUSH_RELEASE: {
1653         QXLReleaseRing *ring = &d->ram->release_ring;
1654         if (ring->prod - ring->cons + 1 == ring->num_items) {
1655             fprintf(stderr,
1656                 "ERROR: no flush, full release ring [p%d,%dc]\n",
1657                 ring->prod, ring->cons);
1658         }
1659         qxl_push_free_res(d, 1 /* flush */);
1660         break;
1661     }
1662     case QXL_IO_FLUSH_SURFACES_ASYNC:
1663         qxl_spice_flush_surfaces_async(d);
1664         break;
1665     case QXL_IO_DESTROY_ALL_SURFACES:
1666         d->mode = QXL_MODE_UNDEFINED;
1667         qxl_spice_destroy_surfaces(d, async);
1668         break;
1669     case QXL_IO_MONITORS_CONFIG_ASYNC:
1670         qxl_spice_monitors_config_async(d, 0);
1671         break;
1672     default:
1673         qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1674     }
1675     return;
1676 cancel_async:
1677     if (async) {
1678         qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1679         qemu_mutex_lock(&d->async_lock);
1680         d->current_async = QXL_UNDEFINED_IO;
1681         qemu_mutex_unlock(&d->async_lock);
1682     }
1683 }
1684 
1685 static uint64_t ioport_read(void *opaque, hwaddr addr,
1686                             unsigned size)
1687 {
1688     PCIQXLDevice *qxl = opaque;
1689 
1690     trace_qxl_io_read_unexpected(qxl->id);
1691     return 0xff;
1692 }
1693 
1694 static const MemoryRegionOps qxl_io_ops = {
1695     .read = ioport_read,
1696     .write = ioport_write,
1697     .valid = {
1698         .min_access_size = 1,
1699         .max_access_size = 1,
1700     },
1701 };
1702 
1703 static void pipe_read(void *opaque)
1704 {
1705     PCIQXLDevice *d = opaque;
1706     char dummy;
1707     int len;
1708 
1709     do {
1710         len = read(d->pipe[0], &dummy, sizeof(dummy));
1711     } while (len == sizeof(dummy));
1712     qxl_update_irq(d);
1713 }
1714 
1715 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1716 {
1717     uint32_t old_pending;
1718     uint32_t le_events = cpu_to_le32(events);
1719 
1720     trace_qxl_send_events(d->id, events);
1721     if (!qemu_spice_display_is_running(&d->ssd)) {
1722         /* spice-server tracks guest running state and should not do this */
1723         fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1724                 __func__);
1725         trace_qxl_send_events_vm_stopped(d->id, events);
1726         return;
1727     }
1728     old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1729     if ((old_pending & le_events) == le_events) {
1730         return;
1731     }
1732     if (qemu_thread_is_self(&d->main)) {
1733         qxl_update_irq(d);
1734     } else {
1735         if (write(d->pipe[1], d, 1) != 1) {
1736             dprint(d, 1, "%s: write to pipe failed\n", __func__);
1737         }
1738     }
1739 }
1740 
1741 static void init_pipe_signaling(PCIQXLDevice *d)
1742 {
1743     if (pipe(d->pipe) < 0) {
1744         fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
1745                 __FILE__, __func__);
1746         exit(1);
1747     }
1748     fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1749     fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1750     fcntl(d->pipe[0], F_SETOWN, getpid());
1751 
1752     qemu_thread_get_self(&d->main);
1753     qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1754 }
1755 
1756 /* graphics console */
1757 
1758 static void qxl_hw_update(void *opaque)
1759 {
1760     PCIQXLDevice *qxl = opaque;
1761     VGACommonState *vga = &qxl->vga;
1762 
1763     switch (qxl->mode) {
1764     case QXL_MODE_VGA:
1765         vga->hw_ops->gfx_update(vga);
1766         break;
1767     case QXL_MODE_COMPAT:
1768     case QXL_MODE_NATIVE:
1769         qxl_render_update(qxl);
1770         break;
1771     default:
1772         break;
1773     }
1774 }
1775 
1776 static void qxl_hw_invalidate(void *opaque)
1777 {
1778     PCIQXLDevice *qxl = opaque;
1779     VGACommonState *vga = &qxl->vga;
1780 
1781     if (qxl->mode == QXL_MODE_VGA) {
1782         vga->hw_ops->invalidate(vga);
1783         return;
1784     }
1785 }
1786 
1787 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1788 {
1789     PCIQXLDevice *qxl = opaque;
1790     VGACommonState *vga = &qxl->vga;
1791 
1792     if (qxl->mode == QXL_MODE_VGA) {
1793         vga->hw_ops->text_update(vga, chardata);
1794         return;
1795     }
1796 }
1797 
1798 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1799 {
1800     uintptr_t vram_start;
1801     int i;
1802 
1803     if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1804         return;
1805     }
1806 
1807     /* dirty the primary surface */
1808     qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1809                   qxl->shadow_rom.surface0_area_size);
1810 
1811     vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1812 
1813     /* dirty the off-screen surfaces */
1814     for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1815         QXLSurfaceCmd *cmd;
1816         intptr_t surface_offset;
1817         int surface_size;
1818 
1819         if (qxl->guest_surfaces.cmds[i] == 0) {
1820             continue;
1821         }
1822 
1823         cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1824                             MEMSLOT_GROUP_GUEST);
1825         assert(cmd);
1826         assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1827         surface_offset = (intptr_t)qxl_phys2virt(qxl,
1828                                                  cmd->u.surface_create.data,
1829                                                  MEMSLOT_GROUP_GUEST);
1830         assert(surface_offset);
1831         surface_offset -= vram_start;
1832         surface_size = cmd->u.surface_create.height *
1833                        abs(cmd->u.surface_create.stride);
1834         trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1835         qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1836     }
1837 }
1838 
1839 static void qxl_vm_change_state_handler(void *opaque, int running,
1840                                         RunState state)
1841 {
1842     PCIQXLDevice *qxl = opaque;
1843 
1844     if (running) {
1845         /*
1846          * if qxl_send_events was called from spice server context before
1847          * migration ended, qxl_update_irq for these events might not have been
1848          * called
1849          */
1850          qxl_update_irq(qxl);
1851     } else {
1852         /* make sure surfaces are saved before migration */
1853         qxl_dirty_surfaces(qxl);
1854     }
1855 }
1856 
1857 /* display change listener */
1858 
1859 static void display_update(DisplayChangeListener *dcl,
1860                            int x, int y, int w, int h)
1861 {
1862     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1863 
1864     if (qxl->mode == QXL_MODE_VGA) {
1865         qemu_spice_display_update(&qxl->ssd, x, y, w, h);
1866     }
1867 }
1868 
1869 static void display_switch(DisplayChangeListener *dcl,
1870                            struct DisplaySurface *surface)
1871 {
1872     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1873 
1874     qxl->ssd.ds = surface;
1875     if (qxl->mode == QXL_MODE_VGA) {
1876         qemu_spice_display_switch(&qxl->ssd, surface);
1877     }
1878 }
1879 
1880 static void display_refresh(DisplayChangeListener *dcl)
1881 {
1882     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1883 
1884     if (qxl->mode == QXL_MODE_VGA) {
1885         qemu_spice_display_refresh(&qxl->ssd);
1886     } else {
1887         qemu_mutex_lock(&qxl->ssd.lock);
1888         qemu_spice_cursor_refresh_unlocked(&qxl->ssd);
1889         qemu_mutex_unlock(&qxl->ssd.lock);
1890     }
1891 }
1892 
1893 static DisplayChangeListenerOps display_listener_ops = {
1894     .dpy_name        = "spice/qxl",
1895     .dpy_gfx_update  = display_update,
1896     .dpy_gfx_switch  = display_switch,
1897     .dpy_refresh     = display_refresh,
1898 };
1899 
1900 static void qxl_init_ramsize(PCIQXLDevice *qxl)
1901 {
1902     /* vga mode framebuffer / primary surface (bar 0, first part) */
1903     if (qxl->vgamem_size_mb < 8) {
1904         qxl->vgamem_size_mb = 8;
1905     }
1906     qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1907 
1908     /* vga ram (bar 0, total) */
1909     if (qxl->ram_size_mb != -1) {
1910         qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1911     }
1912     if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1913         qxl->vga.vram_size = qxl->vgamem_size * 2;
1914     }
1915 
1916     /* vram32 (surfaces, 32bit, bar 1) */
1917     if (qxl->vram32_size_mb != -1) {
1918         qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1919     }
1920     if (qxl->vram32_size < 4096) {
1921         qxl->vram32_size = 4096;
1922     }
1923 
1924     /* vram (surfaces, 64bit, bar 4+5) */
1925     if (qxl->vram_size_mb != -1) {
1926         qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1927     }
1928     if (qxl->vram_size < qxl->vram32_size) {
1929         qxl->vram_size = qxl->vram32_size;
1930     }
1931 
1932     if (qxl->revision == 1) {
1933         qxl->vram32_size = 4096;
1934         qxl->vram_size = 4096;
1935     }
1936     qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
1937     qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1938     qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
1939     qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1940 }
1941 
1942 static int qxl_init_common(PCIQXLDevice *qxl)
1943 {
1944     uint8_t* config = qxl->pci.config;
1945     uint32_t pci_device_rev;
1946     uint32_t io_size;
1947 
1948     qxl->mode = QXL_MODE_UNDEFINED;
1949     qxl->generation = 1;
1950     qxl->num_memslots = NUM_MEMSLOTS;
1951     qemu_mutex_init(&qxl->track_lock);
1952     qemu_mutex_init(&qxl->async_lock);
1953     qxl->current_async = QXL_UNDEFINED_IO;
1954     qxl->guest_bug = 0;
1955 
1956     switch (qxl->revision) {
1957     case 1: /* spice 0.4 -- qxl-1 */
1958         pci_device_rev = QXL_REVISION_STABLE_V04;
1959         io_size = 8;
1960         break;
1961     case 2: /* spice 0.6 -- qxl-2 */
1962         pci_device_rev = QXL_REVISION_STABLE_V06;
1963         io_size = 16;
1964         break;
1965     case 3: /* qxl-3 */
1966         pci_device_rev = QXL_REVISION_STABLE_V10;
1967         io_size = 32; /* PCI region size must be pow2 */
1968         break;
1969     case 4: /* qxl-4 */
1970         pci_device_rev = QXL_REVISION_STABLE_V12;
1971         io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1972         break;
1973     default:
1974         error_report("Invalid revision %d for qxl device (max %d)",
1975                      qxl->revision, QXL_DEFAULT_REVISION);
1976         return -1;
1977     }
1978 
1979     pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1980     pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1981 
1982     qxl->rom_size = qxl_rom_size();
1983     memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1984     vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1985     init_qxl_rom(qxl);
1986     init_qxl_ram(qxl);
1987 
1988     qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
1989     memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1990     vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1991     memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
1992                              0, qxl->vram32_size);
1993 
1994     memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1995                           "qxl-ioports", io_size);
1996     if (qxl->id == 0) {
1997         vga_dirty_log_start(&qxl->vga);
1998     }
1999     memory_region_set_flush_coalesced(&qxl->io_bar);
2000 
2001 
2002     pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2003                      PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2004 
2005     pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2006                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2007 
2008     pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2009                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2010 
2011     pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2012                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2013 
2014     if (qxl->vram32_size < qxl->vram_size) {
2015         /*
2016          * Make the 64bit vram bar show up only in case it is
2017          * configured to be larger than the 32bit vram bar.
2018          */
2019         pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2020                          PCI_BASE_ADDRESS_SPACE_MEMORY |
2021                          PCI_BASE_ADDRESS_MEM_TYPE_64 |
2022                          PCI_BASE_ADDRESS_MEM_PREFETCH,
2023                          &qxl->vram_bar);
2024     }
2025 
2026     /* print pci bar details */
2027     dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2028            qxl->id == 0 ? "pri" : "sec",
2029            qxl->vga.vram_size / (1024*1024));
2030     dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2031            qxl->vram32_size / (1024*1024));
2032     dprint(qxl, 1, "vram/64: %d MB %s\n",
2033            qxl->vram_size / (1024*1024),
2034            qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2035 
2036     qxl->ssd.qxl.base.sif = &qxl_interface.base;
2037     qxl->ssd.qxl.id = qxl->id;
2038     if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) {
2039         error_report("qxl interface %d.%d not supported by spice-server",
2040                      SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2041         return -1;
2042     }
2043     qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2044 
2045     init_pipe_signaling(qxl);
2046     qxl_reset_state(qxl);
2047 
2048     qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2049 
2050     return 0;
2051 }
2052 
2053 static const GraphicHwOps qxl_ops = {
2054     .invalidate  = qxl_hw_invalidate,
2055     .gfx_update  = qxl_hw_update,
2056     .text_update = qxl_hw_text_update,
2057 };
2058 
2059 static int qxl_init_primary(PCIDevice *dev)
2060 {
2061     PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2062     VGACommonState *vga = &qxl->vga;
2063     PortioList *qxl_vga_port_list = g_new(PortioList, 1);
2064     int rc;
2065 
2066     qxl->id = 0;
2067     qxl_init_ramsize(qxl);
2068     vga->vram_size_mb = qxl->vga.vram_size >> 20;
2069     vga_common_init(vga);
2070     vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
2071     portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
2072     portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
2073 
2074     vga->con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl);
2075     qemu_spice_display_init_common(&qxl->ssd);
2076 
2077     rc = qxl_init_common(qxl);
2078     if (rc != 0) {
2079         return rc;
2080     }
2081 
2082     qxl->ssd.dcl.ops = &display_listener_ops;
2083     qxl->ssd.dcl.con = vga->con;
2084     register_displaychangelistener(&qxl->ssd.dcl);
2085     return rc;
2086 }
2087 
2088 static int qxl_init_secondary(PCIDevice *dev)
2089 {
2090     static int device_id = 1;
2091     PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2092 
2093     qxl->id = device_id++;
2094     qxl_init_ramsize(qxl);
2095     memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
2096     vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
2097     qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2098     qxl->vga.con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl);
2099 
2100     return qxl_init_common(qxl);
2101 }
2102 
2103 static void qxl_pre_save(void *opaque)
2104 {
2105     PCIQXLDevice* d = opaque;
2106     uint8_t *ram_start = d->vga.vram_ptr;
2107 
2108     trace_qxl_pre_save(d->id);
2109     if (d->last_release == NULL) {
2110         d->last_release_offset = 0;
2111     } else {
2112         d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2113     }
2114     assert(d->last_release_offset < d->vga.vram_size);
2115 }
2116 
2117 static int qxl_pre_load(void *opaque)
2118 {
2119     PCIQXLDevice* d = opaque;
2120 
2121     trace_qxl_pre_load(d->id);
2122     qxl_hard_reset(d, 1);
2123     qxl_exit_vga_mode(d);
2124     return 0;
2125 }
2126 
2127 static void qxl_create_memslots(PCIQXLDevice *d)
2128 {
2129     int i;
2130 
2131     for (i = 0; i < NUM_MEMSLOTS; i++) {
2132         if (!d->guest_slots[i].active) {
2133             continue;
2134         }
2135         qxl_add_memslot(d, i, 0, QXL_SYNC);
2136     }
2137 }
2138 
2139 static int qxl_post_load(void *opaque, int version)
2140 {
2141     PCIQXLDevice* d = opaque;
2142     uint8_t *ram_start = d->vga.vram_ptr;
2143     QXLCommandExt *cmds;
2144     int in, out, newmode;
2145 
2146     assert(d->last_release_offset < d->vga.vram_size);
2147     if (d->last_release_offset == 0) {
2148         d->last_release = NULL;
2149     } else {
2150         d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2151     }
2152 
2153     d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2154 
2155     trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2156     newmode = d->mode;
2157     d->mode = QXL_MODE_UNDEFINED;
2158 
2159     switch (newmode) {
2160     case QXL_MODE_UNDEFINED:
2161         qxl_create_memslots(d);
2162         break;
2163     case QXL_MODE_VGA:
2164         qxl_create_memslots(d);
2165         qxl_enter_vga_mode(d);
2166         break;
2167     case QXL_MODE_NATIVE:
2168         qxl_create_memslots(d);
2169         qxl_create_guest_primary(d, 1, QXL_SYNC);
2170 
2171         /* replay surface-create and cursor-set commands */
2172         cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2173         for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2174             if (d->guest_surfaces.cmds[in] == 0) {
2175                 continue;
2176             }
2177             cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2178             cmds[out].cmd.type = QXL_CMD_SURFACE;
2179             cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2180             out++;
2181         }
2182         if (d->guest_cursor) {
2183             cmds[out].cmd.data = d->guest_cursor;
2184             cmds[out].cmd.type = QXL_CMD_CURSOR;
2185             cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2186             out++;
2187         }
2188         qxl_spice_loadvm_commands(d, cmds, out);
2189         g_free(cmds);
2190         if (d->guest_monitors_config) {
2191             qxl_spice_monitors_config_async(d, 1);
2192         }
2193         break;
2194     case QXL_MODE_COMPAT:
2195         /* note: no need to call qxl_create_memslots, qxl_set_mode
2196          * creates the mem slot. */
2197         qxl_set_mode(d, d->shadow_rom.mode, 1);
2198         break;
2199     }
2200     return 0;
2201 }
2202 
2203 #define QXL_SAVE_VERSION 21
2204 
2205 static bool qxl_monitors_config_needed(void *opaque)
2206 {
2207     PCIQXLDevice *qxl = opaque;
2208 
2209     return qxl->guest_monitors_config != 0;
2210 }
2211 
2212 
2213 static VMStateDescription qxl_memslot = {
2214     .name               = "qxl-memslot",
2215     .version_id         = QXL_SAVE_VERSION,
2216     .minimum_version_id = QXL_SAVE_VERSION,
2217     .fields = (VMStateField[]) {
2218         VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2219         VMSTATE_UINT64(slot.mem_end,   struct guest_slots),
2220         VMSTATE_UINT32(active,         struct guest_slots),
2221         VMSTATE_END_OF_LIST()
2222     }
2223 };
2224 
2225 static VMStateDescription qxl_surface = {
2226     .name               = "qxl-surface",
2227     .version_id         = QXL_SAVE_VERSION,
2228     .minimum_version_id = QXL_SAVE_VERSION,
2229     .fields = (VMStateField[]) {
2230         VMSTATE_UINT32(width,      QXLSurfaceCreate),
2231         VMSTATE_UINT32(height,     QXLSurfaceCreate),
2232         VMSTATE_INT32(stride,      QXLSurfaceCreate),
2233         VMSTATE_UINT32(format,     QXLSurfaceCreate),
2234         VMSTATE_UINT32(position,   QXLSurfaceCreate),
2235         VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2236         VMSTATE_UINT32(flags,      QXLSurfaceCreate),
2237         VMSTATE_UINT32(type,       QXLSurfaceCreate),
2238         VMSTATE_UINT64(mem,        QXLSurfaceCreate),
2239         VMSTATE_END_OF_LIST()
2240     }
2241 };
2242 
2243 static VMStateDescription qxl_vmstate_monitors_config = {
2244     .name               = "qxl/monitors-config",
2245     .version_id         = 1,
2246     .minimum_version_id = 1,
2247     .fields = (VMStateField[]) {
2248         VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2249         VMSTATE_END_OF_LIST()
2250     },
2251 };
2252 
2253 static VMStateDescription qxl_vmstate = {
2254     .name               = "qxl",
2255     .version_id         = QXL_SAVE_VERSION,
2256     .minimum_version_id = QXL_SAVE_VERSION,
2257     .pre_save           = qxl_pre_save,
2258     .pre_load           = qxl_pre_load,
2259     .post_load          = qxl_post_load,
2260     .fields = (VMStateField[]) {
2261         VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2262         VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2263         VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2264         VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2265         VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2266         VMSTATE_UINT32(mode, PCIQXLDevice),
2267         VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2268         VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2269         VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2270                              qxl_memslot, struct guest_slots),
2271         VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2272                        qxl_surface, QXLSurfaceCreate),
2273         VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2274         VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2275                              ssd.num_surfaces, 0,
2276                              vmstate_info_uint64, uint64_t),
2277         VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2278         VMSTATE_END_OF_LIST()
2279     },
2280     .subsections = (VMStateSubsection[]) {
2281         {
2282             .vmsd = &qxl_vmstate_monitors_config,
2283             .needed = qxl_monitors_config_needed,
2284         }, {
2285             /* empty */
2286         }
2287     }
2288 };
2289 
2290 static Property qxl_properties[] = {
2291         DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2292                            64 * 1024 * 1024),
2293         DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
2294                            64 * 1024 * 1024),
2295         DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2296                            QXL_DEFAULT_REVISION),
2297         DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2298         DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2299         DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2300         DEFINE_PROP_UINT32("ram_size_mb",  PCIQXLDevice, ram_size_mb, -1),
2301         DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2302         DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2303         DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2304         DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2305         DEFINE_PROP_END_OF_LIST(),
2306 };
2307 
2308 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2309 {
2310     DeviceClass *dc = DEVICE_CLASS(klass);
2311     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2312 
2313     k->no_hotplug = 1;
2314     k->init = qxl_init_primary;
2315     k->romfile = "vgabios-qxl.bin";
2316     k->vendor_id = REDHAT_PCI_VENDOR_ID;
2317     k->device_id = QXL_DEVICE_ID_STABLE;
2318     k->class_id = PCI_CLASS_DISPLAY_VGA;
2319     dc->desc = "Spice QXL GPU (primary, vga compatible)";
2320     dc->reset = qxl_reset_handler;
2321     dc->vmsd = &qxl_vmstate;
2322     dc->props = qxl_properties;
2323 }
2324 
2325 static const TypeInfo qxl_primary_info = {
2326     .name          = "qxl-vga",
2327     .parent        = TYPE_PCI_DEVICE,
2328     .instance_size = sizeof(PCIQXLDevice),
2329     .class_init    = qxl_primary_class_init,
2330 };
2331 
2332 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2333 {
2334     DeviceClass *dc = DEVICE_CLASS(klass);
2335     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2336 
2337     k->init = qxl_init_secondary;
2338     k->vendor_id = REDHAT_PCI_VENDOR_ID;
2339     k->device_id = QXL_DEVICE_ID_STABLE;
2340     k->class_id = PCI_CLASS_DISPLAY_OTHER;
2341     dc->desc = "Spice QXL GPU (secondary)";
2342     dc->reset = qxl_reset_handler;
2343     dc->vmsd = &qxl_vmstate;
2344     dc->props = qxl_properties;
2345 }
2346 
2347 static const TypeInfo qxl_secondary_info = {
2348     .name          = "qxl",
2349     .parent        = TYPE_PCI_DEVICE,
2350     .instance_size = sizeof(PCIQXLDevice),
2351     .class_init    = qxl_secondary_class_init,
2352 };
2353 
2354 static void qxl_register_types(void)
2355 {
2356     type_register_static(&qxl_primary_info);
2357     type_register_static(&qxl_secondary_info);
2358 }
2359 
2360 type_init(qxl_register_types)
2361