1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <zlib.h> 22 23 #include "qemu-common.h" 24 #include "qemu/timer.h" 25 #include "qemu/queue.h" 26 #include "monitor/monitor.h" 27 #include "sysemu/sysemu.h" 28 #include "trace.h" 29 30 #include "qxl.h" 31 32 /* 33 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as 34 * such can be changed by the guest, so to avoid a guest trigerrable 35 * abort we just qxl_set_guest_bug and set the return to NULL. Still 36 * it may happen as a result of emulator bug as well. 37 */ 38 #undef SPICE_RING_PROD_ITEM 39 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ 40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ 41 if (prod >= ARRAY_SIZE((r)->items)) { \ 42 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ 43 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ 44 ret = NULL; \ 45 } else { \ 46 ret = &(r)->items[prod].el; \ 47 } \ 48 } 49 50 #undef SPICE_RING_CONS_ITEM 51 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 52 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 53 if (cons >= ARRAY_SIZE((r)->items)) { \ 54 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 55 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 56 ret = NULL; \ 57 } else { \ 58 ret = &(r)->items[cons].el; \ 59 } \ 60 } 61 62 #undef ALIGN 63 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 64 65 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 66 67 #define QXL_MODE(_x, _y, _b, _o) \ 68 { .x_res = _x, \ 69 .y_res = _y, \ 70 .bits = _b, \ 71 .stride = (_x) * (_b) / 8, \ 72 .x_mili = PIXEL_SIZE * (_x), \ 73 .y_mili = PIXEL_SIZE * (_y), \ 74 .orientation = _o, \ 75 } 76 77 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 78 QXL_MODE(x_res, y_res, 16, orientation), \ 79 QXL_MODE(x_res, y_res, 32, orientation) 80 81 #define QXL_MODE_EX(x_res, y_res) \ 82 QXL_MODE_16_32(x_res, y_res, 0), \ 83 QXL_MODE_16_32(x_res, y_res, 1) 84 85 static QXLMode qxl_modes[] = { 86 QXL_MODE_EX(640, 480), 87 QXL_MODE_EX(800, 480), 88 QXL_MODE_EX(800, 600), 89 QXL_MODE_EX(832, 624), 90 QXL_MODE_EX(960, 640), 91 QXL_MODE_EX(1024, 600), 92 QXL_MODE_EX(1024, 768), 93 QXL_MODE_EX(1152, 864), 94 QXL_MODE_EX(1152, 870), 95 QXL_MODE_EX(1280, 720), 96 QXL_MODE_EX(1280, 760), 97 QXL_MODE_EX(1280, 768), 98 QXL_MODE_EX(1280, 800), 99 QXL_MODE_EX(1280, 960), 100 QXL_MODE_EX(1280, 1024), 101 QXL_MODE_EX(1360, 768), 102 QXL_MODE_EX(1366, 768), 103 QXL_MODE_EX(1400, 1050), 104 QXL_MODE_EX(1440, 900), 105 QXL_MODE_EX(1600, 900), 106 QXL_MODE_EX(1600, 1200), 107 QXL_MODE_EX(1680, 1050), 108 QXL_MODE_EX(1920, 1080), 109 /* these modes need more than 8 MB video memory */ 110 QXL_MODE_EX(1920, 1200), 111 QXL_MODE_EX(1920, 1440), 112 QXL_MODE_EX(2000, 2000), 113 QXL_MODE_EX(2048, 1536), 114 QXL_MODE_EX(2048, 2048), 115 QXL_MODE_EX(2560, 1440), 116 QXL_MODE_EX(2560, 1600), 117 /* these modes need more than 16 MB video memory */ 118 QXL_MODE_EX(2560, 2048), 119 QXL_MODE_EX(2800, 2100), 120 QXL_MODE_EX(3200, 2400), 121 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 122 QXL_MODE_EX(4096, 2160), /* 4k */ 123 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 124 QXL_MODE_EX(8192, 4320), /* 8k */ 125 }; 126 127 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 128 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 129 static void qxl_reset_memslots(PCIQXLDevice *d); 130 static void qxl_reset_surfaces(PCIQXLDevice *d); 131 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 132 133 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 134 { 135 trace_qxl_set_guest_bug(qxl->id); 136 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 137 qxl->guest_bug = 1; 138 if (qxl->guestdebug) { 139 va_list ap; 140 va_start(ap, msg); 141 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 142 vfprintf(stderr, msg, ap); 143 fprintf(stderr, "\n"); 144 va_end(ap); 145 } 146 } 147 148 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 149 { 150 qxl->guest_bug = 0; 151 } 152 153 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 154 struct QXLRect *area, struct QXLRect *dirty_rects, 155 uint32_t num_dirty_rects, 156 uint32_t clear_dirty_region, 157 qxl_async_io async, struct QXLCookie *cookie) 158 { 159 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 160 area->top, area->bottom); 161 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 162 clear_dirty_region); 163 if (async == QXL_SYNC) { 164 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, 165 dirty_rects, num_dirty_rects, clear_dirty_region); 166 } else { 167 assert(cookie != NULL); 168 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 169 clear_dirty_region, (uintptr_t)cookie); 170 } 171 } 172 173 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 174 uint32_t id) 175 { 176 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 177 qemu_mutex_lock(&qxl->track_lock); 178 qxl->guest_surfaces.cmds[id] = 0; 179 qxl->guest_surfaces.count--; 180 qemu_mutex_unlock(&qxl->track_lock); 181 } 182 183 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 184 qxl_async_io async) 185 { 186 QXLCookie *cookie; 187 188 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 189 if (async) { 190 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 191 QXL_IO_DESTROY_SURFACE_ASYNC); 192 cookie->u.surface_id = id; 193 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 194 } else { 195 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); 196 qxl_spice_destroy_surface_wait_complete(qxl, id); 197 } 198 } 199 200 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 201 { 202 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 203 qxl->num_free_res); 204 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 205 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 206 QXL_IO_FLUSH_SURFACES_ASYNC)); 207 } 208 209 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 210 uint32_t count) 211 { 212 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 213 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); 214 } 215 216 void qxl_spice_oom(PCIQXLDevice *qxl) 217 { 218 trace_qxl_spice_oom(qxl->id); 219 qxl->ssd.worker->oom(qxl->ssd.worker); 220 } 221 222 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 223 { 224 trace_qxl_spice_reset_memslots(qxl->id); 225 qxl->ssd.worker->reset_memslots(qxl->ssd.worker); 226 } 227 228 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 229 { 230 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 231 qemu_mutex_lock(&qxl->track_lock); 232 memset(qxl->guest_surfaces.cmds, 0, 233 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 234 qxl->guest_surfaces.count = 0; 235 qemu_mutex_unlock(&qxl->track_lock); 236 } 237 238 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 239 { 240 trace_qxl_spice_destroy_surfaces(qxl->id, async); 241 if (async) { 242 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 243 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 244 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 245 } else { 246 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); 247 qxl_spice_destroy_surfaces_complete(qxl); 248 } 249 } 250 251 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 252 { 253 trace_qxl_spice_monitors_config(qxl->id); 254 if (replay) { 255 /* 256 * don't use QXL_COOKIE_TYPE_IO: 257 * - we are not running yet (post_load), we will assert 258 * in send_events 259 * - this is not a guest io, but a reply, so async_io isn't set. 260 */ 261 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 262 qxl->guest_monitors_config, 263 MEMSLOT_GROUP_GUEST, 264 (uintptr_t)qxl_cookie_new( 265 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 266 0)); 267 } else { 268 qxl->guest_monitors_config = qxl->ram->monitors_config; 269 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 270 qxl->ram->monitors_config, 271 MEMSLOT_GROUP_GUEST, 272 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 273 QXL_IO_MONITORS_CONFIG_ASYNC)); 274 } 275 } 276 277 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 278 { 279 trace_qxl_spice_reset_image_cache(qxl->id); 280 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); 281 } 282 283 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 284 { 285 trace_qxl_spice_reset_cursor(qxl->id); 286 qxl->ssd.worker->reset_cursor(qxl->ssd.worker); 287 qemu_mutex_lock(&qxl->track_lock); 288 qxl->guest_cursor = 0; 289 qemu_mutex_unlock(&qxl->track_lock); 290 if (qxl->ssd.cursor) { 291 cursor_put(qxl->ssd.cursor); 292 } 293 qxl->ssd.cursor = cursor_builtin_hidden(); 294 } 295 296 297 static inline uint32_t msb_mask(uint32_t val) 298 { 299 uint32_t mask; 300 301 do { 302 mask = ~(val - 1) & val; 303 val &= ~mask; 304 } while (mask < val); 305 306 return mask; 307 } 308 309 static ram_addr_t qxl_rom_size(void) 310 { 311 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) + 312 sizeof(qxl_modes); 313 uint32_t rom_size = 8192; /* two pages */ 314 315 required_rom_size = MAX(required_rom_size, TARGET_PAGE_SIZE); 316 required_rom_size = msb_mask(required_rom_size * 2 - 1); 317 assert(required_rom_size <= rom_size); 318 return rom_size; 319 } 320 321 static void init_qxl_rom(PCIQXLDevice *d) 322 { 323 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 324 QXLModes *modes = (QXLModes *)(rom + 1); 325 uint32_t ram_header_size; 326 uint32_t surface0_area_size; 327 uint32_t num_pages; 328 uint32_t fb; 329 int i, n; 330 331 memset(rom, 0, d->rom_size); 332 333 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 334 rom->id = cpu_to_le32(d->id); 335 rom->log_level = cpu_to_le32(d->guestdebug); 336 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 337 338 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 339 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 340 rom->slots_start = 1; 341 rom->slots_end = NUM_MEMSLOTS - 1; 342 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 343 344 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 345 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 346 if (fb > d->vgamem_size) { 347 continue; 348 } 349 modes->modes[n].id = cpu_to_le32(i); 350 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 351 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 352 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 353 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 354 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 355 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 356 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 357 n++; 358 } 359 modes->n_modes = cpu_to_le32(n); 360 361 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 362 surface0_area_size = ALIGN(d->vgamem_size, 4096); 363 num_pages = d->vga.vram_size; 364 num_pages -= ram_header_size; 365 num_pages -= surface0_area_size; 366 num_pages = num_pages / TARGET_PAGE_SIZE; 367 368 rom->draw_area_offset = cpu_to_le32(0); 369 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 370 rom->pages_offset = cpu_to_le32(surface0_area_size); 371 rom->num_pages = cpu_to_le32(num_pages); 372 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 373 374 d->shadow_rom = *rom; 375 d->rom = rom; 376 d->modes = modes; 377 } 378 379 static void init_qxl_ram(PCIQXLDevice *d) 380 { 381 uint8_t *buf; 382 uint64_t *item; 383 384 buf = d->vga.vram_ptr; 385 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 386 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 387 d->ram->int_pending = cpu_to_le32(0); 388 d->ram->int_mask = cpu_to_le32(0); 389 d->ram->update_surface = 0; 390 d->ram->monitors_config = 0; 391 SPICE_RING_INIT(&d->ram->cmd_ring); 392 SPICE_RING_INIT(&d->ram->cursor_ring); 393 SPICE_RING_INIT(&d->ram->release_ring); 394 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); 395 assert(item); 396 *item = 0; 397 qxl_ring_set_dirty(d); 398 } 399 400 /* can be called from spice server thread context */ 401 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 402 { 403 memory_region_set_dirty(mr, addr, end - addr); 404 } 405 406 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 407 { 408 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 409 } 410 411 /* called from spice server thread context only */ 412 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 413 { 414 void *base = qxl->vga.vram_ptr; 415 intptr_t offset; 416 417 offset = ptr - base; 418 offset &= ~(TARGET_PAGE_SIZE-1); 419 assert(offset < qxl->vga.vram_size); 420 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); 421 } 422 423 /* can be called from spice server thread context */ 424 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 425 { 426 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 427 ram_addr_t end = qxl->vga.vram_size; 428 qxl_set_dirty(&qxl->vga.vram, addr, end); 429 } 430 431 /* 432 * keep track of some command state, for savevm/loadvm. 433 * called from spice server thread context only 434 */ 435 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 436 { 437 switch (le32_to_cpu(ext->cmd.type)) { 438 case QXL_CMD_SURFACE: 439 { 440 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 441 442 if (!cmd) { 443 return 1; 444 } 445 uint32_t id = le32_to_cpu(cmd->surface_id); 446 447 if (id >= qxl->ssd.num_surfaces) { 448 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 449 qxl->ssd.num_surfaces); 450 return 1; 451 } 452 if (cmd->type == QXL_SURFACE_CMD_CREATE && 453 (cmd->u.surface_create.stride & 0x03) != 0) { 454 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 455 cmd->u.surface_create.stride); 456 return 1; 457 } 458 qemu_mutex_lock(&qxl->track_lock); 459 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 460 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 461 qxl->guest_surfaces.count++; 462 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) 463 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 464 } 465 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 466 qxl->guest_surfaces.cmds[id] = 0; 467 qxl->guest_surfaces.count--; 468 } 469 qemu_mutex_unlock(&qxl->track_lock); 470 break; 471 } 472 case QXL_CMD_CURSOR: 473 { 474 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 475 476 if (!cmd) { 477 return 1; 478 } 479 if (cmd->type == QXL_CURSOR_SET) { 480 qemu_mutex_lock(&qxl->track_lock); 481 qxl->guest_cursor = ext->cmd.data; 482 qemu_mutex_unlock(&qxl->track_lock); 483 } 484 break; 485 } 486 } 487 return 0; 488 } 489 490 /* spice display interface callbacks */ 491 492 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 493 { 494 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 495 496 trace_qxl_interface_attach_worker(qxl->id); 497 qxl->ssd.worker = qxl_worker; 498 } 499 500 static void interface_set_compression_level(QXLInstance *sin, int level) 501 { 502 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 503 504 trace_qxl_interface_set_compression_level(qxl->id, level); 505 qxl->shadow_rom.compression_level = cpu_to_le32(level); 506 qxl->rom->compression_level = cpu_to_le32(level); 507 qxl_rom_set_dirty(qxl); 508 } 509 510 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 511 { 512 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 513 514 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 515 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 516 qxl->rom->mm_clock = cpu_to_le32(mm_time); 517 qxl_rom_set_dirty(qxl); 518 } 519 520 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 521 { 522 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 523 524 trace_qxl_interface_get_init_info(qxl->id); 525 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 526 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 527 info->num_memslots = NUM_MEMSLOTS; 528 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 529 info->internal_groupslot_id = 0; 530 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; 531 info->n_surfaces = qxl->ssd.num_surfaces; 532 } 533 534 static const char *qxl_mode_to_string(int mode) 535 { 536 switch (mode) { 537 case QXL_MODE_COMPAT: 538 return "compat"; 539 case QXL_MODE_NATIVE: 540 return "native"; 541 case QXL_MODE_UNDEFINED: 542 return "undefined"; 543 case QXL_MODE_VGA: 544 return "vga"; 545 } 546 return "INVALID"; 547 } 548 549 static const char *io_port_to_string(uint32_t io_port) 550 { 551 if (io_port >= QXL_IO_RANGE_SIZE) { 552 return "out of range"; 553 } 554 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 555 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 556 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 557 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 558 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 559 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 560 [QXL_IO_RESET] = "QXL_IO_RESET", 561 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 562 [QXL_IO_LOG] = "QXL_IO_LOG", 563 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 564 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 565 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 566 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 567 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 568 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 569 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 570 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 571 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 572 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 573 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 574 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 575 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 576 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 577 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 578 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 579 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 580 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 581 }; 582 return io_port_to_string[io_port]; 583 } 584 585 /* called from spice server thread context only */ 586 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 587 { 588 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 589 SimpleSpiceUpdate *update; 590 QXLCommandRing *ring; 591 QXLCommand *cmd; 592 int notify, ret; 593 594 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 595 596 switch (qxl->mode) { 597 case QXL_MODE_VGA: 598 ret = false; 599 qemu_mutex_lock(&qxl->ssd.lock); 600 update = QTAILQ_FIRST(&qxl->ssd.updates); 601 if (update != NULL) { 602 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 603 *ext = update->ext; 604 ret = true; 605 } 606 qemu_mutex_unlock(&qxl->ssd.lock); 607 if (ret) { 608 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 609 qxl_log_command(qxl, "vga", ext); 610 } 611 return ret; 612 case QXL_MODE_COMPAT: 613 case QXL_MODE_NATIVE: 614 case QXL_MODE_UNDEFINED: 615 ring = &qxl->ram->cmd_ring; 616 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 617 return false; 618 } 619 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 620 if (!cmd) { 621 return false; 622 } 623 ext->cmd = *cmd; 624 ext->group_id = MEMSLOT_GROUP_GUEST; 625 ext->flags = qxl->cmdflags; 626 SPICE_RING_POP(ring, notify); 627 qxl_ring_set_dirty(qxl); 628 if (notify) { 629 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 630 } 631 qxl->guest_primary.commands++; 632 qxl_track_command(qxl, ext); 633 qxl_log_command(qxl, "cmd", ext); 634 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 635 return true; 636 default: 637 return false; 638 } 639 } 640 641 /* called from spice server thread context only */ 642 static int interface_req_cmd_notification(QXLInstance *sin) 643 { 644 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 645 int wait = 1; 646 647 trace_qxl_ring_command_req_notification(qxl->id); 648 switch (qxl->mode) { 649 case QXL_MODE_COMPAT: 650 case QXL_MODE_NATIVE: 651 case QXL_MODE_UNDEFINED: 652 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 653 qxl_ring_set_dirty(qxl); 654 break; 655 default: 656 /* nothing */ 657 break; 658 } 659 return wait; 660 } 661 662 /* called from spice server thread context only */ 663 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 664 { 665 QXLReleaseRing *ring = &d->ram->release_ring; 666 uint64_t *item; 667 int notify; 668 669 #define QXL_FREE_BUNCH_SIZE 32 670 671 if (ring->prod - ring->cons + 1 == ring->num_items) { 672 /* ring full -- can't push */ 673 return; 674 } 675 if (!flush && d->oom_running) { 676 /* collect everything from oom handler before pushing */ 677 return; 678 } 679 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 680 /* collect a bit more before pushing */ 681 return; 682 } 683 684 SPICE_RING_PUSH(ring, notify); 685 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 686 d->guest_surfaces.count, d->num_free_res, 687 d->last_release, notify ? "yes" : "no"); 688 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 689 ring->num_items, ring->prod, ring->cons); 690 if (notify) { 691 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 692 } 693 SPICE_RING_PROD_ITEM(d, ring, item); 694 if (!item) { 695 return; 696 } 697 *item = 0; 698 d->num_free_res = 0; 699 d->last_release = NULL; 700 qxl_ring_set_dirty(d); 701 } 702 703 /* called from spice server thread context only */ 704 static void interface_release_resource(QXLInstance *sin, 705 struct QXLReleaseInfoExt ext) 706 { 707 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 708 QXLReleaseRing *ring; 709 uint64_t *item, id; 710 711 if (ext.group_id == MEMSLOT_GROUP_HOST) { 712 /* host group -> vga mode update request */ 713 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id); 714 return; 715 } 716 717 /* 718 * ext->info points into guest-visible memory 719 * pci bar 0, $command.release_info 720 */ 721 ring = &qxl->ram->release_ring; 722 SPICE_RING_PROD_ITEM(qxl, ring, item); 723 if (!item) { 724 return; 725 } 726 if (*item == 0) { 727 /* stick head into the ring */ 728 id = ext.info->id; 729 ext.info->next = 0; 730 qxl_ram_set_dirty(qxl, &ext.info->next); 731 *item = id; 732 qxl_ring_set_dirty(qxl); 733 } else { 734 /* append item to the list */ 735 qxl->last_release->next = ext.info->id; 736 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 737 ext.info->next = 0; 738 qxl_ram_set_dirty(qxl, &ext.info->next); 739 } 740 qxl->last_release = ext.info; 741 qxl->num_free_res++; 742 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 743 qxl_push_free_res(qxl, 0); 744 } 745 746 /* called from spice server thread context only */ 747 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 748 { 749 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 750 QXLCursorRing *ring; 751 QXLCommand *cmd; 752 int notify; 753 754 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 755 756 switch (qxl->mode) { 757 case QXL_MODE_COMPAT: 758 case QXL_MODE_NATIVE: 759 case QXL_MODE_UNDEFINED: 760 ring = &qxl->ram->cursor_ring; 761 if (SPICE_RING_IS_EMPTY(ring)) { 762 return false; 763 } 764 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 765 if (!cmd) { 766 return false; 767 } 768 ext->cmd = *cmd; 769 ext->group_id = MEMSLOT_GROUP_GUEST; 770 ext->flags = qxl->cmdflags; 771 SPICE_RING_POP(ring, notify); 772 qxl_ring_set_dirty(qxl); 773 if (notify) { 774 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 775 } 776 qxl->guest_primary.commands++; 777 qxl_track_command(qxl, ext); 778 qxl_log_command(qxl, "csr", ext); 779 if (qxl->id == 0) { 780 qxl_render_cursor(qxl, ext); 781 } 782 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 783 return true; 784 default: 785 return false; 786 } 787 } 788 789 /* called from spice server thread context only */ 790 static int interface_req_cursor_notification(QXLInstance *sin) 791 { 792 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 793 int wait = 1; 794 795 trace_qxl_ring_cursor_req_notification(qxl->id); 796 switch (qxl->mode) { 797 case QXL_MODE_COMPAT: 798 case QXL_MODE_NATIVE: 799 case QXL_MODE_UNDEFINED: 800 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 801 qxl_ring_set_dirty(qxl); 802 break; 803 default: 804 /* nothing */ 805 break; 806 } 807 return wait; 808 } 809 810 /* called from spice server thread context */ 811 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 812 { 813 /* 814 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 815 * use by xf86-video-qxl and is defined out in the qxl windows driver. 816 * Probably was at some earlier version that is prior to git start (2009), 817 * and is still guest trigerrable. 818 */ 819 fprintf(stderr, "%s: deprecated\n", __func__); 820 } 821 822 /* called from spice server thread context only */ 823 static int interface_flush_resources(QXLInstance *sin) 824 { 825 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 826 int ret; 827 828 ret = qxl->num_free_res; 829 if (ret) { 830 qxl_push_free_res(qxl, 1); 831 } 832 return ret; 833 } 834 835 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 836 837 /* called from spice server thread context only */ 838 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 839 { 840 uint32_t current_async; 841 842 qemu_mutex_lock(&qxl->async_lock); 843 current_async = qxl->current_async; 844 qxl->current_async = QXL_UNDEFINED_IO; 845 qemu_mutex_unlock(&qxl->async_lock); 846 847 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 848 if (!cookie) { 849 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 850 return; 851 } 852 if (cookie && current_async != cookie->io) { 853 fprintf(stderr, 854 "qxl: %s: error: current_async = %d != %" 855 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 856 } 857 switch (current_async) { 858 case QXL_IO_MEMSLOT_ADD_ASYNC: 859 case QXL_IO_DESTROY_PRIMARY_ASYNC: 860 case QXL_IO_UPDATE_AREA_ASYNC: 861 case QXL_IO_FLUSH_SURFACES_ASYNC: 862 case QXL_IO_MONITORS_CONFIG_ASYNC: 863 break; 864 case QXL_IO_CREATE_PRIMARY_ASYNC: 865 qxl_create_guest_primary_complete(qxl); 866 break; 867 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 868 qxl_spice_destroy_surfaces_complete(qxl); 869 break; 870 case QXL_IO_DESTROY_SURFACE_ASYNC: 871 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 872 break; 873 default: 874 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 875 current_async); 876 } 877 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 878 } 879 880 /* called from spice server thread context only */ 881 static void interface_update_area_complete(QXLInstance *sin, 882 uint32_t surface_id, 883 QXLRect *dirty, uint32_t num_updated_rects) 884 { 885 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 886 int i; 887 int qxl_i; 888 889 qemu_mutex_lock(&qxl->ssd.lock); 890 if (surface_id != 0 || !qxl->render_update_cookie_num) { 891 qemu_mutex_unlock(&qxl->ssd.lock); 892 return; 893 } 894 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 895 dirty->right, dirty->top, dirty->bottom); 896 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 897 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 898 /* 899 * overflow - treat this as a full update. Not expected to be common. 900 */ 901 trace_qxl_interface_update_area_complete_overflow(qxl->id, 902 QXL_NUM_DIRTY_RECTS); 903 qxl->guest_primary.resized = 1; 904 } 905 if (qxl->guest_primary.resized) { 906 /* 907 * Don't bother copying or scheduling the bh since we will flip 908 * the whole area anyway on completion of the update_area async call 909 */ 910 qemu_mutex_unlock(&qxl->ssd.lock); 911 return; 912 } 913 qxl_i = qxl->num_dirty_rects; 914 for (i = 0; i < num_updated_rects; i++) { 915 qxl->dirty[qxl_i++] = dirty[i]; 916 } 917 qxl->num_dirty_rects += num_updated_rects; 918 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 919 qxl->num_dirty_rects); 920 qemu_bh_schedule(qxl->update_area_bh); 921 qemu_mutex_unlock(&qxl->ssd.lock); 922 } 923 924 /* called from spice server thread context only */ 925 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 926 { 927 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 928 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 929 930 switch (cookie->type) { 931 case QXL_COOKIE_TYPE_IO: 932 interface_async_complete_io(qxl, cookie); 933 g_free(cookie); 934 break; 935 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 936 qxl_render_update_area_done(qxl, cookie); 937 break; 938 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 939 break; 940 default: 941 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 942 __func__, cookie->type); 943 g_free(cookie); 944 } 945 } 946 947 /* called from spice server thread context only */ 948 static void interface_set_client_capabilities(QXLInstance *sin, 949 uint8_t client_present, 950 uint8_t caps[58]) 951 { 952 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 953 954 if (qxl->revision < 4) { 955 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 956 qxl->revision); 957 return; 958 } 959 960 if (runstate_check(RUN_STATE_INMIGRATE) || 961 runstate_check(RUN_STATE_POSTMIGRATE)) { 962 return; 963 } 964 965 qxl->shadow_rom.client_present = client_present; 966 memcpy(qxl->shadow_rom.client_capabilities, caps, 967 sizeof(qxl->shadow_rom.client_capabilities)); 968 qxl->rom->client_present = client_present; 969 memcpy(qxl->rom->client_capabilities, caps, 970 sizeof(qxl->rom->client_capabilities)); 971 qxl_rom_set_dirty(qxl); 972 973 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 974 } 975 976 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 977 { 978 /* 979 * zlib xors the seed with 0xffffffff, and xors the result 980 * again with 0xffffffff; Both are not done with linux's crc32, 981 * which we want to be compatible with, so undo that. 982 */ 983 return crc32(0xffffffff, p, len) ^ 0xffffffff; 984 } 985 986 /* called from main context only */ 987 static int interface_client_monitors_config(QXLInstance *sin, 988 VDAgentMonitorsConfig *monitors_config) 989 { 990 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 991 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 992 int i; 993 994 if (qxl->revision < 4) { 995 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 996 qxl->revision); 997 return 0; 998 } 999 /* 1000 * Older windows drivers set int_mask to 0 when their ISR is called, 1001 * then later set it to ~0. So it doesn't relate to the actual interrupts 1002 * handled. However, they are old, so clearly they don't support this 1003 * interrupt 1004 */ 1005 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1006 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1007 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1008 qxl->ram->int_mask, 1009 monitors_config); 1010 return 0; 1011 } 1012 if (!monitors_config) { 1013 return 1; 1014 } 1015 memset(&rom->client_monitors_config, 0, 1016 sizeof(rom->client_monitors_config)); 1017 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1018 /* monitors_config->flags ignored */ 1019 if (rom->client_monitors_config.count >= 1020 ARRAY_SIZE(rom->client_monitors_config.heads)) { 1021 trace_qxl_client_monitors_config_capped(qxl->id, 1022 monitors_config->num_of_monitors, 1023 ARRAY_SIZE(rom->client_monitors_config.heads)); 1024 rom->client_monitors_config.count = 1025 ARRAY_SIZE(rom->client_monitors_config.heads); 1026 } 1027 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1028 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1029 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1030 /* monitor->depth ignored */ 1031 rect->left = monitor->x; 1032 rect->top = monitor->y; 1033 rect->right = monitor->x + monitor->width; 1034 rect->bottom = monitor->y + monitor->height; 1035 } 1036 rom->client_monitors_config_crc = qxl_crc32( 1037 (const uint8_t *)&rom->client_monitors_config, 1038 sizeof(rom->client_monitors_config)); 1039 trace_qxl_client_monitors_config_crc(qxl->id, 1040 sizeof(rom->client_monitors_config), 1041 rom->client_monitors_config_crc); 1042 1043 trace_qxl_interrupt_client_monitors_config(qxl->id, 1044 rom->client_monitors_config.count, 1045 rom->client_monitors_config.heads); 1046 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1047 return 1; 1048 } 1049 1050 static const QXLInterface qxl_interface = { 1051 .base.type = SPICE_INTERFACE_QXL, 1052 .base.description = "qxl gpu", 1053 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1054 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1055 1056 .attache_worker = interface_attach_worker, 1057 .set_compression_level = interface_set_compression_level, 1058 .set_mm_time = interface_set_mm_time, 1059 .get_init_info = interface_get_init_info, 1060 1061 /* the callbacks below are called from spice server thread context */ 1062 .get_command = interface_get_command, 1063 .req_cmd_notification = interface_req_cmd_notification, 1064 .release_resource = interface_release_resource, 1065 .get_cursor_command = interface_get_cursor_command, 1066 .req_cursor_notification = interface_req_cursor_notification, 1067 .notify_update = interface_notify_update, 1068 .flush_resources = interface_flush_resources, 1069 .async_complete = interface_async_complete, 1070 .update_area_complete = interface_update_area_complete, 1071 .set_client_capabilities = interface_set_client_capabilities, 1072 .client_monitors_config = interface_client_monitors_config, 1073 }; 1074 1075 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1076 { 1077 if (d->mode == QXL_MODE_VGA) { 1078 return; 1079 } 1080 trace_qxl_enter_vga_mode(d->id); 1081 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */ 1082 spice_qxl_driver_unload(&d->ssd.qxl); 1083 #endif 1084 qemu_spice_create_host_primary(&d->ssd); 1085 d->mode = QXL_MODE_VGA; 1086 vga_dirty_log_start(&d->vga); 1087 graphic_hw_update(d->vga.con); 1088 } 1089 1090 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1091 { 1092 if (d->mode != QXL_MODE_VGA) { 1093 return; 1094 } 1095 trace_qxl_exit_vga_mode(d->id); 1096 vga_dirty_log_stop(&d->vga); 1097 qxl_destroy_primary(d, QXL_SYNC); 1098 } 1099 1100 static void qxl_update_irq(PCIQXLDevice *d) 1101 { 1102 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1103 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1104 int level = !!(pending & mask); 1105 qemu_set_irq(d->pci.irq[0], level); 1106 qxl_ring_set_dirty(d); 1107 } 1108 1109 static void qxl_check_state(PCIQXLDevice *d) 1110 { 1111 QXLRam *ram = d->ram; 1112 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1113 1114 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1115 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1116 } 1117 1118 static void qxl_reset_state(PCIQXLDevice *d) 1119 { 1120 QXLRom *rom = d->rom; 1121 1122 qxl_check_state(d); 1123 d->shadow_rom.update_id = cpu_to_le32(0); 1124 *rom = d->shadow_rom; 1125 qxl_rom_set_dirty(d); 1126 init_qxl_ram(d); 1127 d->num_free_res = 0; 1128 d->last_release = NULL; 1129 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1130 } 1131 1132 static void qxl_soft_reset(PCIQXLDevice *d) 1133 { 1134 trace_qxl_soft_reset(d->id); 1135 qxl_check_state(d); 1136 qxl_clear_guest_bug(d); 1137 d->current_async = QXL_UNDEFINED_IO; 1138 1139 if (d->id == 0) { 1140 qxl_enter_vga_mode(d); 1141 } else { 1142 d->mode = QXL_MODE_UNDEFINED; 1143 } 1144 } 1145 1146 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1147 { 1148 trace_qxl_hard_reset(d->id, loadvm); 1149 1150 qxl_spice_reset_cursor(d); 1151 qxl_spice_reset_image_cache(d); 1152 qxl_reset_surfaces(d); 1153 qxl_reset_memslots(d); 1154 1155 /* pre loadvm reset must not touch QXLRam. This lives in 1156 * device memory, is migrated together with RAM and thus 1157 * already loaded at this point */ 1158 if (!loadvm) { 1159 qxl_reset_state(d); 1160 } 1161 qemu_spice_create_host_memslot(&d->ssd); 1162 qxl_soft_reset(d); 1163 } 1164 1165 static void qxl_reset_handler(DeviceState *dev) 1166 { 1167 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); 1168 1169 qxl_hard_reset(d, 0); 1170 } 1171 1172 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1173 { 1174 VGACommonState *vga = opaque; 1175 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1176 1177 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1178 if (qxl->mode != QXL_MODE_VGA) { 1179 qxl_destroy_primary(qxl, QXL_SYNC); 1180 qxl_soft_reset(qxl); 1181 } 1182 vga_ioport_write(opaque, addr, val); 1183 } 1184 1185 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1186 { 0x04, 2, 1, .read = vga_ioport_read, 1187 .write = qxl_vga_ioport_write }, /* 3b4 */ 1188 { 0x0a, 1, 1, .read = vga_ioport_read, 1189 .write = qxl_vga_ioport_write }, /* 3ba */ 1190 { 0x10, 16, 1, .read = vga_ioport_read, 1191 .write = qxl_vga_ioport_write }, /* 3c0 */ 1192 { 0x24, 2, 1, .read = vga_ioport_read, 1193 .write = qxl_vga_ioport_write }, /* 3d4 */ 1194 { 0x2a, 1, 1, .read = vga_ioport_read, 1195 .write = qxl_vga_ioport_write }, /* 3da */ 1196 PORTIO_END_OF_LIST(), 1197 }; 1198 1199 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1200 qxl_async_io async) 1201 { 1202 static const int regions[] = { 1203 QXL_RAM_RANGE_INDEX, 1204 QXL_VRAM_RANGE_INDEX, 1205 QXL_VRAM64_RANGE_INDEX, 1206 }; 1207 uint64_t guest_start; 1208 uint64_t guest_end; 1209 int pci_region; 1210 pcibus_t pci_start; 1211 pcibus_t pci_end; 1212 intptr_t virt_start; 1213 QXLDevMemSlot memslot; 1214 int i; 1215 1216 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1217 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1218 1219 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1220 1221 if (slot_id >= NUM_MEMSLOTS) { 1222 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1223 slot_id, NUM_MEMSLOTS); 1224 return 1; 1225 } 1226 if (guest_start > guest_end) { 1227 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1228 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1229 return 1; 1230 } 1231 1232 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1233 pci_region = regions[i]; 1234 pci_start = d->pci.io_regions[pci_region].addr; 1235 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1236 /* mapped? */ 1237 if (pci_start == -1) { 1238 continue; 1239 } 1240 /* start address in range ? */ 1241 if (guest_start < pci_start || guest_start > pci_end) { 1242 continue; 1243 } 1244 /* end address in range ? */ 1245 if (guest_end > pci_end) { 1246 continue; 1247 } 1248 /* passed */ 1249 break; 1250 } 1251 if (i == ARRAY_SIZE(regions)) { 1252 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1253 return 1; 1254 } 1255 1256 switch (pci_region) { 1257 case QXL_RAM_RANGE_INDEX: 1258 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); 1259 break; 1260 case QXL_VRAM_RANGE_INDEX: 1261 case 4 /* vram 64bit */: 1262 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); 1263 break; 1264 default: 1265 /* should not happen */ 1266 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1267 return 1; 1268 } 1269 1270 memslot.slot_id = slot_id; 1271 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1272 memslot.virt_start = virt_start + (guest_start - pci_start); 1273 memslot.virt_end = virt_start + (guest_end - pci_start); 1274 memslot.addr_delta = memslot.virt_start - delta; 1275 memslot.generation = d->rom->slot_generation = 0; 1276 qxl_rom_set_dirty(d); 1277 1278 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1279 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; 1280 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1281 d->guest_slots[slot_id].delta = delta; 1282 d->guest_slots[slot_id].active = 1; 1283 return 0; 1284 } 1285 1286 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1287 { 1288 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1289 d->guest_slots[slot_id].active = 0; 1290 } 1291 1292 static void qxl_reset_memslots(PCIQXLDevice *d) 1293 { 1294 qxl_spice_reset_memslots(d); 1295 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1296 } 1297 1298 static void qxl_reset_surfaces(PCIQXLDevice *d) 1299 { 1300 trace_qxl_reset_surfaces(d->id); 1301 d->mode = QXL_MODE_UNDEFINED; 1302 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1303 } 1304 1305 /* can be also called from spice server thread context */ 1306 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1307 { 1308 uint64_t phys = le64_to_cpu(pqxl); 1309 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1310 uint64_t offset = phys & 0xffffffffffff; 1311 1312 switch (group_id) { 1313 case MEMSLOT_GROUP_HOST: 1314 return (void *)(intptr_t)offset; 1315 case MEMSLOT_GROUP_GUEST: 1316 if (slot >= NUM_MEMSLOTS) { 1317 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1318 NUM_MEMSLOTS); 1319 return NULL; 1320 } 1321 if (!qxl->guest_slots[slot].active) { 1322 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1323 return NULL; 1324 } 1325 if (offset < qxl->guest_slots[slot].delta) { 1326 qxl_set_guest_bug(qxl, 1327 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1328 slot, offset, qxl->guest_slots[slot].delta); 1329 return NULL; 1330 } 1331 offset -= qxl->guest_slots[slot].delta; 1332 if (offset > qxl->guest_slots[slot].size) { 1333 qxl_set_guest_bug(qxl, 1334 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1335 slot, offset, qxl->guest_slots[slot].size); 1336 return NULL; 1337 } 1338 return qxl->guest_slots[slot].ptr + offset; 1339 } 1340 return NULL; 1341 } 1342 1343 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1344 { 1345 /* for local rendering */ 1346 qxl_render_resize(qxl); 1347 } 1348 1349 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1350 qxl_async_io async) 1351 { 1352 QXLDevSurfaceCreate surface; 1353 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1354 int size; 1355 int requested_height = le32_to_cpu(sc->height); 1356 int requested_stride = le32_to_cpu(sc->stride); 1357 1358 size = abs(requested_stride) * requested_height; 1359 if (size > qxl->vgamem_size) { 1360 qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer" 1361 " size", __func__); 1362 return; 1363 } 1364 1365 if (qxl->mode == QXL_MODE_NATIVE) { 1366 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1367 __func__); 1368 } 1369 qxl_exit_vga_mode(qxl); 1370 1371 surface.format = le32_to_cpu(sc->format); 1372 surface.height = le32_to_cpu(sc->height); 1373 surface.mem = le64_to_cpu(sc->mem); 1374 surface.position = le32_to_cpu(sc->position); 1375 surface.stride = le32_to_cpu(sc->stride); 1376 surface.width = le32_to_cpu(sc->width); 1377 surface.type = le32_to_cpu(sc->type); 1378 surface.flags = le32_to_cpu(sc->flags); 1379 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1380 sc->format, sc->position); 1381 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1382 sc->flags); 1383 1384 if ((surface.stride & 0x3) != 0) { 1385 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1386 surface.stride); 1387 return; 1388 } 1389 1390 surface.mouse_mode = true; 1391 surface.group_id = MEMSLOT_GROUP_GUEST; 1392 if (loadvm) { 1393 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1394 } 1395 1396 qxl->mode = QXL_MODE_NATIVE; 1397 qxl->cmdflags = 0; 1398 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1399 1400 if (async == QXL_SYNC) { 1401 qxl_create_guest_primary_complete(qxl); 1402 } 1403 } 1404 1405 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1406 * done (in QXL_SYNC case), 0 otherwise. */ 1407 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1408 { 1409 if (d->mode == QXL_MODE_UNDEFINED) { 1410 return 0; 1411 } 1412 trace_qxl_destroy_primary(d->id); 1413 d->mode = QXL_MODE_UNDEFINED; 1414 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1415 qxl_spice_reset_cursor(d); 1416 return 1; 1417 } 1418 1419 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) 1420 { 1421 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1422 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1423 QXLMode *mode = d->modes->modes + modenr; 1424 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1425 QXLMemSlot slot = { 1426 .mem_start = start, 1427 .mem_end = end 1428 }; 1429 QXLSurfaceCreate surface = { 1430 .width = mode->x_res, 1431 .height = mode->y_res, 1432 .stride = -mode->x_res * 4, 1433 .format = SPICE_SURFACE_FMT_32_xRGB, 1434 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1435 .mouse_mode = true, 1436 .mem = devmem + d->shadow_rom.draw_area_offset, 1437 }; 1438 1439 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1440 devmem); 1441 if (!loadvm) { 1442 qxl_hard_reset(d, 0); 1443 } 1444 1445 d->guest_slots[0].slot = slot; 1446 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1447 1448 d->guest_primary.surface = surface; 1449 qxl_create_guest_primary(d, 0, QXL_SYNC); 1450 1451 d->mode = QXL_MODE_COMPAT; 1452 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1453 if (mode->bits == 16) { 1454 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1455 } 1456 d->shadow_rom.mode = cpu_to_le32(modenr); 1457 d->rom->mode = cpu_to_le32(modenr); 1458 qxl_rom_set_dirty(d); 1459 } 1460 1461 static void ioport_write(void *opaque, hwaddr addr, 1462 uint64_t val, unsigned size) 1463 { 1464 PCIQXLDevice *d = opaque; 1465 uint32_t io_port = addr; 1466 qxl_async_io async = QXL_SYNC; 1467 uint32_t orig_io_port = io_port; 1468 1469 if (d->guest_bug && io_port != QXL_IO_RESET) { 1470 return; 1471 } 1472 1473 if (d->revision <= QXL_REVISION_STABLE_V10 && 1474 io_port > QXL_IO_FLUSH_RELEASE) { 1475 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1476 io_port, d->revision); 1477 return; 1478 } 1479 1480 switch (io_port) { 1481 case QXL_IO_RESET: 1482 case QXL_IO_SET_MODE: 1483 case QXL_IO_MEMSLOT_ADD: 1484 case QXL_IO_MEMSLOT_DEL: 1485 case QXL_IO_CREATE_PRIMARY: 1486 case QXL_IO_UPDATE_IRQ: 1487 case QXL_IO_LOG: 1488 case QXL_IO_MEMSLOT_ADD_ASYNC: 1489 case QXL_IO_CREATE_PRIMARY_ASYNC: 1490 break; 1491 default: 1492 if (d->mode != QXL_MODE_VGA) { 1493 break; 1494 } 1495 trace_qxl_io_unexpected_vga_mode(d->id, 1496 addr, val, io_port_to_string(io_port)); 1497 /* be nice to buggy guest drivers */ 1498 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1499 io_port < QXL_IO_RANGE_SIZE) { 1500 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1501 } 1502 return; 1503 } 1504 1505 /* we change the io_port to avoid ifdeffery in the main switch */ 1506 orig_io_port = io_port; 1507 switch (io_port) { 1508 case QXL_IO_UPDATE_AREA_ASYNC: 1509 io_port = QXL_IO_UPDATE_AREA; 1510 goto async_common; 1511 case QXL_IO_MEMSLOT_ADD_ASYNC: 1512 io_port = QXL_IO_MEMSLOT_ADD; 1513 goto async_common; 1514 case QXL_IO_CREATE_PRIMARY_ASYNC: 1515 io_port = QXL_IO_CREATE_PRIMARY; 1516 goto async_common; 1517 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1518 io_port = QXL_IO_DESTROY_PRIMARY; 1519 goto async_common; 1520 case QXL_IO_DESTROY_SURFACE_ASYNC: 1521 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1522 goto async_common; 1523 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1524 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1525 goto async_common; 1526 case QXL_IO_FLUSH_SURFACES_ASYNC: 1527 case QXL_IO_MONITORS_CONFIG_ASYNC: 1528 async_common: 1529 async = QXL_ASYNC; 1530 qemu_mutex_lock(&d->async_lock); 1531 if (d->current_async != QXL_UNDEFINED_IO) { 1532 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1533 io_port, d->current_async); 1534 qemu_mutex_unlock(&d->async_lock); 1535 return; 1536 } 1537 d->current_async = orig_io_port; 1538 qemu_mutex_unlock(&d->async_lock); 1539 break; 1540 default: 1541 break; 1542 } 1543 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size, 1544 async); 1545 1546 switch (io_port) { 1547 case QXL_IO_UPDATE_AREA: 1548 { 1549 QXLCookie *cookie = NULL; 1550 QXLRect update = d->ram->update_area; 1551 1552 if (d->ram->update_surface > d->ssd.num_surfaces) { 1553 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1554 d->ram->update_surface); 1555 break; 1556 } 1557 if (update.left >= update.right || update.top >= update.bottom || 1558 update.left < 0 || update.top < 0) { 1559 qxl_set_guest_bug(d, 1560 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1561 update.left, update.top, update.right, update.bottom); 1562 break; 1563 } 1564 if (async == QXL_ASYNC) { 1565 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1566 QXL_IO_UPDATE_AREA_ASYNC); 1567 cookie->u.area = update; 1568 } 1569 qxl_spice_update_area(d, d->ram->update_surface, 1570 cookie ? &cookie->u.area : &update, 1571 NULL, 0, 0, async, cookie); 1572 break; 1573 } 1574 case QXL_IO_NOTIFY_CMD: 1575 qemu_spice_wakeup(&d->ssd); 1576 break; 1577 case QXL_IO_NOTIFY_CURSOR: 1578 qemu_spice_wakeup(&d->ssd); 1579 break; 1580 case QXL_IO_UPDATE_IRQ: 1581 qxl_update_irq(d); 1582 break; 1583 case QXL_IO_NOTIFY_OOM: 1584 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1585 break; 1586 } 1587 d->oom_running = 1; 1588 qxl_spice_oom(d); 1589 d->oom_running = 0; 1590 break; 1591 case QXL_IO_SET_MODE: 1592 qxl_set_mode(d, val, 0); 1593 break; 1594 case QXL_IO_LOG: 1595 trace_qxl_io_log(d->id, d->ram->log_buf); 1596 if (d->guestdebug) { 1597 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1598 qemu_get_clock_ns(vm_clock), d->ram->log_buf); 1599 } 1600 break; 1601 case QXL_IO_RESET: 1602 qxl_hard_reset(d, 0); 1603 break; 1604 case QXL_IO_MEMSLOT_ADD: 1605 if (val >= NUM_MEMSLOTS) { 1606 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1607 break; 1608 } 1609 if (d->guest_slots[val].active) { 1610 qxl_set_guest_bug(d, 1611 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1612 break; 1613 } 1614 d->guest_slots[val].slot = d->ram->mem_slot; 1615 qxl_add_memslot(d, val, 0, async); 1616 break; 1617 case QXL_IO_MEMSLOT_DEL: 1618 if (val >= NUM_MEMSLOTS) { 1619 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1620 break; 1621 } 1622 qxl_del_memslot(d, val); 1623 break; 1624 case QXL_IO_CREATE_PRIMARY: 1625 if (val != 0) { 1626 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1627 async); 1628 goto cancel_async; 1629 } 1630 d->guest_primary.surface = d->ram->create_surface; 1631 qxl_create_guest_primary(d, 0, async); 1632 break; 1633 case QXL_IO_DESTROY_PRIMARY: 1634 if (val != 0) { 1635 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1636 async); 1637 goto cancel_async; 1638 } 1639 if (!qxl_destroy_primary(d, async)) { 1640 trace_qxl_io_destroy_primary_ignored(d->id, 1641 qxl_mode_to_string(d->mode)); 1642 goto cancel_async; 1643 } 1644 break; 1645 case QXL_IO_DESTROY_SURFACE_WAIT: 1646 if (val >= d->ssd.num_surfaces) { 1647 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1648 "%" PRIu64 " >= NUM_SURFACES", async, val); 1649 goto cancel_async; 1650 } 1651 qxl_spice_destroy_surface_wait(d, val, async); 1652 break; 1653 case QXL_IO_FLUSH_RELEASE: { 1654 QXLReleaseRing *ring = &d->ram->release_ring; 1655 if (ring->prod - ring->cons + 1 == ring->num_items) { 1656 fprintf(stderr, 1657 "ERROR: no flush, full release ring [p%d,%dc]\n", 1658 ring->prod, ring->cons); 1659 } 1660 qxl_push_free_res(d, 1 /* flush */); 1661 break; 1662 } 1663 case QXL_IO_FLUSH_SURFACES_ASYNC: 1664 qxl_spice_flush_surfaces_async(d); 1665 break; 1666 case QXL_IO_DESTROY_ALL_SURFACES: 1667 d->mode = QXL_MODE_UNDEFINED; 1668 qxl_spice_destroy_surfaces(d, async); 1669 break; 1670 case QXL_IO_MONITORS_CONFIG_ASYNC: 1671 qxl_spice_monitors_config_async(d, 0); 1672 break; 1673 default: 1674 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1675 } 1676 return; 1677 cancel_async: 1678 if (async) { 1679 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1680 qemu_mutex_lock(&d->async_lock); 1681 d->current_async = QXL_UNDEFINED_IO; 1682 qemu_mutex_unlock(&d->async_lock); 1683 } 1684 } 1685 1686 static uint64_t ioport_read(void *opaque, hwaddr addr, 1687 unsigned size) 1688 { 1689 PCIQXLDevice *qxl = opaque; 1690 1691 trace_qxl_io_read_unexpected(qxl->id); 1692 return 0xff; 1693 } 1694 1695 static const MemoryRegionOps qxl_io_ops = { 1696 .read = ioport_read, 1697 .write = ioport_write, 1698 .valid = { 1699 .min_access_size = 1, 1700 .max_access_size = 1, 1701 }, 1702 }; 1703 1704 static void pipe_read(void *opaque) 1705 { 1706 PCIQXLDevice *d = opaque; 1707 char dummy; 1708 int len; 1709 1710 do { 1711 len = read(d->pipe[0], &dummy, sizeof(dummy)); 1712 } while (len == sizeof(dummy)); 1713 qxl_update_irq(d); 1714 } 1715 1716 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1717 { 1718 uint32_t old_pending; 1719 uint32_t le_events = cpu_to_le32(events); 1720 1721 trace_qxl_send_events(d->id, events); 1722 if (!qemu_spice_display_is_running(&d->ssd)) { 1723 /* spice-server tracks guest running state and should not do this */ 1724 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1725 __func__); 1726 trace_qxl_send_events_vm_stopped(d->id, events); 1727 return; 1728 } 1729 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); 1730 if ((old_pending & le_events) == le_events) { 1731 return; 1732 } 1733 if (qemu_thread_is_self(&d->main)) { 1734 qxl_update_irq(d); 1735 } else { 1736 if (write(d->pipe[1], d, 1) != 1) { 1737 dprint(d, 1, "%s: write to pipe failed\n", __func__); 1738 } 1739 } 1740 } 1741 1742 static void init_pipe_signaling(PCIQXLDevice *d) 1743 { 1744 if (pipe(d->pipe) < 0) { 1745 fprintf(stderr, "%s:%s: qxl pipe creation failed\n", 1746 __FILE__, __func__); 1747 exit(1); 1748 } 1749 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); 1750 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); 1751 fcntl(d->pipe[0], F_SETOWN, getpid()); 1752 1753 qemu_thread_get_self(&d->main); 1754 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); 1755 } 1756 1757 /* graphics console */ 1758 1759 static void qxl_hw_update(void *opaque) 1760 { 1761 PCIQXLDevice *qxl = opaque; 1762 VGACommonState *vga = &qxl->vga; 1763 1764 switch (qxl->mode) { 1765 case QXL_MODE_VGA: 1766 vga->hw_ops->gfx_update(vga); 1767 break; 1768 case QXL_MODE_COMPAT: 1769 case QXL_MODE_NATIVE: 1770 qxl_render_update(qxl); 1771 break; 1772 default: 1773 break; 1774 } 1775 } 1776 1777 static void qxl_hw_invalidate(void *opaque) 1778 { 1779 PCIQXLDevice *qxl = opaque; 1780 VGACommonState *vga = &qxl->vga; 1781 1782 if (qxl->mode == QXL_MODE_VGA) { 1783 vga->hw_ops->invalidate(vga); 1784 return; 1785 } 1786 } 1787 1788 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) 1789 { 1790 PCIQXLDevice *qxl = opaque; 1791 VGACommonState *vga = &qxl->vga; 1792 1793 if (qxl->mode == QXL_MODE_VGA) { 1794 vga->hw_ops->text_update(vga, chardata); 1795 return; 1796 } 1797 } 1798 1799 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1800 { 1801 uintptr_t vram_start; 1802 int i; 1803 1804 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1805 return; 1806 } 1807 1808 /* dirty the primary surface */ 1809 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, 1810 qxl->shadow_rom.surface0_area_size); 1811 1812 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); 1813 1814 /* dirty the off-screen surfaces */ 1815 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1816 QXLSurfaceCmd *cmd; 1817 intptr_t surface_offset; 1818 int surface_size; 1819 1820 if (qxl->guest_surfaces.cmds[i] == 0) { 1821 continue; 1822 } 1823 1824 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1825 MEMSLOT_GROUP_GUEST); 1826 assert(cmd); 1827 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1828 surface_offset = (intptr_t)qxl_phys2virt(qxl, 1829 cmd->u.surface_create.data, 1830 MEMSLOT_GROUP_GUEST); 1831 assert(surface_offset); 1832 surface_offset -= vram_start; 1833 surface_size = cmd->u.surface_create.height * 1834 abs(cmd->u.surface_create.stride); 1835 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); 1836 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); 1837 } 1838 } 1839 1840 static void qxl_vm_change_state_handler(void *opaque, int running, 1841 RunState state) 1842 { 1843 PCIQXLDevice *qxl = opaque; 1844 1845 if (running) { 1846 /* 1847 * if qxl_send_events was called from spice server context before 1848 * migration ended, qxl_update_irq for these events might not have been 1849 * called 1850 */ 1851 qxl_update_irq(qxl); 1852 } else { 1853 /* make sure surfaces are saved before migration */ 1854 qxl_dirty_surfaces(qxl); 1855 } 1856 } 1857 1858 /* display change listener */ 1859 1860 static void display_update(DisplayChangeListener *dcl, 1861 int x, int y, int w, int h) 1862 { 1863 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1864 1865 if (qxl->mode == QXL_MODE_VGA) { 1866 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 1867 } 1868 } 1869 1870 static void display_switch(DisplayChangeListener *dcl, 1871 struct DisplaySurface *surface) 1872 { 1873 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1874 1875 qxl->ssd.ds = surface; 1876 if (qxl->mode == QXL_MODE_VGA) { 1877 qemu_spice_display_switch(&qxl->ssd, surface); 1878 } 1879 } 1880 1881 static void display_refresh(DisplayChangeListener *dcl) 1882 { 1883 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1884 1885 if (qxl->mode == QXL_MODE_VGA) { 1886 qemu_spice_display_refresh(&qxl->ssd); 1887 } else { 1888 qemu_mutex_lock(&qxl->ssd.lock); 1889 qemu_spice_cursor_refresh_unlocked(&qxl->ssd); 1890 qemu_mutex_unlock(&qxl->ssd.lock); 1891 } 1892 } 1893 1894 static DisplayChangeListenerOps display_listener_ops = { 1895 .dpy_name = "spice/qxl", 1896 .dpy_gfx_update = display_update, 1897 .dpy_gfx_switch = display_switch, 1898 .dpy_refresh = display_refresh, 1899 }; 1900 1901 static void qxl_init_ramsize(PCIQXLDevice *qxl) 1902 { 1903 /* vga mode framebuffer / primary surface (bar 0, first part) */ 1904 if (qxl->vgamem_size_mb < 8) { 1905 qxl->vgamem_size_mb = 8; 1906 } 1907 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; 1908 1909 /* vga ram (bar 0, total) */ 1910 if (qxl->ram_size_mb != -1) { 1911 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; 1912 } 1913 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 1914 qxl->vga.vram_size = qxl->vgamem_size * 2; 1915 } 1916 1917 /* vram32 (surfaces, 32bit, bar 1) */ 1918 if (qxl->vram32_size_mb != -1) { 1919 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; 1920 } 1921 if (qxl->vram32_size < 4096) { 1922 qxl->vram32_size = 4096; 1923 } 1924 1925 /* vram (surfaces, 64bit, bar 4+5) */ 1926 if (qxl->vram_size_mb != -1) { 1927 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; 1928 } 1929 if (qxl->vram_size < qxl->vram32_size) { 1930 qxl->vram_size = qxl->vram32_size; 1931 } 1932 1933 if (qxl->revision == 1) { 1934 qxl->vram32_size = 4096; 1935 qxl->vram_size = 4096; 1936 } 1937 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1); 1938 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); 1939 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); 1940 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); 1941 } 1942 1943 static int qxl_init_common(PCIQXLDevice *qxl) 1944 { 1945 uint8_t* config = qxl->pci.config; 1946 uint32_t pci_device_rev; 1947 uint32_t io_size; 1948 1949 qxl->mode = QXL_MODE_UNDEFINED; 1950 qxl->generation = 1; 1951 qxl->num_memslots = NUM_MEMSLOTS; 1952 qemu_mutex_init(&qxl->track_lock); 1953 qemu_mutex_init(&qxl->async_lock); 1954 qxl->current_async = QXL_UNDEFINED_IO; 1955 qxl->guest_bug = 0; 1956 1957 switch (qxl->revision) { 1958 case 1: /* spice 0.4 -- qxl-1 */ 1959 pci_device_rev = QXL_REVISION_STABLE_V04; 1960 io_size = 8; 1961 break; 1962 case 2: /* spice 0.6 -- qxl-2 */ 1963 pci_device_rev = QXL_REVISION_STABLE_V06; 1964 io_size = 16; 1965 break; 1966 case 3: /* qxl-3 */ 1967 pci_device_rev = QXL_REVISION_STABLE_V10; 1968 io_size = 32; /* PCI region size must be pow2 */ 1969 break; 1970 case 4: /* qxl-4 */ 1971 pci_device_rev = QXL_REVISION_STABLE_V12; 1972 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); 1973 break; 1974 default: 1975 error_report("Invalid revision %d for qxl device (max %d)", 1976 qxl->revision, QXL_DEFAULT_REVISION); 1977 return -1; 1978 } 1979 1980 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 1981 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 1982 1983 qxl->rom_size = qxl_rom_size(); 1984 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size); 1985 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); 1986 init_qxl_rom(qxl); 1987 init_qxl_ram(qxl); 1988 1989 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 1990 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size); 1991 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); 1992 memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar, 1993 0, qxl->vram32_size); 1994 1995 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, 1996 "qxl-ioports", io_size); 1997 if (qxl->id == 0) { 1998 vga_dirty_log_start(&qxl->vga); 1999 } 2000 memory_region_set_flush_coalesced(&qxl->io_bar); 2001 2002 2003 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 2004 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 2005 2006 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 2007 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 2008 2009 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 2010 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 2011 2012 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 2013 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 2014 2015 if (qxl->vram32_size < qxl->vram_size) { 2016 /* 2017 * Make the 64bit vram bar show up only in case it is 2018 * configured to be larger than the 32bit vram bar. 2019 */ 2020 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 2021 PCI_BASE_ADDRESS_SPACE_MEMORY | 2022 PCI_BASE_ADDRESS_MEM_TYPE_64 | 2023 PCI_BASE_ADDRESS_MEM_PREFETCH, 2024 &qxl->vram_bar); 2025 } 2026 2027 /* print pci bar details */ 2028 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", 2029 qxl->id == 0 ? "pri" : "sec", 2030 qxl->vga.vram_size / (1024*1024)); 2031 dprint(qxl, 1, "vram/32: %d MB [region 1]\n", 2032 qxl->vram32_size / (1024*1024)); 2033 dprint(qxl, 1, "vram/64: %d MB %s\n", 2034 qxl->vram_size / (1024*1024), 2035 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2036 2037 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2038 qxl->ssd.qxl.id = qxl->id; 2039 if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) { 2040 error_report("qxl interface %d.%d not supported by spice-server", 2041 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2042 return -1; 2043 } 2044 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2045 2046 init_pipe_signaling(qxl); 2047 qxl_reset_state(qxl); 2048 2049 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2050 2051 return 0; 2052 } 2053 2054 static const GraphicHwOps qxl_ops = { 2055 .invalidate = qxl_hw_invalidate, 2056 .gfx_update = qxl_hw_update, 2057 .text_update = qxl_hw_text_update, 2058 }; 2059 2060 static int qxl_init_primary(PCIDevice *dev) 2061 { 2062 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2063 VGACommonState *vga = &qxl->vga; 2064 PortioList *qxl_vga_port_list = g_new(PortioList, 1); 2065 int rc; 2066 2067 qxl->id = 0; 2068 qxl_init_ramsize(qxl); 2069 vga->vram_size_mb = qxl->vga.vram_size >> 20; 2070 vga_common_init(vga); 2071 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false); 2072 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga"); 2073 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0); 2074 2075 vga->con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl); 2076 qemu_spice_display_init_common(&qxl->ssd); 2077 2078 rc = qxl_init_common(qxl); 2079 if (rc != 0) { 2080 return rc; 2081 } 2082 2083 qxl->ssd.dcl.ops = &display_listener_ops; 2084 qxl->ssd.dcl.con = vga->con; 2085 register_displaychangelistener(&qxl->ssd.dcl); 2086 return rc; 2087 } 2088 2089 static int qxl_init_secondary(PCIDevice *dev) 2090 { 2091 static int device_id = 1; 2092 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2093 2094 qxl->id = device_id++; 2095 qxl_init_ramsize(qxl); 2096 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size); 2097 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); 2098 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2099 qxl->vga.con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl); 2100 2101 return qxl_init_common(qxl); 2102 } 2103 2104 static void qxl_pre_save(void *opaque) 2105 { 2106 PCIQXLDevice* d = opaque; 2107 uint8_t *ram_start = d->vga.vram_ptr; 2108 2109 trace_qxl_pre_save(d->id); 2110 if (d->last_release == NULL) { 2111 d->last_release_offset = 0; 2112 } else { 2113 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2114 } 2115 assert(d->last_release_offset < d->vga.vram_size); 2116 } 2117 2118 static int qxl_pre_load(void *opaque) 2119 { 2120 PCIQXLDevice* d = opaque; 2121 2122 trace_qxl_pre_load(d->id); 2123 qxl_hard_reset(d, 1); 2124 qxl_exit_vga_mode(d); 2125 return 0; 2126 } 2127 2128 static void qxl_create_memslots(PCIQXLDevice *d) 2129 { 2130 int i; 2131 2132 for (i = 0; i < NUM_MEMSLOTS; i++) { 2133 if (!d->guest_slots[i].active) { 2134 continue; 2135 } 2136 qxl_add_memslot(d, i, 0, QXL_SYNC); 2137 } 2138 } 2139 2140 static int qxl_post_load(void *opaque, int version) 2141 { 2142 PCIQXLDevice* d = opaque; 2143 uint8_t *ram_start = d->vga.vram_ptr; 2144 QXLCommandExt *cmds; 2145 int in, out, newmode; 2146 2147 assert(d->last_release_offset < d->vga.vram_size); 2148 if (d->last_release_offset == 0) { 2149 d->last_release = NULL; 2150 } else { 2151 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2152 } 2153 2154 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2155 2156 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2157 newmode = d->mode; 2158 d->mode = QXL_MODE_UNDEFINED; 2159 2160 switch (newmode) { 2161 case QXL_MODE_UNDEFINED: 2162 qxl_create_memslots(d); 2163 break; 2164 case QXL_MODE_VGA: 2165 qxl_create_memslots(d); 2166 qxl_enter_vga_mode(d); 2167 break; 2168 case QXL_MODE_NATIVE: 2169 qxl_create_memslots(d); 2170 qxl_create_guest_primary(d, 1, QXL_SYNC); 2171 2172 /* replay surface-create and cursor-set commands */ 2173 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1)); 2174 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2175 if (d->guest_surfaces.cmds[in] == 0) { 2176 continue; 2177 } 2178 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2179 cmds[out].cmd.type = QXL_CMD_SURFACE; 2180 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2181 out++; 2182 } 2183 if (d->guest_cursor) { 2184 cmds[out].cmd.data = d->guest_cursor; 2185 cmds[out].cmd.type = QXL_CMD_CURSOR; 2186 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2187 out++; 2188 } 2189 qxl_spice_loadvm_commands(d, cmds, out); 2190 g_free(cmds); 2191 if (d->guest_monitors_config) { 2192 qxl_spice_monitors_config_async(d, 1); 2193 } 2194 break; 2195 case QXL_MODE_COMPAT: 2196 /* note: no need to call qxl_create_memslots, qxl_set_mode 2197 * creates the mem slot. */ 2198 qxl_set_mode(d, d->shadow_rom.mode, 1); 2199 break; 2200 } 2201 return 0; 2202 } 2203 2204 #define QXL_SAVE_VERSION 21 2205 2206 static bool qxl_monitors_config_needed(void *opaque) 2207 { 2208 PCIQXLDevice *qxl = opaque; 2209 2210 return qxl->guest_monitors_config != 0; 2211 } 2212 2213 2214 static VMStateDescription qxl_memslot = { 2215 .name = "qxl-memslot", 2216 .version_id = QXL_SAVE_VERSION, 2217 .minimum_version_id = QXL_SAVE_VERSION, 2218 .fields = (VMStateField[]) { 2219 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2220 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2221 VMSTATE_UINT32(active, struct guest_slots), 2222 VMSTATE_END_OF_LIST() 2223 } 2224 }; 2225 2226 static VMStateDescription qxl_surface = { 2227 .name = "qxl-surface", 2228 .version_id = QXL_SAVE_VERSION, 2229 .minimum_version_id = QXL_SAVE_VERSION, 2230 .fields = (VMStateField[]) { 2231 VMSTATE_UINT32(width, QXLSurfaceCreate), 2232 VMSTATE_UINT32(height, QXLSurfaceCreate), 2233 VMSTATE_INT32(stride, QXLSurfaceCreate), 2234 VMSTATE_UINT32(format, QXLSurfaceCreate), 2235 VMSTATE_UINT32(position, QXLSurfaceCreate), 2236 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2237 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2238 VMSTATE_UINT32(type, QXLSurfaceCreate), 2239 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2240 VMSTATE_END_OF_LIST() 2241 } 2242 }; 2243 2244 static VMStateDescription qxl_vmstate_monitors_config = { 2245 .name = "qxl/monitors-config", 2246 .version_id = 1, 2247 .minimum_version_id = 1, 2248 .fields = (VMStateField[]) { 2249 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2250 VMSTATE_END_OF_LIST() 2251 }, 2252 }; 2253 2254 static VMStateDescription qxl_vmstate = { 2255 .name = "qxl", 2256 .version_id = QXL_SAVE_VERSION, 2257 .minimum_version_id = QXL_SAVE_VERSION, 2258 .pre_save = qxl_pre_save, 2259 .pre_load = qxl_pre_load, 2260 .post_load = qxl_post_load, 2261 .fields = (VMStateField[]) { 2262 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2263 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2264 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2265 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2266 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2267 VMSTATE_UINT32(mode, PCIQXLDevice), 2268 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2269 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), 2270 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2271 qxl_memslot, struct guest_slots), 2272 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2273 qxl_surface, QXLSurfaceCreate), 2274 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), 2275 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2276 ssd.num_surfaces, 0, 2277 vmstate_info_uint64, uint64_t), 2278 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2279 VMSTATE_END_OF_LIST() 2280 }, 2281 .subsections = (VMStateSubsection[]) { 2282 { 2283 .vmsd = &qxl_vmstate_monitors_config, 2284 .needed = qxl_monitors_config_needed, 2285 }, { 2286 /* empty */ 2287 } 2288 } 2289 }; 2290 2291 static Property qxl_properties[] = { 2292 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 2293 64 * 1024 * 1024), 2294 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, 2295 64 * 1024 * 1024), 2296 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2297 QXL_DEFAULT_REVISION), 2298 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2299 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2300 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2301 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2302 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2303 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2304 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2305 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2306 DEFINE_PROP_END_OF_LIST(), 2307 }; 2308 2309 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2310 { 2311 DeviceClass *dc = DEVICE_CLASS(klass); 2312 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2313 2314 k->no_hotplug = 1; 2315 k->init = qxl_init_primary; 2316 k->romfile = "vgabios-qxl.bin"; 2317 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2318 k->device_id = QXL_DEVICE_ID_STABLE; 2319 k->class_id = PCI_CLASS_DISPLAY_VGA; 2320 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2321 dc->reset = qxl_reset_handler; 2322 dc->vmsd = &qxl_vmstate; 2323 dc->props = qxl_properties; 2324 } 2325 2326 static const TypeInfo qxl_primary_info = { 2327 .name = "qxl-vga", 2328 .parent = TYPE_PCI_DEVICE, 2329 .instance_size = sizeof(PCIQXLDevice), 2330 .class_init = qxl_primary_class_init, 2331 }; 2332 2333 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2334 { 2335 DeviceClass *dc = DEVICE_CLASS(klass); 2336 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2337 2338 k->init = qxl_init_secondary; 2339 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2340 k->device_id = QXL_DEVICE_ID_STABLE; 2341 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2342 dc->desc = "Spice QXL GPU (secondary)"; 2343 dc->reset = qxl_reset_handler; 2344 dc->vmsd = &qxl_vmstate; 2345 dc->props = qxl_properties; 2346 } 2347 2348 static const TypeInfo qxl_secondary_info = { 2349 .name = "qxl", 2350 .parent = TYPE_PCI_DEVICE, 2351 .instance_size = sizeof(PCIQXLDevice), 2352 .class_init = qxl_secondary_class_init, 2353 }; 2354 2355 static void qxl_register_types(void) 2356 { 2357 type_register_static(&qxl_primary_info); 2358 type_register_static(&qxl_secondary_info); 2359 } 2360 2361 type_init(qxl_register_types) 2362