xref: /openbmc/qemu/hw/display/qxl.c (revision 650d103d3ea959212f826acb9d3fe80cf30e347b)
1 /*
2  * Copyright (C) 2010 Red Hat, Inc.
3  *
4  * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5  * maintained by Gerd Hoffmann <kraxel@redhat.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 or
10  * (at your option) version 3 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include <zlib.h>
24 
25 #include "qapi/error.h"
26 #include "qemu/timer.h"
27 #include "qemu/queue.h"
28 #include "qemu/atomic.h"
29 #include "qemu/module.h"
30 #include "sysemu/sysemu.h"
31 #include "migration/blocker.h"
32 #include "migration/vmstate.h"
33 #include "trace.h"
34 
35 #include "qxl.h"
36 
37 #undef SPICE_RING_CONS_ITEM
38 #define SPICE_RING_CONS_ITEM(qxl, r, ret) {                             \
39         uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r);           \
40         if (cons >= ARRAY_SIZE((r)->items)) {                           \
41             qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
42                           "%u >= %zu", cons, ARRAY_SIZE((r)->items));   \
43             ret = NULL;                                                 \
44         } else {                                                        \
45             ret = &(r)->items[cons].el;                                 \
46         }                                                               \
47     }
48 
49 #undef ALIGN
50 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
51 
52 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
53 
54 #define QXL_MODE(_x, _y, _b, _o)                  \
55     {   .x_res = _x,                              \
56         .y_res = _y,                              \
57         .bits  = _b,                              \
58         .stride = (_x) * (_b) / 8,                \
59         .x_mili = PIXEL_SIZE * (_x),              \
60         .y_mili = PIXEL_SIZE * (_y),              \
61         .orientation = _o,                        \
62     }
63 
64 #define QXL_MODE_16_32(x_res, y_res, orientation) \
65     QXL_MODE(x_res, y_res, 16, orientation),      \
66     QXL_MODE(x_res, y_res, 32, orientation)
67 
68 #define QXL_MODE_EX(x_res, y_res)                 \
69     QXL_MODE_16_32(x_res, y_res, 0),              \
70     QXL_MODE_16_32(x_res, y_res, 1)
71 
72 static QXLMode qxl_modes[] = {
73     QXL_MODE_EX(640, 480),
74     QXL_MODE_EX(800, 480),
75     QXL_MODE_EX(800, 600),
76     QXL_MODE_EX(832, 624),
77     QXL_MODE_EX(960, 640),
78     QXL_MODE_EX(1024, 600),
79     QXL_MODE_EX(1024, 768),
80     QXL_MODE_EX(1152, 864),
81     QXL_MODE_EX(1152, 870),
82     QXL_MODE_EX(1280, 720),
83     QXL_MODE_EX(1280, 760),
84     QXL_MODE_EX(1280, 768),
85     QXL_MODE_EX(1280, 800),
86     QXL_MODE_EX(1280, 960),
87     QXL_MODE_EX(1280, 1024),
88     QXL_MODE_EX(1360, 768),
89     QXL_MODE_EX(1366, 768),
90     QXL_MODE_EX(1400, 1050),
91     QXL_MODE_EX(1440, 900),
92     QXL_MODE_EX(1600, 900),
93     QXL_MODE_EX(1600, 1200),
94     QXL_MODE_EX(1680, 1050),
95     QXL_MODE_EX(1920, 1080),
96     /* these modes need more than 8 MB video memory */
97     QXL_MODE_EX(1920, 1200),
98     QXL_MODE_EX(1920, 1440),
99     QXL_MODE_EX(2000, 2000),
100     QXL_MODE_EX(2048, 1536),
101     QXL_MODE_EX(2048, 2048),
102     QXL_MODE_EX(2560, 1440),
103     QXL_MODE_EX(2560, 1600),
104     /* these modes need more than 16 MB video memory */
105     QXL_MODE_EX(2560, 2048),
106     QXL_MODE_EX(2800, 2100),
107     QXL_MODE_EX(3200, 2400),
108     /* these modes need more than 32 MB video memory */
109     QXL_MODE_EX(3840, 2160), /* 4k mainstream */
110     QXL_MODE_EX(4096, 2160), /* 4k            */
111     /* these modes need more than 64 MB video memory */
112     QXL_MODE_EX(7680, 4320), /* 8k mainstream */
113     /* these modes need more than 128 MB video memory */
114     QXL_MODE_EX(8192, 4320), /* 8k            */
115 };
116 
117 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
118 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
119 static void qxl_reset_memslots(PCIQXLDevice *d);
120 static void qxl_reset_surfaces(PCIQXLDevice *d);
121 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
122 
123 static void qxl_hw_update(void *opaque);
124 
125 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
126 {
127     trace_qxl_set_guest_bug(qxl->id);
128     qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
129     qxl->guest_bug = 1;
130     if (qxl->guestdebug) {
131         va_list ap;
132         va_start(ap, msg);
133         fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
134         vfprintf(stderr, msg, ap);
135         fprintf(stderr, "\n");
136         va_end(ap);
137     }
138 }
139 
140 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
141 {
142     qxl->guest_bug = 0;
143 }
144 
145 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
146                            struct QXLRect *area, struct QXLRect *dirty_rects,
147                            uint32_t num_dirty_rects,
148                            uint32_t clear_dirty_region,
149                            qxl_async_io async, struct QXLCookie *cookie)
150 {
151     trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
152                                 area->top, area->bottom);
153     trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
154                                      clear_dirty_region);
155     if (async == QXL_SYNC) {
156         spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
157                         dirty_rects, num_dirty_rects, clear_dirty_region);
158     } else {
159         assert(cookie != NULL);
160         spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
161                                     clear_dirty_region, (uintptr_t)cookie);
162     }
163 }
164 
165 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
166                                                     uint32_t id)
167 {
168     trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
169     qemu_mutex_lock(&qxl->track_lock);
170     qxl->guest_surfaces.cmds[id] = 0;
171     qxl->guest_surfaces.count--;
172     qemu_mutex_unlock(&qxl->track_lock);
173 }
174 
175 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
176                                            qxl_async_io async)
177 {
178     QXLCookie *cookie;
179 
180     trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
181     if (async) {
182         cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
183                                 QXL_IO_DESTROY_SURFACE_ASYNC);
184         cookie->u.surface_id = id;
185         spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
186     } else {
187         spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
188         qxl_spice_destroy_surface_wait_complete(qxl, id);
189     }
190 }
191 
192 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
193 {
194     trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
195                                          qxl->num_free_res);
196     spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
197         (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
198                                   QXL_IO_FLUSH_SURFACES_ASYNC));
199 }
200 
201 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
202                                uint32_t count)
203 {
204     trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
205     spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
206 }
207 
208 void qxl_spice_oom(PCIQXLDevice *qxl)
209 {
210     trace_qxl_spice_oom(qxl->id);
211     spice_qxl_oom(&qxl->ssd.qxl);
212 }
213 
214 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
215 {
216     trace_qxl_spice_reset_memslots(qxl->id);
217     spice_qxl_reset_memslots(&qxl->ssd.qxl);
218 }
219 
220 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
221 {
222     trace_qxl_spice_destroy_surfaces_complete(qxl->id);
223     qemu_mutex_lock(&qxl->track_lock);
224     memset(qxl->guest_surfaces.cmds, 0,
225            sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
226     qxl->guest_surfaces.count = 0;
227     qemu_mutex_unlock(&qxl->track_lock);
228 }
229 
230 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
231 {
232     trace_qxl_spice_destroy_surfaces(qxl->id, async);
233     if (async) {
234         spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
235                 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
236                                           QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
237     } else {
238         spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
239         qxl_spice_destroy_surfaces_complete(qxl);
240     }
241 }
242 
243 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
244 {
245     QXLMonitorsConfig *cfg;
246 
247     trace_qxl_spice_monitors_config(qxl->id);
248     if (replay) {
249         /*
250          * don't use QXL_COOKIE_TYPE_IO:
251          *  - we are not running yet (post_load), we will assert
252          *    in send_events
253          *  - this is not a guest io, but a reply, so async_io isn't set.
254          */
255         spice_qxl_monitors_config_async(&qxl->ssd.qxl,
256                 qxl->guest_monitors_config,
257                 MEMSLOT_GROUP_GUEST,
258                 (uintptr_t)qxl_cookie_new(
259                     QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
260                     0));
261     } else {
262 /* >= release 0.12.6, < release 0.14.2 */
263 #if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02
264         if (qxl->max_outputs) {
265             spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
266         }
267 #endif
268         qxl->guest_monitors_config = qxl->ram->monitors_config;
269         spice_qxl_monitors_config_async(&qxl->ssd.qxl,
270                 qxl->ram->monitors_config,
271                 MEMSLOT_GROUP_GUEST,
272                 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
273                                           QXL_IO_MONITORS_CONFIG_ASYNC));
274     }
275 
276     cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST);
277     if (cfg != NULL && cfg->count == 1) {
278         qxl->guest_primary.resized = 1;
279         qxl->guest_head0_width  = cfg->heads[0].width;
280         qxl->guest_head0_height = cfg->heads[0].height;
281     } else {
282         qxl->guest_head0_width  = 0;
283         qxl->guest_head0_height = 0;
284     }
285 }
286 
287 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
288 {
289     trace_qxl_spice_reset_image_cache(qxl->id);
290     spice_qxl_reset_image_cache(&qxl->ssd.qxl);
291 }
292 
293 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
294 {
295     trace_qxl_spice_reset_cursor(qxl->id);
296     spice_qxl_reset_cursor(&qxl->ssd.qxl);
297     qemu_mutex_lock(&qxl->track_lock);
298     qxl->guest_cursor = 0;
299     qemu_mutex_unlock(&qxl->track_lock);
300     if (qxl->ssd.cursor) {
301         cursor_put(qxl->ssd.cursor);
302     }
303     qxl->ssd.cursor = cursor_builtin_hidden();
304 }
305 
306 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
307 {
308     /*
309      * zlib xors the seed with 0xffffffff, and xors the result
310      * again with 0xffffffff; Both are not done with linux's crc32,
311      * which we want to be compatible with, so undo that.
312      */
313     return crc32(0xffffffff, p, len) ^ 0xffffffff;
314 }
315 
316 static ram_addr_t qxl_rom_size(void)
317 {
318 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
319 #define QXL_ROM_SZ 8192
320 
321     QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
322     return QXL_ROM_SZ;
323 }
324 
325 static void init_qxl_rom(PCIQXLDevice *d)
326 {
327     QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
328     QXLModes *modes = (QXLModes *)(rom + 1);
329     uint32_t ram_header_size;
330     uint32_t surface0_area_size;
331     uint32_t num_pages;
332     uint32_t fb;
333     int i, n;
334 
335     memset(rom, 0, d->rom_size);
336 
337     rom->magic         = cpu_to_le32(QXL_ROM_MAGIC);
338     rom->id            = cpu_to_le32(d->id);
339     rom->log_level     = cpu_to_le32(d->guestdebug);
340     rom->modes_offset  = cpu_to_le32(sizeof(QXLRom));
341 
342     rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
343     rom->slot_id_bits  = MEMSLOT_SLOT_BITS;
344     rom->slots_start   = 1;
345     rom->slots_end     = NUM_MEMSLOTS - 1;
346     rom->n_surfaces    = cpu_to_le32(d->ssd.num_surfaces);
347 
348     for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
349         fb = qxl_modes[i].y_res * qxl_modes[i].stride;
350         if (fb > d->vgamem_size) {
351             continue;
352         }
353         modes->modes[n].id          = cpu_to_le32(i);
354         modes->modes[n].x_res       = cpu_to_le32(qxl_modes[i].x_res);
355         modes->modes[n].y_res       = cpu_to_le32(qxl_modes[i].y_res);
356         modes->modes[n].bits        = cpu_to_le32(qxl_modes[i].bits);
357         modes->modes[n].stride      = cpu_to_le32(qxl_modes[i].stride);
358         modes->modes[n].x_mili      = cpu_to_le32(qxl_modes[i].x_mili);
359         modes->modes[n].y_mili      = cpu_to_le32(qxl_modes[i].y_mili);
360         modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
361         n++;
362     }
363     modes->n_modes     = cpu_to_le32(n);
364 
365     ram_header_size    = ALIGN(sizeof(QXLRam), 4096);
366     surface0_area_size = ALIGN(d->vgamem_size, 4096);
367     num_pages          = d->vga.vram_size;
368     num_pages         -= ram_header_size;
369     num_pages         -= surface0_area_size;
370     num_pages          = num_pages / QXL_PAGE_SIZE;
371 
372     assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
373 
374     rom->draw_area_offset   = cpu_to_le32(0);
375     rom->surface0_area_size = cpu_to_le32(surface0_area_size);
376     rom->pages_offset       = cpu_to_le32(surface0_area_size);
377     rom->num_pages          = cpu_to_le32(num_pages);
378     rom->ram_header_offset  = cpu_to_le32(d->vga.vram_size - ram_header_size);
379 
380     if (d->xres && d->yres) {
381         /* needs linux kernel 4.12+ to work */
382         rom->client_monitors_config.count = 1;
383         rom->client_monitors_config.heads[0].left = 0;
384         rom->client_monitors_config.heads[0].top = 0;
385         rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
386         rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
387         rom->client_monitors_config_crc = qxl_crc32(
388             (const uint8_t *)&rom->client_monitors_config,
389             sizeof(rom->client_monitors_config));
390     }
391 
392     d->shadow_rom = *rom;
393     d->rom        = rom;
394     d->modes      = modes;
395 }
396 
397 static void init_qxl_ram(PCIQXLDevice *d)
398 {
399     uint8_t *buf;
400     uint32_t prod;
401     QXLReleaseRing *ring;
402 
403     buf = d->vga.vram_ptr;
404     d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
405     d->ram->magic       = cpu_to_le32(QXL_RAM_MAGIC);
406     d->ram->int_pending = cpu_to_le32(0);
407     d->ram->int_mask    = cpu_to_le32(0);
408     d->ram->update_surface = 0;
409     d->ram->monitors_config = 0;
410     SPICE_RING_INIT(&d->ram->cmd_ring);
411     SPICE_RING_INIT(&d->ram->cursor_ring);
412     SPICE_RING_INIT(&d->ram->release_ring);
413 
414     ring = &d->ram->release_ring;
415     prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
416     assert(prod < ARRAY_SIZE(ring->items));
417     ring->items[prod].el = 0;
418 
419     qxl_ring_set_dirty(d);
420 }
421 
422 /* can be called from spice server thread context */
423 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
424 {
425     memory_region_set_dirty(mr, addr, end - addr);
426 }
427 
428 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
429 {
430     qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
431 }
432 
433 /* called from spice server thread context only */
434 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
435 {
436     void *base = qxl->vga.vram_ptr;
437     intptr_t offset;
438 
439     offset = ptr - base;
440     assert(offset < qxl->vga.vram_size);
441     qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
442 }
443 
444 /* can be called from spice server thread context */
445 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
446 {
447     ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
448     ram_addr_t end  = qxl->vga.vram_size;
449     qxl_set_dirty(&qxl->vga.vram, addr, end);
450 }
451 
452 /*
453  * keep track of some command state, for savevm/loadvm.
454  * called from spice server thread context only
455  */
456 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
457 {
458     switch (le32_to_cpu(ext->cmd.type)) {
459     case QXL_CMD_SURFACE:
460     {
461         QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
462 
463         if (!cmd) {
464             return 1;
465         }
466         uint32_t id = le32_to_cpu(cmd->surface_id);
467 
468         if (id >= qxl->ssd.num_surfaces) {
469             qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
470                               qxl->ssd.num_surfaces);
471             return 1;
472         }
473         if (cmd->type == QXL_SURFACE_CMD_CREATE &&
474             (cmd->u.surface_create.stride & 0x03) != 0) {
475             qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
476                               cmd->u.surface_create.stride);
477             return 1;
478         }
479         qemu_mutex_lock(&qxl->track_lock);
480         if (cmd->type == QXL_SURFACE_CMD_CREATE) {
481             qxl->guest_surfaces.cmds[id] = ext->cmd.data;
482             qxl->guest_surfaces.count++;
483             if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
484                 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
485         }
486         if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
487             qxl->guest_surfaces.cmds[id] = 0;
488             qxl->guest_surfaces.count--;
489         }
490         qemu_mutex_unlock(&qxl->track_lock);
491         break;
492     }
493     case QXL_CMD_CURSOR:
494     {
495         QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
496 
497         if (!cmd) {
498             return 1;
499         }
500         if (cmd->type == QXL_CURSOR_SET) {
501             qemu_mutex_lock(&qxl->track_lock);
502             qxl->guest_cursor = ext->cmd.data;
503             qemu_mutex_unlock(&qxl->track_lock);
504         }
505         if (cmd->type == QXL_CURSOR_HIDE) {
506             qemu_mutex_lock(&qxl->track_lock);
507             qxl->guest_cursor = 0;
508             qemu_mutex_unlock(&qxl->track_lock);
509         }
510         break;
511     }
512     }
513     return 0;
514 }
515 
516 /* spice display interface callbacks */
517 
518 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
519 {
520     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
521 
522     trace_qxl_interface_attach_worker(qxl->id);
523 }
524 
525 static void interface_set_compression_level(QXLInstance *sin, int level)
526 {
527     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
528 
529     trace_qxl_interface_set_compression_level(qxl->id, level);
530     qxl->shadow_rom.compression_level = cpu_to_le32(level);
531     qxl->rom->compression_level = cpu_to_le32(level);
532     qxl_rom_set_dirty(qxl);
533 }
534 
535 #if SPICE_NEEDS_SET_MM_TIME
536 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
537 {
538     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
539 
540     if (!qemu_spice_display_is_running(&qxl->ssd)) {
541         return;
542     }
543 
544     trace_qxl_interface_set_mm_time(qxl->id, mm_time);
545     qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
546     qxl->rom->mm_clock = cpu_to_le32(mm_time);
547     qxl_rom_set_dirty(qxl);
548 }
549 #endif
550 
551 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
552 {
553     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
554 
555     trace_qxl_interface_get_init_info(qxl->id);
556     info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
557     info->memslot_id_bits = MEMSLOT_SLOT_BITS;
558     info->num_memslots = NUM_MEMSLOTS;
559     info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
560     info->internal_groupslot_id = 0;
561     info->qxl_ram_size =
562         le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
563     info->n_surfaces = qxl->ssd.num_surfaces;
564 }
565 
566 static const char *qxl_mode_to_string(int mode)
567 {
568     switch (mode) {
569     case QXL_MODE_COMPAT:
570         return "compat";
571     case QXL_MODE_NATIVE:
572         return "native";
573     case QXL_MODE_UNDEFINED:
574         return "undefined";
575     case QXL_MODE_VGA:
576         return "vga";
577     }
578     return "INVALID";
579 }
580 
581 static const char *io_port_to_string(uint32_t io_port)
582 {
583     if (io_port >= QXL_IO_RANGE_SIZE) {
584         return "out of range";
585     }
586     static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
587         [QXL_IO_NOTIFY_CMD]             = "QXL_IO_NOTIFY_CMD",
588         [QXL_IO_NOTIFY_CURSOR]          = "QXL_IO_NOTIFY_CURSOR",
589         [QXL_IO_UPDATE_AREA]            = "QXL_IO_UPDATE_AREA",
590         [QXL_IO_UPDATE_IRQ]             = "QXL_IO_UPDATE_IRQ",
591         [QXL_IO_NOTIFY_OOM]             = "QXL_IO_NOTIFY_OOM",
592         [QXL_IO_RESET]                  = "QXL_IO_RESET",
593         [QXL_IO_SET_MODE]               = "QXL_IO_SET_MODE",
594         [QXL_IO_LOG]                    = "QXL_IO_LOG",
595         [QXL_IO_MEMSLOT_ADD]            = "QXL_IO_MEMSLOT_ADD",
596         [QXL_IO_MEMSLOT_DEL]            = "QXL_IO_MEMSLOT_DEL",
597         [QXL_IO_DETACH_PRIMARY]         = "QXL_IO_DETACH_PRIMARY",
598         [QXL_IO_ATTACH_PRIMARY]         = "QXL_IO_ATTACH_PRIMARY",
599         [QXL_IO_CREATE_PRIMARY]         = "QXL_IO_CREATE_PRIMARY",
600         [QXL_IO_DESTROY_PRIMARY]        = "QXL_IO_DESTROY_PRIMARY",
601         [QXL_IO_DESTROY_SURFACE_WAIT]   = "QXL_IO_DESTROY_SURFACE_WAIT",
602         [QXL_IO_DESTROY_ALL_SURFACES]   = "QXL_IO_DESTROY_ALL_SURFACES",
603         [QXL_IO_UPDATE_AREA_ASYNC]      = "QXL_IO_UPDATE_AREA_ASYNC",
604         [QXL_IO_MEMSLOT_ADD_ASYNC]      = "QXL_IO_MEMSLOT_ADD_ASYNC",
605         [QXL_IO_CREATE_PRIMARY_ASYNC]   = "QXL_IO_CREATE_PRIMARY_ASYNC",
606         [QXL_IO_DESTROY_PRIMARY_ASYNC]  = "QXL_IO_DESTROY_PRIMARY_ASYNC",
607         [QXL_IO_DESTROY_SURFACE_ASYNC]  = "QXL_IO_DESTROY_SURFACE_ASYNC",
608         [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
609                                         = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
610         [QXL_IO_FLUSH_SURFACES_ASYNC]   = "QXL_IO_FLUSH_SURFACES_ASYNC",
611         [QXL_IO_FLUSH_RELEASE]          = "QXL_IO_FLUSH_RELEASE",
612         [QXL_IO_MONITORS_CONFIG_ASYNC]  = "QXL_IO_MONITORS_CONFIG_ASYNC",
613     };
614     return io_port_to_string[io_port];
615 }
616 
617 /* called from spice server thread context only */
618 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
619 {
620     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
621     SimpleSpiceUpdate *update;
622     QXLCommandRing *ring;
623     QXLCommand *cmd;
624     int notify, ret;
625 
626     trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
627 
628     switch (qxl->mode) {
629     case QXL_MODE_VGA:
630         ret = false;
631         qemu_mutex_lock(&qxl->ssd.lock);
632         update = QTAILQ_FIRST(&qxl->ssd.updates);
633         if (update != NULL) {
634             QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
635             *ext = update->ext;
636             ret = true;
637         }
638         qemu_mutex_unlock(&qxl->ssd.lock);
639         if (ret) {
640             trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
641             qxl_log_command(qxl, "vga", ext);
642         }
643         return ret;
644     case QXL_MODE_COMPAT:
645     case QXL_MODE_NATIVE:
646     case QXL_MODE_UNDEFINED:
647         ring = &qxl->ram->cmd_ring;
648         if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
649             return false;
650         }
651         SPICE_RING_CONS_ITEM(qxl, ring, cmd);
652         if (!cmd) {
653             return false;
654         }
655         ext->cmd      = *cmd;
656         ext->group_id = MEMSLOT_GROUP_GUEST;
657         ext->flags    = qxl->cmdflags;
658         SPICE_RING_POP(ring, notify);
659         qxl_ring_set_dirty(qxl);
660         if (notify) {
661             qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
662         }
663         qxl->guest_primary.commands++;
664         qxl_track_command(qxl, ext);
665         qxl_log_command(qxl, "cmd", ext);
666         {
667             /*
668              * Windows 8 drivers place qxl commands in the vram
669              * (instead of the ram) bar.  We can't live migrate such a
670              * guest, so add a migration blocker in case we detect
671              * this, to avoid triggering the assert in pre_save().
672              *
673              * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa
674              */
675             void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
676             if (msg != NULL && (
677                     msg < (void *)qxl->vga.vram_ptr ||
678                     msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) {
679                 if (!qxl->migration_blocker) {
680                     Error *local_err = NULL;
681                     error_setg(&qxl->migration_blocker,
682                                "qxl: guest bug: command not in ram bar");
683                     migrate_add_blocker(qxl->migration_blocker, &local_err);
684                     if (local_err) {
685                         error_report_err(local_err);
686                     }
687                 }
688             }
689         }
690         trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
691         return true;
692     default:
693         return false;
694     }
695 }
696 
697 /* called from spice server thread context only */
698 static int interface_req_cmd_notification(QXLInstance *sin)
699 {
700     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
701     int wait = 1;
702 
703     trace_qxl_ring_command_req_notification(qxl->id);
704     switch (qxl->mode) {
705     case QXL_MODE_COMPAT:
706     case QXL_MODE_NATIVE:
707     case QXL_MODE_UNDEFINED:
708         SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
709         qxl_ring_set_dirty(qxl);
710         break;
711     default:
712         /* nothing */
713         break;
714     }
715     return wait;
716 }
717 
718 /* called from spice server thread context only */
719 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
720 {
721     QXLReleaseRing *ring = &d->ram->release_ring;
722     uint32_t prod;
723     int notify;
724 
725 #define QXL_FREE_BUNCH_SIZE 32
726 
727     if (ring->prod - ring->cons + 1 == ring->num_items) {
728         /* ring full -- can't push */
729         return;
730     }
731     if (!flush && d->oom_running) {
732         /* collect everything from oom handler before pushing */
733         return;
734     }
735     if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
736         /* collect a bit more before pushing */
737         return;
738     }
739 
740     SPICE_RING_PUSH(ring, notify);
741     trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
742            d->guest_surfaces.count, d->num_free_res,
743            d->last_release, notify ? "yes" : "no");
744     trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
745            ring->num_items, ring->prod, ring->cons);
746     if (notify) {
747         qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
748     }
749 
750     ring = &d->ram->release_ring;
751     prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
752     if (prod >= ARRAY_SIZE(ring->items)) {
753         qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
754                           "%u >= %zu", prod, ARRAY_SIZE(ring->items));
755         return;
756     }
757     ring->items[prod].el = 0;
758     d->num_free_res = 0;
759     d->last_release = NULL;
760     qxl_ring_set_dirty(d);
761 }
762 
763 /* called from spice server thread context only */
764 static void interface_release_resource(QXLInstance *sin,
765                                        QXLReleaseInfoExt ext)
766 {
767     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
768     QXLReleaseRing *ring;
769     uint32_t prod;
770     uint64_t id;
771 
772     if (!ext.info) {
773         return;
774     }
775     if (ext.group_id == MEMSLOT_GROUP_HOST) {
776         /* host group -> vga mode update request */
777         QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
778         SimpleSpiceUpdate *update;
779         g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
780         update = container_of(cmdext, SimpleSpiceUpdate, ext);
781         qemu_spice_destroy_update(&qxl->ssd, update);
782         return;
783     }
784 
785     /*
786      * ext->info points into guest-visible memory
787      * pci bar 0, $command.release_info
788      */
789     ring = &qxl->ram->release_ring;
790     prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
791     if (prod >= ARRAY_SIZE(ring->items)) {
792         qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
793                           "%u >= %zu", prod, ARRAY_SIZE(ring->items));
794         return;
795     }
796     if (ring->items[prod].el == 0) {
797         /* stick head into the ring */
798         id = ext.info->id;
799         ext.info->next = 0;
800         qxl_ram_set_dirty(qxl, &ext.info->next);
801         ring->items[prod].el = id;
802         qxl_ring_set_dirty(qxl);
803     } else {
804         /* append item to the list */
805         qxl->last_release->next = ext.info->id;
806         qxl_ram_set_dirty(qxl, &qxl->last_release->next);
807         ext.info->next = 0;
808         qxl_ram_set_dirty(qxl, &ext.info->next);
809     }
810     qxl->last_release = ext.info;
811     qxl->num_free_res++;
812     trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
813     qxl_push_free_res(qxl, 0);
814 }
815 
816 /* called from spice server thread context only */
817 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
818 {
819     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
820     QXLCursorRing *ring;
821     QXLCommand *cmd;
822     int notify;
823 
824     trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
825 
826     switch (qxl->mode) {
827     case QXL_MODE_COMPAT:
828     case QXL_MODE_NATIVE:
829     case QXL_MODE_UNDEFINED:
830         ring = &qxl->ram->cursor_ring;
831         if (SPICE_RING_IS_EMPTY(ring)) {
832             return false;
833         }
834         SPICE_RING_CONS_ITEM(qxl, ring, cmd);
835         if (!cmd) {
836             return false;
837         }
838         ext->cmd      = *cmd;
839         ext->group_id = MEMSLOT_GROUP_GUEST;
840         ext->flags    = qxl->cmdflags;
841         SPICE_RING_POP(ring, notify);
842         qxl_ring_set_dirty(qxl);
843         if (notify) {
844             qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
845         }
846         qxl->guest_primary.commands++;
847         qxl_track_command(qxl, ext);
848         qxl_log_command(qxl, "csr", ext);
849         if (qxl->have_vga) {
850             qxl_render_cursor(qxl, ext);
851         }
852         trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
853         return true;
854     default:
855         return false;
856     }
857 }
858 
859 /* called from spice server thread context only */
860 static int interface_req_cursor_notification(QXLInstance *sin)
861 {
862     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
863     int wait = 1;
864 
865     trace_qxl_ring_cursor_req_notification(qxl->id);
866     switch (qxl->mode) {
867     case QXL_MODE_COMPAT:
868     case QXL_MODE_NATIVE:
869     case QXL_MODE_UNDEFINED:
870         SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
871         qxl_ring_set_dirty(qxl);
872         break;
873     default:
874         /* nothing */
875         break;
876     }
877     return wait;
878 }
879 
880 /* called from spice server thread context */
881 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
882 {
883     /*
884      * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
885      * use by xf86-video-qxl and is defined out in the qxl windows driver.
886      * Probably was at some earlier version that is prior to git start (2009),
887      * and is still guest trigerrable.
888      */
889     fprintf(stderr, "%s: deprecated\n", __func__);
890 }
891 
892 /* called from spice server thread context only */
893 static int interface_flush_resources(QXLInstance *sin)
894 {
895     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
896     int ret;
897 
898     ret = qxl->num_free_res;
899     if (ret) {
900         qxl_push_free_res(qxl, 1);
901     }
902     return ret;
903 }
904 
905 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
906 
907 /* called from spice server thread context only */
908 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
909 {
910     uint32_t current_async;
911 
912     qemu_mutex_lock(&qxl->async_lock);
913     current_async = qxl->current_async;
914     qxl->current_async = QXL_UNDEFINED_IO;
915     qemu_mutex_unlock(&qxl->async_lock);
916 
917     trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
918     if (!cookie) {
919         fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
920         return;
921     }
922     if (cookie && current_async != cookie->io) {
923         fprintf(stderr,
924                 "qxl: %s: error: current_async = %d != %"
925                 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
926     }
927     switch (current_async) {
928     case QXL_IO_MEMSLOT_ADD_ASYNC:
929     case QXL_IO_DESTROY_PRIMARY_ASYNC:
930     case QXL_IO_UPDATE_AREA_ASYNC:
931     case QXL_IO_FLUSH_SURFACES_ASYNC:
932     case QXL_IO_MONITORS_CONFIG_ASYNC:
933         break;
934     case QXL_IO_CREATE_PRIMARY_ASYNC:
935         qxl_create_guest_primary_complete(qxl);
936         break;
937     case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
938         qxl_spice_destroy_surfaces_complete(qxl);
939         break;
940     case QXL_IO_DESTROY_SURFACE_ASYNC:
941         qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
942         break;
943     default:
944         fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
945                 current_async);
946     }
947     qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
948 }
949 
950 /* called from spice server thread context only */
951 static void interface_update_area_complete(QXLInstance *sin,
952         uint32_t surface_id,
953         QXLRect *dirty, uint32_t num_updated_rects)
954 {
955     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
956     int i;
957     int qxl_i;
958 
959     qemu_mutex_lock(&qxl->ssd.lock);
960     if (surface_id != 0 || !num_updated_rects ||
961         !qxl->render_update_cookie_num) {
962         qemu_mutex_unlock(&qxl->ssd.lock);
963         return;
964     }
965     trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
966             dirty->right, dirty->top, dirty->bottom);
967     trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
968     if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
969         /*
970          * overflow - treat this as a full update. Not expected to be common.
971          */
972         trace_qxl_interface_update_area_complete_overflow(qxl->id,
973                                                           QXL_NUM_DIRTY_RECTS);
974         qxl->guest_primary.resized = 1;
975     }
976     if (qxl->guest_primary.resized) {
977         /*
978          * Don't bother copying or scheduling the bh since we will flip
979          * the whole area anyway on completion of the update_area async call
980          */
981         qemu_mutex_unlock(&qxl->ssd.lock);
982         return;
983     }
984     qxl_i = qxl->num_dirty_rects;
985     for (i = 0; i < num_updated_rects; i++) {
986         qxl->dirty[qxl_i++] = dirty[i];
987     }
988     qxl->num_dirty_rects += num_updated_rects;
989     trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
990                                                          qxl->num_dirty_rects);
991     qemu_bh_schedule(qxl->update_area_bh);
992     qemu_mutex_unlock(&qxl->ssd.lock);
993 }
994 
995 /* called from spice server thread context only */
996 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
997 {
998     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
999     QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
1000 
1001     switch (cookie->type) {
1002     case QXL_COOKIE_TYPE_IO:
1003         interface_async_complete_io(qxl, cookie);
1004         g_free(cookie);
1005         break;
1006     case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
1007         qxl_render_update_area_done(qxl, cookie);
1008         break;
1009     case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
1010         break;
1011     default:
1012         fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
1013                 __func__, cookie->type);
1014         g_free(cookie);
1015     }
1016 }
1017 
1018 /* called from spice server thread context only */
1019 static void interface_set_client_capabilities(QXLInstance *sin,
1020                                               uint8_t client_present,
1021                                               uint8_t caps[58])
1022 {
1023     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1024 
1025     if (qxl->revision < 4) {
1026         trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1027                                                               qxl->revision);
1028         return;
1029     }
1030 
1031     if (runstate_check(RUN_STATE_INMIGRATE) ||
1032         runstate_check(RUN_STATE_POSTMIGRATE)) {
1033         return;
1034     }
1035 
1036     qxl->shadow_rom.client_present = client_present;
1037     memcpy(qxl->shadow_rom.client_capabilities, caps,
1038            sizeof(qxl->shadow_rom.client_capabilities));
1039     qxl->rom->client_present = client_present;
1040     memcpy(qxl->rom->client_capabilities, caps,
1041            sizeof(qxl->rom->client_capabilities));
1042     qxl_rom_set_dirty(qxl);
1043 
1044     qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1045 }
1046 
1047 static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1048         VDAgentMonitorsConfig *monitors_config,
1049         unsigned int max_outputs)
1050 {
1051     int i;
1052     unsigned int monitors_count;
1053 
1054     monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1055 
1056     if (rom->client_monitors_config.count != monitors_count) {
1057         return true;
1058     }
1059 
1060     for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1061         VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1062         QXLURect *rect = &rom->client_monitors_config.heads[i];
1063         /* monitor->depth ignored */
1064         if ((rect->left != monitor->x) ||
1065             (rect->top != monitor->y)  ||
1066             (rect->right != monitor->x + monitor->width) ||
1067             (rect->bottom != monitor->y + monitor->height)) {
1068             return true;
1069         }
1070     }
1071 
1072     return false;
1073 }
1074 
1075 /* called from main context only */
1076 static int interface_client_monitors_config(QXLInstance *sin,
1077                                         VDAgentMonitorsConfig *monitors_config)
1078 {
1079     PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1080     QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1081     int i;
1082     unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
1083     bool config_changed = false;
1084 
1085     if (qxl->revision < 4) {
1086         trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1087                                                                qxl->revision);
1088         return 0;
1089     }
1090     /*
1091      * Older windows drivers set int_mask to 0 when their ISR is called,
1092      * then later set it to ~0. So it doesn't relate to the actual interrupts
1093      * handled. However, they are old, so clearly they don't support this
1094      * interrupt
1095      */
1096     if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1097         !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1098         trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1099                                                             qxl->ram->int_mask,
1100                                                             monitors_config);
1101         return 0;
1102     }
1103     if (!monitors_config) {
1104         return 1;
1105     }
1106 
1107 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1108     /* limit number of outputs based on setting limit */
1109     if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1110         max_outputs = qxl->max_outputs;
1111     }
1112 #endif
1113 
1114     config_changed = qxl_rom_monitors_config_changed(rom,
1115                                                      monitors_config,
1116                                                      max_outputs);
1117 
1118     memset(&rom->client_monitors_config, 0,
1119            sizeof(rom->client_monitors_config));
1120     rom->client_monitors_config.count = monitors_config->num_of_monitors;
1121     /* monitors_config->flags ignored */
1122     if (rom->client_monitors_config.count >= max_outputs) {
1123         trace_qxl_client_monitors_config_capped(qxl->id,
1124                                 monitors_config->num_of_monitors,
1125                                 max_outputs);
1126         rom->client_monitors_config.count = max_outputs;
1127     }
1128     for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1129         VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1130         QXLURect *rect = &rom->client_monitors_config.heads[i];
1131         /* monitor->depth ignored */
1132         rect->left = monitor->x;
1133         rect->top = monitor->y;
1134         rect->right = monitor->x + monitor->width;
1135         rect->bottom = monitor->y + monitor->height;
1136     }
1137     rom->client_monitors_config_crc = qxl_crc32(
1138             (const uint8_t *)&rom->client_monitors_config,
1139             sizeof(rom->client_monitors_config));
1140     trace_qxl_client_monitors_config_crc(qxl->id,
1141             sizeof(rom->client_monitors_config),
1142             rom->client_monitors_config_crc);
1143 
1144     trace_qxl_interrupt_client_monitors_config(qxl->id,
1145                         rom->client_monitors_config.count,
1146                         rom->client_monitors_config.heads);
1147     if (config_changed) {
1148         qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1149     }
1150     return 1;
1151 }
1152 
1153 static const QXLInterface qxl_interface = {
1154     .base.type               = SPICE_INTERFACE_QXL,
1155     .base.description        = "qxl gpu",
1156     .base.major_version      = SPICE_INTERFACE_QXL_MAJOR,
1157     .base.minor_version      = SPICE_INTERFACE_QXL_MINOR,
1158 
1159     .attache_worker          = interface_attach_worker,
1160     .set_compression_level   = interface_set_compression_level,
1161 #if SPICE_NEEDS_SET_MM_TIME
1162     .set_mm_time             = interface_set_mm_time,
1163 #endif
1164     .get_init_info           = interface_get_init_info,
1165 
1166     /* the callbacks below are called from spice server thread context */
1167     .get_command             = interface_get_command,
1168     .req_cmd_notification    = interface_req_cmd_notification,
1169     .release_resource        = interface_release_resource,
1170     .get_cursor_command      = interface_get_cursor_command,
1171     .req_cursor_notification = interface_req_cursor_notification,
1172     .notify_update           = interface_notify_update,
1173     .flush_resources         = interface_flush_resources,
1174     .async_complete          = interface_async_complete,
1175     .update_area_complete    = interface_update_area_complete,
1176     .set_client_capabilities = interface_set_client_capabilities,
1177     .client_monitors_config = interface_client_monitors_config,
1178 };
1179 
1180 static const GraphicHwOps qxl_ops = {
1181     .gfx_update  = qxl_hw_update,
1182 };
1183 
1184 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1185 {
1186     if (d->mode == QXL_MODE_VGA) {
1187         return;
1188     }
1189     trace_qxl_enter_vga_mode(d->id);
1190     spice_qxl_driver_unload(&d->ssd.qxl);
1191     graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1192     update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
1193     qemu_spice_create_host_primary(&d->ssd);
1194     d->mode = QXL_MODE_VGA;
1195     qemu_spice_display_switch(&d->ssd, d->ssd.ds);
1196     vga_dirty_log_start(&d->vga);
1197     graphic_hw_update(d->vga.con);
1198 }
1199 
1200 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1201 {
1202     if (d->mode != QXL_MODE_VGA) {
1203         return;
1204     }
1205     trace_qxl_exit_vga_mode(d->id);
1206     graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1207     update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
1208     vga_dirty_log_stop(&d->vga);
1209     qxl_destroy_primary(d, QXL_SYNC);
1210 }
1211 
1212 static void qxl_update_irq(PCIQXLDevice *d)
1213 {
1214     uint32_t pending = le32_to_cpu(d->ram->int_pending);
1215     uint32_t mask    = le32_to_cpu(d->ram->int_mask);
1216     int level = !!(pending & mask);
1217     pci_set_irq(&d->pci, level);
1218     qxl_ring_set_dirty(d);
1219 }
1220 
1221 static void qxl_check_state(PCIQXLDevice *d)
1222 {
1223     QXLRam *ram = d->ram;
1224     int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1225 
1226     assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1227     assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1228 }
1229 
1230 static void qxl_reset_state(PCIQXLDevice *d)
1231 {
1232     QXLRom *rom = d->rom;
1233 
1234     qxl_check_state(d);
1235     d->shadow_rom.update_id = cpu_to_le32(0);
1236     *rom = d->shadow_rom;
1237     qxl_rom_set_dirty(d);
1238     init_qxl_ram(d);
1239     d->num_free_res = 0;
1240     d->last_release = NULL;
1241     memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1242     qxl_update_irq(d);
1243 }
1244 
1245 static void qxl_soft_reset(PCIQXLDevice *d)
1246 {
1247     trace_qxl_soft_reset(d->id);
1248     qxl_check_state(d);
1249     qxl_clear_guest_bug(d);
1250     qemu_mutex_lock(&d->async_lock);
1251     d->current_async = QXL_UNDEFINED_IO;
1252     qemu_mutex_unlock(&d->async_lock);
1253 
1254     if (d->have_vga) {
1255         qxl_enter_vga_mode(d);
1256     } else {
1257         d->mode = QXL_MODE_UNDEFINED;
1258     }
1259 }
1260 
1261 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1262 {
1263     bool startstop = qemu_spice_display_is_running(&d->ssd);
1264 
1265     trace_qxl_hard_reset(d->id, loadvm);
1266 
1267     if (startstop) {
1268         qemu_spice_display_stop();
1269     }
1270 
1271     qxl_spice_reset_cursor(d);
1272     qxl_spice_reset_image_cache(d);
1273     qxl_reset_surfaces(d);
1274     qxl_reset_memslots(d);
1275 
1276     /* pre loadvm reset must not touch QXLRam.  This lives in
1277      * device memory, is migrated together with RAM and thus
1278      * already loaded at this point */
1279     if (!loadvm) {
1280         qxl_reset_state(d);
1281     }
1282     qemu_spice_create_host_memslot(&d->ssd);
1283     qxl_soft_reset(d);
1284 
1285     if (d->migration_blocker) {
1286         migrate_del_blocker(d->migration_blocker);
1287         error_free(d->migration_blocker);
1288         d->migration_blocker = NULL;
1289     }
1290 
1291     if (startstop) {
1292         qemu_spice_display_start();
1293     }
1294 }
1295 
1296 static void qxl_reset_handler(DeviceState *dev)
1297 {
1298     PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
1299 
1300     qxl_hard_reset(d, 0);
1301 }
1302 
1303 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1304 {
1305     VGACommonState *vga = opaque;
1306     PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1307 
1308     trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1309     if (qxl->mode != QXL_MODE_VGA) {
1310         qxl_destroy_primary(qxl, QXL_SYNC);
1311         qxl_soft_reset(qxl);
1312     }
1313     vga_ioport_write(opaque, addr, val);
1314 }
1315 
1316 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1317     { 0x04,  2, 1, .read  = vga_ioport_read,
1318                    .write = qxl_vga_ioport_write }, /* 3b4 */
1319     { 0x0a,  1, 1, .read  = vga_ioport_read,
1320                    .write = qxl_vga_ioport_write }, /* 3ba */
1321     { 0x10, 16, 1, .read  = vga_ioport_read,
1322                    .write = qxl_vga_ioport_write }, /* 3c0 */
1323     { 0x24,  2, 1, .read  = vga_ioport_read,
1324                    .write = qxl_vga_ioport_write }, /* 3d4 */
1325     { 0x2a,  1, 1, .read  = vga_ioport_read,
1326                    .write = qxl_vga_ioport_write }, /* 3da */
1327     PORTIO_END_OF_LIST(),
1328 };
1329 
1330 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1331                            qxl_async_io async)
1332 {
1333     static const int regions[] = {
1334         QXL_RAM_RANGE_INDEX,
1335         QXL_VRAM_RANGE_INDEX,
1336         QXL_VRAM64_RANGE_INDEX,
1337     };
1338     uint64_t guest_start;
1339     uint64_t guest_end;
1340     int pci_region;
1341     pcibus_t pci_start;
1342     pcibus_t pci_end;
1343     MemoryRegion *mr;
1344     intptr_t virt_start;
1345     QXLDevMemSlot memslot;
1346     int i;
1347 
1348     guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1349     guest_end   = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1350 
1351     trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1352 
1353     if (slot_id >= NUM_MEMSLOTS) {
1354         qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1355                       slot_id, NUM_MEMSLOTS);
1356         return 1;
1357     }
1358     if (guest_start > guest_end) {
1359         qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1360                          " > 0x%" PRIx64, __func__, guest_start, guest_end);
1361         return 1;
1362     }
1363 
1364     for (i = 0; i < ARRAY_SIZE(regions); i++) {
1365         pci_region = regions[i];
1366         pci_start = d->pci.io_regions[pci_region].addr;
1367         pci_end = pci_start + d->pci.io_regions[pci_region].size;
1368         /* mapped? */
1369         if (pci_start == -1) {
1370             continue;
1371         }
1372         /* start address in range ? */
1373         if (guest_start < pci_start || guest_start > pci_end) {
1374             continue;
1375         }
1376         /* end address in range ? */
1377         if (guest_end > pci_end) {
1378             continue;
1379         }
1380         /* passed */
1381         break;
1382     }
1383     if (i == ARRAY_SIZE(regions)) {
1384         qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1385         return 1;
1386     }
1387 
1388     switch (pci_region) {
1389     case QXL_RAM_RANGE_INDEX:
1390         mr = &d->vga.vram;
1391         break;
1392     case QXL_VRAM_RANGE_INDEX:
1393     case 4 /* vram 64bit */:
1394         mr = &d->vram_bar;
1395         break;
1396     default:
1397         /* should not happen */
1398         qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1399         return 1;
1400     }
1401 
1402     virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
1403     memslot.slot_id = slot_id;
1404     memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1405     memslot.virt_start = virt_start + (guest_start - pci_start);
1406     memslot.virt_end   = virt_start + (guest_end   - pci_start);
1407     memslot.addr_delta = memslot.virt_start - delta;
1408     memslot.generation = d->rom->slot_generation = 0;
1409     qxl_rom_set_dirty(d);
1410 
1411     qemu_spice_add_memslot(&d->ssd, &memslot, async);
1412     d->guest_slots[slot_id].mr = mr;
1413     d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
1414     d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1415     d->guest_slots[slot_id].delta = delta;
1416     d->guest_slots[slot_id].active = 1;
1417     return 0;
1418 }
1419 
1420 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1421 {
1422     qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1423     d->guest_slots[slot_id].active = 0;
1424 }
1425 
1426 static void qxl_reset_memslots(PCIQXLDevice *d)
1427 {
1428     qxl_spice_reset_memslots(d);
1429     memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1430 }
1431 
1432 static void qxl_reset_surfaces(PCIQXLDevice *d)
1433 {
1434     trace_qxl_reset_surfaces(d->id);
1435     d->mode = QXL_MODE_UNDEFINED;
1436     qxl_spice_destroy_surfaces(d, QXL_SYNC);
1437 }
1438 
1439 /* can be also called from spice server thread context */
1440 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1441                                       uint32_t *s, uint64_t *o)
1442 {
1443     uint64_t phys   = le64_to_cpu(pqxl);
1444     uint32_t slot   = (phys >> (64 -  8)) & 0xff;
1445     uint64_t offset = phys & 0xffffffffffff;
1446 
1447     if (slot >= NUM_MEMSLOTS) {
1448         qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1449                           NUM_MEMSLOTS);
1450         return false;
1451     }
1452     if (!qxl->guest_slots[slot].active) {
1453         qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1454         return false;
1455     }
1456     if (offset < qxl->guest_slots[slot].delta) {
1457         qxl_set_guest_bug(qxl,
1458                           "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1459                           slot, offset, qxl->guest_slots[slot].delta);
1460         return false;
1461     }
1462     offset -= qxl->guest_slots[slot].delta;
1463     if (offset > qxl->guest_slots[slot].size) {
1464         qxl_set_guest_bug(qxl,
1465                           "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1466                           slot, offset, qxl->guest_slots[slot].size);
1467         return false;
1468     }
1469 
1470     *s = slot;
1471     *o = offset;
1472     return true;
1473 }
1474 
1475 /* can be also called from spice server thread context */
1476 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1477 {
1478     uint64_t offset;
1479     uint32_t slot;
1480     void *ptr;
1481 
1482     switch (group_id) {
1483     case MEMSLOT_GROUP_HOST:
1484         offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1485         return (void *)(intptr_t)offset;
1486     case MEMSLOT_GROUP_GUEST:
1487         if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
1488             return NULL;
1489         }
1490         ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1491         ptr += qxl->guest_slots[slot].offset;
1492         ptr += offset;
1493         return ptr;
1494     }
1495     return NULL;
1496 }
1497 
1498 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1499 {
1500     /* for local rendering */
1501     qxl_render_resize(qxl);
1502 }
1503 
1504 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1505                                      qxl_async_io async)
1506 {
1507     QXLDevSurfaceCreate surface;
1508     QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1509     uint32_t requested_height = le32_to_cpu(sc->height);
1510     int requested_stride = le32_to_cpu(sc->stride);
1511 
1512     if (requested_stride == INT32_MIN ||
1513         abs(requested_stride) * (uint64_t)requested_height
1514                                         > qxl->vgamem_size) {
1515         qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1516                                " stride %d x height %" PRIu32 " > %" PRIu32,
1517                                __func__, requested_stride, requested_height,
1518                                qxl->vgamem_size);
1519         return;
1520     }
1521 
1522     if (qxl->mode == QXL_MODE_NATIVE) {
1523         qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1524                       __func__);
1525     }
1526     qxl_exit_vga_mode(qxl);
1527 
1528     surface.format     = le32_to_cpu(sc->format);
1529     surface.height     = le32_to_cpu(sc->height);
1530     surface.mem        = le64_to_cpu(sc->mem);
1531     surface.position   = le32_to_cpu(sc->position);
1532     surface.stride     = le32_to_cpu(sc->stride);
1533     surface.width      = le32_to_cpu(sc->width);
1534     surface.type       = le32_to_cpu(sc->type);
1535     surface.flags      = le32_to_cpu(sc->flags);
1536     trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1537                                    sc->format, sc->position);
1538     trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1539                                         sc->flags);
1540 
1541     if ((surface.stride & 0x3) != 0) {
1542         qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1543                           surface.stride);
1544         return;
1545     }
1546 
1547     surface.mouse_mode = true;
1548     surface.group_id   = MEMSLOT_GROUP_GUEST;
1549     if (loadvm) {
1550         surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1551     }
1552 
1553     qxl->mode = QXL_MODE_NATIVE;
1554     qxl->cmdflags = 0;
1555     qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1556 
1557     if (async == QXL_SYNC) {
1558         qxl_create_guest_primary_complete(qxl);
1559     }
1560 }
1561 
1562 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1563  * done (in QXL_SYNC case), 0 otherwise. */
1564 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1565 {
1566     if (d->mode == QXL_MODE_UNDEFINED) {
1567         return 0;
1568     }
1569     trace_qxl_destroy_primary(d->id);
1570     d->mode = QXL_MODE_UNDEFINED;
1571     qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1572     qxl_spice_reset_cursor(d);
1573     return 1;
1574 }
1575 
1576 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1577 {
1578     pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1579     pcibus_t end   = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1580     QXLMode *mode = d->modes->modes + modenr;
1581     uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1582     QXLMemSlot slot = {
1583         .mem_start = start,
1584         .mem_end = end
1585     };
1586 
1587     if (modenr >= d->modes->n_modes) {
1588         qxl_set_guest_bug(d, "mode number out of range");
1589         return;
1590     }
1591 
1592     QXLSurfaceCreate surface = {
1593         .width      = mode->x_res,
1594         .height     = mode->y_res,
1595         .stride     = -mode->x_res * 4,
1596         .format     = SPICE_SURFACE_FMT_32_xRGB,
1597         .flags      = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1598         .mouse_mode = true,
1599         .mem        = devmem + d->shadow_rom.draw_area_offset,
1600     };
1601 
1602     trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1603                        devmem);
1604     if (!loadvm) {
1605         qxl_hard_reset(d, 0);
1606     }
1607 
1608     d->guest_slots[0].slot = slot;
1609     assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1610 
1611     d->guest_primary.surface = surface;
1612     qxl_create_guest_primary(d, 0, QXL_SYNC);
1613 
1614     d->mode = QXL_MODE_COMPAT;
1615     d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1616     if (mode->bits == 16) {
1617         d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1618     }
1619     d->shadow_rom.mode = cpu_to_le32(modenr);
1620     d->rom->mode = cpu_to_le32(modenr);
1621     qxl_rom_set_dirty(d);
1622 }
1623 
1624 static void ioport_write(void *opaque, hwaddr addr,
1625                          uint64_t val, unsigned size)
1626 {
1627     PCIQXLDevice *d = opaque;
1628     uint32_t io_port = addr;
1629     qxl_async_io async = QXL_SYNC;
1630     uint32_t orig_io_port = io_port;
1631 
1632     if (d->guest_bug && io_port != QXL_IO_RESET) {
1633         return;
1634     }
1635 
1636     if (d->revision <= QXL_REVISION_STABLE_V10 &&
1637         io_port > QXL_IO_FLUSH_RELEASE) {
1638         qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1639             io_port, d->revision);
1640         return;
1641     }
1642 
1643     switch (io_port) {
1644     case QXL_IO_RESET:
1645     case QXL_IO_SET_MODE:
1646     case QXL_IO_MEMSLOT_ADD:
1647     case QXL_IO_MEMSLOT_DEL:
1648     case QXL_IO_CREATE_PRIMARY:
1649     case QXL_IO_UPDATE_IRQ:
1650     case QXL_IO_LOG:
1651     case QXL_IO_MEMSLOT_ADD_ASYNC:
1652     case QXL_IO_CREATE_PRIMARY_ASYNC:
1653         break;
1654     default:
1655         if (d->mode != QXL_MODE_VGA) {
1656             break;
1657         }
1658         trace_qxl_io_unexpected_vga_mode(d->id,
1659             addr, val, io_port_to_string(io_port));
1660         /* be nice to buggy guest drivers */
1661         if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1662             io_port < QXL_IO_RANGE_SIZE) {
1663             qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1664         }
1665         return;
1666     }
1667 
1668     /* we change the io_port to avoid ifdeffery in the main switch */
1669     orig_io_port = io_port;
1670     switch (io_port) {
1671     case QXL_IO_UPDATE_AREA_ASYNC:
1672         io_port = QXL_IO_UPDATE_AREA;
1673         goto async_common;
1674     case QXL_IO_MEMSLOT_ADD_ASYNC:
1675         io_port = QXL_IO_MEMSLOT_ADD;
1676         goto async_common;
1677     case QXL_IO_CREATE_PRIMARY_ASYNC:
1678         io_port = QXL_IO_CREATE_PRIMARY;
1679         goto async_common;
1680     case QXL_IO_DESTROY_PRIMARY_ASYNC:
1681         io_port = QXL_IO_DESTROY_PRIMARY;
1682         goto async_common;
1683     case QXL_IO_DESTROY_SURFACE_ASYNC:
1684         io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1685         goto async_common;
1686     case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1687         io_port = QXL_IO_DESTROY_ALL_SURFACES;
1688         goto async_common;
1689     case QXL_IO_FLUSH_SURFACES_ASYNC:
1690     case QXL_IO_MONITORS_CONFIG_ASYNC:
1691 async_common:
1692         async = QXL_ASYNC;
1693         qemu_mutex_lock(&d->async_lock);
1694         if (d->current_async != QXL_UNDEFINED_IO) {
1695             qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1696                 io_port, d->current_async);
1697             qemu_mutex_unlock(&d->async_lock);
1698             return;
1699         }
1700         d->current_async = orig_io_port;
1701         qemu_mutex_unlock(&d->async_lock);
1702         break;
1703     default:
1704         break;
1705     }
1706     trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1707                        addr, io_port_to_string(addr),
1708                        val, size, async);
1709 
1710     switch (io_port) {
1711     case QXL_IO_UPDATE_AREA:
1712     {
1713         QXLCookie *cookie = NULL;
1714         QXLRect update = d->ram->update_area;
1715 
1716         if (d->ram->update_surface > d->ssd.num_surfaces) {
1717             qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1718                               d->ram->update_surface);
1719             break;
1720         }
1721         if (update.left >= update.right || update.top >= update.bottom ||
1722             update.left < 0 || update.top < 0) {
1723             qxl_set_guest_bug(d,
1724                     "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1725                     update.left, update.top, update.right, update.bottom);
1726             if (update.left == update.right || update.top == update.bottom) {
1727                 /* old drivers may provide empty area, keep going */
1728                 qxl_clear_guest_bug(d);
1729                 goto cancel_async;
1730             }
1731             break;
1732         }
1733         if (async == QXL_ASYNC) {
1734             cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1735                                     QXL_IO_UPDATE_AREA_ASYNC);
1736             cookie->u.area = update;
1737         }
1738         qxl_spice_update_area(d, d->ram->update_surface,
1739                               cookie ? &cookie->u.area : &update,
1740                               NULL, 0, 0, async, cookie);
1741         break;
1742     }
1743     case QXL_IO_NOTIFY_CMD:
1744         qemu_spice_wakeup(&d->ssd);
1745         break;
1746     case QXL_IO_NOTIFY_CURSOR:
1747         qemu_spice_wakeup(&d->ssd);
1748         break;
1749     case QXL_IO_UPDATE_IRQ:
1750         qxl_update_irq(d);
1751         break;
1752     case QXL_IO_NOTIFY_OOM:
1753         if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1754             break;
1755         }
1756         d->oom_running = 1;
1757         qxl_spice_oom(d);
1758         d->oom_running = 0;
1759         break;
1760     case QXL_IO_SET_MODE:
1761         qxl_set_mode(d, val, 0);
1762         break;
1763     case QXL_IO_LOG:
1764         if (TRACE_QXL_IO_LOG_ENABLED || d->guestdebug) {
1765             /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1766             char *log_buf = g_strndup((const char *)d->ram->log_buf,
1767                                       sizeof(d->ram->log_buf));
1768             trace_qxl_io_log(d->id, log_buf);
1769             if (d->guestdebug) {
1770                 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1771                         qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1772             }
1773             g_free(log_buf);
1774         }
1775         break;
1776     case QXL_IO_RESET:
1777         qxl_hard_reset(d, 0);
1778         break;
1779     case QXL_IO_MEMSLOT_ADD:
1780         if (val >= NUM_MEMSLOTS) {
1781             qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1782             break;
1783         }
1784         if (d->guest_slots[val].active) {
1785             qxl_set_guest_bug(d,
1786                         "QXL_IO_MEMSLOT_ADD: memory slot already active");
1787             break;
1788         }
1789         d->guest_slots[val].slot = d->ram->mem_slot;
1790         qxl_add_memslot(d, val, 0, async);
1791         break;
1792     case QXL_IO_MEMSLOT_DEL:
1793         if (val >= NUM_MEMSLOTS) {
1794             qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1795             break;
1796         }
1797         qxl_del_memslot(d, val);
1798         break;
1799     case QXL_IO_CREATE_PRIMARY:
1800         if (val != 0) {
1801             qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1802                           async);
1803             goto cancel_async;
1804         }
1805         d->guest_primary.surface = d->ram->create_surface;
1806         qxl_create_guest_primary(d, 0, async);
1807         break;
1808     case QXL_IO_DESTROY_PRIMARY:
1809         if (val != 0) {
1810             qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1811                           async);
1812             goto cancel_async;
1813         }
1814         if (!qxl_destroy_primary(d, async)) {
1815             trace_qxl_io_destroy_primary_ignored(d->id,
1816                                                  qxl_mode_to_string(d->mode));
1817             goto cancel_async;
1818         }
1819         break;
1820     case QXL_IO_DESTROY_SURFACE_WAIT:
1821         if (val >= d->ssd.num_surfaces) {
1822             qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1823                              "%" PRIu64 " >= NUM_SURFACES", async, val);
1824             goto cancel_async;
1825         }
1826         qxl_spice_destroy_surface_wait(d, val, async);
1827         break;
1828     case QXL_IO_FLUSH_RELEASE: {
1829         QXLReleaseRing *ring = &d->ram->release_ring;
1830         if (ring->prod - ring->cons + 1 == ring->num_items) {
1831             fprintf(stderr,
1832                 "ERROR: no flush, full release ring [p%d,%dc]\n",
1833                 ring->prod, ring->cons);
1834         }
1835         qxl_push_free_res(d, 1 /* flush */);
1836         break;
1837     }
1838     case QXL_IO_FLUSH_SURFACES_ASYNC:
1839         qxl_spice_flush_surfaces_async(d);
1840         break;
1841     case QXL_IO_DESTROY_ALL_SURFACES:
1842         d->mode = QXL_MODE_UNDEFINED;
1843         qxl_spice_destroy_surfaces(d, async);
1844         break;
1845     case QXL_IO_MONITORS_CONFIG_ASYNC:
1846         qxl_spice_monitors_config_async(d, 0);
1847         break;
1848     default:
1849         qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1850     }
1851     return;
1852 cancel_async:
1853     if (async) {
1854         qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1855         qemu_mutex_lock(&d->async_lock);
1856         d->current_async = QXL_UNDEFINED_IO;
1857         qemu_mutex_unlock(&d->async_lock);
1858     }
1859 }
1860 
1861 static uint64_t ioport_read(void *opaque, hwaddr addr,
1862                             unsigned size)
1863 {
1864     PCIQXLDevice *qxl = opaque;
1865 
1866     trace_qxl_io_read_unexpected(qxl->id);
1867     return 0xff;
1868 }
1869 
1870 static const MemoryRegionOps qxl_io_ops = {
1871     .read = ioport_read,
1872     .write = ioport_write,
1873     .valid = {
1874         .min_access_size = 1,
1875         .max_access_size = 1,
1876     },
1877 };
1878 
1879 static void qxl_update_irq_bh(void *opaque)
1880 {
1881     PCIQXLDevice *d = opaque;
1882     qxl_update_irq(d);
1883 }
1884 
1885 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1886 {
1887     uint32_t old_pending;
1888     uint32_t le_events = cpu_to_le32(events);
1889 
1890     trace_qxl_send_events(d->id, events);
1891     if (!qemu_spice_display_is_running(&d->ssd)) {
1892         /* spice-server tracks guest running state and should not do this */
1893         fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1894                 __func__);
1895         trace_qxl_send_events_vm_stopped(d->id, events);
1896         return;
1897     }
1898     /*
1899      * Older versions of Spice forgot to define the QXLRam struct
1900      * with the '__aligned__(4)' attribute. clang 7 and newer will
1901      * thus warn that atomic_fetch_or(&d->ram->int_pending, ...)
1902      * might be a misaligned atomic access, and will generate an
1903      * out-of-line call for it, which results in a link error since
1904      * we don't currently link against libatomic.
1905      *
1906      * In fact we set up d->ram in init_qxl_ram() so it always starts
1907      * at a 4K boundary, so we know that &d->ram->int_pending is
1908      * naturally aligned for a uint32_t. Newer Spice versions
1909      * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1910      * will fix the bug directly. To deal with older versions,
1911      * we tell the compiler to assume the address really is aligned.
1912      * Any compiler which cares about the misalignment will have
1913      * __builtin_assume_aligned.
1914      */
1915 #ifdef HAS_ASSUME_ALIGNED
1916 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1917 #else
1918 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1919 #endif
1920 
1921     old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1922                                   le_events);
1923     if ((old_pending & le_events) == le_events) {
1924         return;
1925     }
1926     qemu_bh_schedule(d->update_irq);
1927 }
1928 
1929 /* graphics console */
1930 
1931 static void qxl_hw_update(void *opaque)
1932 {
1933     PCIQXLDevice *qxl = opaque;
1934 
1935     qxl_render_update(qxl);
1936 }
1937 
1938 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1939                                   uint32_t height, int32_t stride)
1940 {
1941     uint64_t offset, size;
1942     uint32_t slot;
1943     bool rc;
1944 
1945     rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1946     assert(rc == true);
1947     size = (uint64_t)height * abs(stride);
1948     trace_qxl_surfaces_dirty(qxl->id, offset, size);
1949     qxl_set_dirty(qxl->guest_slots[slot].mr,
1950                   qxl->guest_slots[slot].offset + offset,
1951                   qxl->guest_slots[slot].offset + offset + size);
1952 }
1953 
1954 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1955 {
1956     int i;
1957 
1958     if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1959         return;
1960     }
1961 
1962     /* dirty the primary surface */
1963     qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1964                           qxl->guest_primary.surface.height,
1965                           qxl->guest_primary.surface.stride);
1966 
1967     /* dirty the off-screen surfaces */
1968     for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1969         QXLSurfaceCmd *cmd;
1970 
1971         if (qxl->guest_surfaces.cmds[i] == 0) {
1972             continue;
1973         }
1974 
1975         cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1976                             MEMSLOT_GROUP_GUEST);
1977         assert(cmd);
1978         assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1979         qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1980                               cmd->u.surface_create.height,
1981                               cmd->u.surface_create.stride);
1982     }
1983 }
1984 
1985 static void qxl_vm_change_state_handler(void *opaque, int running,
1986                                         RunState state)
1987 {
1988     PCIQXLDevice *qxl = opaque;
1989 
1990     if (running) {
1991         /*
1992          * if qxl_send_events was called from spice server context before
1993          * migration ended, qxl_update_irq for these events might not have been
1994          * called
1995          */
1996          qxl_update_irq(qxl);
1997     } else {
1998         /* make sure surfaces are saved before migration */
1999         qxl_dirty_surfaces(qxl);
2000     }
2001 }
2002 
2003 /* display change listener */
2004 
2005 static void display_update(DisplayChangeListener *dcl,
2006                            int x, int y, int w, int h)
2007 {
2008     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2009 
2010     if (qxl->mode == QXL_MODE_VGA) {
2011         qemu_spice_display_update(&qxl->ssd, x, y, w, h);
2012     }
2013 }
2014 
2015 static void display_switch(DisplayChangeListener *dcl,
2016                            struct DisplaySurface *surface)
2017 {
2018     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2019 
2020     qxl->ssd.ds = surface;
2021     if (qxl->mode == QXL_MODE_VGA) {
2022         qemu_spice_display_switch(&qxl->ssd, surface);
2023     }
2024 }
2025 
2026 static void display_refresh(DisplayChangeListener *dcl)
2027 {
2028     PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2029 
2030     if (qxl->mode == QXL_MODE_VGA) {
2031         qemu_spice_display_refresh(&qxl->ssd);
2032     }
2033 }
2034 
2035 static DisplayChangeListenerOps display_listener_ops = {
2036     .dpy_name        = "spice/qxl",
2037     .dpy_gfx_update  = display_update,
2038     .dpy_gfx_switch  = display_switch,
2039     .dpy_refresh     = display_refresh,
2040 };
2041 
2042 static void qxl_init_ramsize(PCIQXLDevice *qxl)
2043 {
2044     /* vga mode framebuffer / primary surface (bar 0, first part) */
2045     if (qxl->vgamem_size_mb < 8) {
2046         qxl->vgamem_size_mb = 8;
2047     }
2048     /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2049      * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2050      */
2051     if (qxl->vgamem_size_mb > 256) {
2052         qxl->vgamem_size_mb = 256;
2053     }
2054     qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
2055 
2056     /* vga ram (bar 0, total) */
2057     if (qxl->ram_size_mb != -1) {
2058         qxl->vga.vram_size = qxl->ram_size_mb * MiB;
2059     }
2060     if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2061         qxl->vga.vram_size = qxl->vgamem_size * 2;
2062     }
2063 
2064     /* vram32 (surfaces, 32bit, bar 1) */
2065     if (qxl->vram32_size_mb != -1) {
2066         qxl->vram32_size = qxl->vram32_size_mb * MiB;
2067     }
2068     if (qxl->vram32_size < 4096) {
2069         qxl->vram32_size = 4096;
2070     }
2071 
2072     /* vram (surfaces, 64bit, bar 4+5) */
2073     if (qxl->vram_size_mb != -1) {
2074         qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
2075     }
2076     if (qxl->vram_size < qxl->vram32_size) {
2077         qxl->vram_size = qxl->vram32_size;
2078     }
2079 
2080     if (qxl->revision == 1) {
2081         qxl->vram32_size = 4096;
2082         qxl->vram_size = 4096;
2083     }
2084     qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2085     qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2086     qxl->vram32_size = pow2ceil(qxl->vram32_size);
2087     qxl->vram_size = pow2ceil(qxl->vram_size);
2088 }
2089 
2090 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
2091 {
2092     uint8_t* config = qxl->pci.config;
2093     uint32_t pci_device_rev;
2094     uint32_t io_size;
2095 
2096     qemu_spice_display_init_common(&qxl->ssd);
2097     qxl->mode = QXL_MODE_UNDEFINED;
2098     qxl->num_memslots = NUM_MEMSLOTS;
2099     qemu_mutex_init(&qxl->track_lock);
2100     qemu_mutex_init(&qxl->async_lock);
2101     qxl->current_async = QXL_UNDEFINED_IO;
2102     qxl->guest_bug = 0;
2103 
2104     switch (qxl->revision) {
2105     case 1: /* spice 0.4 -- qxl-1 */
2106         pci_device_rev = QXL_REVISION_STABLE_V04;
2107         io_size = 8;
2108         break;
2109     case 2: /* spice 0.6 -- qxl-2 */
2110         pci_device_rev = QXL_REVISION_STABLE_V06;
2111         io_size = 16;
2112         break;
2113     case 3: /* qxl-3 */
2114         pci_device_rev = QXL_REVISION_STABLE_V10;
2115         io_size = 32; /* PCI region size must be pow2 */
2116         break;
2117     case 4: /* qxl-4 */
2118         pci_device_rev = QXL_REVISION_STABLE_V12;
2119         io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2120         break;
2121     default:
2122         error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2123                    qxl->revision, QXL_DEFAULT_REVISION);
2124         return;
2125     }
2126 
2127     pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2128     pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2129 
2130     qxl->rom_size = qxl_rom_size();
2131     memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
2132                            qxl->rom_size, &error_fatal);
2133     init_qxl_rom(qxl);
2134     init_qxl_ram(qxl);
2135 
2136     qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2137     memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
2138                            qxl->vram_size, &error_fatal);
2139     memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2140                              &qxl->vram_bar, 0, qxl->vram32_size);
2141 
2142     memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
2143                           "qxl-ioports", io_size);
2144     if (qxl->have_vga) {
2145         vga_dirty_log_start(&qxl->vga);
2146     }
2147     memory_region_set_flush_coalesced(&qxl->io_bar);
2148 
2149 
2150     pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2151                      PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2152 
2153     pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2154                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2155 
2156     pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2157                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2158 
2159     pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2160                      PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2161 
2162     if (qxl->vram32_size < qxl->vram_size) {
2163         /*
2164          * Make the 64bit vram bar show up only in case it is
2165          * configured to be larger than the 32bit vram bar.
2166          */
2167         pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2168                          PCI_BASE_ADDRESS_SPACE_MEMORY |
2169                          PCI_BASE_ADDRESS_MEM_TYPE_64 |
2170                          PCI_BASE_ADDRESS_MEM_PREFETCH,
2171                          &qxl->vram_bar);
2172     }
2173 
2174     /* print pci bar details */
2175     dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
2176            qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
2177     dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2178            qxl->vram32_size / MiB);
2179     dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2180            qxl->vram_size / MiB,
2181            qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2182 
2183     qxl->ssd.qxl.base.sif = &qxl_interface.base;
2184     if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2185         error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2186                    SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2187         return;
2188     }
2189 
2190 #if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */
2191     char device_address[256] = "";
2192     if (qemu_spice_fill_device_address(qxl->vga.con, device_address, 256)) {
2193         spice_qxl_set_device_info(&qxl->ssd.qxl,
2194                                   device_address,
2195                                   0,
2196                                   qxl->max_outputs);
2197     }
2198 #endif
2199 
2200     qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2201 
2202     qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2203     qxl_reset_state(qxl);
2204 
2205     qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2206     qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
2207 }
2208 
2209 static void qxl_realize_primary(PCIDevice *dev, Error **errp)
2210 {
2211     PCIQXLDevice *qxl = PCI_QXL(dev);
2212     VGACommonState *vga = &qxl->vga;
2213     Error *local_err = NULL;
2214 
2215     qxl_init_ramsize(qxl);
2216     vga->vbe_size = qxl->vgamem_size;
2217     vga->vram_size_mb = qxl->vga.vram_size / MiB;
2218     vga_common_init(vga, OBJECT(dev));
2219     vga_init(vga, OBJECT(dev),
2220              pci_address_space(dev), pci_address_space_io(dev), false);
2221     portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2222                      vga, "vga");
2223     portio_list_set_flush_coalesced(&qxl->vga_port_list);
2224     portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2225     qxl->have_vga = true;
2226 
2227     vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2228     qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2229     if (qxl->id != 0) {
2230         error_setg(errp, "primary qxl-vga device must be console 0 "
2231                    "(first display device on the command line)");
2232         return;
2233     }
2234 
2235     qxl_realize_common(qxl, &local_err);
2236     if (local_err) {
2237         error_propagate(errp, local_err);
2238         return;
2239     }
2240 
2241     qxl->ssd.dcl.ops = &display_listener_ops;
2242     qxl->ssd.dcl.con = vga->con;
2243     register_displaychangelistener(&qxl->ssd.dcl);
2244 }
2245 
2246 static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
2247 {
2248     PCIQXLDevice *qxl = PCI_QXL(dev);
2249 
2250     qxl_init_ramsize(qxl);
2251     memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2252                            qxl->vga.vram_size, &error_fatal);
2253     qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2254     qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2255     qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
2256 
2257     qxl_realize_common(qxl, errp);
2258 }
2259 
2260 static int qxl_pre_save(void *opaque)
2261 {
2262     PCIQXLDevice* d = opaque;
2263     uint8_t *ram_start = d->vga.vram_ptr;
2264 
2265     trace_qxl_pre_save(d->id);
2266     if (d->last_release == NULL) {
2267         d->last_release_offset = 0;
2268     } else {
2269         d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2270     }
2271     assert(d->last_release_offset < d->vga.vram_size);
2272 
2273     return 0;
2274 }
2275 
2276 static int qxl_pre_load(void *opaque)
2277 {
2278     PCIQXLDevice* d = opaque;
2279 
2280     trace_qxl_pre_load(d->id);
2281     qxl_hard_reset(d, 1);
2282     qxl_exit_vga_mode(d);
2283     return 0;
2284 }
2285 
2286 static void qxl_create_memslots(PCIQXLDevice *d)
2287 {
2288     int i;
2289 
2290     for (i = 0; i < NUM_MEMSLOTS; i++) {
2291         if (!d->guest_slots[i].active) {
2292             continue;
2293         }
2294         qxl_add_memslot(d, i, 0, QXL_SYNC);
2295     }
2296 }
2297 
2298 static int qxl_post_load(void *opaque, int version)
2299 {
2300     PCIQXLDevice* d = opaque;
2301     uint8_t *ram_start = d->vga.vram_ptr;
2302     QXLCommandExt *cmds;
2303     int in, out, newmode;
2304 
2305     assert(d->last_release_offset < d->vga.vram_size);
2306     if (d->last_release_offset == 0) {
2307         d->last_release = NULL;
2308     } else {
2309         d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2310     }
2311 
2312     d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2313 
2314     trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2315     newmode = d->mode;
2316     d->mode = QXL_MODE_UNDEFINED;
2317 
2318     switch (newmode) {
2319     case QXL_MODE_UNDEFINED:
2320         qxl_create_memslots(d);
2321         break;
2322     case QXL_MODE_VGA:
2323         qxl_create_memslots(d);
2324         qxl_enter_vga_mode(d);
2325         break;
2326     case QXL_MODE_NATIVE:
2327         qxl_create_memslots(d);
2328         qxl_create_guest_primary(d, 1, QXL_SYNC);
2329 
2330         /* replay surface-create and cursor-set commands */
2331         cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
2332         for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2333             if (d->guest_surfaces.cmds[in] == 0) {
2334                 continue;
2335             }
2336             cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2337             cmds[out].cmd.type = QXL_CMD_SURFACE;
2338             cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2339             out++;
2340         }
2341         if (d->guest_cursor) {
2342             cmds[out].cmd.data = d->guest_cursor;
2343             cmds[out].cmd.type = QXL_CMD_CURSOR;
2344             cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2345             out++;
2346         }
2347         qxl_spice_loadvm_commands(d, cmds, out);
2348         g_free(cmds);
2349         if (d->guest_monitors_config) {
2350             qxl_spice_monitors_config_async(d, 1);
2351         }
2352         break;
2353     case QXL_MODE_COMPAT:
2354         /* note: no need to call qxl_create_memslots, qxl_set_mode
2355          * creates the mem slot. */
2356         qxl_set_mode(d, d->shadow_rom.mode, 1);
2357         break;
2358     }
2359     return 0;
2360 }
2361 
2362 #define QXL_SAVE_VERSION 21
2363 
2364 static bool qxl_monitors_config_needed(void *opaque)
2365 {
2366     PCIQXLDevice *qxl = opaque;
2367 
2368     return qxl->guest_monitors_config != 0;
2369 }
2370 
2371 
2372 static VMStateDescription qxl_memslot = {
2373     .name               = "qxl-memslot",
2374     .version_id         = QXL_SAVE_VERSION,
2375     .minimum_version_id = QXL_SAVE_VERSION,
2376     .fields = (VMStateField[]) {
2377         VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2378         VMSTATE_UINT64(slot.mem_end,   struct guest_slots),
2379         VMSTATE_UINT32(active,         struct guest_slots),
2380         VMSTATE_END_OF_LIST()
2381     }
2382 };
2383 
2384 static VMStateDescription qxl_surface = {
2385     .name               = "qxl-surface",
2386     .version_id         = QXL_SAVE_VERSION,
2387     .minimum_version_id = QXL_SAVE_VERSION,
2388     .fields = (VMStateField[]) {
2389         VMSTATE_UINT32(width,      QXLSurfaceCreate),
2390         VMSTATE_UINT32(height,     QXLSurfaceCreate),
2391         VMSTATE_INT32(stride,      QXLSurfaceCreate),
2392         VMSTATE_UINT32(format,     QXLSurfaceCreate),
2393         VMSTATE_UINT32(position,   QXLSurfaceCreate),
2394         VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2395         VMSTATE_UINT32(flags,      QXLSurfaceCreate),
2396         VMSTATE_UINT32(type,       QXLSurfaceCreate),
2397         VMSTATE_UINT64(mem,        QXLSurfaceCreate),
2398         VMSTATE_END_OF_LIST()
2399     }
2400 };
2401 
2402 static VMStateDescription qxl_vmstate_monitors_config = {
2403     .name               = "qxl/monitors-config",
2404     .version_id         = 1,
2405     .minimum_version_id = 1,
2406     .needed = qxl_monitors_config_needed,
2407     .fields = (VMStateField[]) {
2408         VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2409         VMSTATE_END_OF_LIST()
2410     },
2411 };
2412 
2413 static VMStateDescription qxl_vmstate = {
2414     .name               = "qxl",
2415     .version_id         = QXL_SAVE_VERSION,
2416     .minimum_version_id = QXL_SAVE_VERSION,
2417     .pre_save           = qxl_pre_save,
2418     .pre_load           = qxl_pre_load,
2419     .post_load          = qxl_post_load,
2420     .fields = (VMStateField[]) {
2421         VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2422         VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2423         VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2424         VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2425         VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2426         VMSTATE_UINT32(mode, PCIQXLDevice),
2427         VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2428         VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
2429         VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2430                              qxl_memslot, struct guest_slots),
2431         VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2432                        qxl_surface, QXLSurfaceCreate),
2433         VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
2434         VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2435                              ssd.num_surfaces, 0,
2436                              vmstate_info_uint64, uint64_t),
2437         VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2438         VMSTATE_END_OF_LIST()
2439     },
2440     .subsections = (const VMStateDescription*[]) {
2441         &qxl_vmstate_monitors_config,
2442         NULL
2443     }
2444 };
2445 
2446 static Property qxl_properties[] = {
2447         DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2448         DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
2449         DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2450                            QXL_DEFAULT_REVISION),
2451         DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2452         DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2453         DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2454         DEFINE_PROP_UINT32("ram_size_mb",  PCIQXLDevice, ram_size_mb, -1),
2455         DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2456         DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2457         DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2458         DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2459 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2460         DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2461 #endif
2462         DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2463         DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
2464         DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
2465         DEFINE_PROP_END_OF_LIST(),
2466 };
2467 
2468 static void qxl_pci_class_init(ObjectClass *klass, void *data)
2469 {
2470     DeviceClass *dc = DEVICE_CLASS(klass);
2471     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2472 
2473     k->vendor_id = REDHAT_PCI_VENDOR_ID;
2474     k->device_id = QXL_DEVICE_ID_STABLE;
2475     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2476     dc->reset = qxl_reset_handler;
2477     dc->vmsd = &qxl_vmstate;
2478     dc->props = qxl_properties;
2479 }
2480 
2481 static const TypeInfo qxl_pci_type_info = {
2482     .name = TYPE_PCI_QXL,
2483     .parent = TYPE_PCI_DEVICE,
2484     .instance_size = sizeof(PCIQXLDevice),
2485     .abstract = true,
2486     .class_init = qxl_pci_class_init,
2487     .interfaces = (InterfaceInfo[]) {
2488         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2489         { },
2490     },
2491 };
2492 
2493 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2494 {
2495     DeviceClass *dc = DEVICE_CLASS(klass);
2496     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2497 
2498     k->realize = qxl_realize_primary;
2499     k->romfile = "vgabios-qxl.bin";
2500     k->class_id = PCI_CLASS_DISPLAY_VGA;
2501     dc->desc = "Spice QXL GPU (primary, vga compatible)";
2502     dc->hotpluggable = false;
2503 }
2504 
2505 static const TypeInfo qxl_primary_info = {
2506     .name          = "qxl-vga",
2507     .parent        = TYPE_PCI_QXL,
2508     .class_init    = qxl_primary_class_init,
2509 };
2510 
2511 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2512 {
2513     DeviceClass *dc = DEVICE_CLASS(klass);
2514     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2515 
2516     k->realize = qxl_realize_secondary;
2517     k->class_id = PCI_CLASS_DISPLAY_OTHER;
2518     dc->desc = "Spice QXL GPU (secondary)";
2519 }
2520 
2521 static const TypeInfo qxl_secondary_info = {
2522     .name          = "qxl",
2523     .parent        = TYPE_PCI_QXL,
2524     .class_init    = qxl_secondary_class_init,
2525 };
2526 
2527 static void qxl_register_types(void)
2528 {
2529     type_register_static(&qxl_pci_type_info);
2530     type_register_static(&qxl_primary_info);
2531     type_register_static(&qxl_secondary_info);
2532 }
2533 
2534 type_init(qxl_register_types)
2535