1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include <zlib.h> 24 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "qemu/timer.h" 28 #include "qemu/queue.h" 29 #include "qemu/atomic.h" 30 #include "sysemu/sysemu.h" 31 #include "migration/blocker.h" 32 #include "trace.h" 33 34 #include "qxl.h" 35 36 /* 37 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as 38 * such can be changed by the guest, so to avoid a guest trigerrable 39 * abort we just qxl_set_guest_bug and set the return to NULL. Still 40 * it may happen as a result of emulator bug as well. 41 */ 42 #undef SPICE_RING_PROD_ITEM 43 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ 44 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ 45 if (prod >= ARRAY_SIZE((r)->items)) { \ 46 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ 47 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ 48 ret = NULL; \ 49 } else { \ 50 ret = &(r)->items[prod].el; \ 51 } \ 52 } 53 54 #undef SPICE_RING_CONS_ITEM 55 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 56 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 57 if (cons >= ARRAY_SIZE((r)->items)) { \ 58 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 59 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 60 ret = NULL; \ 61 } else { \ 62 ret = &(r)->items[cons].el; \ 63 } \ 64 } 65 66 #undef ALIGN 67 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 68 69 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 70 71 #define QXL_MODE(_x, _y, _b, _o) \ 72 { .x_res = _x, \ 73 .y_res = _y, \ 74 .bits = _b, \ 75 .stride = (_x) * (_b) / 8, \ 76 .x_mili = PIXEL_SIZE * (_x), \ 77 .y_mili = PIXEL_SIZE * (_y), \ 78 .orientation = _o, \ 79 } 80 81 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 82 QXL_MODE(x_res, y_res, 16, orientation), \ 83 QXL_MODE(x_res, y_res, 32, orientation) 84 85 #define QXL_MODE_EX(x_res, y_res) \ 86 QXL_MODE_16_32(x_res, y_res, 0), \ 87 QXL_MODE_16_32(x_res, y_res, 1) 88 89 static QXLMode qxl_modes[] = { 90 QXL_MODE_EX(640, 480), 91 QXL_MODE_EX(800, 480), 92 QXL_MODE_EX(800, 600), 93 QXL_MODE_EX(832, 624), 94 QXL_MODE_EX(960, 640), 95 QXL_MODE_EX(1024, 600), 96 QXL_MODE_EX(1024, 768), 97 QXL_MODE_EX(1152, 864), 98 QXL_MODE_EX(1152, 870), 99 QXL_MODE_EX(1280, 720), 100 QXL_MODE_EX(1280, 760), 101 QXL_MODE_EX(1280, 768), 102 QXL_MODE_EX(1280, 800), 103 QXL_MODE_EX(1280, 960), 104 QXL_MODE_EX(1280, 1024), 105 QXL_MODE_EX(1360, 768), 106 QXL_MODE_EX(1366, 768), 107 QXL_MODE_EX(1400, 1050), 108 QXL_MODE_EX(1440, 900), 109 QXL_MODE_EX(1600, 900), 110 QXL_MODE_EX(1600, 1200), 111 QXL_MODE_EX(1680, 1050), 112 QXL_MODE_EX(1920, 1080), 113 /* these modes need more than 8 MB video memory */ 114 QXL_MODE_EX(1920, 1200), 115 QXL_MODE_EX(1920, 1440), 116 QXL_MODE_EX(2000, 2000), 117 QXL_MODE_EX(2048, 1536), 118 QXL_MODE_EX(2048, 2048), 119 QXL_MODE_EX(2560, 1440), 120 QXL_MODE_EX(2560, 1600), 121 /* these modes need more than 16 MB video memory */ 122 QXL_MODE_EX(2560, 2048), 123 QXL_MODE_EX(2800, 2100), 124 QXL_MODE_EX(3200, 2400), 125 /* these modes need more than 32 MB video memory */ 126 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 127 QXL_MODE_EX(4096, 2160), /* 4k */ 128 /* these modes need more than 64 MB video memory */ 129 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 130 /* these modes need more than 128 MB video memory */ 131 QXL_MODE_EX(8192, 4320), /* 8k */ 132 }; 133 134 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 135 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 136 static void qxl_reset_memslots(PCIQXLDevice *d); 137 static void qxl_reset_surfaces(PCIQXLDevice *d); 138 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 139 140 static void qxl_hw_update(void *opaque); 141 142 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 143 { 144 trace_qxl_set_guest_bug(qxl->id); 145 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 146 qxl->guest_bug = 1; 147 if (qxl->guestdebug) { 148 va_list ap; 149 va_start(ap, msg); 150 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 151 vfprintf(stderr, msg, ap); 152 fprintf(stderr, "\n"); 153 va_end(ap); 154 } 155 } 156 157 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 158 { 159 qxl->guest_bug = 0; 160 } 161 162 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 163 struct QXLRect *area, struct QXLRect *dirty_rects, 164 uint32_t num_dirty_rects, 165 uint32_t clear_dirty_region, 166 qxl_async_io async, struct QXLCookie *cookie) 167 { 168 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 169 area->top, area->bottom); 170 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 171 clear_dirty_region); 172 if (async == QXL_SYNC) { 173 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area, 174 dirty_rects, num_dirty_rects, clear_dirty_region); 175 } else { 176 assert(cookie != NULL); 177 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 178 clear_dirty_region, (uintptr_t)cookie); 179 } 180 } 181 182 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 183 uint32_t id) 184 { 185 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 186 qemu_mutex_lock(&qxl->track_lock); 187 qxl->guest_surfaces.cmds[id] = 0; 188 qxl->guest_surfaces.count--; 189 qemu_mutex_unlock(&qxl->track_lock); 190 } 191 192 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 193 qxl_async_io async) 194 { 195 QXLCookie *cookie; 196 197 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 198 if (async) { 199 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 200 QXL_IO_DESTROY_SURFACE_ASYNC); 201 cookie->u.surface_id = id; 202 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 203 } else { 204 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id); 205 qxl_spice_destroy_surface_wait_complete(qxl, id); 206 } 207 } 208 209 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 210 { 211 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 212 qxl->num_free_res); 213 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 214 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 215 QXL_IO_FLUSH_SURFACES_ASYNC)); 216 } 217 218 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 219 uint32_t count) 220 { 221 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 222 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count); 223 } 224 225 void qxl_spice_oom(PCIQXLDevice *qxl) 226 { 227 trace_qxl_spice_oom(qxl->id); 228 spice_qxl_oom(&qxl->ssd.qxl); 229 } 230 231 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 232 { 233 trace_qxl_spice_reset_memslots(qxl->id); 234 spice_qxl_reset_memslots(&qxl->ssd.qxl); 235 } 236 237 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 238 { 239 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 240 qemu_mutex_lock(&qxl->track_lock); 241 memset(qxl->guest_surfaces.cmds, 0, 242 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 243 qxl->guest_surfaces.count = 0; 244 qemu_mutex_unlock(&qxl->track_lock); 245 } 246 247 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 248 { 249 trace_qxl_spice_destroy_surfaces(qxl->id, async); 250 if (async) { 251 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 252 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 253 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 254 } else { 255 spice_qxl_destroy_surfaces(&qxl->ssd.qxl); 256 qxl_spice_destroy_surfaces_complete(qxl); 257 } 258 } 259 260 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 261 { 262 QXLMonitorsConfig *cfg; 263 264 trace_qxl_spice_monitors_config(qxl->id); 265 if (replay) { 266 /* 267 * don't use QXL_COOKIE_TYPE_IO: 268 * - we are not running yet (post_load), we will assert 269 * in send_events 270 * - this is not a guest io, but a reply, so async_io isn't set. 271 */ 272 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 273 qxl->guest_monitors_config, 274 MEMSLOT_GROUP_GUEST, 275 (uintptr_t)qxl_cookie_new( 276 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 277 0)); 278 } else { 279 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 280 if (qxl->max_outputs) { 281 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs); 282 } 283 #endif 284 qxl->guest_monitors_config = qxl->ram->monitors_config; 285 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 286 qxl->ram->monitors_config, 287 MEMSLOT_GROUP_GUEST, 288 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 289 QXL_IO_MONITORS_CONFIG_ASYNC)); 290 } 291 292 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST); 293 if (cfg != NULL && cfg->count == 1) { 294 qxl->guest_primary.resized = 1; 295 qxl->guest_head0_width = cfg->heads[0].width; 296 qxl->guest_head0_height = cfg->heads[0].height; 297 } else { 298 qxl->guest_head0_width = 0; 299 qxl->guest_head0_height = 0; 300 } 301 } 302 303 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 304 { 305 trace_qxl_spice_reset_image_cache(qxl->id); 306 spice_qxl_reset_image_cache(&qxl->ssd.qxl); 307 } 308 309 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 310 { 311 trace_qxl_spice_reset_cursor(qxl->id); 312 spice_qxl_reset_cursor(&qxl->ssd.qxl); 313 qemu_mutex_lock(&qxl->track_lock); 314 qxl->guest_cursor = 0; 315 qemu_mutex_unlock(&qxl->track_lock); 316 if (qxl->ssd.cursor) { 317 cursor_put(qxl->ssd.cursor); 318 } 319 qxl->ssd.cursor = cursor_builtin_hidden(); 320 } 321 322 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 323 { 324 /* 325 * zlib xors the seed with 0xffffffff, and xors the result 326 * again with 0xffffffff; Both are not done with linux's crc32, 327 * which we want to be compatible with, so undo that. 328 */ 329 return crc32(0xffffffff, p, len) ^ 0xffffffff; 330 } 331 332 static ram_addr_t qxl_rom_size(void) 333 { 334 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes)) 335 #define QXL_ROM_SZ 8192 336 337 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ); 338 return QXL_ROM_SZ; 339 } 340 341 static void init_qxl_rom(PCIQXLDevice *d) 342 { 343 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 344 QXLModes *modes = (QXLModes *)(rom + 1); 345 uint32_t ram_header_size; 346 uint32_t surface0_area_size; 347 uint32_t num_pages; 348 uint32_t fb; 349 int i, n; 350 351 memset(rom, 0, d->rom_size); 352 353 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 354 rom->id = cpu_to_le32(d->id); 355 rom->log_level = cpu_to_le32(d->guestdebug); 356 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 357 358 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 359 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 360 rom->slots_start = 1; 361 rom->slots_end = NUM_MEMSLOTS - 1; 362 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 363 364 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 365 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 366 if (fb > d->vgamem_size) { 367 continue; 368 } 369 modes->modes[n].id = cpu_to_le32(i); 370 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 371 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 372 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 373 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 374 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 375 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 376 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 377 n++; 378 } 379 modes->n_modes = cpu_to_le32(n); 380 381 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 382 surface0_area_size = ALIGN(d->vgamem_size, 4096); 383 num_pages = d->vga.vram_size; 384 num_pages -= ram_header_size; 385 num_pages -= surface0_area_size; 386 num_pages = num_pages / QXL_PAGE_SIZE; 387 388 assert(ram_header_size + surface0_area_size <= d->vga.vram_size); 389 390 rom->draw_area_offset = cpu_to_le32(0); 391 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 392 rom->pages_offset = cpu_to_le32(surface0_area_size); 393 rom->num_pages = cpu_to_le32(num_pages); 394 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 395 396 if (d->xres && d->yres) { 397 /* needs linux kernel 4.12+ to work */ 398 rom->client_monitors_config.count = 1; 399 rom->client_monitors_config.heads[0].left = 0; 400 rom->client_monitors_config.heads[0].top = 0; 401 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres); 402 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres); 403 rom->client_monitors_config_crc = qxl_crc32( 404 (const uint8_t *)&rom->client_monitors_config, 405 sizeof(rom->client_monitors_config)); 406 } 407 408 d->shadow_rom = *rom; 409 d->rom = rom; 410 d->modes = modes; 411 } 412 413 static void init_qxl_ram(PCIQXLDevice *d) 414 { 415 uint8_t *buf; 416 uint64_t *item; 417 418 buf = d->vga.vram_ptr; 419 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 420 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 421 d->ram->int_pending = cpu_to_le32(0); 422 d->ram->int_mask = cpu_to_le32(0); 423 d->ram->update_surface = 0; 424 d->ram->monitors_config = 0; 425 SPICE_RING_INIT(&d->ram->cmd_ring); 426 SPICE_RING_INIT(&d->ram->cursor_ring); 427 SPICE_RING_INIT(&d->ram->release_ring); 428 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); 429 assert(item); 430 *item = 0; 431 qxl_ring_set_dirty(d); 432 } 433 434 /* can be called from spice server thread context */ 435 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 436 { 437 memory_region_set_dirty(mr, addr, end - addr); 438 } 439 440 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 441 { 442 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 443 } 444 445 /* called from spice server thread context only */ 446 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 447 { 448 void *base = qxl->vga.vram_ptr; 449 intptr_t offset; 450 451 offset = ptr - base; 452 assert(offset < qxl->vga.vram_size); 453 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3); 454 } 455 456 /* can be called from spice server thread context */ 457 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 458 { 459 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 460 ram_addr_t end = qxl->vga.vram_size; 461 qxl_set_dirty(&qxl->vga.vram, addr, end); 462 } 463 464 /* 465 * keep track of some command state, for savevm/loadvm. 466 * called from spice server thread context only 467 */ 468 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 469 { 470 switch (le32_to_cpu(ext->cmd.type)) { 471 case QXL_CMD_SURFACE: 472 { 473 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 474 475 if (!cmd) { 476 return 1; 477 } 478 uint32_t id = le32_to_cpu(cmd->surface_id); 479 480 if (id >= qxl->ssd.num_surfaces) { 481 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 482 qxl->ssd.num_surfaces); 483 return 1; 484 } 485 if (cmd->type == QXL_SURFACE_CMD_CREATE && 486 (cmd->u.surface_create.stride & 0x03) != 0) { 487 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 488 cmd->u.surface_create.stride); 489 return 1; 490 } 491 qemu_mutex_lock(&qxl->track_lock); 492 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 493 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 494 qxl->guest_surfaces.count++; 495 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) 496 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 497 } 498 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 499 qxl->guest_surfaces.cmds[id] = 0; 500 qxl->guest_surfaces.count--; 501 } 502 qemu_mutex_unlock(&qxl->track_lock); 503 break; 504 } 505 case QXL_CMD_CURSOR: 506 { 507 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 508 509 if (!cmd) { 510 return 1; 511 } 512 if (cmd->type == QXL_CURSOR_SET) { 513 qemu_mutex_lock(&qxl->track_lock); 514 qxl->guest_cursor = ext->cmd.data; 515 qemu_mutex_unlock(&qxl->track_lock); 516 } 517 if (cmd->type == QXL_CURSOR_HIDE) { 518 qemu_mutex_lock(&qxl->track_lock); 519 qxl->guest_cursor = 0; 520 qemu_mutex_unlock(&qxl->track_lock); 521 } 522 break; 523 } 524 } 525 return 0; 526 } 527 528 /* spice display interface callbacks */ 529 530 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 531 { 532 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 533 534 trace_qxl_interface_attach_worker(qxl->id); 535 } 536 537 static void interface_set_compression_level(QXLInstance *sin, int level) 538 { 539 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 540 541 trace_qxl_interface_set_compression_level(qxl->id, level); 542 qxl->shadow_rom.compression_level = cpu_to_le32(level); 543 qxl->rom->compression_level = cpu_to_le32(level); 544 qxl_rom_set_dirty(qxl); 545 } 546 547 #if SPICE_NEEDS_SET_MM_TIME 548 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 549 { 550 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 551 552 if (!qemu_spice_display_is_running(&qxl->ssd)) { 553 return; 554 } 555 556 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 557 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 558 qxl->rom->mm_clock = cpu_to_le32(mm_time); 559 qxl_rom_set_dirty(qxl); 560 } 561 #endif 562 563 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 564 { 565 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 566 567 trace_qxl_interface_get_init_info(qxl->id); 568 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 569 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 570 info->num_memslots = NUM_MEMSLOTS; 571 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 572 info->internal_groupslot_id = 0; 573 info->qxl_ram_size = 574 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS; 575 info->n_surfaces = qxl->ssd.num_surfaces; 576 } 577 578 static const char *qxl_mode_to_string(int mode) 579 { 580 switch (mode) { 581 case QXL_MODE_COMPAT: 582 return "compat"; 583 case QXL_MODE_NATIVE: 584 return "native"; 585 case QXL_MODE_UNDEFINED: 586 return "undefined"; 587 case QXL_MODE_VGA: 588 return "vga"; 589 } 590 return "INVALID"; 591 } 592 593 static const char *io_port_to_string(uint32_t io_port) 594 { 595 if (io_port >= QXL_IO_RANGE_SIZE) { 596 return "out of range"; 597 } 598 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 599 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 600 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 601 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 602 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 603 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 604 [QXL_IO_RESET] = "QXL_IO_RESET", 605 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 606 [QXL_IO_LOG] = "QXL_IO_LOG", 607 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 608 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 609 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 610 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 611 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 612 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 613 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 614 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 615 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 616 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 617 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 618 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 619 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 620 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 621 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 622 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 623 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 624 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 625 }; 626 return io_port_to_string[io_port]; 627 } 628 629 /* called from spice server thread context only */ 630 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 631 { 632 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 633 SimpleSpiceUpdate *update; 634 QXLCommandRing *ring; 635 QXLCommand *cmd; 636 int notify, ret; 637 638 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 639 640 switch (qxl->mode) { 641 case QXL_MODE_VGA: 642 ret = false; 643 qemu_mutex_lock(&qxl->ssd.lock); 644 update = QTAILQ_FIRST(&qxl->ssd.updates); 645 if (update != NULL) { 646 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 647 *ext = update->ext; 648 ret = true; 649 } 650 qemu_mutex_unlock(&qxl->ssd.lock); 651 if (ret) { 652 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 653 qxl_log_command(qxl, "vga", ext); 654 } 655 return ret; 656 case QXL_MODE_COMPAT: 657 case QXL_MODE_NATIVE: 658 case QXL_MODE_UNDEFINED: 659 ring = &qxl->ram->cmd_ring; 660 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 661 return false; 662 } 663 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 664 if (!cmd) { 665 return false; 666 } 667 ext->cmd = *cmd; 668 ext->group_id = MEMSLOT_GROUP_GUEST; 669 ext->flags = qxl->cmdflags; 670 SPICE_RING_POP(ring, notify); 671 qxl_ring_set_dirty(qxl); 672 if (notify) { 673 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 674 } 675 qxl->guest_primary.commands++; 676 qxl_track_command(qxl, ext); 677 qxl_log_command(qxl, "cmd", ext); 678 { 679 /* 680 * Windows 8 drivers place qxl commands in the vram 681 * (instead of the ram) bar. We can't live migrate such a 682 * guest, so add a migration blocker in case we detect 683 * this, to avoid triggering the assert in pre_save(). 684 * 685 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa 686 */ 687 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 688 if (msg != NULL && ( 689 msg < (void *)qxl->vga.vram_ptr || 690 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) { 691 if (!qxl->migration_blocker) { 692 Error *local_err = NULL; 693 error_setg(&qxl->migration_blocker, 694 "qxl: guest bug: command not in ram bar"); 695 migrate_add_blocker(qxl->migration_blocker, &local_err); 696 if (local_err) { 697 error_report_err(local_err); 698 } 699 } 700 } 701 } 702 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 703 return true; 704 default: 705 return false; 706 } 707 } 708 709 /* called from spice server thread context only */ 710 static int interface_req_cmd_notification(QXLInstance *sin) 711 { 712 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 713 int wait = 1; 714 715 trace_qxl_ring_command_req_notification(qxl->id); 716 switch (qxl->mode) { 717 case QXL_MODE_COMPAT: 718 case QXL_MODE_NATIVE: 719 case QXL_MODE_UNDEFINED: 720 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 721 qxl_ring_set_dirty(qxl); 722 break; 723 default: 724 /* nothing */ 725 break; 726 } 727 return wait; 728 } 729 730 /* called from spice server thread context only */ 731 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 732 { 733 QXLReleaseRing *ring = &d->ram->release_ring; 734 uint64_t *item; 735 int notify; 736 737 #define QXL_FREE_BUNCH_SIZE 32 738 739 if (ring->prod - ring->cons + 1 == ring->num_items) { 740 /* ring full -- can't push */ 741 return; 742 } 743 if (!flush && d->oom_running) { 744 /* collect everything from oom handler before pushing */ 745 return; 746 } 747 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 748 /* collect a bit more before pushing */ 749 return; 750 } 751 752 SPICE_RING_PUSH(ring, notify); 753 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 754 d->guest_surfaces.count, d->num_free_res, 755 d->last_release, notify ? "yes" : "no"); 756 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 757 ring->num_items, ring->prod, ring->cons); 758 if (notify) { 759 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 760 } 761 SPICE_RING_PROD_ITEM(d, ring, item); 762 if (!item) { 763 return; 764 } 765 *item = 0; 766 d->num_free_res = 0; 767 d->last_release = NULL; 768 qxl_ring_set_dirty(d); 769 } 770 771 /* called from spice server thread context only */ 772 static void interface_release_resource(QXLInstance *sin, 773 QXLReleaseInfoExt ext) 774 { 775 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 776 QXLReleaseRing *ring; 777 uint64_t *item, id; 778 779 if (ext.group_id == MEMSLOT_GROUP_HOST) { 780 /* host group -> vga mode update request */ 781 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id); 782 SimpleSpiceUpdate *update; 783 g_assert(cmdext->cmd.type == QXL_CMD_DRAW); 784 update = container_of(cmdext, SimpleSpiceUpdate, ext); 785 qemu_spice_destroy_update(&qxl->ssd, update); 786 return; 787 } 788 789 /* 790 * ext->info points into guest-visible memory 791 * pci bar 0, $command.release_info 792 */ 793 ring = &qxl->ram->release_ring; 794 SPICE_RING_PROD_ITEM(qxl, ring, item); 795 if (!item) { 796 return; 797 } 798 if (*item == 0) { 799 /* stick head into the ring */ 800 id = ext.info->id; 801 ext.info->next = 0; 802 qxl_ram_set_dirty(qxl, &ext.info->next); 803 *item = id; 804 qxl_ring_set_dirty(qxl); 805 } else { 806 /* append item to the list */ 807 qxl->last_release->next = ext.info->id; 808 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 809 ext.info->next = 0; 810 qxl_ram_set_dirty(qxl, &ext.info->next); 811 } 812 qxl->last_release = ext.info; 813 qxl->num_free_res++; 814 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 815 qxl_push_free_res(qxl, 0); 816 } 817 818 /* called from spice server thread context only */ 819 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 820 { 821 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 822 QXLCursorRing *ring; 823 QXLCommand *cmd; 824 int notify; 825 826 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 827 828 switch (qxl->mode) { 829 case QXL_MODE_COMPAT: 830 case QXL_MODE_NATIVE: 831 case QXL_MODE_UNDEFINED: 832 ring = &qxl->ram->cursor_ring; 833 if (SPICE_RING_IS_EMPTY(ring)) { 834 return false; 835 } 836 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 837 if (!cmd) { 838 return false; 839 } 840 ext->cmd = *cmd; 841 ext->group_id = MEMSLOT_GROUP_GUEST; 842 ext->flags = qxl->cmdflags; 843 SPICE_RING_POP(ring, notify); 844 qxl_ring_set_dirty(qxl); 845 if (notify) { 846 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 847 } 848 qxl->guest_primary.commands++; 849 qxl_track_command(qxl, ext); 850 qxl_log_command(qxl, "csr", ext); 851 if (qxl->have_vga) { 852 qxl_render_cursor(qxl, ext); 853 } 854 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 855 return true; 856 default: 857 return false; 858 } 859 } 860 861 /* called from spice server thread context only */ 862 static int interface_req_cursor_notification(QXLInstance *sin) 863 { 864 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 865 int wait = 1; 866 867 trace_qxl_ring_cursor_req_notification(qxl->id); 868 switch (qxl->mode) { 869 case QXL_MODE_COMPAT: 870 case QXL_MODE_NATIVE: 871 case QXL_MODE_UNDEFINED: 872 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 873 qxl_ring_set_dirty(qxl); 874 break; 875 default: 876 /* nothing */ 877 break; 878 } 879 return wait; 880 } 881 882 /* called from spice server thread context */ 883 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 884 { 885 /* 886 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 887 * use by xf86-video-qxl and is defined out in the qxl windows driver. 888 * Probably was at some earlier version that is prior to git start (2009), 889 * and is still guest trigerrable. 890 */ 891 fprintf(stderr, "%s: deprecated\n", __func__); 892 } 893 894 /* called from spice server thread context only */ 895 static int interface_flush_resources(QXLInstance *sin) 896 { 897 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 898 int ret; 899 900 ret = qxl->num_free_res; 901 if (ret) { 902 qxl_push_free_res(qxl, 1); 903 } 904 return ret; 905 } 906 907 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 908 909 /* called from spice server thread context only */ 910 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 911 { 912 uint32_t current_async; 913 914 qemu_mutex_lock(&qxl->async_lock); 915 current_async = qxl->current_async; 916 qxl->current_async = QXL_UNDEFINED_IO; 917 qemu_mutex_unlock(&qxl->async_lock); 918 919 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 920 if (!cookie) { 921 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 922 return; 923 } 924 if (cookie && current_async != cookie->io) { 925 fprintf(stderr, 926 "qxl: %s: error: current_async = %d != %" 927 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 928 } 929 switch (current_async) { 930 case QXL_IO_MEMSLOT_ADD_ASYNC: 931 case QXL_IO_DESTROY_PRIMARY_ASYNC: 932 case QXL_IO_UPDATE_AREA_ASYNC: 933 case QXL_IO_FLUSH_SURFACES_ASYNC: 934 case QXL_IO_MONITORS_CONFIG_ASYNC: 935 break; 936 case QXL_IO_CREATE_PRIMARY_ASYNC: 937 qxl_create_guest_primary_complete(qxl); 938 break; 939 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 940 qxl_spice_destroy_surfaces_complete(qxl); 941 break; 942 case QXL_IO_DESTROY_SURFACE_ASYNC: 943 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 944 break; 945 default: 946 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 947 current_async); 948 } 949 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 950 } 951 952 /* called from spice server thread context only */ 953 static void interface_update_area_complete(QXLInstance *sin, 954 uint32_t surface_id, 955 QXLRect *dirty, uint32_t num_updated_rects) 956 { 957 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 958 int i; 959 int qxl_i; 960 961 qemu_mutex_lock(&qxl->ssd.lock); 962 if (surface_id != 0 || !num_updated_rects || 963 !qxl->render_update_cookie_num) { 964 qemu_mutex_unlock(&qxl->ssd.lock); 965 return; 966 } 967 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 968 dirty->right, dirty->top, dirty->bottom); 969 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 970 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 971 /* 972 * overflow - treat this as a full update. Not expected to be common. 973 */ 974 trace_qxl_interface_update_area_complete_overflow(qxl->id, 975 QXL_NUM_DIRTY_RECTS); 976 qxl->guest_primary.resized = 1; 977 } 978 if (qxl->guest_primary.resized) { 979 /* 980 * Don't bother copying or scheduling the bh since we will flip 981 * the whole area anyway on completion of the update_area async call 982 */ 983 qemu_mutex_unlock(&qxl->ssd.lock); 984 return; 985 } 986 qxl_i = qxl->num_dirty_rects; 987 for (i = 0; i < num_updated_rects; i++) { 988 qxl->dirty[qxl_i++] = dirty[i]; 989 } 990 qxl->num_dirty_rects += num_updated_rects; 991 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 992 qxl->num_dirty_rects); 993 qemu_bh_schedule(qxl->update_area_bh); 994 qemu_mutex_unlock(&qxl->ssd.lock); 995 } 996 997 /* called from spice server thread context only */ 998 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 999 { 1000 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 1001 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 1002 1003 switch (cookie->type) { 1004 case QXL_COOKIE_TYPE_IO: 1005 interface_async_complete_io(qxl, cookie); 1006 g_free(cookie); 1007 break; 1008 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 1009 qxl_render_update_area_done(qxl, cookie); 1010 break; 1011 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 1012 break; 1013 default: 1014 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 1015 __func__, cookie->type); 1016 g_free(cookie); 1017 } 1018 } 1019 1020 /* called from spice server thread context only */ 1021 static void interface_set_client_capabilities(QXLInstance *sin, 1022 uint8_t client_present, 1023 uint8_t caps[58]) 1024 { 1025 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 1026 1027 if (qxl->revision < 4) { 1028 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 1029 qxl->revision); 1030 return; 1031 } 1032 1033 if (runstate_check(RUN_STATE_INMIGRATE) || 1034 runstate_check(RUN_STATE_POSTMIGRATE)) { 1035 return; 1036 } 1037 1038 qxl->shadow_rom.client_present = client_present; 1039 memcpy(qxl->shadow_rom.client_capabilities, caps, 1040 sizeof(qxl->shadow_rom.client_capabilities)); 1041 qxl->rom->client_present = client_present; 1042 memcpy(qxl->rom->client_capabilities, caps, 1043 sizeof(qxl->rom->client_capabilities)); 1044 qxl_rom_set_dirty(qxl); 1045 1046 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 1047 } 1048 1049 static bool qxl_rom_monitors_config_changed(QXLRom *rom, 1050 VDAgentMonitorsConfig *monitors_config, 1051 unsigned int max_outputs) 1052 { 1053 int i; 1054 unsigned int monitors_count; 1055 1056 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs); 1057 1058 if (rom->client_monitors_config.count != monitors_count) { 1059 return true; 1060 } 1061 1062 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1063 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1064 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1065 /* monitor->depth ignored */ 1066 if ((rect->left != monitor->x) || 1067 (rect->top != monitor->y) || 1068 (rect->right != monitor->x + monitor->width) || 1069 (rect->bottom != monitor->y + monitor->height)) { 1070 return true; 1071 } 1072 } 1073 1074 return false; 1075 } 1076 1077 /* called from main context only */ 1078 static int interface_client_monitors_config(QXLInstance *sin, 1079 VDAgentMonitorsConfig *monitors_config) 1080 { 1081 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 1082 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 1083 int i; 1084 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads); 1085 bool config_changed = false; 1086 1087 if (qxl->revision < 4) { 1088 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 1089 qxl->revision); 1090 return 0; 1091 } 1092 /* 1093 * Older windows drivers set int_mask to 0 when their ISR is called, 1094 * then later set it to ~0. So it doesn't relate to the actual interrupts 1095 * handled. However, they are old, so clearly they don't support this 1096 * interrupt 1097 */ 1098 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1099 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1100 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1101 qxl->ram->int_mask, 1102 monitors_config); 1103 return 0; 1104 } 1105 if (!monitors_config) { 1106 return 1; 1107 } 1108 1109 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 1110 /* limit number of outputs based on setting limit */ 1111 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) { 1112 max_outputs = qxl->max_outputs; 1113 } 1114 #endif 1115 1116 config_changed = qxl_rom_monitors_config_changed(rom, 1117 monitors_config, 1118 max_outputs); 1119 1120 memset(&rom->client_monitors_config, 0, 1121 sizeof(rom->client_monitors_config)); 1122 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1123 /* monitors_config->flags ignored */ 1124 if (rom->client_monitors_config.count >= max_outputs) { 1125 trace_qxl_client_monitors_config_capped(qxl->id, 1126 monitors_config->num_of_monitors, 1127 max_outputs); 1128 rom->client_monitors_config.count = max_outputs; 1129 } 1130 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1131 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1132 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1133 /* monitor->depth ignored */ 1134 rect->left = monitor->x; 1135 rect->top = monitor->y; 1136 rect->right = monitor->x + monitor->width; 1137 rect->bottom = monitor->y + monitor->height; 1138 } 1139 rom->client_monitors_config_crc = qxl_crc32( 1140 (const uint8_t *)&rom->client_monitors_config, 1141 sizeof(rom->client_monitors_config)); 1142 trace_qxl_client_monitors_config_crc(qxl->id, 1143 sizeof(rom->client_monitors_config), 1144 rom->client_monitors_config_crc); 1145 1146 trace_qxl_interrupt_client_monitors_config(qxl->id, 1147 rom->client_monitors_config.count, 1148 rom->client_monitors_config.heads); 1149 if (config_changed) { 1150 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1151 } 1152 return 1; 1153 } 1154 1155 static const QXLInterface qxl_interface = { 1156 .base.type = SPICE_INTERFACE_QXL, 1157 .base.description = "qxl gpu", 1158 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1159 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1160 1161 .attache_worker = interface_attach_worker, 1162 .set_compression_level = interface_set_compression_level, 1163 #if SPICE_NEEDS_SET_MM_TIME 1164 .set_mm_time = interface_set_mm_time, 1165 #endif 1166 .get_init_info = interface_get_init_info, 1167 1168 /* the callbacks below are called from spice server thread context */ 1169 .get_command = interface_get_command, 1170 .req_cmd_notification = interface_req_cmd_notification, 1171 .release_resource = interface_release_resource, 1172 .get_cursor_command = interface_get_cursor_command, 1173 .req_cursor_notification = interface_req_cursor_notification, 1174 .notify_update = interface_notify_update, 1175 .flush_resources = interface_flush_resources, 1176 .async_complete = interface_async_complete, 1177 .update_area_complete = interface_update_area_complete, 1178 .set_client_capabilities = interface_set_client_capabilities, 1179 .client_monitors_config = interface_client_monitors_config, 1180 }; 1181 1182 static const GraphicHwOps qxl_ops = { 1183 .gfx_update = qxl_hw_update, 1184 }; 1185 1186 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1187 { 1188 if (d->mode == QXL_MODE_VGA) { 1189 return; 1190 } 1191 trace_qxl_enter_vga_mode(d->id); 1192 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */ 1193 spice_qxl_driver_unload(&d->ssd.qxl); 1194 #endif 1195 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga); 1196 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT); 1197 qemu_spice_create_host_primary(&d->ssd); 1198 d->mode = QXL_MODE_VGA; 1199 qemu_spice_display_switch(&d->ssd, d->ssd.ds); 1200 vga_dirty_log_start(&d->vga); 1201 graphic_hw_update(d->vga.con); 1202 } 1203 1204 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1205 { 1206 if (d->mode != QXL_MODE_VGA) { 1207 return; 1208 } 1209 trace_qxl_exit_vga_mode(d->id); 1210 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d); 1211 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE); 1212 vga_dirty_log_stop(&d->vga); 1213 qxl_destroy_primary(d, QXL_SYNC); 1214 } 1215 1216 static void qxl_update_irq(PCIQXLDevice *d) 1217 { 1218 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1219 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1220 int level = !!(pending & mask); 1221 pci_set_irq(&d->pci, level); 1222 qxl_ring_set_dirty(d); 1223 } 1224 1225 static void qxl_check_state(PCIQXLDevice *d) 1226 { 1227 QXLRam *ram = d->ram; 1228 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1229 1230 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1231 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1232 } 1233 1234 static void qxl_reset_state(PCIQXLDevice *d) 1235 { 1236 QXLRom *rom = d->rom; 1237 1238 qxl_check_state(d); 1239 d->shadow_rom.update_id = cpu_to_le32(0); 1240 *rom = d->shadow_rom; 1241 qxl_rom_set_dirty(d); 1242 init_qxl_ram(d); 1243 d->num_free_res = 0; 1244 d->last_release = NULL; 1245 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1246 qxl_update_irq(d); 1247 } 1248 1249 static void qxl_soft_reset(PCIQXLDevice *d) 1250 { 1251 trace_qxl_soft_reset(d->id); 1252 qxl_check_state(d); 1253 qxl_clear_guest_bug(d); 1254 qemu_mutex_lock(&d->async_lock); 1255 d->current_async = QXL_UNDEFINED_IO; 1256 qemu_mutex_unlock(&d->async_lock); 1257 1258 if (d->have_vga) { 1259 qxl_enter_vga_mode(d); 1260 } else { 1261 d->mode = QXL_MODE_UNDEFINED; 1262 } 1263 } 1264 1265 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1266 { 1267 bool startstop = qemu_spice_display_is_running(&d->ssd); 1268 1269 trace_qxl_hard_reset(d->id, loadvm); 1270 1271 if (startstop) { 1272 qemu_spice_display_stop(); 1273 } 1274 1275 qxl_spice_reset_cursor(d); 1276 qxl_spice_reset_image_cache(d); 1277 qxl_reset_surfaces(d); 1278 qxl_reset_memslots(d); 1279 1280 /* pre loadvm reset must not touch QXLRam. This lives in 1281 * device memory, is migrated together with RAM and thus 1282 * already loaded at this point */ 1283 if (!loadvm) { 1284 qxl_reset_state(d); 1285 } 1286 qemu_spice_create_host_memslot(&d->ssd); 1287 qxl_soft_reset(d); 1288 1289 if (d->migration_blocker) { 1290 migrate_del_blocker(d->migration_blocker); 1291 error_free(d->migration_blocker); 1292 d->migration_blocker = NULL; 1293 } 1294 1295 if (startstop) { 1296 qemu_spice_display_start(); 1297 } 1298 } 1299 1300 static void qxl_reset_handler(DeviceState *dev) 1301 { 1302 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev)); 1303 1304 qxl_hard_reset(d, 0); 1305 } 1306 1307 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1308 { 1309 VGACommonState *vga = opaque; 1310 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1311 1312 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1313 if (qxl->mode != QXL_MODE_VGA) { 1314 qxl_destroy_primary(qxl, QXL_SYNC); 1315 qxl_soft_reset(qxl); 1316 } 1317 vga_ioport_write(opaque, addr, val); 1318 } 1319 1320 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1321 { 0x04, 2, 1, .read = vga_ioport_read, 1322 .write = qxl_vga_ioport_write }, /* 3b4 */ 1323 { 0x0a, 1, 1, .read = vga_ioport_read, 1324 .write = qxl_vga_ioport_write }, /* 3ba */ 1325 { 0x10, 16, 1, .read = vga_ioport_read, 1326 .write = qxl_vga_ioport_write }, /* 3c0 */ 1327 { 0x24, 2, 1, .read = vga_ioport_read, 1328 .write = qxl_vga_ioport_write }, /* 3d4 */ 1329 { 0x2a, 1, 1, .read = vga_ioport_read, 1330 .write = qxl_vga_ioport_write }, /* 3da */ 1331 PORTIO_END_OF_LIST(), 1332 }; 1333 1334 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1335 qxl_async_io async) 1336 { 1337 static const int regions[] = { 1338 QXL_RAM_RANGE_INDEX, 1339 QXL_VRAM_RANGE_INDEX, 1340 QXL_VRAM64_RANGE_INDEX, 1341 }; 1342 uint64_t guest_start; 1343 uint64_t guest_end; 1344 int pci_region; 1345 pcibus_t pci_start; 1346 pcibus_t pci_end; 1347 MemoryRegion *mr; 1348 intptr_t virt_start; 1349 QXLDevMemSlot memslot; 1350 int i; 1351 1352 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1353 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1354 1355 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1356 1357 if (slot_id >= NUM_MEMSLOTS) { 1358 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1359 slot_id, NUM_MEMSLOTS); 1360 return 1; 1361 } 1362 if (guest_start > guest_end) { 1363 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1364 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1365 return 1; 1366 } 1367 1368 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1369 pci_region = regions[i]; 1370 pci_start = d->pci.io_regions[pci_region].addr; 1371 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1372 /* mapped? */ 1373 if (pci_start == -1) { 1374 continue; 1375 } 1376 /* start address in range ? */ 1377 if (guest_start < pci_start || guest_start > pci_end) { 1378 continue; 1379 } 1380 /* end address in range ? */ 1381 if (guest_end > pci_end) { 1382 continue; 1383 } 1384 /* passed */ 1385 break; 1386 } 1387 if (i == ARRAY_SIZE(regions)) { 1388 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1389 return 1; 1390 } 1391 1392 switch (pci_region) { 1393 case QXL_RAM_RANGE_INDEX: 1394 mr = &d->vga.vram; 1395 break; 1396 case QXL_VRAM_RANGE_INDEX: 1397 case 4 /* vram 64bit */: 1398 mr = &d->vram_bar; 1399 break; 1400 default: 1401 /* should not happen */ 1402 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1403 return 1; 1404 } 1405 1406 virt_start = (intptr_t)memory_region_get_ram_ptr(mr); 1407 memslot.slot_id = slot_id; 1408 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1409 memslot.virt_start = virt_start + (guest_start - pci_start); 1410 memslot.virt_end = virt_start + (guest_end - pci_start); 1411 memslot.addr_delta = memslot.virt_start - delta; 1412 memslot.generation = d->rom->slot_generation = 0; 1413 qxl_rom_set_dirty(d); 1414 1415 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1416 d->guest_slots[slot_id].mr = mr; 1417 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start; 1418 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1419 d->guest_slots[slot_id].delta = delta; 1420 d->guest_slots[slot_id].active = 1; 1421 return 0; 1422 } 1423 1424 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1425 { 1426 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1427 d->guest_slots[slot_id].active = 0; 1428 } 1429 1430 static void qxl_reset_memslots(PCIQXLDevice *d) 1431 { 1432 qxl_spice_reset_memslots(d); 1433 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1434 } 1435 1436 static void qxl_reset_surfaces(PCIQXLDevice *d) 1437 { 1438 trace_qxl_reset_surfaces(d->id); 1439 d->mode = QXL_MODE_UNDEFINED; 1440 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1441 } 1442 1443 /* can be also called from spice server thread context */ 1444 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, 1445 uint32_t *s, uint64_t *o) 1446 { 1447 uint64_t phys = le64_to_cpu(pqxl); 1448 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1449 uint64_t offset = phys & 0xffffffffffff; 1450 1451 if (slot >= NUM_MEMSLOTS) { 1452 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1453 NUM_MEMSLOTS); 1454 return false; 1455 } 1456 if (!qxl->guest_slots[slot].active) { 1457 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1458 return false; 1459 } 1460 if (offset < qxl->guest_slots[slot].delta) { 1461 qxl_set_guest_bug(qxl, 1462 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1463 slot, offset, qxl->guest_slots[slot].delta); 1464 return false; 1465 } 1466 offset -= qxl->guest_slots[slot].delta; 1467 if (offset > qxl->guest_slots[slot].size) { 1468 qxl_set_guest_bug(qxl, 1469 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1470 slot, offset, qxl->guest_slots[slot].size); 1471 return false; 1472 } 1473 1474 *s = slot; 1475 *o = offset; 1476 return true; 1477 } 1478 1479 /* can be also called from spice server thread context */ 1480 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1481 { 1482 uint64_t offset; 1483 uint32_t slot; 1484 void *ptr; 1485 1486 switch (group_id) { 1487 case MEMSLOT_GROUP_HOST: 1488 offset = le64_to_cpu(pqxl) & 0xffffffffffff; 1489 return (void *)(intptr_t)offset; 1490 case MEMSLOT_GROUP_GUEST: 1491 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) { 1492 return NULL; 1493 } 1494 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr); 1495 ptr += qxl->guest_slots[slot].offset; 1496 ptr += offset; 1497 return ptr; 1498 } 1499 return NULL; 1500 } 1501 1502 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1503 { 1504 /* for local rendering */ 1505 qxl_render_resize(qxl); 1506 } 1507 1508 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1509 qxl_async_io async) 1510 { 1511 QXLDevSurfaceCreate surface; 1512 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1513 uint32_t requested_height = le32_to_cpu(sc->height); 1514 int requested_stride = le32_to_cpu(sc->stride); 1515 1516 if (requested_stride == INT32_MIN || 1517 abs(requested_stride) * (uint64_t)requested_height 1518 > qxl->vgamem_size) { 1519 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer" 1520 " stride %d x height %" PRIu32 " > %" PRIu32, 1521 __func__, requested_stride, requested_height, 1522 qxl->vgamem_size); 1523 return; 1524 } 1525 1526 if (qxl->mode == QXL_MODE_NATIVE) { 1527 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1528 __func__); 1529 } 1530 qxl_exit_vga_mode(qxl); 1531 1532 surface.format = le32_to_cpu(sc->format); 1533 surface.height = le32_to_cpu(sc->height); 1534 surface.mem = le64_to_cpu(sc->mem); 1535 surface.position = le32_to_cpu(sc->position); 1536 surface.stride = le32_to_cpu(sc->stride); 1537 surface.width = le32_to_cpu(sc->width); 1538 surface.type = le32_to_cpu(sc->type); 1539 surface.flags = le32_to_cpu(sc->flags); 1540 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1541 sc->format, sc->position); 1542 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1543 sc->flags); 1544 1545 if ((surface.stride & 0x3) != 0) { 1546 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1547 surface.stride); 1548 return; 1549 } 1550 1551 surface.mouse_mode = true; 1552 surface.group_id = MEMSLOT_GROUP_GUEST; 1553 if (loadvm) { 1554 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1555 } 1556 1557 qxl->mode = QXL_MODE_NATIVE; 1558 qxl->cmdflags = 0; 1559 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1560 1561 if (async == QXL_SYNC) { 1562 qxl_create_guest_primary_complete(qxl); 1563 } 1564 } 1565 1566 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1567 * done (in QXL_SYNC case), 0 otherwise. */ 1568 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1569 { 1570 if (d->mode == QXL_MODE_UNDEFINED) { 1571 return 0; 1572 } 1573 trace_qxl_destroy_primary(d->id); 1574 d->mode = QXL_MODE_UNDEFINED; 1575 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1576 qxl_spice_reset_cursor(d); 1577 return 1; 1578 } 1579 1580 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm) 1581 { 1582 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1583 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1584 QXLMode *mode = d->modes->modes + modenr; 1585 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1586 QXLMemSlot slot = { 1587 .mem_start = start, 1588 .mem_end = end 1589 }; 1590 1591 if (modenr >= d->modes->n_modes) { 1592 qxl_set_guest_bug(d, "mode number out of range"); 1593 return; 1594 } 1595 1596 QXLSurfaceCreate surface = { 1597 .width = mode->x_res, 1598 .height = mode->y_res, 1599 .stride = -mode->x_res * 4, 1600 .format = SPICE_SURFACE_FMT_32_xRGB, 1601 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1602 .mouse_mode = true, 1603 .mem = devmem + d->shadow_rom.draw_area_offset, 1604 }; 1605 1606 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1607 devmem); 1608 if (!loadvm) { 1609 qxl_hard_reset(d, 0); 1610 } 1611 1612 d->guest_slots[0].slot = slot; 1613 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1614 1615 d->guest_primary.surface = surface; 1616 qxl_create_guest_primary(d, 0, QXL_SYNC); 1617 1618 d->mode = QXL_MODE_COMPAT; 1619 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1620 if (mode->bits == 16) { 1621 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1622 } 1623 d->shadow_rom.mode = cpu_to_le32(modenr); 1624 d->rom->mode = cpu_to_le32(modenr); 1625 qxl_rom_set_dirty(d); 1626 } 1627 1628 static void ioport_write(void *opaque, hwaddr addr, 1629 uint64_t val, unsigned size) 1630 { 1631 PCIQXLDevice *d = opaque; 1632 uint32_t io_port = addr; 1633 qxl_async_io async = QXL_SYNC; 1634 uint32_t orig_io_port = io_port; 1635 1636 if (d->guest_bug && io_port != QXL_IO_RESET) { 1637 return; 1638 } 1639 1640 if (d->revision <= QXL_REVISION_STABLE_V10 && 1641 io_port > QXL_IO_FLUSH_RELEASE) { 1642 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1643 io_port, d->revision); 1644 return; 1645 } 1646 1647 switch (io_port) { 1648 case QXL_IO_RESET: 1649 case QXL_IO_SET_MODE: 1650 case QXL_IO_MEMSLOT_ADD: 1651 case QXL_IO_MEMSLOT_DEL: 1652 case QXL_IO_CREATE_PRIMARY: 1653 case QXL_IO_UPDATE_IRQ: 1654 case QXL_IO_LOG: 1655 case QXL_IO_MEMSLOT_ADD_ASYNC: 1656 case QXL_IO_CREATE_PRIMARY_ASYNC: 1657 break; 1658 default: 1659 if (d->mode != QXL_MODE_VGA) { 1660 break; 1661 } 1662 trace_qxl_io_unexpected_vga_mode(d->id, 1663 addr, val, io_port_to_string(io_port)); 1664 /* be nice to buggy guest drivers */ 1665 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1666 io_port < QXL_IO_RANGE_SIZE) { 1667 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1668 } 1669 return; 1670 } 1671 1672 /* we change the io_port to avoid ifdeffery in the main switch */ 1673 orig_io_port = io_port; 1674 switch (io_port) { 1675 case QXL_IO_UPDATE_AREA_ASYNC: 1676 io_port = QXL_IO_UPDATE_AREA; 1677 goto async_common; 1678 case QXL_IO_MEMSLOT_ADD_ASYNC: 1679 io_port = QXL_IO_MEMSLOT_ADD; 1680 goto async_common; 1681 case QXL_IO_CREATE_PRIMARY_ASYNC: 1682 io_port = QXL_IO_CREATE_PRIMARY; 1683 goto async_common; 1684 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1685 io_port = QXL_IO_DESTROY_PRIMARY; 1686 goto async_common; 1687 case QXL_IO_DESTROY_SURFACE_ASYNC: 1688 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1689 goto async_common; 1690 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1691 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1692 goto async_common; 1693 case QXL_IO_FLUSH_SURFACES_ASYNC: 1694 case QXL_IO_MONITORS_CONFIG_ASYNC: 1695 async_common: 1696 async = QXL_ASYNC; 1697 qemu_mutex_lock(&d->async_lock); 1698 if (d->current_async != QXL_UNDEFINED_IO) { 1699 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1700 io_port, d->current_async); 1701 qemu_mutex_unlock(&d->async_lock); 1702 return; 1703 } 1704 d->current_async = orig_io_port; 1705 qemu_mutex_unlock(&d->async_lock); 1706 break; 1707 default: 1708 break; 1709 } 1710 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), 1711 addr, io_port_to_string(addr), 1712 val, size, async); 1713 1714 switch (io_port) { 1715 case QXL_IO_UPDATE_AREA: 1716 { 1717 QXLCookie *cookie = NULL; 1718 QXLRect update = d->ram->update_area; 1719 1720 if (d->ram->update_surface > d->ssd.num_surfaces) { 1721 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1722 d->ram->update_surface); 1723 break; 1724 } 1725 if (update.left >= update.right || update.top >= update.bottom || 1726 update.left < 0 || update.top < 0) { 1727 qxl_set_guest_bug(d, 1728 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1729 update.left, update.top, update.right, update.bottom); 1730 if (update.left == update.right || update.top == update.bottom) { 1731 /* old drivers may provide empty area, keep going */ 1732 qxl_clear_guest_bug(d); 1733 goto cancel_async; 1734 } 1735 break; 1736 } 1737 if (async == QXL_ASYNC) { 1738 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1739 QXL_IO_UPDATE_AREA_ASYNC); 1740 cookie->u.area = update; 1741 } 1742 qxl_spice_update_area(d, d->ram->update_surface, 1743 cookie ? &cookie->u.area : &update, 1744 NULL, 0, 0, async, cookie); 1745 break; 1746 } 1747 case QXL_IO_NOTIFY_CMD: 1748 qemu_spice_wakeup(&d->ssd); 1749 break; 1750 case QXL_IO_NOTIFY_CURSOR: 1751 qemu_spice_wakeup(&d->ssd); 1752 break; 1753 case QXL_IO_UPDATE_IRQ: 1754 qxl_update_irq(d); 1755 break; 1756 case QXL_IO_NOTIFY_OOM: 1757 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1758 break; 1759 } 1760 d->oom_running = 1; 1761 qxl_spice_oom(d); 1762 d->oom_running = 0; 1763 break; 1764 case QXL_IO_SET_MODE: 1765 qxl_set_mode(d, val, 0); 1766 break; 1767 case QXL_IO_LOG: 1768 trace_qxl_io_log(d->id, d->ram->log_buf); 1769 if (d->guestdebug) { 1770 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1771 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf); 1772 } 1773 break; 1774 case QXL_IO_RESET: 1775 qxl_hard_reset(d, 0); 1776 break; 1777 case QXL_IO_MEMSLOT_ADD: 1778 if (val >= NUM_MEMSLOTS) { 1779 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1780 break; 1781 } 1782 if (d->guest_slots[val].active) { 1783 qxl_set_guest_bug(d, 1784 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1785 break; 1786 } 1787 d->guest_slots[val].slot = d->ram->mem_slot; 1788 qxl_add_memslot(d, val, 0, async); 1789 break; 1790 case QXL_IO_MEMSLOT_DEL: 1791 if (val >= NUM_MEMSLOTS) { 1792 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1793 break; 1794 } 1795 qxl_del_memslot(d, val); 1796 break; 1797 case QXL_IO_CREATE_PRIMARY: 1798 if (val != 0) { 1799 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1800 async); 1801 goto cancel_async; 1802 } 1803 d->guest_primary.surface = d->ram->create_surface; 1804 qxl_create_guest_primary(d, 0, async); 1805 break; 1806 case QXL_IO_DESTROY_PRIMARY: 1807 if (val != 0) { 1808 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1809 async); 1810 goto cancel_async; 1811 } 1812 if (!qxl_destroy_primary(d, async)) { 1813 trace_qxl_io_destroy_primary_ignored(d->id, 1814 qxl_mode_to_string(d->mode)); 1815 goto cancel_async; 1816 } 1817 break; 1818 case QXL_IO_DESTROY_SURFACE_WAIT: 1819 if (val >= d->ssd.num_surfaces) { 1820 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1821 "%" PRIu64 " >= NUM_SURFACES", async, val); 1822 goto cancel_async; 1823 } 1824 qxl_spice_destroy_surface_wait(d, val, async); 1825 break; 1826 case QXL_IO_FLUSH_RELEASE: { 1827 QXLReleaseRing *ring = &d->ram->release_ring; 1828 if (ring->prod - ring->cons + 1 == ring->num_items) { 1829 fprintf(stderr, 1830 "ERROR: no flush, full release ring [p%d,%dc]\n", 1831 ring->prod, ring->cons); 1832 } 1833 qxl_push_free_res(d, 1 /* flush */); 1834 break; 1835 } 1836 case QXL_IO_FLUSH_SURFACES_ASYNC: 1837 qxl_spice_flush_surfaces_async(d); 1838 break; 1839 case QXL_IO_DESTROY_ALL_SURFACES: 1840 d->mode = QXL_MODE_UNDEFINED; 1841 qxl_spice_destroy_surfaces(d, async); 1842 break; 1843 case QXL_IO_MONITORS_CONFIG_ASYNC: 1844 qxl_spice_monitors_config_async(d, 0); 1845 break; 1846 default: 1847 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1848 } 1849 return; 1850 cancel_async: 1851 if (async) { 1852 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1853 qemu_mutex_lock(&d->async_lock); 1854 d->current_async = QXL_UNDEFINED_IO; 1855 qemu_mutex_unlock(&d->async_lock); 1856 } 1857 } 1858 1859 static uint64_t ioport_read(void *opaque, hwaddr addr, 1860 unsigned size) 1861 { 1862 PCIQXLDevice *qxl = opaque; 1863 1864 trace_qxl_io_read_unexpected(qxl->id); 1865 return 0xff; 1866 } 1867 1868 static const MemoryRegionOps qxl_io_ops = { 1869 .read = ioport_read, 1870 .write = ioport_write, 1871 .valid = { 1872 .min_access_size = 1, 1873 .max_access_size = 1, 1874 }, 1875 }; 1876 1877 static void qxl_update_irq_bh(void *opaque) 1878 { 1879 PCIQXLDevice *d = opaque; 1880 qxl_update_irq(d); 1881 } 1882 1883 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1884 { 1885 uint32_t old_pending; 1886 uint32_t le_events = cpu_to_le32(events); 1887 1888 trace_qxl_send_events(d->id, events); 1889 if (!qemu_spice_display_is_running(&d->ssd)) { 1890 /* spice-server tracks guest running state and should not do this */ 1891 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1892 __func__); 1893 trace_qxl_send_events_vm_stopped(d->id, events); 1894 return; 1895 } 1896 /* 1897 * Older versions of Spice forgot to define the QXLRam struct 1898 * with the '__aligned__(4)' attribute. clang 7 and newer will 1899 * thus warn that atomic_fetch_or(&d->ram->int_pending, ...) 1900 * might be a misaligned atomic access, and will generate an 1901 * out-of-line call for it, which results in a link error since 1902 * we don't currently link against libatomic. 1903 * 1904 * In fact we set up d->ram in init_qxl_ram() so it always starts 1905 * at a 4K boundary, so we know that &d->ram->int_pending is 1906 * naturally aligned for a uint32_t. Newer Spice versions 1907 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1) 1908 * will fix the bug directly. To deal with older versions, 1909 * we tell the compiler to assume the address really is aligned. 1910 * Any compiler which cares about the misalignment will have 1911 * __builtin_assume_aligned. 1912 */ 1913 #ifdef HAS_ASSUME_ALIGNED 1914 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4)) 1915 #else 1916 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P) 1917 #endif 1918 1919 old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending), 1920 le_events); 1921 if ((old_pending & le_events) == le_events) { 1922 return; 1923 } 1924 qemu_bh_schedule(d->update_irq); 1925 } 1926 1927 /* graphics console */ 1928 1929 static void qxl_hw_update(void *opaque) 1930 { 1931 PCIQXLDevice *qxl = opaque; 1932 1933 qxl_render_update(qxl); 1934 } 1935 1936 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, 1937 uint32_t height, int32_t stride) 1938 { 1939 uint64_t offset, size; 1940 uint32_t slot; 1941 bool rc; 1942 1943 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset); 1944 assert(rc == true); 1945 size = (uint64_t)height * abs(stride); 1946 trace_qxl_surfaces_dirty(qxl->id, offset, size); 1947 qxl_set_dirty(qxl->guest_slots[slot].mr, 1948 qxl->guest_slots[slot].offset + offset, 1949 qxl->guest_slots[slot].offset + offset + size); 1950 } 1951 1952 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1953 { 1954 int i; 1955 1956 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1957 return; 1958 } 1959 1960 /* dirty the primary surface */ 1961 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem, 1962 qxl->guest_primary.surface.height, 1963 qxl->guest_primary.surface.stride); 1964 1965 /* dirty the off-screen surfaces */ 1966 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1967 QXLSurfaceCmd *cmd; 1968 1969 if (qxl->guest_surfaces.cmds[i] == 0) { 1970 continue; 1971 } 1972 1973 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1974 MEMSLOT_GROUP_GUEST); 1975 assert(cmd); 1976 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1977 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data, 1978 cmd->u.surface_create.height, 1979 cmd->u.surface_create.stride); 1980 } 1981 } 1982 1983 static void qxl_vm_change_state_handler(void *opaque, int running, 1984 RunState state) 1985 { 1986 PCIQXLDevice *qxl = opaque; 1987 1988 if (running) { 1989 /* 1990 * if qxl_send_events was called from spice server context before 1991 * migration ended, qxl_update_irq for these events might not have been 1992 * called 1993 */ 1994 qxl_update_irq(qxl); 1995 } else { 1996 /* make sure surfaces are saved before migration */ 1997 qxl_dirty_surfaces(qxl); 1998 } 1999 } 2000 2001 /* display change listener */ 2002 2003 static void display_update(DisplayChangeListener *dcl, 2004 int x, int y, int w, int h) 2005 { 2006 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2007 2008 if (qxl->mode == QXL_MODE_VGA) { 2009 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 2010 } 2011 } 2012 2013 static void display_switch(DisplayChangeListener *dcl, 2014 struct DisplaySurface *surface) 2015 { 2016 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2017 2018 qxl->ssd.ds = surface; 2019 if (qxl->mode == QXL_MODE_VGA) { 2020 qemu_spice_display_switch(&qxl->ssd, surface); 2021 } 2022 } 2023 2024 static void display_refresh(DisplayChangeListener *dcl) 2025 { 2026 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2027 2028 if (qxl->mode == QXL_MODE_VGA) { 2029 qemu_spice_display_refresh(&qxl->ssd); 2030 } 2031 } 2032 2033 static DisplayChangeListenerOps display_listener_ops = { 2034 .dpy_name = "spice/qxl", 2035 .dpy_gfx_update = display_update, 2036 .dpy_gfx_switch = display_switch, 2037 .dpy_refresh = display_refresh, 2038 }; 2039 2040 static void qxl_init_ramsize(PCIQXLDevice *qxl) 2041 { 2042 /* vga mode framebuffer / primary surface (bar 0, first part) */ 2043 if (qxl->vgamem_size_mb < 8) { 2044 qxl->vgamem_size_mb = 8; 2045 } 2046 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be 2047 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now). 2048 */ 2049 if (qxl->vgamem_size_mb > 256) { 2050 qxl->vgamem_size_mb = 256; 2051 } 2052 qxl->vgamem_size = qxl->vgamem_size_mb * MiB; 2053 2054 /* vga ram (bar 0, total) */ 2055 if (qxl->ram_size_mb != -1) { 2056 qxl->vga.vram_size = qxl->ram_size_mb * MiB; 2057 } 2058 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 2059 qxl->vga.vram_size = qxl->vgamem_size * 2; 2060 } 2061 2062 /* vram32 (surfaces, 32bit, bar 1) */ 2063 if (qxl->vram32_size_mb != -1) { 2064 qxl->vram32_size = qxl->vram32_size_mb * MiB; 2065 } 2066 if (qxl->vram32_size < 4096) { 2067 qxl->vram32_size = 4096; 2068 } 2069 2070 /* vram (surfaces, 64bit, bar 4+5) */ 2071 if (qxl->vram_size_mb != -1) { 2072 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB; 2073 } 2074 if (qxl->vram_size < qxl->vram32_size) { 2075 qxl->vram_size = qxl->vram32_size; 2076 } 2077 2078 if (qxl->revision == 1) { 2079 qxl->vram32_size = 4096; 2080 qxl->vram_size = 4096; 2081 } 2082 qxl->vgamem_size = pow2ceil(qxl->vgamem_size); 2083 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size); 2084 qxl->vram32_size = pow2ceil(qxl->vram32_size); 2085 qxl->vram_size = pow2ceil(qxl->vram_size); 2086 } 2087 2088 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp) 2089 { 2090 uint8_t* config = qxl->pci.config; 2091 uint32_t pci_device_rev; 2092 uint32_t io_size; 2093 2094 qemu_spice_display_init_common(&qxl->ssd); 2095 qxl->mode = QXL_MODE_UNDEFINED; 2096 qxl->num_memslots = NUM_MEMSLOTS; 2097 qemu_mutex_init(&qxl->track_lock); 2098 qemu_mutex_init(&qxl->async_lock); 2099 qxl->current_async = QXL_UNDEFINED_IO; 2100 qxl->guest_bug = 0; 2101 2102 switch (qxl->revision) { 2103 case 1: /* spice 0.4 -- qxl-1 */ 2104 pci_device_rev = QXL_REVISION_STABLE_V04; 2105 io_size = 8; 2106 break; 2107 case 2: /* spice 0.6 -- qxl-2 */ 2108 pci_device_rev = QXL_REVISION_STABLE_V06; 2109 io_size = 16; 2110 break; 2111 case 3: /* qxl-3 */ 2112 pci_device_rev = QXL_REVISION_STABLE_V10; 2113 io_size = 32; /* PCI region size must be pow2 */ 2114 break; 2115 case 4: /* qxl-4 */ 2116 pci_device_rev = QXL_REVISION_STABLE_V12; 2117 io_size = pow2ceil(QXL_IO_RANGE_SIZE); 2118 break; 2119 default: 2120 error_setg(errp, "Invalid revision %d for qxl device (max %d)", 2121 qxl->revision, QXL_DEFAULT_REVISION); 2122 return; 2123 } 2124 2125 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 2126 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 2127 2128 qxl->rom_size = qxl_rom_size(); 2129 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", 2130 qxl->rom_size, &error_fatal); 2131 init_qxl_rom(qxl); 2132 init_qxl_ram(qxl); 2133 2134 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 2135 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", 2136 qxl->vram_size, &error_fatal); 2137 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32", 2138 &qxl->vram_bar, 0, qxl->vram32_size); 2139 2140 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl, 2141 "qxl-ioports", io_size); 2142 if (qxl->have_vga) { 2143 vga_dirty_log_start(&qxl->vga); 2144 } 2145 memory_region_set_flush_coalesced(&qxl->io_bar); 2146 2147 2148 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 2149 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 2150 2151 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 2152 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 2153 2154 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 2155 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 2156 2157 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 2158 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 2159 2160 if (qxl->vram32_size < qxl->vram_size) { 2161 /* 2162 * Make the 64bit vram bar show up only in case it is 2163 * configured to be larger than the 32bit vram bar. 2164 */ 2165 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 2166 PCI_BASE_ADDRESS_SPACE_MEMORY | 2167 PCI_BASE_ADDRESS_MEM_TYPE_64 | 2168 PCI_BASE_ADDRESS_MEM_PREFETCH, 2169 &qxl->vram_bar); 2170 } 2171 2172 /* print pci bar details */ 2173 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n", 2174 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB); 2175 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n", 2176 qxl->vram32_size / MiB); 2177 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n", 2178 qxl->vram_size / MiB, 2179 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2180 2181 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2182 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) { 2183 error_setg(errp, "qxl interface %d.%d not supported by spice-server", 2184 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2185 return; 2186 } 2187 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2188 2189 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl); 2190 qxl_reset_state(qxl); 2191 2192 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2193 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd); 2194 } 2195 2196 static void qxl_realize_primary(PCIDevice *dev, Error **errp) 2197 { 2198 PCIQXLDevice *qxl = PCI_QXL(dev); 2199 VGACommonState *vga = &qxl->vga; 2200 Error *local_err = NULL; 2201 2202 qxl_init_ramsize(qxl); 2203 vga->vbe_size = qxl->vgamem_size; 2204 vga->vram_size_mb = qxl->vga.vram_size / MiB; 2205 vga_common_init(vga, OBJECT(dev)); 2206 vga_init(vga, OBJECT(dev), 2207 pci_address_space(dev), pci_address_space_io(dev), false); 2208 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list, 2209 vga, "vga"); 2210 portio_list_set_flush_coalesced(&qxl->vga_port_list); 2211 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0); 2212 qxl->have_vga = true; 2213 2214 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2215 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */ 2216 if (qxl->id != 0) { 2217 error_setg(errp, "primary qxl-vga device must be console 0 " 2218 "(first display device on the command line)"); 2219 return; 2220 } 2221 2222 qxl_realize_common(qxl, &local_err); 2223 if (local_err) { 2224 error_propagate(errp, local_err); 2225 return; 2226 } 2227 2228 qxl->ssd.dcl.ops = &display_listener_ops; 2229 qxl->ssd.dcl.con = vga->con; 2230 register_displaychangelistener(&qxl->ssd.dcl); 2231 } 2232 2233 static void qxl_realize_secondary(PCIDevice *dev, Error **errp) 2234 { 2235 PCIQXLDevice *qxl = PCI_QXL(dev); 2236 2237 qxl_init_ramsize(qxl); 2238 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram", 2239 qxl->vga.vram_size, &error_fatal); 2240 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2241 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2242 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */ 2243 2244 qxl_realize_common(qxl, errp); 2245 } 2246 2247 static int qxl_pre_save(void *opaque) 2248 { 2249 PCIQXLDevice* d = opaque; 2250 uint8_t *ram_start = d->vga.vram_ptr; 2251 2252 trace_qxl_pre_save(d->id); 2253 if (d->last_release == NULL) { 2254 d->last_release_offset = 0; 2255 } else { 2256 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2257 } 2258 assert(d->last_release_offset < d->vga.vram_size); 2259 2260 return 0; 2261 } 2262 2263 static int qxl_pre_load(void *opaque) 2264 { 2265 PCIQXLDevice* d = opaque; 2266 2267 trace_qxl_pre_load(d->id); 2268 qxl_hard_reset(d, 1); 2269 qxl_exit_vga_mode(d); 2270 return 0; 2271 } 2272 2273 static void qxl_create_memslots(PCIQXLDevice *d) 2274 { 2275 int i; 2276 2277 for (i = 0; i < NUM_MEMSLOTS; i++) { 2278 if (!d->guest_slots[i].active) { 2279 continue; 2280 } 2281 qxl_add_memslot(d, i, 0, QXL_SYNC); 2282 } 2283 } 2284 2285 static int qxl_post_load(void *opaque, int version) 2286 { 2287 PCIQXLDevice* d = opaque; 2288 uint8_t *ram_start = d->vga.vram_ptr; 2289 QXLCommandExt *cmds; 2290 int in, out, newmode; 2291 2292 assert(d->last_release_offset < d->vga.vram_size); 2293 if (d->last_release_offset == 0) { 2294 d->last_release = NULL; 2295 } else { 2296 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2297 } 2298 2299 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2300 2301 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2302 newmode = d->mode; 2303 d->mode = QXL_MODE_UNDEFINED; 2304 2305 switch (newmode) { 2306 case QXL_MODE_UNDEFINED: 2307 qxl_create_memslots(d); 2308 break; 2309 case QXL_MODE_VGA: 2310 qxl_create_memslots(d); 2311 qxl_enter_vga_mode(d); 2312 break; 2313 case QXL_MODE_NATIVE: 2314 qxl_create_memslots(d); 2315 qxl_create_guest_primary(d, 1, QXL_SYNC); 2316 2317 /* replay surface-create and cursor-set commands */ 2318 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1); 2319 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2320 if (d->guest_surfaces.cmds[in] == 0) { 2321 continue; 2322 } 2323 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2324 cmds[out].cmd.type = QXL_CMD_SURFACE; 2325 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2326 out++; 2327 } 2328 if (d->guest_cursor) { 2329 cmds[out].cmd.data = d->guest_cursor; 2330 cmds[out].cmd.type = QXL_CMD_CURSOR; 2331 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2332 out++; 2333 } 2334 qxl_spice_loadvm_commands(d, cmds, out); 2335 g_free(cmds); 2336 if (d->guest_monitors_config) { 2337 qxl_spice_monitors_config_async(d, 1); 2338 } 2339 break; 2340 case QXL_MODE_COMPAT: 2341 /* note: no need to call qxl_create_memslots, qxl_set_mode 2342 * creates the mem slot. */ 2343 qxl_set_mode(d, d->shadow_rom.mode, 1); 2344 break; 2345 } 2346 return 0; 2347 } 2348 2349 #define QXL_SAVE_VERSION 21 2350 2351 static bool qxl_monitors_config_needed(void *opaque) 2352 { 2353 PCIQXLDevice *qxl = opaque; 2354 2355 return qxl->guest_monitors_config != 0; 2356 } 2357 2358 2359 static VMStateDescription qxl_memslot = { 2360 .name = "qxl-memslot", 2361 .version_id = QXL_SAVE_VERSION, 2362 .minimum_version_id = QXL_SAVE_VERSION, 2363 .fields = (VMStateField[]) { 2364 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2365 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2366 VMSTATE_UINT32(active, struct guest_slots), 2367 VMSTATE_END_OF_LIST() 2368 } 2369 }; 2370 2371 static VMStateDescription qxl_surface = { 2372 .name = "qxl-surface", 2373 .version_id = QXL_SAVE_VERSION, 2374 .minimum_version_id = QXL_SAVE_VERSION, 2375 .fields = (VMStateField[]) { 2376 VMSTATE_UINT32(width, QXLSurfaceCreate), 2377 VMSTATE_UINT32(height, QXLSurfaceCreate), 2378 VMSTATE_INT32(stride, QXLSurfaceCreate), 2379 VMSTATE_UINT32(format, QXLSurfaceCreate), 2380 VMSTATE_UINT32(position, QXLSurfaceCreate), 2381 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2382 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2383 VMSTATE_UINT32(type, QXLSurfaceCreate), 2384 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2385 VMSTATE_END_OF_LIST() 2386 } 2387 }; 2388 2389 static VMStateDescription qxl_vmstate_monitors_config = { 2390 .name = "qxl/monitors-config", 2391 .version_id = 1, 2392 .minimum_version_id = 1, 2393 .needed = qxl_monitors_config_needed, 2394 .fields = (VMStateField[]) { 2395 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2396 VMSTATE_END_OF_LIST() 2397 }, 2398 }; 2399 2400 static VMStateDescription qxl_vmstate = { 2401 .name = "qxl", 2402 .version_id = QXL_SAVE_VERSION, 2403 .minimum_version_id = QXL_SAVE_VERSION, 2404 .pre_save = qxl_pre_save, 2405 .pre_load = qxl_pre_load, 2406 .post_load = qxl_post_load, 2407 .fields = (VMStateField[]) { 2408 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2409 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2410 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2411 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2412 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2413 VMSTATE_UINT32(mode, PCIQXLDevice), 2414 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2415 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL), 2416 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2417 qxl_memslot, struct guest_slots), 2418 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2419 qxl_surface, QXLSurfaceCreate), 2420 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL), 2421 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2422 ssd.num_surfaces, 0, 2423 vmstate_info_uint64, uint64_t), 2424 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2425 VMSTATE_END_OF_LIST() 2426 }, 2427 .subsections = (const VMStateDescription*[]) { 2428 &qxl_vmstate_monitors_config, 2429 NULL 2430 } 2431 }; 2432 2433 static Property qxl_properties[] = { 2434 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB), 2435 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB), 2436 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2437 QXL_DEFAULT_REVISION), 2438 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2439 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2440 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2441 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2442 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2443 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2444 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2445 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2446 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 2447 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0), 2448 #endif 2449 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0), 2450 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0), 2451 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false), 2452 DEFINE_PROP_END_OF_LIST(), 2453 }; 2454 2455 static void qxl_pci_class_init(ObjectClass *klass, void *data) 2456 { 2457 DeviceClass *dc = DEVICE_CLASS(klass); 2458 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2459 2460 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2461 k->device_id = QXL_DEVICE_ID_STABLE; 2462 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2463 dc->reset = qxl_reset_handler; 2464 dc->vmsd = &qxl_vmstate; 2465 dc->props = qxl_properties; 2466 } 2467 2468 static const TypeInfo qxl_pci_type_info = { 2469 .name = TYPE_PCI_QXL, 2470 .parent = TYPE_PCI_DEVICE, 2471 .instance_size = sizeof(PCIQXLDevice), 2472 .abstract = true, 2473 .class_init = qxl_pci_class_init, 2474 .interfaces = (InterfaceInfo[]) { 2475 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2476 { }, 2477 }, 2478 }; 2479 2480 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2481 { 2482 DeviceClass *dc = DEVICE_CLASS(klass); 2483 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2484 2485 k->realize = qxl_realize_primary; 2486 k->romfile = "vgabios-qxl.bin"; 2487 k->class_id = PCI_CLASS_DISPLAY_VGA; 2488 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2489 dc->hotpluggable = false; 2490 } 2491 2492 static const TypeInfo qxl_primary_info = { 2493 .name = "qxl-vga", 2494 .parent = TYPE_PCI_QXL, 2495 .class_init = qxl_primary_class_init, 2496 }; 2497 2498 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2499 { 2500 DeviceClass *dc = DEVICE_CLASS(klass); 2501 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2502 2503 k->realize = qxl_realize_secondary; 2504 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2505 dc->desc = "Spice QXL GPU (secondary)"; 2506 } 2507 2508 static const TypeInfo qxl_secondary_info = { 2509 .name = "qxl", 2510 .parent = TYPE_PCI_QXL, 2511 .class_init = qxl_secondary_class_init, 2512 }; 2513 2514 static void qxl_register_types(void) 2515 { 2516 type_register_static(&qxl_pci_type_info); 2517 type_register_static(&qxl_primary_info); 2518 type_register_static(&qxl_secondary_info); 2519 } 2520 2521 type_init(qxl_register_types) 2522