1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <zlib.h> 22 23 #include "qemu-common.h" 24 #include "qemu/timer.h" 25 #include "qemu/queue.h" 26 #include "monitor/monitor.h" 27 #include "sysemu/sysemu.h" 28 #include "trace.h" 29 30 #include "qxl.h" 31 32 /* 33 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as 34 * such can be changed by the guest, so to avoid a guest trigerrable 35 * abort we just qxl_set_guest_bug and set the return to NULL. Still 36 * it may happen as a result of emulator bug as well. 37 */ 38 #undef SPICE_RING_PROD_ITEM 39 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ 40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ 41 if (prod >= ARRAY_SIZE((r)->items)) { \ 42 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ 43 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ 44 ret = NULL; \ 45 } else { \ 46 ret = &(r)->items[prod].el; \ 47 } \ 48 } 49 50 #undef SPICE_RING_CONS_ITEM 51 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 52 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 53 if (cons >= ARRAY_SIZE((r)->items)) { \ 54 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 55 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 56 ret = NULL; \ 57 } else { \ 58 ret = &(r)->items[cons].el; \ 59 } \ 60 } 61 62 #undef ALIGN 63 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 64 65 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 66 67 #define QXL_MODE(_x, _y, _b, _o) \ 68 { .x_res = _x, \ 69 .y_res = _y, \ 70 .bits = _b, \ 71 .stride = (_x) * (_b) / 8, \ 72 .x_mili = PIXEL_SIZE * (_x), \ 73 .y_mili = PIXEL_SIZE * (_y), \ 74 .orientation = _o, \ 75 } 76 77 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 78 QXL_MODE(x_res, y_res, 16, orientation), \ 79 QXL_MODE(x_res, y_res, 32, orientation) 80 81 #define QXL_MODE_EX(x_res, y_res) \ 82 QXL_MODE_16_32(x_res, y_res, 0), \ 83 QXL_MODE_16_32(x_res, y_res, 1) 84 85 static QXLMode qxl_modes[] = { 86 QXL_MODE_EX(640, 480), 87 QXL_MODE_EX(800, 480), 88 QXL_MODE_EX(800, 600), 89 QXL_MODE_EX(832, 624), 90 QXL_MODE_EX(960, 640), 91 QXL_MODE_EX(1024, 600), 92 QXL_MODE_EX(1024, 768), 93 QXL_MODE_EX(1152, 864), 94 QXL_MODE_EX(1152, 870), 95 QXL_MODE_EX(1280, 720), 96 QXL_MODE_EX(1280, 760), 97 QXL_MODE_EX(1280, 768), 98 QXL_MODE_EX(1280, 800), 99 QXL_MODE_EX(1280, 960), 100 QXL_MODE_EX(1280, 1024), 101 QXL_MODE_EX(1360, 768), 102 QXL_MODE_EX(1366, 768), 103 QXL_MODE_EX(1400, 1050), 104 QXL_MODE_EX(1440, 900), 105 QXL_MODE_EX(1600, 900), 106 QXL_MODE_EX(1600, 1200), 107 QXL_MODE_EX(1680, 1050), 108 QXL_MODE_EX(1920, 1080), 109 /* these modes need more than 8 MB video memory */ 110 QXL_MODE_EX(1920, 1200), 111 QXL_MODE_EX(1920, 1440), 112 QXL_MODE_EX(2000, 2000), 113 QXL_MODE_EX(2048, 1536), 114 QXL_MODE_EX(2048, 2048), 115 QXL_MODE_EX(2560, 1440), 116 QXL_MODE_EX(2560, 1600), 117 /* these modes need more than 16 MB video memory */ 118 QXL_MODE_EX(2560, 2048), 119 QXL_MODE_EX(2800, 2100), 120 QXL_MODE_EX(3200, 2400), 121 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 122 QXL_MODE_EX(4096, 2160), /* 4k */ 123 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 124 QXL_MODE_EX(8192, 4320), /* 8k */ 125 }; 126 127 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 128 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 129 static void qxl_reset_memslots(PCIQXLDevice *d); 130 static void qxl_reset_surfaces(PCIQXLDevice *d); 131 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 132 133 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 134 { 135 trace_qxl_set_guest_bug(qxl->id); 136 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 137 qxl->guest_bug = 1; 138 if (qxl->guestdebug) { 139 va_list ap; 140 va_start(ap, msg); 141 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 142 vfprintf(stderr, msg, ap); 143 fprintf(stderr, "\n"); 144 va_end(ap); 145 } 146 } 147 148 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 149 { 150 qxl->guest_bug = 0; 151 } 152 153 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 154 struct QXLRect *area, struct QXLRect *dirty_rects, 155 uint32_t num_dirty_rects, 156 uint32_t clear_dirty_region, 157 qxl_async_io async, struct QXLCookie *cookie) 158 { 159 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 160 area->top, area->bottom); 161 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 162 clear_dirty_region); 163 if (async == QXL_SYNC) { 164 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, 165 dirty_rects, num_dirty_rects, clear_dirty_region); 166 } else { 167 assert(cookie != NULL); 168 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 169 clear_dirty_region, (uintptr_t)cookie); 170 } 171 } 172 173 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 174 uint32_t id) 175 { 176 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 177 qemu_mutex_lock(&qxl->track_lock); 178 qxl->guest_surfaces.cmds[id] = 0; 179 qxl->guest_surfaces.count--; 180 qemu_mutex_unlock(&qxl->track_lock); 181 } 182 183 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 184 qxl_async_io async) 185 { 186 QXLCookie *cookie; 187 188 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 189 if (async) { 190 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 191 QXL_IO_DESTROY_SURFACE_ASYNC); 192 cookie->u.surface_id = id; 193 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 194 } else { 195 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); 196 qxl_spice_destroy_surface_wait_complete(qxl, id); 197 } 198 } 199 200 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 201 { 202 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 203 qxl->num_free_res); 204 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 205 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 206 QXL_IO_FLUSH_SURFACES_ASYNC)); 207 } 208 209 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 210 uint32_t count) 211 { 212 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 213 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); 214 } 215 216 void qxl_spice_oom(PCIQXLDevice *qxl) 217 { 218 trace_qxl_spice_oom(qxl->id); 219 qxl->ssd.worker->oom(qxl->ssd.worker); 220 } 221 222 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 223 { 224 trace_qxl_spice_reset_memslots(qxl->id); 225 qxl->ssd.worker->reset_memslots(qxl->ssd.worker); 226 } 227 228 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 229 { 230 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 231 qemu_mutex_lock(&qxl->track_lock); 232 memset(qxl->guest_surfaces.cmds, 0, 233 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 234 qxl->guest_surfaces.count = 0; 235 qemu_mutex_unlock(&qxl->track_lock); 236 } 237 238 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 239 { 240 trace_qxl_spice_destroy_surfaces(qxl->id, async); 241 if (async) { 242 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 243 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 244 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 245 } else { 246 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); 247 qxl_spice_destroy_surfaces_complete(qxl); 248 } 249 } 250 251 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 252 { 253 trace_qxl_spice_monitors_config(qxl->id); 254 if (replay) { 255 /* 256 * don't use QXL_COOKIE_TYPE_IO: 257 * - we are not running yet (post_load), we will assert 258 * in send_events 259 * - this is not a guest io, but a reply, so async_io isn't set. 260 */ 261 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 262 qxl->guest_monitors_config, 263 MEMSLOT_GROUP_GUEST, 264 (uintptr_t)qxl_cookie_new( 265 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 266 0)); 267 } else { 268 qxl->guest_monitors_config = qxl->ram->monitors_config; 269 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 270 qxl->ram->monitors_config, 271 MEMSLOT_GROUP_GUEST, 272 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 273 QXL_IO_MONITORS_CONFIG_ASYNC)); 274 } 275 } 276 277 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 278 { 279 trace_qxl_spice_reset_image_cache(qxl->id); 280 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); 281 } 282 283 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 284 { 285 trace_qxl_spice_reset_cursor(qxl->id); 286 qxl->ssd.worker->reset_cursor(qxl->ssd.worker); 287 qemu_mutex_lock(&qxl->track_lock); 288 qxl->guest_cursor = 0; 289 qemu_mutex_unlock(&qxl->track_lock); 290 if (qxl->ssd.cursor) { 291 cursor_put(qxl->ssd.cursor); 292 } 293 qxl->ssd.cursor = cursor_builtin_hidden(); 294 } 295 296 297 static inline uint32_t msb_mask(uint32_t val) 298 { 299 uint32_t mask; 300 301 do { 302 mask = ~(val - 1) & val; 303 val &= ~mask; 304 } while (mask < val); 305 306 return mask; 307 } 308 309 static ram_addr_t qxl_rom_size(void) 310 { 311 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) + 312 sizeof(qxl_modes); 313 uint32_t rom_size = 8192; /* two pages */ 314 315 required_rom_size = MAX(required_rom_size, TARGET_PAGE_SIZE); 316 required_rom_size = msb_mask(required_rom_size * 2 - 1); 317 assert(required_rom_size <= rom_size); 318 return rom_size; 319 } 320 321 static void init_qxl_rom(PCIQXLDevice *d) 322 { 323 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 324 QXLModes *modes = (QXLModes *)(rom + 1); 325 uint32_t ram_header_size; 326 uint32_t surface0_area_size; 327 uint32_t num_pages; 328 uint32_t fb; 329 int i, n; 330 331 memset(rom, 0, d->rom_size); 332 333 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 334 rom->id = cpu_to_le32(d->id); 335 rom->log_level = cpu_to_le32(d->guestdebug); 336 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 337 338 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 339 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 340 rom->slots_start = 1; 341 rom->slots_end = NUM_MEMSLOTS - 1; 342 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 343 344 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 345 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 346 if (fb > d->vgamem_size) { 347 continue; 348 } 349 modes->modes[n].id = cpu_to_le32(i); 350 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 351 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 352 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 353 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 354 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 355 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 356 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 357 n++; 358 } 359 modes->n_modes = cpu_to_le32(n); 360 361 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 362 surface0_area_size = ALIGN(d->vgamem_size, 4096); 363 num_pages = d->vga.vram_size; 364 num_pages -= ram_header_size; 365 num_pages -= surface0_area_size; 366 num_pages = num_pages / TARGET_PAGE_SIZE; 367 368 rom->draw_area_offset = cpu_to_le32(0); 369 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 370 rom->pages_offset = cpu_to_le32(surface0_area_size); 371 rom->num_pages = cpu_to_le32(num_pages); 372 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 373 374 d->shadow_rom = *rom; 375 d->rom = rom; 376 d->modes = modes; 377 } 378 379 static void init_qxl_ram(PCIQXLDevice *d) 380 { 381 uint8_t *buf; 382 uint64_t *item; 383 384 buf = d->vga.vram_ptr; 385 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 386 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 387 d->ram->int_pending = cpu_to_le32(0); 388 d->ram->int_mask = cpu_to_le32(0); 389 d->ram->update_surface = 0; 390 SPICE_RING_INIT(&d->ram->cmd_ring); 391 SPICE_RING_INIT(&d->ram->cursor_ring); 392 SPICE_RING_INIT(&d->ram->release_ring); 393 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); 394 assert(item); 395 *item = 0; 396 qxl_ring_set_dirty(d); 397 } 398 399 /* can be called from spice server thread context */ 400 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 401 { 402 memory_region_set_dirty(mr, addr, end - addr); 403 } 404 405 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 406 { 407 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 408 } 409 410 /* called from spice server thread context only */ 411 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 412 { 413 void *base = qxl->vga.vram_ptr; 414 intptr_t offset; 415 416 offset = ptr - base; 417 offset &= ~(TARGET_PAGE_SIZE-1); 418 assert(offset < qxl->vga.vram_size); 419 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); 420 } 421 422 /* can be called from spice server thread context */ 423 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 424 { 425 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 426 ram_addr_t end = qxl->vga.vram_size; 427 qxl_set_dirty(&qxl->vga.vram, addr, end); 428 } 429 430 /* 431 * keep track of some command state, for savevm/loadvm. 432 * called from spice server thread context only 433 */ 434 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 435 { 436 switch (le32_to_cpu(ext->cmd.type)) { 437 case QXL_CMD_SURFACE: 438 { 439 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 440 441 if (!cmd) { 442 return 1; 443 } 444 uint32_t id = le32_to_cpu(cmd->surface_id); 445 446 if (id >= qxl->ssd.num_surfaces) { 447 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 448 qxl->ssd.num_surfaces); 449 return 1; 450 } 451 if (cmd->type == QXL_SURFACE_CMD_CREATE && 452 (cmd->u.surface_create.stride & 0x03) != 0) { 453 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 454 cmd->u.surface_create.stride); 455 return 1; 456 } 457 qemu_mutex_lock(&qxl->track_lock); 458 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 459 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 460 qxl->guest_surfaces.count++; 461 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) 462 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 463 } 464 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 465 qxl->guest_surfaces.cmds[id] = 0; 466 qxl->guest_surfaces.count--; 467 } 468 qemu_mutex_unlock(&qxl->track_lock); 469 break; 470 } 471 case QXL_CMD_CURSOR: 472 { 473 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 474 475 if (!cmd) { 476 return 1; 477 } 478 if (cmd->type == QXL_CURSOR_SET) { 479 qemu_mutex_lock(&qxl->track_lock); 480 qxl->guest_cursor = ext->cmd.data; 481 qemu_mutex_unlock(&qxl->track_lock); 482 } 483 break; 484 } 485 } 486 return 0; 487 } 488 489 /* spice display interface callbacks */ 490 491 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 492 { 493 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 494 495 trace_qxl_interface_attach_worker(qxl->id); 496 qxl->ssd.worker = qxl_worker; 497 } 498 499 static void interface_set_compression_level(QXLInstance *sin, int level) 500 { 501 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 502 503 trace_qxl_interface_set_compression_level(qxl->id, level); 504 qxl->shadow_rom.compression_level = cpu_to_le32(level); 505 qxl->rom->compression_level = cpu_to_le32(level); 506 qxl_rom_set_dirty(qxl); 507 } 508 509 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 510 { 511 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 512 513 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 514 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 515 qxl->rom->mm_clock = cpu_to_le32(mm_time); 516 qxl_rom_set_dirty(qxl); 517 } 518 519 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 520 { 521 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 522 523 trace_qxl_interface_get_init_info(qxl->id); 524 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 525 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 526 info->num_memslots = NUM_MEMSLOTS; 527 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 528 info->internal_groupslot_id = 0; 529 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; 530 info->n_surfaces = qxl->ssd.num_surfaces; 531 } 532 533 static const char *qxl_mode_to_string(int mode) 534 { 535 switch (mode) { 536 case QXL_MODE_COMPAT: 537 return "compat"; 538 case QXL_MODE_NATIVE: 539 return "native"; 540 case QXL_MODE_UNDEFINED: 541 return "undefined"; 542 case QXL_MODE_VGA: 543 return "vga"; 544 } 545 return "INVALID"; 546 } 547 548 static const char *io_port_to_string(uint32_t io_port) 549 { 550 if (io_port >= QXL_IO_RANGE_SIZE) { 551 return "out of range"; 552 } 553 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 554 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 555 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 556 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 557 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 558 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 559 [QXL_IO_RESET] = "QXL_IO_RESET", 560 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 561 [QXL_IO_LOG] = "QXL_IO_LOG", 562 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 563 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 564 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 565 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 566 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 567 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 568 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 569 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 570 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 571 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 572 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 573 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 574 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 575 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 576 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 577 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 578 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 579 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 580 }; 581 return io_port_to_string[io_port]; 582 } 583 584 /* called from spice server thread context only */ 585 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 586 { 587 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 588 SimpleSpiceUpdate *update; 589 QXLCommandRing *ring; 590 QXLCommand *cmd; 591 int notify, ret; 592 593 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 594 595 switch (qxl->mode) { 596 case QXL_MODE_VGA: 597 ret = false; 598 qemu_mutex_lock(&qxl->ssd.lock); 599 update = QTAILQ_FIRST(&qxl->ssd.updates); 600 if (update != NULL) { 601 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 602 *ext = update->ext; 603 ret = true; 604 } 605 qemu_mutex_unlock(&qxl->ssd.lock); 606 if (ret) { 607 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 608 qxl_log_command(qxl, "vga", ext); 609 } 610 return ret; 611 case QXL_MODE_COMPAT: 612 case QXL_MODE_NATIVE: 613 case QXL_MODE_UNDEFINED: 614 ring = &qxl->ram->cmd_ring; 615 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 616 return false; 617 } 618 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 619 if (!cmd) { 620 return false; 621 } 622 ext->cmd = *cmd; 623 ext->group_id = MEMSLOT_GROUP_GUEST; 624 ext->flags = qxl->cmdflags; 625 SPICE_RING_POP(ring, notify); 626 qxl_ring_set_dirty(qxl); 627 if (notify) { 628 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 629 } 630 qxl->guest_primary.commands++; 631 qxl_track_command(qxl, ext); 632 qxl_log_command(qxl, "cmd", ext); 633 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 634 return true; 635 default: 636 return false; 637 } 638 } 639 640 /* called from spice server thread context only */ 641 static int interface_req_cmd_notification(QXLInstance *sin) 642 { 643 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 644 int wait = 1; 645 646 trace_qxl_ring_command_req_notification(qxl->id); 647 switch (qxl->mode) { 648 case QXL_MODE_COMPAT: 649 case QXL_MODE_NATIVE: 650 case QXL_MODE_UNDEFINED: 651 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 652 qxl_ring_set_dirty(qxl); 653 break; 654 default: 655 /* nothing */ 656 break; 657 } 658 return wait; 659 } 660 661 /* called from spice server thread context only */ 662 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 663 { 664 QXLReleaseRing *ring = &d->ram->release_ring; 665 uint64_t *item; 666 int notify; 667 668 #define QXL_FREE_BUNCH_SIZE 32 669 670 if (ring->prod - ring->cons + 1 == ring->num_items) { 671 /* ring full -- can't push */ 672 return; 673 } 674 if (!flush && d->oom_running) { 675 /* collect everything from oom handler before pushing */ 676 return; 677 } 678 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 679 /* collect a bit more before pushing */ 680 return; 681 } 682 683 SPICE_RING_PUSH(ring, notify); 684 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 685 d->guest_surfaces.count, d->num_free_res, 686 d->last_release, notify ? "yes" : "no"); 687 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 688 ring->num_items, ring->prod, ring->cons); 689 if (notify) { 690 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 691 } 692 SPICE_RING_PROD_ITEM(d, ring, item); 693 if (!item) { 694 return; 695 } 696 *item = 0; 697 d->num_free_res = 0; 698 d->last_release = NULL; 699 qxl_ring_set_dirty(d); 700 } 701 702 /* called from spice server thread context only */ 703 static void interface_release_resource(QXLInstance *sin, 704 struct QXLReleaseInfoExt ext) 705 { 706 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 707 QXLReleaseRing *ring; 708 uint64_t *item, id; 709 710 if (ext.group_id == MEMSLOT_GROUP_HOST) { 711 /* host group -> vga mode update request */ 712 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id); 713 return; 714 } 715 716 /* 717 * ext->info points into guest-visible memory 718 * pci bar 0, $command.release_info 719 */ 720 ring = &qxl->ram->release_ring; 721 SPICE_RING_PROD_ITEM(qxl, ring, item); 722 if (!item) { 723 return; 724 } 725 if (*item == 0) { 726 /* stick head into the ring */ 727 id = ext.info->id; 728 ext.info->next = 0; 729 qxl_ram_set_dirty(qxl, &ext.info->next); 730 *item = id; 731 qxl_ring_set_dirty(qxl); 732 } else { 733 /* append item to the list */ 734 qxl->last_release->next = ext.info->id; 735 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 736 ext.info->next = 0; 737 qxl_ram_set_dirty(qxl, &ext.info->next); 738 } 739 qxl->last_release = ext.info; 740 qxl->num_free_res++; 741 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 742 qxl_push_free_res(qxl, 0); 743 } 744 745 /* called from spice server thread context only */ 746 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 747 { 748 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 749 QXLCursorRing *ring; 750 QXLCommand *cmd; 751 int notify; 752 753 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 754 755 switch (qxl->mode) { 756 case QXL_MODE_COMPAT: 757 case QXL_MODE_NATIVE: 758 case QXL_MODE_UNDEFINED: 759 ring = &qxl->ram->cursor_ring; 760 if (SPICE_RING_IS_EMPTY(ring)) { 761 return false; 762 } 763 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 764 if (!cmd) { 765 return false; 766 } 767 ext->cmd = *cmd; 768 ext->group_id = MEMSLOT_GROUP_GUEST; 769 ext->flags = qxl->cmdflags; 770 SPICE_RING_POP(ring, notify); 771 qxl_ring_set_dirty(qxl); 772 if (notify) { 773 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 774 } 775 qxl->guest_primary.commands++; 776 qxl_track_command(qxl, ext); 777 qxl_log_command(qxl, "csr", ext); 778 if (qxl->id == 0) { 779 qxl_render_cursor(qxl, ext); 780 } 781 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 782 return true; 783 default: 784 return false; 785 } 786 } 787 788 /* called from spice server thread context only */ 789 static int interface_req_cursor_notification(QXLInstance *sin) 790 { 791 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 792 int wait = 1; 793 794 trace_qxl_ring_cursor_req_notification(qxl->id); 795 switch (qxl->mode) { 796 case QXL_MODE_COMPAT: 797 case QXL_MODE_NATIVE: 798 case QXL_MODE_UNDEFINED: 799 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 800 qxl_ring_set_dirty(qxl); 801 break; 802 default: 803 /* nothing */ 804 break; 805 } 806 return wait; 807 } 808 809 /* called from spice server thread context */ 810 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 811 { 812 /* 813 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 814 * use by xf86-video-qxl and is defined out in the qxl windows driver. 815 * Probably was at some earlier version that is prior to git start (2009), 816 * and is still guest trigerrable. 817 */ 818 fprintf(stderr, "%s: deprecated\n", __func__); 819 } 820 821 /* called from spice server thread context only */ 822 static int interface_flush_resources(QXLInstance *sin) 823 { 824 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 825 int ret; 826 827 ret = qxl->num_free_res; 828 if (ret) { 829 qxl_push_free_res(qxl, 1); 830 } 831 return ret; 832 } 833 834 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 835 836 /* called from spice server thread context only */ 837 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 838 { 839 uint32_t current_async; 840 841 qemu_mutex_lock(&qxl->async_lock); 842 current_async = qxl->current_async; 843 qxl->current_async = QXL_UNDEFINED_IO; 844 qemu_mutex_unlock(&qxl->async_lock); 845 846 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 847 if (!cookie) { 848 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 849 return; 850 } 851 if (cookie && current_async != cookie->io) { 852 fprintf(stderr, 853 "qxl: %s: error: current_async = %d != %" 854 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 855 } 856 switch (current_async) { 857 case QXL_IO_MEMSLOT_ADD_ASYNC: 858 case QXL_IO_DESTROY_PRIMARY_ASYNC: 859 case QXL_IO_UPDATE_AREA_ASYNC: 860 case QXL_IO_FLUSH_SURFACES_ASYNC: 861 case QXL_IO_MONITORS_CONFIG_ASYNC: 862 break; 863 case QXL_IO_CREATE_PRIMARY_ASYNC: 864 qxl_create_guest_primary_complete(qxl); 865 break; 866 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 867 qxl_spice_destroy_surfaces_complete(qxl); 868 break; 869 case QXL_IO_DESTROY_SURFACE_ASYNC: 870 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 871 break; 872 default: 873 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 874 current_async); 875 } 876 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 877 } 878 879 /* called from spice server thread context only */ 880 static void interface_update_area_complete(QXLInstance *sin, 881 uint32_t surface_id, 882 QXLRect *dirty, uint32_t num_updated_rects) 883 { 884 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 885 int i; 886 int qxl_i; 887 888 qemu_mutex_lock(&qxl->ssd.lock); 889 if (surface_id != 0 || !qxl->render_update_cookie_num) { 890 qemu_mutex_unlock(&qxl->ssd.lock); 891 return; 892 } 893 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 894 dirty->right, dirty->top, dirty->bottom); 895 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 896 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 897 /* 898 * overflow - treat this as a full update. Not expected to be common. 899 */ 900 trace_qxl_interface_update_area_complete_overflow(qxl->id, 901 QXL_NUM_DIRTY_RECTS); 902 qxl->guest_primary.resized = 1; 903 } 904 if (qxl->guest_primary.resized) { 905 /* 906 * Don't bother copying or scheduling the bh since we will flip 907 * the whole area anyway on completion of the update_area async call 908 */ 909 qemu_mutex_unlock(&qxl->ssd.lock); 910 return; 911 } 912 qxl_i = qxl->num_dirty_rects; 913 for (i = 0; i < num_updated_rects; i++) { 914 qxl->dirty[qxl_i++] = dirty[i]; 915 } 916 qxl->num_dirty_rects += num_updated_rects; 917 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 918 qxl->num_dirty_rects); 919 qemu_bh_schedule(qxl->update_area_bh); 920 qemu_mutex_unlock(&qxl->ssd.lock); 921 } 922 923 /* called from spice server thread context only */ 924 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 925 { 926 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 927 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 928 929 switch (cookie->type) { 930 case QXL_COOKIE_TYPE_IO: 931 interface_async_complete_io(qxl, cookie); 932 g_free(cookie); 933 break; 934 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 935 qxl_render_update_area_done(qxl, cookie); 936 break; 937 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 938 break; 939 default: 940 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 941 __func__, cookie->type); 942 g_free(cookie); 943 } 944 } 945 946 /* called from spice server thread context only */ 947 static void interface_set_client_capabilities(QXLInstance *sin, 948 uint8_t client_present, 949 uint8_t caps[58]) 950 { 951 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 952 953 if (qxl->revision < 4) { 954 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 955 qxl->revision); 956 return; 957 } 958 959 if (runstate_check(RUN_STATE_INMIGRATE) || 960 runstate_check(RUN_STATE_POSTMIGRATE)) { 961 return; 962 } 963 964 qxl->shadow_rom.client_present = client_present; 965 memcpy(qxl->shadow_rom.client_capabilities, caps, 966 sizeof(qxl->shadow_rom.client_capabilities)); 967 qxl->rom->client_present = client_present; 968 memcpy(qxl->rom->client_capabilities, caps, 969 sizeof(qxl->rom->client_capabilities)); 970 qxl_rom_set_dirty(qxl); 971 972 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 973 } 974 975 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 976 { 977 /* 978 * zlib xors the seed with 0xffffffff, and xors the result 979 * again with 0xffffffff; Both are not done with linux's crc32, 980 * which we want to be compatible with, so undo that. 981 */ 982 return crc32(0xffffffff, p, len) ^ 0xffffffff; 983 } 984 985 /* called from main context only */ 986 static int interface_client_monitors_config(QXLInstance *sin, 987 VDAgentMonitorsConfig *monitors_config) 988 { 989 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 990 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 991 int i; 992 993 if (qxl->revision < 4) { 994 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 995 qxl->revision); 996 return 0; 997 } 998 /* 999 * Older windows drivers set int_mask to 0 when their ISR is called, 1000 * then later set it to ~0. So it doesn't relate to the actual interrupts 1001 * handled. However, they are old, so clearly they don't support this 1002 * interrupt 1003 */ 1004 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1005 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1006 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1007 qxl->ram->int_mask, 1008 monitors_config); 1009 return 0; 1010 } 1011 if (!monitors_config) { 1012 return 1; 1013 } 1014 memset(&rom->client_monitors_config, 0, 1015 sizeof(rom->client_monitors_config)); 1016 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1017 /* monitors_config->flags ignored */ 1018 if (rom->client_monitors_config.count >= 1019 ARRAY_SIZE(rom->client_monitors_config.heads)) { 1020 trace_qxl_client_monitors_config_capped(qxl->id, 1021 monitors_config->num_of_monitors, 1022 ARRAY_SIZE(rom->client_monitors_config.heads)); 1023 rom->client_monitors_config.count = 1024 ARRAY_SIZE(rom->client_monitors_config.heads); 1025 } 1026 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1027 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1028 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1029 /* monitor->depth ignored */ 1030 rect->left = monitor->x; 1031 rect->top = monitor->y; 1032 rect->right = monitor->x + monitor->width; 1033 rect->bottom = monitor->y + monitor->height; 1034 } 1035 rom->client_monitors_config_crc = qxl_crc32( 1036 (const uint8_t *)&rom->client_monitors_config, 1037 sizeof(rom->client_monitors_config)); 1038 trace_qxl_client_monitors_config_crc(qxl->id, 1039 sizeof(rom->client_monitors_config), 1040 rom->client_monitors_config_crc); 1041 1042 trace_qxl_interrupt_client_monitors_config(qxl->id, 1043 rom->client_monitors_config.count, 1044 rom->client_monitors_config.heads); 1045 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1046 return 1; 1047 } 1048 1049 static const QXLInterface qxl_interface = { 1050 .base.type = SPICE_INTERFACE_QXL, 1051 .base.description = "qxl gpu", 1052 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1053 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1054 1055 .attache_worker = interface_attach_worker, 1056 .set_compression_level = interface_set_compression_level, 1057 .set_mm_time = interface_set_mm_time, 1058 .get_init_info = interface_get_init_info, 1059 1060 /* the callbacks below are called from spice server thread context */ 1061 .get_command = interface_get_command, 1062 .req_cmd_notification = interface_req_cmd_notification, 1063 .release_resource = interface_release_resource, 1064 .get_cursor_command = interface_get_cursor_command, 1065 .req_cursor_notification = interface_req_cursor_notification, 1066 .notify_update = interface_notify_update, 1067 .flush_resources = interface_flush_resources, 1068 .async_complete = interface_async_complete, 1069 .update_area_complete = interface_update_area_complete, 1070 .set_client_capabilities = interface_set_client_capabilities, 1071 .client_monitors_config = interface_client_monitors_config, 1072 }; 1073 1074 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1075 { 1076 if (d->mode == QXL_MODE_VGA) { 1077 return; 1078 } 1079 trace_qxl_enter_vga_mode(d->id); 1080 qemu_spice_create_host_primary(&d->ssd); 1081 d->mode = QXL_MODE_VGA; 1082 vga_dirty_log_start(&d->vga); 1083 graphic_hw_update(d->vga.con); 1084 } 1085 1086 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1087 { 1088 if (d->mode != QXL_MODE_VGA) { 1089 return; 1090 } 1091 trace_qxl_exit_vga_mode(d->id); 1092 vga_dirty_log_stop(&d->vga); 1093 qxl_destroy_primary(d, QXL_SYNC); 1094 } 1095 1096 static void qxl_update_irq(PCIQXLDevice *d) 1097 { 1098 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1099 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1100 int level = !!(pending & mask); 1101 qemu_set_irq(d->pci.irq[0], level); 1102 qxl_ring_set_dirty(d); 1103 } 1104 1105 static void qxl_check_state(PCIQXLDevice *d) 1106 { 1107 QXLRam *ram = d->ram; 1108 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1109 1110 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1111 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1112 } 1113 1114 static void qxl_reset_state(PCIQXLDevice *d) 1115 { 1116 QXLRom *rom = d->rom; 1117 1118 qxl_check_state(d); 1119 d->shadow_rom.update_id = cpu_to_le32(0); 1120 *rom = d->shadow_rom; 1121 qxl_rom_set_dirty(d); 1122 init_qxl_ram(d); 1123 d->num_free_res = 0; 1124 d->last_release = NULL; 1125 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1126 } 1127 1128 static void qxl_soft_reset(PCIQXLDevice *d) 1129 { 1130 trace_qxl_soft_reset(d->id); 1131 qxl_check_state(d); 1132 qxl_clear_guest_bug(d); 1133 d->current_async = QXL_UNDEFINED_IO; 1134 1135 if (d->id == 0) { 1136 qxl_enter_vga_mode(d); 1137 } else { 1138 d->mode = QXL_MODE_UNDEFINED; 1139 } 1140 } 1141 1142 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1143 { 1144 trace_qxl_hard_reset(d->id, loadvm); 1145 1146 qxl_spice_reset_cursor(d); 1147 qxl_spice_reset_image_cache(d); 1148 qxl_reset_surfaces(d); 1149 qxl_reset_memslots(d); 1150 1151 /* pre loadvm reset must not touch QXLRam. This lives in 1152 * device memory, is migrated together with RAM and thus 1153 * already loaded at this point */ 1154 if (!loadvm) { 1155 qxl_reset_state(d); 1156 } 1157 qemu_spice_create_host_memslot(&d->ssd); 1158 qxl_soft_reset(d); 1159 } 1160 1161 static void qxl_reset_handler(DeviceState *dev) 1162 { 1163 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); 1164 1165 qxl_hard_reset(d, 0); 1166 } 1167 1168 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1169 { 1170 VGACommonState *vga = opaque; 1171 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1172 1173 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1174 if (qxl->mode != QXL_MODE_VGA) { 1175 qxl_destroy_primary(qxl, QXL_SYNC); 1176 qxl_soft_reset(qxl); 1177 } 1178 vga_ioport_write(opaque, addr, val); 1179 } 1180 1181 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1182 { 0x04, 2, 1, .read = vga_ioport_read, 1183 .write = qxl_vga_ioport_write }, /* 3b4 */ 1184 { 0x0a, 1, 1, .read = vga_ioport_read, 1185 .write = qxl_vga_ioport_write }, /* 3ba */ 1186 { 0x10, 16, 1, .read = vga_ioport_read, 1187 .write = qxl_vga_ioport_write }, /* 3c0 */ 1188 { 0x24, 2, 1, .read = vga_ioport_read, 1189 .write = qxl_vga_ioport_write }, /* 3d4 */ 1190 { 0x2a, 1, 1, .read = vga_ioport_read, 1191 .write = qxl_vga_ioport_write }, /* 3da */ 1192 PORTIO_END_OF_LIST(), 1193 }; 1194 1195 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1196 qxl_async_io async) 1197 { 1198 static const int regions[] = { 1199 QXL_RAM_RANGE_INDEX, 1200 QXL_VRAM_RANGE_INDEX, 1201 QXL_VRAM64_RANGE_INDEX, 1202 }; 1203 uint64_t guest_start; 1204 uint64_t guest_end; 1205 int pci_region; 1206 pcibus_t pci_start; 1207 pcibus_t pci_end; 1208 intptr_t virt_start; 1209 QXLDevMemSlot memslot; 1210 int i; 1211 1212 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1213 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1214 1215 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1216 1217 if (slot_id >= NUM_MEMSLOTS) { 1218 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1219 slot_id, NUM_MEMSLOTS); 1220 return 1; 1221 } 1222 if (guest_start > guest_end) { 1223 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1224 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1225 return 1; 1226 } 1227 1228 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1229 pci_region = regions[i]; 1230 pci_start = d->pci.io_regions[pci_region].addr; 1231 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1232 /* mapped? */ 1233 if (pci_start == -1) { 1234 continue; 1235 } 1236 /* start address in range ? */ 1237 if (guest_start < pci_start || guest_start > pci_end) { 1238 continue; 1239 } 1240 /* end address in range ? */ 1241 if (guest_end > pci_end) { 1242 continue; 1243 } 1244 /* passed */ 1245 break; 1246 } 1247 if (i == ARRAY_SIZE(regions)) { 1248 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1249 return 1; 1250 } 1251 1252 switch (pci_region) { 1253 case QXL_RAM_RANGE_INDEX: 1254 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); 1255 break; 1256 case QXL_VRAM_RANGE_INDEX: 1257 case 4 /* vram 64bit */: 1258 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); 1259 break; 1260 default: 1261 /* should not happen */ 1262 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1263 return 1; 1264 } 1265 1266 memslot.slot_id = slot_id; 1267 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1268 memslot.virt_start = virt_start + (guest_start - pci_start); 1269 memslot.virt_end = virt_start + (guest_end - pci_start); 1270 memslot.addr_delta = memslot.virt_start - delta; 1271 memslot.generation = d->rom->slot_generation = 0; 1272 qxl_rom_set_dirty(d); 1273 1274 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1275 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; 1276 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1277 d->guest_slots[slot_id].delta = delta; 1278 d->guest_slots[slot_id].active = 1; 1279 return 0; 1280 } 1281 1282 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1283 { 1284 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1285 d->guest_slots[slot_id].active = 0; 1286 } 1287 1288 static void qxl_reset_memslots(PCIQXLDevice *d) 1289 { 1290 qxl_spice_reset_memslots(d); 1291 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1292 } 1293 1294 static void qxl_reset_surfaces(PCIQXLDevice *d) 1295 { 1296 trace_qxl_reset_surfaces(d->id); 1297 d->mode = QXL_MODE_UNDEFINED; 1298 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1299 } 1300 1301 /* can be also called from spice server thread context */ 1302 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1303 { 1304 uint64_t phys = le64_to_cpu(pqxl); 1305 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1306 uint64_t offset = phys & 0xffffffffffff; 1307 1308 switch (group_id) { 1309 case MEMSLOT_GROUP_HOST: 1310 return (void *)(intptr_t)offset; 1311 case MEMSLOT_GROUP_GUEST: 1312 if (slot >= NUM_MEMSLOTS) { 1313 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1314 NUM_MEMSLOTS); 1315 return NULL; 1316 } 1317 if (!qxl->guest_slots[slot].active) { 1318 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1319 return NULL; 1320 } 1321 if (offset < qxl->guest_slots[slot].delta) { 1322 qxl_set_guest_bug(qxl, 1323 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1324 slot, offset, qxl->guest_slots[slot].delta); 1325 return NULL; 1326 } 1327 offset -= qxl->guest_slots[slot].delta; 1328 if (offset > qxl->guest_slots[slot].size) { 1329 qxl_set_guest_bug(qxl, 1330 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1331 slot, offset, qxl->guest_slots[slot].size); 1332 return NULL; 1333 } 1334 return qxl->guest_slots[slot].ptr + offset; 1335 } 1336 return NULL; 1337 } 1338 1339 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1340 { 1341 /* for local rendering */ 1342 qxl_render_resize(qxl); 1343 } 1344 1345 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1346 qxl_async_io async) 1347 { 1348 QXLDevSurfaceCreate surface; 1349 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1350 int size; 1351 int requested_height = le32_to_cpu(sc->height); 1352 int requested_stride = le32_to_cpu(sc->stride); 1353 1354 size = abs(requested_stride) * requested_height; 1355 if (size > qxl->vgamem_size) { 1356 qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer" 1357 " size", __func__); 1358 return; 1359 } 1360 1361 if (qxl->mode == QXL_MODE_NATIVE) { 1362 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1363 __func__); 1364 } 1365 qxl_exit_vga_mode(qxl); 1366 1367 surface.format = le32_to_cpu(sc->format); 1368 surface.height = le32_to_cpu(sc->height); 1369 surface.mem = le64_to_cpu(sc->mem); 1370 surface.position = le32_to_cpu(sc->position); 1371 surface.stride = le32_to_cpu(sc->stride); 1372 surface.width = le32_to_cpu(sc->width); 1373 surface.type = le32_to_cpu(sc->type); 1374 surface.flags = le32_to_cpu(sc->flags); 1375 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1376 sc->format, sc->position); 1377 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1378 sc->flags); 1379 1380 if ((surface.stride & 0x3) != 0) { 1381 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1382 surface.stride); 1383 return; 1384 } 1385 1386 surface.mouse_mode = true; 1387 surface.group_id = MEMSLOT_GROUP_GUEST; 1388 if (loadvm) { 1389 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1390 } 1391 1392 qxl->mode = QXL_MODE_NATIVE; 1393 qxl->cmdflags = 0; 1394 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1395 1396 if (async == QXL_SYNC) { 1397 qxl_create_guest_primary_complete(qxl); 1398 } 1399 } 1400 1401 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1402 * done (in QXL_SYNC case), 0 otherwise. */ 1403 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1404 { 1405 if (d->mode == QXL_MODE_UNDEFINED) { 1406 return 0; 1407 } 1408 trace_qxl_destroy_primary(d->id); 1409 d->mode = QXL_MODE_UNDEFINED; 1410 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1411 qxl_spice_reset_cursor(d); 1412 return 1; 1413 } 1414 1415 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) 1416 { 1417 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1418 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1419 QXLMode *mode = d->modes->modes + modenr; 1420 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1421 QXLMemSlot slot = { 1422 .mem_start = start, 1423 .mem_end = end 1424 }; 1425 QXLSurfaceCreate surface = { 1426 .width = mode->x_res, 1427 .height = mode->y_res, 1428 .stride = -mode->x_res * 4, 1429 .format = SPICE_SURFACE_FMT_32_xRGB, 1430 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1431 .mouse_mode = true, 1432 .mem = devmem + d->shadow_rom.draw_area_offset, 1433 }; 1434 1435 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1436 devmem); 1437 if (!loadvm) { 1438 qxl_hard_reset(d, 0); 1439 } 1440 1441 d->guest_slots[0].slot = slot; 1442 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1443 1444 d->guest_primary.surface = surface; 1445 qxl_create_guest_primary(d, 0, QXL_SYNC); 1446 1447 d->mode = QXL_MODE_COMPAT; 1448 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1449 if (mode->bits == 16) { 1450 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1451 } 1452 d->shadow_rom.mode = cpu_to_le32(modenr); 1453 d->rom->mode = cpu_to_le32(modenr); 1454 qxl_rom_set_dirty(d); 1455 } 1456 1457 static void ioport_write(void *opaque, hwaddr addr, 1458 uint64_t val, unsigned size) 1459 { 1460 PCIQXLDevice *d = opaque; 1461 uint32_t io_port = addr; 1462 qxl_async_io async = QXL_SYNC; 1463 uint32_t orig_io_port = io_port; 1464 1465 if (d->guest_bug && io_port != QXL_IO_RESET) { 1466 return; 1467 } 1468 1469 if (d->revision <= QXL_REVISION_STABLE_V10 && 1470 io_port > QXL_IO_FLUSH_RELEASE) { 1471 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1472 io_port, d->revision); 1473 return; 1474 } 1475 1476 switch (io_port) { 1477 case QXL_IO_RESET: 1478 case QXL_IO_SET_MODE: 1479 case QXL_IO_MEMSLOT_ADD: 1480 case QXL_IO_MEMSLOT_DEL: 1481 case QXL_IO_CREATE_PRIMARY: 1482 case QXL_IO_UPDATE_IRQ: 1483 case QXL_IO_LOG: 1484 case QXL_IO_MEMSLOT_ADD_ASYNC: 1485 case QXL_IO_CREATE_PRIMARY_ASYNC: 1486 break; 1487 default: 1488 if (d->mode != QXL_MODE_VGA) { 1489 break; 1490 } 1491 trace_qxl_io_unexpected_vga_mode(d->id, 1492 addr, val, io_port_to_string(io_port)); 1493 /* be nice to buggy guest drivers */ 1494 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1495 io_port < QXL_IO_RANGE_SIZE) { 1496 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1497 } 1498 return; 1499 } 1500 1501 /* we change the io_port to avoid ifdeffery in the main switch */ 1502 orig_io_port = io_port; 1503 switch (io_port) { 1504 case QXL_IO_UPDATE_AREA_ASYNC: 1505 io_port = QXL_IO_UPDATE_AREA; 1506 goto async_common; 1507 case QXL_IO_MEMSLOT_ADD_ASYNC: 1508 io_port = QXL_IO_MEMSLOT_ADD; 1509 goto async_common; 1510 case QXL_IO_CREATE_PRIMARY_ASYNC: 1511 io_port = QXL_IO_CREATE_PRIMARY; 1512 goto async_common; 1513 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1514 io_port = QXL_IO_DESTROY_PRIMARY; 1515 goto async_common; 1516 case QXL_IO_DESTROY_SURFACE_ASYNC: 1517 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1518 goto async_common; 1519 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1520 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1521 goto async_common; 1522 case QXL_IO_FLUSH_SURFACES_ASYNC: 1523 case QXL_IO_MONITORS_CONFIG_ASYNC: 1524 async_common: 1525 async = QXL_ASYNC; 1526 qemu_mutex_lock(&d->async_lock); 1527 if (d->current_async != QXL_UNDEFINED_IO) { 1528 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1529 io_port, d->current_async); 1530 qemu_mutex_unlock(&d->async_lock); 1531 return; 1532 } 1533 d->current_async = orig_io_port; 1534 qemu_mutex_unlock(&d->async_lock); 1535 break; 1536 default: 1537 break; 1538 } 1539 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size, 1540 async); 1541 1542 switch (io_port) { 1543 case QXL_IO_UPDATE_AREA: 1544 { 1545 QXLCookie *cookie = NULL; 1546 QXLRect update = d->ram->update_area; 1547 1548 if (d->ram->update_surface > d->ssd.num_surfaces) { 1549 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1550 d->ram->update_surface); 1551 break; 1552 } 1553 if (update.left >= update.right || update.top >= update.bottom || 1554 update.left < 0 || update.top < 0) { 1555 qxl_set_guest_bug(d, 1556 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1557 update.left, update.top, update.right, update.bottom); 1558 break; 1559 } 1560 if (async == QXL_ASYNC) { 1561 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1562 QXL_IO_UPDATE_AREA_ASYNC); 1563 cookie->u.area = update; 1564 } 1565 qxl_spice_update_area(d, d->ram->update_surface, 1566 cookie ? &cookie->u.area : &update, 1567 NULL, 0, 0, async, cookie); 1568 break; 1569 } 1570 case QXL_IO_NOTIFY_CMD: 1571 qemu_spice_wakeup(&d->ssd); 1572 break; 1573 case QXL_IO_NOTIFY_CURSOR: 1574 qemu_spice_wakeup(&d->ssd); 1575 break; 1576 case QXL_IO_UPDATE_IRQ: 1577 qxl_update_irq(d); 1578 break; 1579 case QXL_IO_NOTIFY_OOM: 1580 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1581 break; 1582 } 1583 d->oom_running = 1; 1584 qxl_spice_oom(d); 1585 d->oom_running = 0; 1586 break; 1587 case QXL_IO_SET_MODE: 1588 qxl_set_mode(d, val, 0); 1589 break; 1590 case QXL_IO_LOG: 1591 trace_qxl_io_log(d->id, d->ram->log_buf); 1592 if (d->guestdebug) { 1593 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1594 qemu_get_clock_ns(vm_clock), d->ram->log_buf); 1595 } 1596 break; 1597 case QXL_IO_RESET: 1598 qxl_hard_reset(d, 0); 1599 break; 1600 case QXL_IO_MEMSLOT_ADD: 1601 if (val >= NUM_MEMSLOTS) { 1602 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1603 break; 1604 } 1605 if (d->guest_slots[val].active) { 1606 qxl_set_guest_bug(d, 1607 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1608 break; 1609 } 1610 d->guest_slots[val].slot = d->ram->mem_slot; 1611 qxl_add_memslot(d, val, 0, async); 1612 break; 1613 case QXL_IO_MEMSLOT_DEL: 1614 if (val >= NUM_MEMSLOTS) { 1615 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1616 break; 1617 } 1618 qxl_del_memslot(d, val); 1619 break; 1620 case QXL_IO_CREATE_PRIMARY: 1621 if (val != 0) { 1622 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1623 async); 1624 goto cancel_async; 1625 } 1626 d->guest_primary.surface = d->ram->create_surface; 1627 qxl_create_guest_primary(d, 0, async); 1628 break; 1629 case QXL_IO_DESTROY_PRIMARY: 1630 if (val != 0) { 1631 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1632 async); 1633 goto cancel_async; 1634 } 1635 if (!qxl_destroy_primary(d, async)) { 1636 trace_qxl_io_destroy_primary_ignored(d->id, 1637 qxl_mode_to_string(d->mode)); 1638 goto cancel_async; 1639 } 1640 break; 1641 case QXL_IO_DESTROY_SURFACE_WAIT: 1642 if (val >= d->ssd.num_surfaces) { 1643 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1644 "%" PRIu64 " >= NUM_SURFACES", async, val); 1645 goto cancel_async; 1646 } 1647 qxl_spice_destroy_surface_wait(d, val, async); 1648 break; 1649 case QXL_IO_FLUSH_RELEASE: { 1650 QXLReleaseRing *ring = &d->ram->release_ring; 1651 if (ring->prod - ring->cons + 1 == ring->num_items) { 1652 fprintf(stderr, 1653 "ERROR: no flush, full release ring [p%d,%dc]\n", 1654 ring->prod, ring->cons); 1655 } 1656 qxl_push_free_res(d, 1 /* flush */); 1657 break; 1658 } 1659 case QXL_IO_FLUSH_SURFACES_ASYNC: 1660 qxl_spice_flush_surfaces_async(d); 1661 break; 1662 case QXL_IO_DESTROY_ALL_SURFACES: 1663 d->mode = QXL_MODE_UNDEFINED; 1664 qxl_spice_destroy_surfaces(d, async); 1665 break; 1666 case QXL_IO_MONITORS_CONFIG_ASYNC: 1667 qxl_spice_monitors_config_async(d, 0); 1668 break; 1669 default: 1670 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1671 } 1672 return; 1673 cancel_async: 1674 if (async) { 1675 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1676 qemu_mutex_lock(&d->async_lock); 1677 d->current_async = QXL_UNDEFINED_IO; 1678 qemu_mutex_unlock(&d->async_lock); 1679 } 1680 } 1681 1682 static uint64_t ioport_read(void *opaque, hwaddr addr, 1683 unsigned size) 1684 { 1685 PCIQXLDevice *qxl = opaque; 1686 1687 trace_qxl_io_read_unexpected(qxl->id); 1688 return 0xff; 1689 } 1690 1691 static const MemoryRegionOps qxl_io_ops = { 1692 .read = ioport_read, 1693 .write = ioport_write, 1694 .valid = { 1695 .min_access_size = 1, 1696 .max_access_size = 1, 1697 }, 1698 }; 1699 1700 static void pipe_read(void *opaque) 1701 { 1702 PCIQXLDevice *d = opaque; 1703 char dummy; 1704 int len; 1705 1706 do { 1707 len = read(d->pipe[0], &dummy, sizeof(dummy)); 1708 } while (len == sizeof(dummy)); 1709 qxl_update_irq(d); 1710 } 1711 1712 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1713 { 1714 uint32_t old_pending; 1715 uint32_t le_events = cpu_to_le32(events); 1716 1717 trace_qxl_send_events(d->id, events); 1718 if (!qemu_spice_display_is_running(&d->ssd)) { 1719 /* spice-server tracks guest running state and should not do this */ 1720 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1721 __func__); 1722 trace_qxl_send_events_vm_stopped(d->id, events); 1723 return; 1724 } 1725 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); 1726 if ((old_pending & le_events) == le_events) { 1727 return; 1728 } 1729 if (qemu_thread_is_self(&d->main)) { 1730 qxl_update_irq(d); 1731 } else { 1732 if (write(d->pipe[1], d, 1) != 1) { 1733 dprint(d, 1, "%s: write to pipe failed\n", __func__); 1734 } 1735 } 1736 } 1737 1738 static void init_pipe_signaling(PCIQXLDevice *d) 1739 { 1740 if (pipe(d->pipe) < 0) { 1741 fprintf(stderr, "%s:%s: qxl pipe creation failed\n", 1742 __FILE__, __func__); 1743 exit(1); 1744 } 1745 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); 1746 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); 1747 fcntl(d->pipe[0], F_SETOWN, getpid()); 1748 1749 qemu_thread_get_self(&d->main); 1750 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); 1751 } 1752 1753 /* graphics console */ 1754 1755 static void qxl_hw_update(void *opaque) 1756 { 1757 PCIQXLDevice *qxl = opaque; 1758 VGACommonState *vga = &qxl->vga; 1759 1760 switch (qxl->mode) { 1761 case QXL_MODE_VGA: 1762 vga->hw_ops->gfx_update(vga); 1763 break; 1764 case QXL_MODE_COMPAT: 1765 case QXL_MODE_NATIVE: 1766 qxl_render_update(qxl); 1767 break; 1768 default: 1769 break; 1770 } 1771 } 1772 1773 static void qxl_hw_invalidate(void *opaque) 1774 { 1775 PCIQXLDevice *qxl = opaque; 1776 VGACommonState *vga = &qxl->vga; 1777 1778 if (qxl->mode == QXL_MODE_VGA) { 1779 vga->hw_ops->invalidate(vga); 1780 return; 1781 } 1782 } 1783 1784 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) 1785 { 1786 PCIQXLDevice *qxl = opaque; 1787 VGACommonState *vga = &qxl->vga; 1788 1789 if (qxl->mode == QXL_MODE_VGA) { 1790 vga->hw_ops->text_update(vga, chardata); 1791 return; 1792 } 1793 } 1794 1795 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1796 { 1797 uintptr_t vram_start; 1798 int i; 1799 1800 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1801 return; 1802 } 1803 1804 /* dirty the primary surface */ 1805 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, 1806 qxl->shadow_rom.surface0_area_size); 1807 1808 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); 1809 1810 /* dirty the off-screen surfaces */ 1811 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1812 QXLSurfaceCmd *cmd; 1813 intptr_t surface_offset; 1814 int surface_size; 1815 1816 if (qxl->guest_surfaces.cmds[i] == 0) { 1817 continue; 1818 } 1819 1820 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1821 MEMSLOT_GROUP_GUEST); 1822 assert(cmd); 1823 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1824 surface_offset = (intptr_t)qxl_phys2virt(qxl, 1825 cmd->u.surface_create.data, 1826 MEMSLOT_GROUP_GUEST); 1827 assert(surface_offset); 1828 surface_offset -= vram_start; 1829 surface_size = cmd->u.surface_create.height * 1830 abs(cmd->u.surface_create.stride); 1831 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); 1832 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); 1833 } 1834 } 1835 1836 static void qxl_vm_change_state_handler(void *opaque, int running, 1837 RunState state) 1838 { 1839 PCIQXLDevice *qxl = opaque; 1840 1841 if (running) { 1842 /* 1843 * if qxl_send_events was called from spice server context before 1844 * migration ended, qxl_update_irq for these events might not have been 1845 * called 1846 */ 1847 qxl_update_irq(qxl); 1848 } else { 1849 /* make sure surfaces are saved before migration */ 1850 qxl_dirty_surfaces(qxl); 1851 } 1852 } 1853 1854 /* display change listener */ 1855 1856 static void display_update(DisplayChangeListener *dcl, 1857 int x, int y, int w, int h) 1858 { 1859 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1860 1861 if (qxl->mode == QXL_MODE_VGA) { 1862 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 1863 } 1864 } 1865 1866 static void display_switch(DisplayChangeListener *dcl, 1867 struct DisplaySurface *surface) 1868 { 1869 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1870 1871 qxl->ssd.ds = surface; 1872 if (qxl->mode == QXL_MODE_VGA) { 1873 qemu_spice_display_switch(&qxl->ssd, surface); 1874 } 1875 } 1876 1877 static void display_refresh(DisplayChangeListener *dcl) 1878 { 1879 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1880 1881 if (qxl->mode == QXL_MODE_VGA) { 1882 qemu_spice_display_refresh(&qxl->ssd); 1883 } else { 1884 qemu_mutex_lock(&qxl->ssd.lock); 1885 qemu_spice_cursor_refresh_unlocked(&qxl->ssd); 1886 qemu_mutex_unlock(&qxl->ssd.lock); 1887 } 1888 } 1889 1890 static DisplayChangeListenerOps display_listener_ops = { 1891 .dpy_name = "spice/qxl", 1892 .dpy_gfx_update = display_update, 1893 .dpy_gfx_switch = display_switch, 1894 .dpy_refresh = display_refresh, 1895 }; 1896 1897 static void qxl_init_ramsize(PCIQXLDevice *qxl) 1898 { 1899 /* vga mode framebuffer / primary surface (bar 0, first part) */ 1900 if (qxl->vgamem_size_mb < 8) { 1901 qxl->vgamem_size_mb = 8; 1902 } 1903 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; 1904 1905 /* vga ram (bar 0, total) */ 1906 if (qxl->ram_size_mb != -1) { 1907 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; 1908 } 1909 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 1910 qxl->vga.vram_size = qxl->vgamem_size * 2; 1911 } 1912 1913 /* vram32 (surfaces, 32bit, bar 1) */ 1914 if (qxl->vram32_size_mb != -1) { 1915 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; 1916 } 1917 if (qxl->vram32_size < 4096) { 1918 qxl->vram32_size = 4096; 1919 } 1920 1921 /* vram (surfaces, 64bit, bar 4+5) */ 1922 if (qxl->vram_size_mb != -1) { 1923 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; 1924 } 1925 if (qxl->vram_size < qxl->vram32_size) { 1926 qxl->vram_size = qxl->vram32_size; 1927 } 1928 1929 if (qxl->revision == 1) { 1930 qxl->vram32_size = 4096; 1931 qxl->vram_size = 4096; 1932 } 1933 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1); 1934 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); 1935 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); 1936 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); 1937 } 1938 1939 static int qxl_init_common(PCIQXLDevice *qxl) 1940 { 1941 uint8_t* config = qxl->pci.config; 1942 uint32_t pci_device_rev; 1943 uint32_t io_size; 1944 1945 qxl->mode = QXL_MODE_UNDEFINED; 1946 qxl->generation = 1; 1947 qxl->num_memslots = NUM_MEMSLOTS; 1948 qemu_mutex_init(&qxl->track_lock); 1949 qemu_mutex_init(&qxl->async_lock); 1950 qxl->current_async = QXL_UNDEFINED_IO; 1951 qxl->guest_bug = 0; 1952 1953 switch (qxl->revision) { 1954 case 1: /* spice 0.4 -- qxl-1 */ 1955 pci_device_rev = QXL_REVISION_STABLE_V04; 1956 io_size = 8; 1957 break; 1958 case 2: /* spice 0.6 -- qxl-2 */ 1959 pci_device_rev = QXL_REVISION_STABLE_V06; 1960 io_size = 16; 1961 break; 1962 case 3: /* qxl-3 */ 1963 pci_device_rev = QXL_REVISION_STABLE_V10; 1964 io_size = 32; /* PCI region size must be pow2 */ 1965 break; 1966 case 4: /* qxl-4 */ 1967 pci_device_rev = QXL_REVISION_STABLE_V12; 1968 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); 1969 break; 1970 default: 1971 error_report("Invalid revision %d for qxl device (max %d)", 1972 qxl->revision, QXL_DEFAULT_REVISION); 1973 return -1; 1974 } 1975 1976 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 1977 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 1978 1979 qxl->rom_size = qxl_rom_size(); 1980 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size); 1981 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); 1982 init_qxl_rom(qxl); 1983 init_qxl_ram(qxl); 1984 1985 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 1986 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size); 1987 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); 1988 memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar, 1989 0, qxl->vram32_size); 1990 1991 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, 1992 "qxl-ioports", io_size); 1993 if (qxl->id == 0) { 1994 vga_dirty_log_start(&qxl->vga); 1995 } 1996 memory_region_set_flush_coalesced(&qxl->io_bar); 1997 1998 1999 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 2000 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 2001 2002 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 2003 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 2004 2005 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 2006 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 2007 2008 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 2009 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 2010 2011 if (qxl->vram32_size < qxl->vram_size) { 2012 /* 2013 * Make the 64bit vram bar show up only in case it is 2014 * configured to be larger than the 32bit vram bar. 2015 */ 2016 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 2017 PCI_BASE_ADDRESS_SPACE_MEMORY | 2018 PCI_BASE_ADDRESS_MEM_TYPE_64 | 2019 PCI_BASE_ADDRESS_MEM_PREFETCH, 2020 &qxl->vram_bar); 2021 } 2022 2023 /* print pci bar details */ 2024 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", 2025 qxl->id == 0 ? "pri" : "sec", 2026 qxl->vga.vram_size / (1024*1024)); 2027 dprint(qxl, 1, "vram/32: %d MB [region 1]\n", 2028 qxl->vram32_size / (1024*1024)); 2029 dprint(qxl, 1, "vram/64: %d MB %s\n", 2030 qxl->vram_size / (1024*1024), 2031 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2032 2033 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2034 qxl->ssd.qxl.id = qxl->id; 2035 if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) { 2036 error_report("qxl interface %d.%d not supported by spice-server", 2037 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2038 return -1; 2039 } 2040 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2041 2042 init_pipe_signaling(qxl); 2043 qxl_reset_state(qxl); 2044 2045 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2046 2047 return 0; 2048 } 2049 2050 static const GraphicHwOps qxl_ops = { 2051 .invalidate = qxl_hw_invalidate, 2052 .gfx_update = qxl_hw_update, 2053 .text_update = qxl_hw_text_update, 2054 }; 2055 2056 static int qxl_init_primary(PCIDevice *dev) 2057 { 2058 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2059 VGACommonState *vga = &qxl->vga; 2060 PortioList *qxl_vga_port_list = g_new(PortioList, 1); 2061 DisplayState *ds; 2062 int rc; 2063 2064 qxl->id = 0; 2065 qxl_init_ramsize(qxl); 2066 vga->vram_size_mb = qxl->vga.vram_size >> 20; 2067 vga_common_init(vga); 2068 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false); 2069 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga"); 2070 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0); 2071 2072 vga->con = graphic_console_init(&qxl_ops, qxl); 2073 qemu_spice_display_init_common(&qxl->ssd); 2074 2075 rc = qxl_init_common(qxl); 2076 if (rc != 0) { 2077 return rc; 2078 } 2079 2080 qxl->ssd.dcl.ops = &display_listener_ops; 2081 qxl->ssd.dcl.con = vga->con; 2082 ds = qemu_console_displaystate(vga->con); 2083 register_displaychangelistener(ds, &qxl->ssd.dcl); 2084 return rc; 2085 } 2086 2087 static int qxl_init_secondary(PCIDevice *dev) 2088 { 2089 static int device_id = 1; 2090 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2091 2092 qxl->id = device_id++; 2093 qxl_init_ramsize(qxl); 2094 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size); 2095 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); 2096 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2097 qxl->vga.con = graphic_console_init(&qxl_ops, qxl); 2098 2099 return qxl_init_common(qxl); 2100 } 2101 2102 static void qxl_pre_save(void *opaque) 2103 { 2104 PCIQXLDevice* d = opaque; 2105 uint8_t *ram_start = d->vga.vram_ptr; 2106 2107 trace_qxl_pre_save(d->id); 2108 if (d->last_release == NULL) { 2109 d->last_release_offset = 0; 2110 } else { 2111 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2112 } 2113 assert(d->last_release_offset < d->vga.vram_size); 2114 } 2115 2116 static int qxl_pre_load(void *opaque) 2117 { 2118 PCIQXLDevice* d = opaque; 2119 2120 trace_qxl_pre_load(d->id); 2121 qxl_hard_reset(d, 1); 2122 qxl_exit_vga_mode(d); 2123 return 0; 2124 } 2125 2126 static void qxl_create_memslots(PCIQXLDevice *d) 2127 { 2128 int i; 2129 2130 for (i = 0; i < NUM_MEMSLOTS; i++) { 2131 if (!d->guest_slots[i].active) { 2132 continue; 2133 } 2134 qxl_add_memslot(d, i, 0, QXL_SYNC); 2135 } 2136 } 2137 2138 static int qxl_post_load(void *opaque, int version) 2139 { 2140 PCIQXLDevice* d = opaque; 2141 uint8_t *ram_start = d->vga.vram_ptr; 2142 QXLCommandExt *cmds; 2143 int in, out, newmode; 2144 2145 assert(d->last_release_offset < d->vga.vram_size); 2146 if (d->last_release_offset == 0) { 2147 d->last_release = NULL; 2148 } else { 2149 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2150 } 2151 2152 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2153 2154 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2155 newmode = d->mode; 2156 d->mode = QXL_MODE_UNDEFINED; 2157 2158 switch (newmode) { 2159 case QXL_MODE_UNDEFINED: 2160 qxl_create_memslots(d); 2161 break; 2162 case QXL_MODE_VGA: 2163 qxl_create_memslots(d); 2164 qxl_enter_vga_mode(d); 2165 break; 2166 case QXL_MODE_NATIVE: 2167 qxl_create_memslots(d); 2168 qxl_create_guest_primary(d, 1, QXL_SYNC); 2169 2170 /* replay surface-create and cursor-set commands */ 2171 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1)); 2172 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2173 if (d->guest_surfaces.cmds[in] == 0) { 2174 continue; 2175 } 2176 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2177 cmds[out].cmd.type = QXL_CMD_SURFACE; 2178 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2179 out++; 2180 } 2181 if (d->guest_cursor) { 2182 cmds[out].cmd.data = d->guest_cursor; 2183 cmds[out].cmd.type = QXL_CMD_CURSOR; 2184 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2185 out++; 2186 } 2187 qxl_spice_loadvm_commands(d, cmds, out); 2188 g_free(cmds); 2189 if (d->guest_monitors_config) { 2190 qxl_spice_monitors_config_async(d, 1); 2191 } 2192 break; 2193 case QXL_MODE_COMPAT: 2194 /* note: no need to call qxl_create_memslots, qxl_set_mode 2195 * creates the mem slot. */ 2196 qxl_set_mode(d, d->shadow_rom.mode, 1); 2197 break; 2198 } 2199 return 0; 2200 } 2201 2202 #define QXL_SAVE_VERSION 21 2203 2204 static bool qxl_monitors_config_needed(void *opaque) 2205 { 2206 PCIQXLDevice *qxl = opaque; 2207 2208 return qxl->guest_monitors_config != 0; 2209 } 2210 2211 2212 static VMStateDescription qxl_memslot = { 2213 .name = "qxl-memslot", 2214 .version_id = QXL_SAVE_VERSION, 2215 .minimum_version_id = QXL_SAVE_VERSION, 2216 .fields = (VMStateField[]) { 2217 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2218 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2219 VMSTATE_UINT32(active, struct guest_slots), 2220 VMSTATE_END_OF_LIST() 2221 } 2222 }; 2223 2224 static VMStateDescription qxl_surface = { 2225 .name = "qxl-surface", 2226 .version_id = QXL_SAVE_VERSION, 2227 .minimum_version_id = QXL_SAVE_VERSION, 2228 .fields = (VMStateField[]) { 2229 VMSTATE_UINT32(width, QXLSurfaceCreate), 2230 VMSTATE_UINT32(height, QXLSurfaceCreate), 2231 VMSTATE_INT32(stride, QXLSurfaceCreate), 2232 VMSTATE_UINT32(format, QXLSurfaceCreate), 2233 VMSTATE_UINT32(position, QXLSurfaceCreate), 2234 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2235 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2236 VMSTATE_UINT32(type, QXLSurfaceCreate), 2237 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2238 VMSTATE_END_OF_LIST() 2239 } 2240 }; 2241 2242 static VMStateDescription qxl_vmstate_monitors_config = { 2243 .name = "qxl/monitors-config", 2244 .version_id = 1, 2245 .minimum_version_id = 1, 2246 .fields = (VMStateField[]) { 2247 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2248 VMSTATE_END_OF_LIST() 2249 }, 2250 }; 2251 2252 static VMStateDescription qxl_vmstate = { 2253 .name = "qxl", 2254 .version_id = QXL_SAVE_VERSION, 2255 .minimum_version_id = QXL_SAVE_VERSION, 2256 .pre_save = qxl_pre_save, 2257 .pre_load = qxl_pre_load, 2258 .post_load = qxl_post_load, 2259 .fields = (VMStateField[]) { 2260 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2261 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2262 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2263 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2264 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2265 VMSTATE_UINT32(mode, PCIQXLDevice), 2266 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2267 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), 2268 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2269 qxl_memslot, struct guest_slots), 2270 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2271 qxl_surface, QXLSurfaceCreate), 2272 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), 2273 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2274 ssd.num_surfaces, 0, 2275 vmstate_info_uint64, uint64_t), 2276 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2277 VMSTATE_END_OF_LIST() 2278 }, 2279 .subsections = (VMStateSubsection[]) { 2280 { 2281 .vmsd = &qxl_vmstate_monitors_config, 2282 .needed = qxl_monitors_config_needed, 2283 }, { 2284 /* empty */ 2285 } 2286 } 2287 }; 2288 2289 static Property qxl_properties[] = { 2290 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 2291 64 * 1024 * 1024), 2292 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, 2293 64 * 1024 * 1024), 2294 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2295 QXL_DEFAULT_REVISION), 2296 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2297 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2298 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2299 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2300 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2301 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2302 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2303 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2304 DEFINE_PROP_END_OF_LIST(), 2305 }; 2306 2307 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2308 { 2309 DeviceClass *dc = DEVICE_CLASS(klass); 2310 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2311 2312 k->no_hotplug = 1; 2313 k->init = qxl_init_primary; 2314 k->romfile = "vgabios-qxl.bin"; 2315 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2316 k->device_id = QXL_DEVICE_ID_STABLE; 2317 k->class_id = PCI_CLASS_DISPLAY_VGA; 2318 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2319 dc->reset = qxl_reset_handler; 2320 dc->vmsd = &qxl_vmstate; 2321 dc->props = qxl_properties; 2322 } 2323 2324 static const TypeInfo qxl_primary_info = { 2325 .name = "qxl-vga", 2326 .parent = TYPE_PCI_DEVICE, 2327 .instance_size = sizeof(PCIQXLDevice), 2328 .class_init = qxl_primary_class_init, 2329 }; 2330 2331 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2332 { 2333 DeviceClass *dc = DEVICE_CLASS(klass); 2334 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2335 2336 k->init = qxl_init_secondary; 2337 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2338 k->device_id = QXL_DEVICE_ID_STABLE; 2339 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2340 dc->desc = "Spice QXL GPU (secondary)"; 2341 dc->reset = qxl_reset_handler; 2342 dc->vmsd = &qxl_vmstate; 2343 dc->props = qxl_properties; 2344 } 2345 2346 static const TypeInfo qxl_secondary_info = { 2347 .name = "qxl", 2348 .parent = TYPE_PCI_DEVICE, 2349 .instance_size = sizeof(PCIQXLDevice), 2350 .class_init = qxl_secondary_class_init, 2351 }; 2352 2353 static void qxl_register_types(void) 2354 { 2355 type_register_static(&qxl_primary_info); 2356 type_register_static(&qxl_secondary_info); 2357 } 2358 2359 type_init(qxl_register_types) 2360