1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <zlib.h> 22 #include <stdint.h> 23 24 #include "qemu-common.h" 25 #include "qemu/timer.h" 26 #include "qemu/queue.h" 27 #include "qemu/atomic.h" 28 #include "monitor/monitor.h" 29 #include "sysemu/sysemu.h" 30 #include "trace.h" 31 32 #include "qxl.h" 33 34 /* 35 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as 36 * such can be changed by the guest, so to avoid a guest trigerrable 37 * abort we just qxl_set_guest_bug and set the return to NULL. Still 38 * it may happen as a result of emulator bug as well. 39 */ 40 #undef SPICE_RING_PROD_ITEM 41 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ 42 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ 43 if (prod >= ARRAY_SIZE((r)->items)) { \ 44 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ 45 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ 46 ret = NULL; \ 47 } else { \ 48 ret = &(r)->items[prod].el; \ 49 } \ 50 } 51 52 #undef SPICE_RING_CONS_ITEM 53 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 54 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 55 if (cons >= ARRAY_SIZE((r)->items)) { \ 56 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 57 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 58 ret = NULL; \ 59 } else { \ 60 ret = &(r)->items[cons].el; \ 61 } \ 62 } 63 64 #undef ALIGN 65 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 66 67 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 68 69 #define QXL_MODE(_x, _y, _b, _o) \ 70 { .x_res = _x, \ 71 .y_res = _y, \ 72 .bits = _b, \ 73 .stride = (_x) * (_b) / 8, \ 74 .x_mili = PIXEL_SIZE * (_x), \ 75 .y_mili = PIXEL_SIZE * (_y), \ 76 .orientation = _o, \ 77 } 78 79 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 80 QXL_MODE(x_res, y_res, 16, orientation), \ 81 QXL_MODE(x_res, y_res, 32, orientation) 82 83 #define QXL_MODE_EX(x_res, y_res) \ 84 QXL_MODE_16_32(x_res, y_res, 0), \ 85 QXL_MODE_16_32(x_res, y_res, 1) 86 87 static QXLMode qxl_modes[] = { 88 QXL_MODE_EX(640, 480), 89 QXL_MODE_EX(800, 480), 90 QXL_MODE_EX(800, 600), 91 QXL_MODE_EX(832, 624), 92 QXL_MODE_EX(960, 640), 93 QXL_MODE_EX(1024, 600), 94 QXL_MODE_EX(1024, 768), 95 QXL_MODE_EX(1152, 864), 96 QXL_MODE_EX(1152, 870), 97 QXL_MODE_EX(1280, 720), 98 QXL_MODE_EX(1280, 760), 99 QXL_MODE_EX(1280, 768), 100 QXL_MODE_EX(1280, 800), 101 QXL_MODE_EX(1280, 960), 102 QXL_MODE_EX(1280, 1024), 103 QXL_MODE_EX(1360, 768), 104 QXL_MODE_EX(1366, 768), 105 QXL_MODE_EX(1400, 1050), 106 QXL_MODE_EX(1440, 900), 107 QXL_MODE_EX(1600, 900), 108 QXL_MODE_EX(1600, 1200), 109 QXL_MODE_EX(1680, 1050), 110 QXL_MODE_EX(1920, 1080), 111 /* these modes need more than 8 MB video memory */ 112 QXL_MODE_EX(1920, 1200), 113 QXL_MODE_EX(1920, 1440), 114 QXL_MODE_EX(2000, 2000), 115 QXL_MODE_EX(2048, 1536), 116 QXL_MODE_EX(2048, 2048), 117 QXL_MODE_EX(2560, 1440), 118 QXL_MODE_EX(2560, 1600), 119 /* these modes need more than 16 MB video memory */ 120 QXL_MODE_EX(2560, 2048), 121 QXL_MODE_EX(2800, 2100), 122 QXL_MODE_EX(3200, 2400), 123 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 124 QXL_MODE_EX(4096, 2160), /* 4k */ 125 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 126 QXL_MODE_EX(8192, 4320), /* 8k */ 127 }; 128 129 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 130 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 131 static void qxl_reset_memslots(PCIQXLDevice *d); 132 static void qxl_reset_surfaces(PCIQXLDevice *d); 133 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 134 135 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 136 { 137 trace_qxl_set_guest_bug(qxl->id); 138 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 139 qxl->guest_bug = 1; 140 if (qxl->guestdebug) { 141 va_list ap; 142 va_start(ap, msg); 143 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 144 vfprintf(stderr, msg, ap); 145 fprintf(stderr, "\n"); 146 va_end(ap); 147 } 148 } 149 150 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 151 { 152 qxl->guest_bug = 0; 153 } 154 155 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 156 struct QXLRect *area, struct QXLRect *dirty_rects, 157 uint32_t num_dirty_rects, 158 uint32_t clear_dirty_region, 159 qxl_async_io async, struct QXLCookie *cookie) 160 { 161 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 162 area->top, area->bottom); 163 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 164 clear_dirty_region); 165 if (async == QXL_SYNC) { 166 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area, 167 dirty_rects, num_dirty_rects, clear_dirty_region); 168 } else { 169 assert(cookie != NULL); 170 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 171 clear_dirty_region, (uintptr_t)cookie); 172 } 173 } 174 175 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 176 uint32_t id) 177 { 178 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 179 qemu_mutex_lock(&qxl->track_lock); 180 qxl->guest_surfaces.cmds[id] = 0; 181 qxl->guest_surfaces.count--; 182 qemu_mutex_unlock(&qxl->track_lock); 183 } 184 185 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 186 qxl_async_io async) 187 { 188 QXLCookie *cookie; 189 190 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 191 if (async) { 192 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 193 QXL_IO_DESTROY_SURFACE_ASYNC); 194 cookie->u.surface_id = id; 195 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 196 } else { 197 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id); 198 qxl_spice_destroy_surface_wait_complete(qxl, id); 199 } 200 } 201 202 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 203 { 204 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 205 qxl->num_free_res); 206 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 207 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 208 QXL_IO_FLUSH_SURFACES_ASYNC)); 209 } 210 211 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 212 uint32_t count) 213 { 214 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 215 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count); 216 } 217 218 void qxl_spice_oom(PCIQXLDevice *qxl) 219 { 220 trace_qxl_spice_oom(qxl->id); 221 spice_qxl_oom(&qxl->ssd.qxl); 222 } 223 224 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 225 { 226 trace_qxl_spice_reset_memslots(qxl->id); 227 spice_qxl_reset_memslots(&qxl->ssd.qxl); 228 } 229 230 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 231 { 232 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 233 qemu_mutex_lock(&qxl->track_lock); 234 memset(qxl->guest_surfaces.cmds, 0, 235 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 236 qxl->guest_surfaces.count = 0; 237 qemu_mutex_unlock(&qxl->track_lock); 238 } 239 240 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 241 { 242 trace_qxl_spice_destroy_surfaces(qxl->id, async); 243 if (async) { 244 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 245 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 246 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 247 } else { 248 spice_qxl_destroy_surfaces(&qxl->ssd.qxl); 249 qxl_spice_destroy_surfaces_complete(qxl); 250 } 251 } 252 253 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 254 { 255 trace_qxl_spice_monitors_config(qxl->id); 256 if (replay) { 257 /* 258 * don't use QXL_COOKIE_TYPE_IO: 259 * - we are not running yet (post_load), we will assert 260 * in send_events 261 * - this is not a guest io, but a reply, so async_io isn't set. 262 */ 263 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 264 qxl->guest_monitors_config, 265 MEMSLOT_GROUP_GUEST, 266 (uintptr_t)qxl_cookie_new( 267 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 268 0)); 269 } else { 270 qxl->guest_monitors_config = qxl->ram->monitors_config; 271 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 272 qxl->ram->monitors_config, 273 MEMSLOT_GROUP_GUEST, 274 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 275 QXL_IO_MONITORS_CONFIG_ASYNC)); 276 } 277 } 278 279 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 280 { 281 trace_qxl_spice_reset_image_cache(qxl->id); 282 spice_qxl_reset_image_cache(&qxl->ssd.qxl); 283 } 284 285 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 286 { 287 trace_qxl_spice_reset_cursor(qxl->id); 288 spice_qxl_reset_cursor(&qxl->ssd.qxl); 289 qemu_mutex_lock(&qxl->track_lock); 290 qxl->guest_cursor = 0; 291 qemu_mutex_unlock(&qxl->track_lock); 292 if (qxl->ssd.cursor) { 293 cursor_put(qxl->ssd.cursor); 294 } 295 qxl->ssd.cursor = cursor_builtin_hidden(); 296 } 297 298 299 static inline uint32_t msb_mask(uint32_t val) 300 { 301 uint32_t mask; 302 303 do { 304 mask = ~(val - 1) & val; 305 val &= ~mask; 306 } while (mask < val); 307 308 return mask; 309 } 310 311 static ram_addr_t qxl_rom_size(void) 312 { 313 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) + 314 sizeof(qxl_modes); 315 uint32_t rom_size = 8192; /* two pages */ 316 317 QEMU_BUILD_BUG_ON(required_rom_size > rom_size); 318 return rom_size; 319 } 320 321 static void init_qxl_rom(PCIQXLDevice *d) 322 { 323 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 324 QXLModes *modes = (QXLModes *)(rom + 1); 325 uint32_t ram_header_size; 326 uint32_t surface0_area_size; 327 uint32_t num_pages; 328 uint32_t fb; 329 int i, n; 330 331 memset(rom, 0, d->rom_size); 332 333 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 334 rom->id = cpu_to_le32(d->id); 335 rom->log_level = cpu_to_le32(d->guestdebug); 336 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 337 338 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 339 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 340 rom->slots_start = 1; 341 rom->slots_end = NUM_MEMSLOTS - 1; 342 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 343 344 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 345 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 346 if (fb > d->vgamem_size) { 347 continue; 348 } 349 modes->modes[n].id = cpu_to_le32(i); 350 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 351 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 352 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 353 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 354 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 355 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 356 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 357 n++; 358 } 359 modes->n_modes = cpu_to_le32(n); 360 361 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 362 surface0_area_size = ALIGN(d->vgamem_size, 4096); 363 num_pages = d->vga.vram_size; 364 num_pages -= ram_header_size; 365 num_pages -= surface0_area_size; 366 num_pages = num_pages / QXL_PAGE_SIZE; 367 368 rom->draw_area_offset = cpu_to_le32(0); 369 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 370 rom->pages_offset = cpu_to_le32(surface0_area_size); 371 rom->num_pages = cpu_to_le32(num_pages); 372 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 373 374 d->shadow_rom = *rom; 375 d->rom = rom; 376 d->modes = modes; 377 } 378 379 static void init_qxl_ram(PCIQXLDevice *d) 380 { 381 uint8_t *buf; 382 uint64_t *item; 383 384 buf = d->vga.vram_ptr; 385 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 386 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 387 d->ram->int_pending = cpu_to_le32(0); 388 d->ram->int_mask = cpu_to_le32(0); 389 d->ram->update_surface = 0; 390 d->ram->monitors_config = 0; 391 SPICE_RING_INIT(&d->ram->cmd_ring); 392 SPICE_RING_INIT(&d->ram->cursor_ring); 393 SPICE_RING_INIT(&d->ram->release_ring); 394 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); 395 assert(item); 396 *item = 0; 397 qxl_ring_set_dirty(d); 398 } 399 400 /* can be called from spice server thread context */ 401 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 402 { 403 memory_region_set_dirty(mr, addr, end - addr); 404 } 405 406 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 407 { 408 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 409 } 410 411 /* called from spice server thread context only */ 412 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 413 { 414 void *base = qxl->vga.vram_ptr; 415 intptr_t offset; 416 417 offset = ptr - base; 418 assert(offset < qxl->vga.vram_size); 419 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3); 420 } 421 422 /* can be called from spice server thread context */ 423 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 424 { 425 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 426 ram_addr_t end = qxl->vga.vram_size; 427 qxl_set_dirty(&qxl->vga.vram, addr, end); 428 } 429 430 /* 431 * keep track of some command state, for savevm/loadvm. 432 * called from spice server thread context only 433 */ 434 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 435 { 436 switch (le32_to_cpu(ext->cmd.type)) { 437 case QXL_CMD_SURFACE: 438 { 439 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 440 441 if (!cmd) { 442 return 1; 443 } 444 uint32_t id = le32_to_cpu(cmd->surface_id); 445 446 if (id >= qxl->ssd.num_surfaces) { 447 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 448 qxl->ssd.num_surfaces); 449 return 1; 450 } 451 if (cmd->type == QXL_SURFACE_CMD_CREATE && 452 (cmd->u.surface_create.stride & 0x03) != 0) { 453 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 454 cmd->u.surface_create.stride); 455 return 1; 456 } 457 qemu_mutex_lock(&qxl->track_lock); 458 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 459 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 460 qxl->guest_surfaces.count++; 461 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) 462 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 463 } 464 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 465 qxl->guest_surfaces.cmds[id] = 0; 466 qxl->guest_surfaces.count--; 467 } 468 qemu_mutex_unlock(&qxl->track_lock); 469 break; 470 } 471 case QXL_CMD_CURSOR: 472 { 473 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 474 475 if (!cmd) { 476 return 1; 477 } 478 if (cmd->type == QXL_CURSOR_SET) { 479 qemu_mutex_lock(&qxl->track_lock); 480 qxl->guest_cursor = ext->cmd.data; 481 qemu_mutex_unlock(&qxl->track_lock); 482 } 483 break; 484 } 485 } 486 return 0; 487 } 488 489 /* spice display interface callbacks */ 490 491 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 492 { 493 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 494 495 trace_qxl_interface_attach_worker(qxl->id); 496 qxl->ssd.worker = qxl_worker; 497 } 498 499 static void interface_set_compression_level(QXLInstance *sin, int level) 500 { 501 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 502 503 trace_qxl_interface_set_compression_level(qxl->id, level); 504 qxl->shadow_rom.compression_level = cpu_to_le32(level); 505 qxl->rom->compression_level = cpu_to_le32(level); 506 qxl_rom_set_dirty(qxl); 507 } 508 509 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 510 { 511 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 512 513 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 514 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 515 qxl->rom->mm_clock = cpu_to_le32(mm_time); 516 qxl_rom_set_dirty(qxl); 517 } 518 519 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 520 { 521 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 522 523 trace_qxl_interface_get_init_info(qxl->id); 524 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 525 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 526 info->num_memslots = NUM_MEMSLOTS; 527 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 528 info->internal_groupslot_id = 0; 529 info->qxl_ram_size = 530 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS; 531 info->n_surfaces = qxl->ssd.num_surfaces; 532 } 533 534 static const char *qxl_mode_to_string(int mode) 535 { 536 switch (mode) { 537 case QXL_MODE_COMPAT: 538 return "compat"; 539 case QXL_MODE_NATIVE: 540 return "native"; 541 case QXL_MODE_UNDEFINED: 542 return "undefined"; 543 case QXL_MODE_VGA: 544 return "vga"; 545 } 546 return "INVALID"; 547 } 548 549 static const char *io_port_to_string(uint32_t io_port) 550 { 551 if (io_port >= QXL_IO_RANGE_SIZE) { 552 return "out of range"; 553 } 554 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 555 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 556 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 557 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 558 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 559 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 560 [QXL_IO_RESET] = "QXL_IO_RESET", 561 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 562 [QXL_IO_LOG] = "QXL_IO_LOG", 563 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 564 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 565 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 566 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 567 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 568 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 569 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 570 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 571 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 572 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 573 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 574 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 575 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 576 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 577 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 578 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 579 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 580 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 581 }; 582 return io_port_to_string[io_port]; 583 } 584 585 /* called from spice server thread context only */ 586 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 587 { 588 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 589 SimpleSpiceUpdate *update; 590 QXLCommandRing *ring; 591 QXLCommand *cmd; 592 int notify, ret; 593 594 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 595 596 switch (qxl->mode) { 597 case QXL_MODE_VGA: 598 ret = false; 599 qemu_mutex_lock(&qxl->ssd.lock); 600 update = QTAILQ_FIRST(&qxl->ssd.updates); 601 if (update != NULL) { 602 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 603 *ext = update->ext; 604 ret = true; 605 } 606 qemu_mutex_unlock(&qxl->ssd.lock); 607 if (ret) { 608 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 609 qxl_log_command(qxl, "vga", ext); 610 } 611 return ret; 612 case QXL_MODE_COMPAT: 613 case QXL_MODE_NATIVE: 614 case QXL_MODE_UNDEFINED: 615 ring = &qxl->ram->cmd_ring; 616 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 617 return false; 618 } 619 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 620 if (!cmd) { 621 return false; 622 } 623 ext->cmd = *cmd; 624 ext->group_id = MEMSLOT_GROUP_GUEST; 625 ext->flags = qxl->cmdflags; 626 SPICE_RING_POP(ring, notify); 627 qxl_ring_set_dirty(qxl); 628 if (notify) { 629 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 630 } 631 qxl->guest_primary.commands++; 632 qxl_track_command(qxl, ext); 633 qxl_log_command(qxl, "cmd", ext); 634 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 635 return true; 636 default: 637 return false; 638 } 639 } 640 641 /* called from spice server thread context only */ 642 static int interface_req_cmd_notification(QXLInstance *sin) 643 { 644 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 645 int wait = 1; 646 647 trace_qxl_ring_command_req_notification(qxl->id); 648 switch (qxl->mode) { 649 case QXL_MODE_COMPAT: 650 case QXL_MODE_NATIVE: 651 case QXL_MODE_UNDEFINED: 652 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 653 qxl_ring_set_dirty(qxl); 654 break; 655 default: 656 /* nothing */ 657 break; 658 } 659 return wait; 660 } 661 662 /* called from spice server thread context only */ 663 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 664 { 665 QXLReleaseRing *ring = &d->ram->release_ring; 666 uint64_t *item; 667 int notify; 668 669 #define QXL_FREE_BUNCH_SIZE 32 670 671 if (ring->prod - ring->cons + 1 == ring->num_items) { 672 /* ring full -- can't push */ 673 return; 674 } 675 if (!flush && d->oom_running) { 676 /* collect everything from oom handler before pushing */ 677 return; 678 } 679 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 680 /* collect a bit more before pushing */ 681 return; 682 } 683 684 SPICE_RING_PUSH(ring, notify); 685 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 686 d->guest_surfaces.count, d->num_free_res, 687 d->last_release, notify ? "yes" : "no"); 688 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 689 ring->num_items, ring->prod, ring->cons); 690 if (notify) { 691 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 692 } 693 SPICE_RING_PROD_ITEM(d, ring, item); 694 if (!item) { 695 return; 696 } 697 *item = 0; 698 d->num_free_res = 0; 699 d->last_release = NULL; 700 qxl_ring_set_dirty(d); 701 } 702 703 /* called from spice server thread context only */ 704 static void interface_release_resource(QXLInstance *sin, 705 struct QXLReleaseInfoExt ext) 706 { 707 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 708 QXLReleaseRing *ring; 709 uint64_t *item, id; 710 711 if (ext.group_id == MEMSLOT_GROUP_HOST) { 712 /* host group -> vga mode update request */ 713 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id); 714 SimpleSpiceUpdate *update; 715 g_assert(cmdext->cmd.type == QXL_CMD_DRAW); 716 update = container_of(cmdext, SimpleSpiceUpdate, ext); 717 qemu_spice_destroy_update(&qxl->ssd, update); 718 return; 719 } 720 721 /* 722 * ext->info points into guest-visible memory 723 * pci bar 0, $command.release_info 724 */ 725 ring = &qxl->ram->release_ring; 726 SPICE_RING_PROD_ITEM(qxl, ring, item); 727 if (!item) { 728 return; 729 } 730 if (*item == 0) { 731 /* stick head into the ring */ 732 id = ext.info->id; 733 ext.info->next = 0; 734 qxl_ram_set_dirty(qxl, &ext.info->next); 735 *item = id; 736 qxl_ring_set_dirty(qxl); 737 } else { 738 /* append item to the list */ 739 qxl->last_release->next = ext.info->id; 740 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 741 ext.info->next = 0; 742 qxl_ram_set_dirty(qxl, &ext.info->next); 743 } 744 qxl->last_release = ext.info; 745 qxl->num_free_res++; 746 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 747 qxl_push_free_res(qxl, 0); 748 } 749 750 /* called from spice server thread context only */ 751 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 752 { 753 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 754 QXLCursorRing *ring; 755 QXLCommand *cmd; 756 int notify; 757 758 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 759 760 switch (qxl->mode) { 761 case QXL_MODE_COMPAT: 762 case QXL_MODE_NATIVE: 763 case QXL_MODE_UNDEFINED: 764 ring = &qxl->ram->cursor_ring; 765 if (SPICE_RING_IS_EMPTY(ring)) { 766 return false; 767 } 768 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 769 if (!cmd) { 770 return false; 771 } 772 ext->cmd = *cmd; 773 ext->group_id = MEMSLOT_GROUP_GUEST; 774 ext->flags = qxl->cmdflags; 775 SPICE_RING_POP(ring, notify); 776 qxl_ring_set_dirty(qxl); 777 if (notify) { 778 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 779 } 780 qxl->guest_primary.commands++; 781 qxl_track_command(qxl, ext); 782 qxl_log_command(qxl, "csr", ext); 783 if (qxl->id == 0) { 784 qxl_render_cursor(qxl, ext); 785 } 786 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 787 return true; 788 default: 789 return false; 790 } 791 } 792 793 /* called from spice server thread context only */ 794 static int interface_req_cursor_notification(QXLInstance *sin) 795 { 796 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 797 int wait = 1; 798 799 trace_qxl_ring_cursor_req_notification(qxl->id); 800 switch (qxl->mode) { 801 case QXL_MODE_COMPAT: 802 case QXL_MODE_NATIVE: 803 case QXL_MODE_UNDEFINED: 804 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 805 qxl_ring_set_dirty(qxl); 806 break; 807 default: 808 /* nothing */ 809 break; 810 } 811 return wait; 812 } 813 814 /* called from spice server thread context */ 815 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 816 { 817 /* 818 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 819 * use by xf86-video-qxl and is defined out in the qxl windows driver. 820 * Probably was at some earlier version that is prior to git start (2009), 821 * and is still guest trigerrable. 822 */ 823 fprintf(stderr, "%s: deprecated\n", __func__); 824 } 825 826 /* called from spice server thread context only */ 827 static int interface_flush_resources(QXLInstance *sin) 828 { 829 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 830 int ret; 831 832 ret = qxl->num_free_res; 833 if (ret) { 834 qxl_push_free_res(qxl, 1); 835 } 836 return ret; 837 } 838 839 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 840 841 /* called from spice server thread context only */ 842 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 843 { 844 uint32_t current_async; 845 846 qemu_mutex_lock(&qxl->async_lock); 847 current_async = qxl->current_async; 848 qxl->current_async = QXL_UNDEFINED_IO; 849 qemu_mutex_unlock(&qxl->async_lock); 850 851 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 852 if (!cookie) { 853 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 854 return; 855 } 856 if (cookie && current_async != cookie->io) { 857 fprintf(stderr, 858 "qxl: %s: error: current_async = %d != %" 859 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 860 } 861 switch (current_async) { 862 case QXL_IO_MEMSLOT_ADD_ASYNC: 863 case QXL_IO_DESTROY_PRIMARY_ASYNC: 864 case QXL_IO_UPDATE_AREA_ASYNC: 865 case QXL_IO_FLUSH_SURFACES_ASYNC: 866 case QXL_IO_MONITORS_CONFIG_ASYNC: 867 break; 868 case QXL_IO_CREATE_PRIMARY_ASYNC: 869 qxl_create_guest_primary_complete(qxl); 870 break; 871 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 872 qxl_spice_destroy_surfaces_complete(qxl); 873 break; 874 case QXL_IO_DESTROY_SURFACE_ASYNC: 875 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 876 break; 877 default: 878 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 879 current_async); 880 } 881 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 882 } 883 884 /* called from spice server thread context only */ 885 static void interface_update_area_complete(QXLInstance *sin, 886 uint32_t surface_id, 887 QXLRect *dirty, uint32_t num_updated_rects) 888 { 889 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 890 int i; 891 int qxl_i; 892 893 qemu_mutex_lock(&qxl->ssd.lock); 894 if (surface_id != 0 || !qxl->render_update_cookie_num) { 895 qemu_mutex_unlock(&qxl->ssd.lock); 896 return; 897 } 898 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 899 dirty->right, dirty->top, dirty->bottom); 900 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 901 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 902 /* 903 * overflow - treat this as a full update. Not expected to be common. 904 */ 905 trace_qxl_interface_update_area_complete_overflow(qxl->id, 906 QXL_NUM_DIRTY_RECTS); 907 qxl->guest_primary.resized = 1; 908 } 909 if (qxl->guest_primary.resized) { 910 /* 911 * Don't bother copying or scheduling the bh since we will flip 912 * the whole area anyway on completion of the update_area async call 913 */ 914 qemu_mutex_unlock(&qxl->ssd.lock); 915 return; 916 } 917 qxl_i = qxl->num_dirty_rects; 918 for (i = 0; i < num_updated_rects; i++) { 919 qxl->dirty[qxl_i++] = dirty[i]; 920 } 921 qxl->num_dirty_rects += num_updated_rects; 922 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 923 qxl->num_dirty_rects); 924 qemu_bh_schedule(qxl->update_area_bh); 925 qemu_mutex_unlock(&qxl->ssd.lock); 926 } 927 928 /* called from spice server thread context only */ 929 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 930 { 931 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 932 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 933 934 switch (cookie->type) { 935 case QXL_COOKIE_TYPE_IO: 936 interface_async_complete_io(qxl, cookie); 937 g_free(cookie); 938 break; 939 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 940 qxl_render_update_area_done(qxl, cookie); 941 break; 942 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 943 break; 944 default: 945 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 946 __func__, cookie->type); 947 g_free(cookie); 948 } 949 } 950 951 /* called from spice server thread context only */ 952 static void interface_set_client_capabilities(QXLInstance *sin, 953 uint8_t client_present, 954 uint8_t caps[58]) 955 { 956 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 957 958 if (qxl->revision < 4) { 959 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 960 qxl->revision); 961 return; 962 } 963 964 if (runstate_check(RUN_STATE_INMIGRATE) || 965 runstate_check(RUN_STATE_POSTMIGRATE)) { 966 return; 967 } 968 969 qxl->shadow_rom.client_present = client_present; 970 memcpy(qxl->shadow_rom.client_capabilities, caps, 971 sizeof(qxl->shadow_rom.client_capabilities)); 972 qxl->rom->client_present = client_present; 973 memcpy(qxl->rom->client_capabilities, caps, 974 sizeof(qxl->rom->client_capabilities)); 975 qxl_rom_set_dirty(qxl); 976 977 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 978 } 979 980 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 981 { 982 /* 983 * zlib xors the seed with 0xffffffff, and xors the result 984 * again with 0xffffffff; Both are not done with linux's crc32, 985 * which we want to be compatible with, so undo that. 986 */ 987 return crc32(0xffffffff, p, len) ^ 0xffffffff; 988 } 989 990 /* called from main context only */ 991 static int interface_client_monitors_config(QXLInstance *sin, 992 VDAgentMonitorsConfig *monitors_config) 993 { 994 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 995 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 996 int i; 997 998 if (qxl->revision < 4) { 999 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 1000 qxl->revision); 1001 return 0; 1002 } 1003 /* 1004 * Older windows drivers set int_mask to 0 when their ISR is called, 1005 * then later set it to ~0. So it doesn't relate to the actual interrupts 1006 * handled. However, they are old, so clearly they don't support this 1007 * interrupt 1008 */ 1009 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1010 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1011 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1012 qxl->ram->int_mask, 1013 monitors_config); 1014 return 0; 1015 } 1016 if (!monitors_config) { 1017 return 1; 1018 } 1019 memset(&rom->client_monitors_config, 0, 1020 sizeof(rom->client_monitors_config)); 1021 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1022 /* monitors_config->flags ignored */ 1023 if (rom->client_monitors_config.count >= 1024 ARRAY_SIZE(rom->client_monitors_config.heads)) { 1025 trace_qxl_client_monitors_config_capped(qxl->id, 1026 monitors_config->num_of_monitors, 1027 ARRAY_SIZE(rom->client_monitors_config.heads)); 1028 rom->client_monitors_config.count = 1029 ARRAY_SIZE(rom->client_monitors_config.heads); 1030 } 1031 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1032 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1033 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1034 /* monitor->depth ignored */ 1035 rect->left = monitor->x; 1036 rect->top = monitor->y; 1037 rect->right = monitor->x + monitor->width; 1038 rect->bottom = monitor->y + monitor->height; 1039 } 1040 rom->client_monitors_config_crc = qxl_crc32( 1041 (const uint8_t *)&rom->client_monitors_config, 1042 sizeof(rom->client_monitors_config)); 1043 trace_qxl_client_monitors_config_crc(qxl->id, 1044 sizeof(rom->client_monitors_config), 1045 rom->client_monitors_config_crc); 1046 1047 trace_qxl_interrupt_client_monitors_config(qxl->id, 1048 rom->client_monitors_config.count, 1049 rom->client_monitors_config.heads); 1050 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1051 return 1; 1052 } 1053 1054 static const QXLInterface qxl_interface = { 1055 .base.type = SPICE_INTERFACE_QXL, 1056 .base.description = "qxl gpu", 1057 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1058 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1059 1060 .attache_worker = interface_attach_worker, 1061 .set_compression_level = interface_set_compression_level, 1062 .set_mm_time = interface_set_mm_time, 1063 .get_init_info = interface_get_init_info, 1064 1065 /* the callbacks below are called from spice server thread context */ 1066 .get_command = interface_get_command, 1067 .req_cmd_notification = interface_req_cmd_notification, 1068 .release_resource = interface_release_resource, 1069 .get_cursor_command = interface_get_cursor_command, 1070 .req_cursor_notification = interface_req_cursor_notification, 1071 .notify_update = interface_notify_update, 1072 .flush_resources = interface_flush_resources, 1073 .async_complete = interface_async_complete, 1074 .update_area_complete = interface_update_area_complete, 1075 .set_client_capabilities = interface_set_client_capabilities, 1076 .client_monitors_config = interface_client_monitors_config, 1077 }; 1078 1079 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1080 { 1081 if (d->mode == QXL_MODE_VGA) { 1082 return; 1083 } 1084 trace_qxl_enter_vga_mode(d->id); 1085 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */ 1086 spice_qxl_driver_unload(&d->ssd.qxl); 1087 #endif 1088 qemu_spice_create_host_primary(&d->ssd); 1089 d->mode = QXL_MODE_VGA; 1090 vga_dirty_log_start(&d->vga); 1091 graphic_hw_update(d->vga.con); 1092 } 1093 1094 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1095 { 1096 if (d->mode != QXL_MODE_VGA) { 1097 return; 1098 } 1099 trace_qxl_exit_vga_mode(d->id); 1100 vga_dirty_log_stop(&d->vga); 1101 qxl_destroy_primary(d, QXL_SYNC); 1102 } 1103 1104 static void qxl_update_irq(PCIQXLDevice *d) 1105 { 1106 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1107 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1108 int level = !!(pending & mask); 1109 pci_set_irq(&d->pci, level); 1110 qxl_ring_set_dirty(d); 1111 } 1112 1113 static void qxl_check_state(PCIQXLDevice *d) 1114 { 1115 QXLRam *ram = d->ram; 1116 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1117 1118 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1119 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1120 } 1121 1122 static void qxl_reset_state(PCIQXLDevice *d) 1123 { 1124 QXLRom *rom = d->rom; 1125 1126 qxl_check_state(d); 1127 d->shadow_rom.update_id = cpu_to_le32(0); 1128 *rom = d->shadow_rom; 1129 qxl_rom_set_dirty(d); 1130 init_qxl_ram(d); 1131 d->num_free_res = 0; 1132 d->last_release = NULL; 1133 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1134 qxl_update_irq(d); 1135 } 1136 1137 static void qxl_soft_reset(PCIQXLDevice *d) 1138 { 1139 trace_qxl_soft_reset(d->id); 1140 qxl_check_state(d); 1141 qxl_clear_guest_bug(d); 1142 d->current_async = QXL_UNDEFINED_IO; 1143 1144 if (d->id == 0) { 1145 qxl_enter_vga_mode(d); 1146 } else { 1147 d->mode = QXL_MODE_UNDEFINED; 1148 } 1149 } 1150 1151 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1152 { 1153 bool startstop = qemu_spice_display_is_running(&d->ssd); 1154 1155 trace_qxl_hard_reset(d->id, loadvm); 1156 1157 if (startstop) { 1158 qemu_spice_display_stop(); 1159 } 1160 1161 qxl_spice_reset_cursor(d); 1162 qxl_spice_reset_image_cache(d); 1163 qxl_reset_surfaces(d); 1164 qxl_reset_memslots(d); 1165 1166 /* pre loadvm reset must not touch QXLRam. This lives in 1167 * device memory, is migrated together with RAM and thus 1168 * already loaded at this point */ 1169 if (!loadvm) { 1170 qxl_reset_state(d); 1171 } 1172 qemu_spice_create_host_memslot(&d->ssd); 1173 qxl_soft_reset(d); 1174 1175 if (startstop) { 1176 qemu_spice_display_start(); 1177 } 1178 } 1179 1180 static void qxl_reset_handler(DeviceState *dev) 1181 { 1182 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); 1183 1184 qxl_hard_reset(d, 0); 1185 } 1186 1187 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1188 { 1189 VGACommonState *vga = opaque; 1190 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1191 1192 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1193 if (qxl->mode != QXL_MODE_VGA) { 1194 qxl_destroy_primary(qxl, QXL_SYNC); 1195 qxl_soft_reset(qxl); 1196 } 1197 vga_ioport_write(opaque, addr, val); 1198 } 1199 1200 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1201 { 0x04, 2, 1, .read = vga_ioport_read, 1202 .write = qxl_vga_ioport_write }, /* 3b4 */ 1203 { 0x0a, 1, 1, .read = vga_ioport_read, 1204 .write = qxl_vga_ioport_write }, /* 3ba */ 1205 { 0x10, 16, 1, .read = vga_ioport_read, 1206 .write = qxl_vga_ioport_write }, /* 3c0 */ 1207 { 0x24, 2, 1, .read = vga_ioport_read, 1208 .write = qxl_vga_ioport_write }, /* 3d4 */ 1209 { 0x2a, 1, 1, .read = vga_ioport_read, 1210 .write = qxl_vga_ioport_write }, /* 3da */ 1211 PORTIO_END_OF_LIST(), 1212 }; 1213 1214 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1215 qxl_async_io async) 1216 { 1217 static const int regions[] = { 1218 QXL_RAM_RANGE_INDEX, 1219 QXL_VRAM_RANGE_INDEX, 1220 QXL_VRAM64_RANGE_INDEX, 1221 }; 1222 uint64_t guest_start; 1223 uint64_t guest_end; 1224 int pci_region; 1225 pcibus_t pci_start; 1226 pcibus_t pci_end; 1227 intptr_t virt_start; 1228 QXLDevMemSlot memslot; 1229 int i; 1230 1231 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1232 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1233 1234 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1235 1236 if (slot_id >= NUM_MEMSLOTS) { 1237 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1238 slot_id, NUM_MEMSLOTS); 1239 return 1; 1240 } 1241 if (guest_start > guest_end) { 1242 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1243 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1244 return 1; 1245 } 1246 1247 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1248 pci_region = regions[i]; 1249 pci_start = d->pci.io_regions[pci_region].addr; 1250 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1251 /* mapped? */ 1252 if (pci_start == -1) { 1253 continue; 1254 } 1255 /* start address in range ? */ 1256 if (guest_start < pci_start || guest_start > pci_end) { 1257 continue; 1258 } 1259 /* end address in range ? */ 1260 if (guest_end > pci_end) { 1261 continue; 1262 } 1263 /* passed */ 1264 break; 1265 } 1266 if (i == ARRAY_SIZE(regions)) { 1267 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1268 return 1; 1269 } 1270 1271 switch (pci_region) { 1272 case QXL_RAM_RANGE_INDEX: 1273 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); 1274 break; 1275 case QXL_VRAM_RANGE_INDEX: 1276 case 4 /* vram 64bit */: 1277 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); 1278 break; 1279 default: 1280 /* should not happen */ 1281 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1282 return 1; 1283 } 1284 1285 memslot.slot_id = slot_id; 1286 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1287 memslot.virt_start = virt_start + (guest_start - pci_start); 1288 memslot.virt_end = virt_start + (guest_end - pci_start); 1289 memslot.addr_delta = memslot.virt_start - delta; 1290 memslot.generation = d->rom->slot_generation = 0; 1291 qxl_rom_set_dirty(d); 1292 1293 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1294 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; 1295 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1296 d->guest_slots[slot_id].delta = delta; 1297 d->guest_slots[slot_id].active = 1; 1298 return 0; 1299 } 1300 1301 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1302 { 1303 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1304 d->guest_slots[slot_id].active = 0; 1305 } 1306 1307 static void qxl_reset_memslots(PCIQXLDevice *d) 1308 { 1309 qxl_spice_reset_memslots(d); 1310 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1311 } 1312 1313 static void qxl_reset_surfaces(PCIQXLDevice *d) 1314 { 1315 trace_qxl_reset_surfaces(d->id); 1316 d->mode = QXL_MODE_UNDEFINED; 1317 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1318 } 1319 1320 /* can be also called from spice server thread context */ 1321 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1322 { 1323 uint64_t phys = le64_to_cpu(pqxl); 1324 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1325 uint64_t offset = phys & 0xffffffffffff; 1326 1327 switch (group_id) { 1328 case MEMSLOT_GROUP_HOST: 1329 return (void *)(intptr_t)offset; 1330 case MEMSLOT_GROUP_GUEST: 1331 if (slot >= NUM_MEMSLOTS) { 1332 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1333 NUM_MEMSLOTS); 1334 return NULL; 1335 } 1336 if (!qxl->guest_slots[slot].active) { 1337 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1338 return NULL; 1339 } 1340 if (offset < qxl->guest_slots[slot].delta) { 1341 qxl_set_guest_bug(qxl, 1342 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1343 slot, offset, qxl->guest_slots[slot].delta); 1344 return NULL; 1345 } 1346 offset -= qxl->guest_slots[slot].delta; 1347 if (offset > qxl->guest_slots[slot].size) { 1348 qxl_set_guest_bug(qxl, 1349 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1350 slot, offset, qxl->guest_slots[slot].size); 1351 return NULL; 1352 } 1353 return qxl->guest_slots[slot].ptr + offset; 1354 } 1355 return NULL; 1356 } 1357 1358 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1359 { 1360 /* for local rendering */ 1361 qxl_render_resize(qxl); 1362 } 1363 1364 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1365 qxl_async_io async) 1366 { 1367 QXLDevSurfaceCreate surface; 1368 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1369 uint32_t requested_height = le32_to_cpu(sc->height); 1370 int requested_stride = le32_to_cpu(sc->stride); 1371 1372 if (requested_stride == INT32_MIN || 1373 abs(requested_stride) * (uint64_t)requested_height 1374 > qxl->vgamem_size) { 1375 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer" 1376 " stride %d x height %" PRIu32 " > %" PRIu32, 1377 __func__, requested_stride, requested_height, 1378 qxl->vgamem_size); 1379 return; 1380 } 1381 1382 if (qxl->mode == QXL_MODE_NATIVE) { 1383 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1384 __func__); 1385 } 1386 qxl_exit_vga_mode(qxl); 1387 1388 surface.format = le32_to_cpu(sc->format); 1389 surface.height = le32_to_cpu(sc->height); 1390 surface.mem = le64_to_cpu(sc->mem); 1391 surface.position = le32_to_cpu(sc->position); 1392 surface.stride = le32_to_cpu(sc->stride); 1393 surface.width = le32_to_cpu(sc->width); 1394 surface.type = le32_to_cpu(sc->type); 1395 surface.flags = le32_to_cpu(sc->flags); 1396 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1397 sc->format, sc->position); 1398 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1399 sc->flags); 1400 1401 if ((surface.stride & 0x3) != 0) { 1402 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1403 surface.stride); 1404 return; 1405 } 1406 1407 surface.mouse_mode = true; 1408 surface.group_id = MEMSLOT_GROUP_GUEST; 1409 if (loadvm) { 1410 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1411 } 1412 1413 qxl->mode = QXL_MODE_NATIVE; 1414 qxl->cmdflags = 0; 1415 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1416 1417 if (async == QXL_SYNC) { 1418 qxl_create_guest_primary_complete(qxl); 1419 } 1420 } 1421 1422 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1423 * done (in QXL_SYNC case), 0 otherwise. */ 1424 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1425 { 1426 if (d->mode == QXL_MODE_UNDEFINED) { 1427 return 0; 1428 } 1429 trace_qxl_destroy_primary(d->id); 1430 d->mode = QXL_MODE_UNDEFINED; 1431 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1432 qxl_spice_reset_cursor(d); 1433 return 1; 1434 } 1435 1436 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm) 1437 { 1438 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1439 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1440 QXLMode *mode = d->modes->modes + modenr; 1441 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1442 QXLMemSlot slot = { 1443 .mem_start = start, 1444 .mem_end = end 1445 }; 1446 1447 if (modenr >= d->modes->n_modes) { 1448 qxl_set_guest_bug(d, "mode number out of range"); 1449 return; 1450 } 1451 1452 QXLSurfaceCreate surface = { 1453 .width = mode->x_res, 1454 .height = mode->y_res, 1455 .stride = -mode->x_res * 4, 1456 .format = SPICE_SURFACE_FMT_32_xRGB, 1457 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1458 .mouse_mode = true, 1459 .mem = devmem + d->shadow_rom.draw_area_offset, 1460 }; 1461 1462 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1463 devmem); 1464 if (!loadvm) { 1465 qxl_hard_reset(d, 0); 1466 } 1467 1468 d->guest_slots[0].slot = slot; 1469 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1470 1471 d->guest_primary.surface = surface; 1472 qxl_create_guest_primary(d, 0, QXL_SYNC); 1473 1474 d->mode = QXL_MODE_COMPAT; 1475 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1476 if (mode->bits == 16) { 1477 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1478 } 1479 d->shadow_rom.mode = cpu_to_le32(modenr); 1480 d->rom->mode = cpu_to_le32(modenr); 1481 qxl_rom_set_dirty(d); 1482 } 1483 1484 static void ioport_write(void *opaque, hwaddr addr, 1485 uint64_t val, unsigned size) 1486 { 1487 PCIQXLDevice *d = opaque; 1488 uint32_t io_port = addr; 1489 qxl_async_io async = QXL_SYNC; 1490 uint32_t orig_io_port = io_port; 1491 1492 if (d->guest_bug && io_port != QXL_IO_RESET) { 1493 return; 1494 } 1495 1496 if (d->revision <= QXL_REVISION_STABLE_V10 && 1497 io_port > QXL_IO_FLUSH_RELEASE) { 1498 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1499 io_port, d->revision); 1500 return; 1501 } 1502 1503 switch (io_port) { 1504 case QXL_IO_RESET: 1505 case QXL_IO_SET_MODE: 1506 case QXL_IO_MEMSLOT_ADD: 1507 case QXL_IO_MEMSLOT_DEL: 1508 case QXL_IO_CREATE_PRIMARY: 1509 case QXL_IO_UPDATE_IRQ: 1510 case QXL_IO_LOG: 1511 case QXL_IO_MEMSLOT_ADD_ASYNC: 1512 case QXL_IO_CREATE_PRIMARY_ASYNC: 1513 break; 1514 default: 1515 if (d->mode != QXL_MODE_VGA) { 1516 break; 1517 } 1518 trace_qxl_io_unexpected_vga_mode(d->id, 1519 addr, val, io_port_to_string(io_port)); 1520 /* be nice to buggy guest drivers */ 1521 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1522 io_port < QXL_IO_RANGE_SIZE) { 1523 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1524 } 1525 return; 1526 } 1527 1528 /* we change the io_port to avoid ifdeffery in the main switch */ 1529 orig_io_port = io_port; 1530 switch (io_port) { 1531 case QXL_IO_UPDATE_AREA_ASYNC: 1532 io_port = QXL_IO_UPDATE_AREA; 1533 goto async_common; 1534 case QXL_IO_MEMSLOT_ADD_ASYNC: 1535 io_port = QXL_IO_MEMSLOT_ADD; 1536 goto async_common; 1537 case QXL_IO_CREATE_PRIMARY_ASYNC: 1538 io_port = QXL_IO_CREATE_PRIMARY; 1539 goto async_common; 1540 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1541 io_port = QXL_IO_DESTROY_PRIMARY; 1542 goto async_common; 1543 case QXL_IO_DESTROY_SURFACE_ASYNC: 1544 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1545 goto async_common; 1546 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1547 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1548 goto async_common; 1549 case QXL_IO_FLUSH_SURFACES_ASYNC: 1550 case QXL_IO_MONITORS_CONFIG_ASYNC: 1551 async_common: 1552 async = QXL_ASYNC; 1553 qemu_mutex_lock(&d->async_lock); 1554 if (d->current_async != QXL_UNDEFINED_IO) { 1555 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1556 io_port, d->current_async); 1557 qemu_mutex_unlock(&d->async_lock); 1558 return; 1559 } 1560 d->current_async = orig_io_port; 1561 qemu_mutex_unlock(&d->async_lock); 1562 break; 1563 default: 1564 break; 1565 } 1566 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), 1567 addr, io_port_to_string(addr), 1568 val, size, async); 1569 1570 switch (io_port) { 1571 case QXL_IO_UPDATE_AREA: 1572 { 1573 QXLCookie *cookie = NULL; 1574 QXLRect update = d->ram->update_area; 1575 1576 if (d->ram->update_surface > d->ssd.num_surfaces) { 1577 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1578 d->ram->update_surface); 1579 break; 1580 } 1581 if (update.left >= update.right || update.top >= update.bottom || 1582 update.left < 0 || update.top < 0) { 1583 qxl_set_guest_bug(d, 1584 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1585 update.left, update.top, update.right, update.bottom); 1586 break; 1587 } 1588 if (async == QXL_ASYNC) { 1589 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1590 QXL_IO_UPDATE_AREA_ASYNC); 1591 cookie->u.area = update; 1592 } 1593 qxl_spice_update_area(d, d->ram->update_surface, 1594 cookie ? &cookie->u.area : &update, 1595 NULL, 0, 0, async, cookie); 1596 break; 1597 } 1598 case QXL_IO_NOTIFY_CMD: 1599 qemu_spice_wakeup(&d->ssd); 1600 break; 1601 case QXL_IO_NOTIFY_CURSOR: 1602 qemu_spice_wakeup(&d->ssd); 1603 break; 1604 case QXL_IO_UPDATE_IRQ: 1605 qxl_update_irq(d); 1606 break; 1607 case QXL_IO_NOTIFY_OOM: 1608 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1609 break; 1610 } 1611 d->oom_running = 1; 1612 qxl_spice_oom(d); 1613 d->oom_running = 0; 1614 break; 1615 case QXL_IO_SET_MODE: 1616 qxl_set_mode(d, val, 0); 1617 break; 1618 case QXL_IO_LOG: 1619 trace_qxl_io_log(d->id, d->ram->log_buf); 1620 if (d->guestdebug) { 1621 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1622 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf); 1623 } 1624 break; 1625 case QXL_IO_RESET: 1626 qxl_hard_reset(d, 0); 1627 break; 1628 case QXL_IO_MEMSLOT_ADD: 1629 if (val >= NUM_MEMSLOTS) { 1630 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1631 break; 1632 } 1633 if (d->guest_slots[val].active) { 1634 qxl_set_guest_bug(d, 1635 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1636 break; 1637 } 1638 d->guest_slots[val].slot = d->ram->mem_slot; 1639 qxl_add_memslot(d, val, 0, async); 1640 break; 1641 case QXL_IO_MEMSLOT_DEL: 1642 if (val >= NUM_MEMSLOTS) { 1643 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1644 break; 1645 } 1646 qxl_del_memslot(d, val); 1647 break; 1648 case QXL_IO_CREATE_PRIMARY: 1649 if (val != 0) { 1650 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1651 async); 1652 goto cancel_async; 1653 } 1654 d->guest_primary.surface = d->ram->create_surface; 1655 qxl_create_guest_primary(d, 0, async); 1656 break; 1657 case QXL_IO_DESTROY_PRIMARY: 1658 if (val != 0) { 1659 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1660 async); 1661 goto cancel_async; 1662 } 1663 if (!qxl_destroy_primary(d, async)) { 1664 trace_qxl_io_destroy_primary_ignored(d->id, 1665 qxl_mode_to_string(d->mode)); 1666 goto cancel_async; 1667 } 1668 break; 1669 case QXL_IO_DESTROY_SURFACE_WAIT: 1670 if (val >= d->ssd.num_surfaces) { 1671 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1672 "%" PRIu64 " >= NUM_SURFACES", async, val); 1673 goto cancel_async; 1674 } 1675 qxl_spice_destroy_surface_wait(d, val, async); 1676 break; 1677 case QXL_IO_FLUSH_RELEASE: { 1678 QXLReleaseRing *ring = &d->ram->release_ring; 1679 if (ring->prod - ring->cons + 1 == ring->num_items) { 1680 fprintf(stderr, 1681 "ERROR: no flush, full release ring [p%d,%dc]\n", 1682 ring->prod, ring->cons); 1683 } 1684 qxl_push_free_res(d, 1 /* flush */); 1685 break; 1686 } 1687 case QXL_IO_FLUSH_SURFACES_ASYNC: 1688 qxl_spice_flush_surfaces_async(d); 1689 break; 1690 case QXL_IO_DESTROY_ALL_SURFACES: 1691 d->mode = QXL_MODE_UNDEFINED; 1692 qxl_spice_destroy_surfaces(d, async); 1693 break; 1694 case QXL_IO_MONITORS_CONFIG_ASYNC: 1695 qxl_spice_monitors_config_async(d, 0); 1696 break; 1697 default: 1698 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1699 } 1700 return; 1701 cancel_async: 1702 if (async) { 1703 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1704 qemu_mutex_lock(&d->async_lock); 1705 d->current_async = QXL_UNDEFINED_IO; 1706 qemu_mutex_unlock(&d->async_lock); 1707 } 1708 } 1709 1710 static uint64_t ioport_read(void *opaque, hwaddr addr, 1711 unsigned size) 1712 { 1713 PCIQXLDevice *qxl = opaque; 1714 1715 trace_qxl_io_read_unexpected(qxl->id); 1716 return 0xff; 1717 } 1718 1719 static const MemoryRegionOps qxl_io_ops = { 1720 .read = ioport_read, 1721 .write = ioport_write, 1722 .valid = { 1723 .min_access_size = 1, 1724 .max_access_size = 1, 1725 }, 1726 }; 1727 1728 static void qxl_update_irq_bh(void *opaque) 1729 { 1730 PCIQXLDevice *d = opaque; 1731 qxl_update_irq(d); 1732 } 1733 1734 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1735 { 1736 uint32_t old_pending; 1737 uint32_t le_events = cpu_to_le32(events); 1738 1739 trace_qxl_send_events(d->id, events); 1740 if (!qemu_spice_display_is_running(&d->ssd)) { 1741 /* spice-server tracks guest running state and should not do this */ 1742 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1743 __func__); 1744 trace_qxl_send_events_vm_stopped(d->id, events); 1745 return; 1746 } 1747 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events); 1748 if ((old_pending & le_events) == le_events) { 1749 return; 1750 } 1751 qemu_bh_schedule(d->update_irq); 1752 } 1753 1754 /* graphics console */ 1755 1756 static void qxl_hw_update(void *opaque) 1757 { 1758 PCIQXLDevice *qxl = opaque; 1759 VGACommonState *vga = &qxl->vga; 1760 1761 switch (qxl->mode) { 1762 case QXL_MODE_VGA: 1763 vga->hw_ops->gfx_update(vga); 1764 break; 1765 case QXL_MODE_COMPAT: 1766 case QXL_MODE_NATIVE: 1767 qxl_render_update(qxl); 1768 break; 1769 default: 1770 break; 1771 } 1772 } 1773 1774 static void qxl_hw_invalidate(void *opaque) 1775 { 1776 PCIQXLDevice *qxl = opaque; 1777 VGACommonState *vga = &qxl->vga; 1778 1779 if (qxl->mode == QXL_MODE_VGA) { 1780 vga->hw_ops->invalidate(vga); 1781 return; 1782 } 1783 } 1784 1785 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) 1786 { 1787 PCIQXLDevice *qxl = opaque; 1788 VGACommonState *vga = &qxl->vga; 1789 1790 if (qxl->mode == QXL_MODE_VGA) { 1791 vga->hw_ops->text_update(vga, chardata); 1792 return; 1793 } 1794 } 1795 1796 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1797 { 1798 uintptr_t vram_start; 1799 int i; 1800 1801 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1802 return; 1803 } 1804 1805 /* dirty the primary surface */ 1806 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, 1807 qxl->shadow_rom.surface0_area_size); 1808 1809 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); 1810 1811 /* dirty the off-screen surfaces */ 1812 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1813 QXLSurfaceCmd *cmd; 1814 intptr_t surface_offset; 1815 int surface_size; 1816 1817 if (qxl->guest_surfaces.cmds[i] == 0) { 1818 continue; 1819 } 1820 1821 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1822 MEMSLOT_GROUP_GUEST); 1823 assert(cmd); 1824 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1825 surface_offset = (intptr_t)qxl_phys2virt(qxl, 1826 cmd->u.surface_create.data, 1827 MEMSLOT_GROUP_GUEST); 1828 assert(surface_offset); 1829 surface_offset -= vram_start; 1830 surface_size = cmd->u.surface_create.height * 1831 abs(cmd->u.surface_create.stride); 1832 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); 1833 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); 1834 } 1835 } 1836 1837 static void qxl_vm_change_state_handler(void *opaque, int running, 1838 RunState state) 1839 { 1840 PCIQXLDevice *qxl = opaque; 1841 1842 if (running) { 1843 /* 1844 * if qxl_send_events was called from spice server context before 1845 * migration ended, qxl_update_irq for these events might not have been 1846 * called 1847 */ 1848 qxl_update_irq(qxl); 1849 } else { 1850 /* make sure surfaces are saved before migration */ 1851 qxl_dirty_surfaces(qxl); 1852 } 1853 } 1854 1855 /* display change listener */ 1856 1857 static void display_update(DisplayChangeListener *dcl, 1858 int x, int y, int w, int h) 1859 { 1860 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1861 1862 if (qxl->mode == QXL_MODE_VGA) { 1863 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 1864 } 1865 } 1866 1867 static void display_switch(DisplayChangeListener *dcl, 1868 struct DisplaySurface *surface) 1869 { 1870 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1871 1872 qxl->ssd.ds = surface; 1873 if (qxl->mode == QXL_MODE_VGA) { 1874 qemu_spice_display_switch(&qxl->ssd, surface); 1875 } 1876 } 1877 1878 static void display_refresh(DisplayChangeListener *dcl) 1879 { 1880 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1881 1882 if (qxl->mode == QXL_MODE_VGA) { 1883 qemu_spice_display_refresh(&qxl->ssd); 1884 } else { 1885 qemu_mutex_lock(&qxl->ssd.lock); 1886 qemu_spice_cursor_refresh_unlocked(&qxl->ssd); 1887 qemu_mutex_unlock(&qxl->ssd.lock); 1888 } 1889 } 1890 1891 static DisplayChangeListenerOps display_listener_ops = { 1892 .dpy_name = "spice/qxl", 1893 .dpy_gfx_update = display_update, 1894 .dpy_gfx_switch = display_switch, 1895 .dpy_refresh = display_refresh, 1896 }; 1897 1898 static void qxl_init_ramsize(PCIQXLDevice *qxl) 1899 { 1900 /* vga mode framebuffer / primary surface (bar 0, first part) */ 1901 if (qxl->vgamem_size_mb < 8) { 1902 qxl->vgamem_size_mb = 8; 1903 } 1904 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; 1905 1906 /* vga ram (bar 0, total) */ 1907 if (qxl->ram_size_mb != -1) { 1908 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; 1909 } 1910 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 1911 qxl->vga.vram_size = qxl->vgamem_size * 2; 1912 } 1913 1914 /* vram32 (surfaces, 32bit, bar 1) */ 1915 if (qxl->vram32_size_mb != -1) { 1916 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; 1917 } 1918 if (qxl->vram32_size < 4096) { 1919 qxl->vram32_size = 4096; 1920 } 1921 1922 /* vram (surfaces, 64bit, bar 4+5) */ 1923 if (qxl->vram_size_mb != -1) { 1924 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; 1925 } 1926 if (qxl->vram_size < qxl->vram32_size) { 1927 qxl->vram_size = qxl->vram32_size; 1928 } 1929 1930 if (qxl->revision == 1) { 1931 qxl->vram32_size = 4096; 1932 qxl->vram_size = 4096; 1933 } 1934 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1); 1935 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); 1936 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); 1937 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); 1938 } 1939 1940 static int qxl_init_common(PCIQXLDevice *qxl) 1941 { 1942 uint8_t* config = qxl->pci.config; 1943 uint32_t pci_device_rev; 1944 uint32_t io_size; 1945 1946 qxl->mode = QXL_MODE_UNDEFINED; 1947 qxl->generation = 1; 1948 qxl->num_memslots = NUM_MEMSLOTS; 1949 qemu_mutex_init(&qxl->track_lock); 1950 qemu_mutex_init(&qxl->async_lock); 1951 qxl->current_async = QXL_UNDEFINED_IO; 1952 qxl->guest_bug = 0; 1953 1954 switch (qxl->revision) { 1955 case 1: /* spice 0.4 -- qxl-1 */ 1956 pci_device_rev = QXL_REVISION_STABLE_V04; 1957 io_size = 8; 1958 break; 1959 case 2: /* spice 0.6 -- qxl-2 */ 1960 pci_device_rev = QXL_REVISION_STABLE_V06; 1961 io_size = 16; 1962 break; 1963 case 3: /* qxl-3 */ 1964 pci_device_rev = QXL_REVISION_STABLE_V10; 1965 io_size = 32; /* PCI region size must be pow2 */ 1966 break; 1967 case 4: /* qxl-4 */ 1968 pci_device_rev = QXL_REVISION_STABLE_V12; 1969 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); 1970 break; 1971 default: 1972 error_report("Invalid revision %d for qxl device (max %d)", 1973 qxl->revision, QXL_DEFAULT_REVISION); 1974 return -1; 1975 } 1976 1977 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 1978 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 1979 1980 qxl->rom_size = qxl_rom_size(); 1981 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", 1982 qxl->rom_size); 1983 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); 1984 init_qxl_rom(qxl); 1985 init_qxl_ram(qxl); 1986 1987 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 1988 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", 1989 qxl->vram_size); 1990 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); 1991 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32", 1992 &qxl->vram_bar, 0, qxl->vram32_size); 1993 1994 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl, 1995 "qxl-ioports", io_size); 1996 if (qxl->id == 0) { 1997 vga_dirty_log_start(&qxl->vga); 1998 } 1999 memory_region_set_flush_coalesced(&qxl->io_bar); 2000 2001 2002 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 2003 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 2004 2005 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 2006 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 2007 2008 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 2009 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 2010 2011 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 2012 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 2013 2014 if (qxl->vram32_size < qxl->vram_size) { 2015 /* 2016 * Make the 64bit vram bar show up only in case it is 2017 * configured to be larger than the 32bit vram bar. 2018 */ 2019 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 2020 PCI_BASE_ADDRESS_SPACE_MEMORY | 2021 PCI_BASE_ADDRESS_MEM_TYPE_64 | 2022 PCI_BASE_ADDRESS_MEM_PREFETCH, 2023 &qxl->vram_bar); 2024 } 2025 2026 /* print pci bar details */ 2027 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", 2028 qxl->id == 0 ? "pri" : "sec", 2029 qxl->vga.vram_size / (1024*1024)); 2030 dprint(qxl, 1, "vram/32: %d MB [region 1]\n", 2031 qxl->vram32_size / (1024*1024)); 2032 dprint(qxl, 1, "vram/64: %d MB %s\n", 2033 qxl->vram_size / (1024*1024), 2034 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2035 2036 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2037 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) { 2038 error_report("qxl interface %d.%d not supported by spice-server", 2039 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2040 return -1; 2041 } 2042 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2043 2044 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl); 2045 qxl_reset_state(qxl); 2046 2047 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2048 2049 return 0; 2050 } 2051 2052 static const GraphicHwOps qxl_ops = { 2053 .invalidate = qxl_hw_invalidate, 2054 .gfx_update = qxl_hw_update, 2055 .text_update = qxl_hw_text_update, 2056 }; 2057 2058 static int qxl_init_primary(PCIDevice *dev) 2059 { 2060 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2061 VGACommonState *vga = &qxl->vga; 2062 int rc; 2063 2064 qxl->id = 0; 2065 qxl_init_ramsize(qxl); 2066 vga->vram_size_mb = qxl->vga.vram_size >> 20; 2067 vga_common_init(vga, OBJECT(dev), true); 2068 vga_init(vga, OBJECT(dev), 2069 pci_address_space(dev), pci_address_space_io(dev), false); 2070 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list, 2071 vga, "vga"); 2072 portio_list_set_flush_coalesced(&qxl->vga_port_list); 2073 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0); 2074 2075 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2076 qemu_spice_display_init_common(&qxl->ssd); 2077 2078 rc = qxl_init_common(qxl); 2079 if (rc != 0) { 2080 return rc; 2081 } 2082 2083 qxl->ssd.dcl.ops = &display_listener_ops; 2084 qxl->ssd.dcl.con = vga->con; 2085 register_displaychangelistener(&qxl->ssd.dcl); 2086 return rc; 2087 } 2088 2089 static int qxl_init_secondary(PCIDevice *dev) 2090 { 2091 static int device_id = 1; 2092 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2093 2094 qxl->id = device_id++; 2095 qxl_init_ramsize(qxl); 2096 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram", 2097 qxl->vga.vram_size); 2098 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); 2099 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2100 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2101 2102 return qxl_init_common(qxl); 2103 } 2104 2105 static void qxl_pre_save(void *opaque) 2106 { 2107 PCIQXLDevice* d = opaque; 2108 uint8_t *ram_start = d->vga.vram_ptr; 2109 2110 trace_qxl_pre_save(d->id); 2111 if (d->last_release == NULL) { 2112 d->last_release_offset = 0; 2113 } else { 2114 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2115 } 2116 assert(d->last_release_offset < d->vga.vram_size); 2117 } 2118 2119 static int qxl_pre_load(void *opaque) 2120 { 2121 PCIQXLDevice* d = opaque; 2122 2123 trace_qxl_pre_load(d->id); 2124 qxl_hard_reset(d, 1); 2125 qxl_exit_vga_mode(d); 2126 return 0; 2127 } 2128 2129 static void qxl_create_memslots(PCIQXLDevice *d) 2130 { 2131 int i; 2132 2133 for (i = 0; i < NUM_MEMSLOTS; i++) { 2134 if (!d->guest_slots[i].active) { 2135 continue; 2136 } 2137 qxl_add_memslot(d, i, 0, QXL_SYNC); 2138 } 2139 } 2140 2141 static int qxl_post_load(void *opaque, int version) 2142 { 2143 PCIQXLDevice* d = opaque; 2144 uint8_t *ram_start = d->vga.vram_ptr; 2145 QXLCommandExt *cmds; 2146 int in, out, newmode; 2147 2148 assert(d->last_release_offset < d->vga.vram_size); 2149 if (d->last_release_offset == 0) { 2150 d->last_release = NULL; 2151 } else { 2152 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2153 } 2154 2155 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2156 2157 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2158 newmode = d->mode; 2159 d->mode = QXL_MODE_UNDEFINED; 2160 2161 switch (newmode) { 2162 case QXL_MODE_UNDEFINED: 2163 qxl_create_memslots(d); 2164 break; 2165 case QXL_MODE_VGA: 2166 qxl_create_memslots(d); 2167 qxl_enter_vga_mode(d); 2168 break; 2169 case QXL_MODE_NATIVE: 2170 qxl_create_memslots(d); 2171 qxl_create_guest_primary(d, 1, QXL_SYNC); 2172 2173 /* replay surface-create and cursor-set commands */ 2174 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1)); 2175 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2176 if (d->guest_surfaces.cmds[in] == 0) { 2177 continue; 2178 } 2179 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2180 cmds[out].cmd.type = QXL_CMD_SURFACE; 2181 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2182 out++; 2183 } 2184 if (d->guest_cursor) { 2185 cmds[out].cmd.data = d->guest_cursor; 2186 cmds[out].cmd.type = QXL_CMD_CURSOR; 2187 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2188 out++; 2189 } 2190 qxl_spice_loadvm_commands(d, cmds, out); 2191 g_free(cmds); 2192 if (d->guest_monitors_config) { 2193 qxl_spice_monitors_config_async(d, 1); 2194 } 2195 break; 2196 case QXL_MODE_COMPAT: 2197 /* note: no need to call qxl_create_memslots, qxl_set_mode 2198 * creates the mem slot. */ 2199 qxl_set_mode(d, d->shadow_rom.mode, 1); 2200 break; 2201 } 2202 return 0; 2203 } 2204 2205 #define QXL_SAVE_VERSION 21 2206 2207 static bool qxl_monitors_config_needed(void *opaque) 2208 { 2209 PCIQXLDevice *qxl = opaque; 2210 2211 return qxl->guest_monitors_config != 0; 2212 } 2213 2214 2215 static VMStateDescription qxl_memslot = { 2216 .name = "qxl-memslot", 2217 .version_id = QXL_SAVE_VERSION, 2218 .minimum_version_id = QXL_SAVE_VERSION, 2219 .fields = (VMStateField[]) { 2220 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2221 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2222 VMSTATE_UINT32(active, struct guest_slots), 2223 VMSTATE_END_OF_LIST() 2224 } 2225 }; 2226 2227 static VMStateDescription qxl_surface = { 2228 .name = "qxl-surface", 2229 .version_id = QXL_SAVE_VERSION, 2230 .minimum_version_id = QXL_SAVE_VERSION, 2231 .fields = (VMStateField[]) { 2232 VMSTATE_UINT32(width, QXLSurfaceCreate), 2233 VMSTATE_UINT32(height, QXLSurfaceCreate), 2234 VMSTATE_INT32(stride, QXLSurfaceCreate), 2235 VMSTATE_UINT32(format, QXLSurfaceCreate), 2236 VMSTATE_UINT32(position, QXLSurfaceCreate), 2237 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2238 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2239 VMSTATE_UINT32(type, QXLSurfaceCreate), 2240 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2241 VMSTATE_END_OF_LIST() 2242 } 2243 }; 2244 2245 static VMStateDescription qxl_vmstate_monitors_config = { 2246 .name = "qxl/monitors-config", 2247 .version_id = 1, 2248 .minimum_version_id = 1, 2249 .fields = (VMStateField[]) { 2250 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2251 VMSTATE_END_OF_LIST() 2252 }, 2253 }; 2254 2255 static VMStateDescription qxl_vmstate = { 2256 .name = "qxl", 2257 .version_id = QXL_SAVE_VERSION, 2258 .minimum_version_id = QXL_SAVE_VERSION, 2259 .pre_save = qxl_pre_save, 2260 .pre_load = qxl_pre_load, 2261 .post_load = qxl_post_load, 2262 .fields = (VMStateField[]) { 2263 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2264 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2265 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2266 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2267 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2268 VMSTATE_UINT32(mode, PCIQXLDevice), 2269 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2270 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), 2271 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2272 qxl_memslot, struct guest_slots), 2273 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2274 qxl_surface, QXLSurfaceCreate), 2275 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), 2276 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2277 ssd.num_surfaces, 0, 2278 vmstate_info_uint64, uint64_t), 2279 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2280 VMSTATE_END_OF_LIST() 2281 }, 2282 .subsections = (VMStateSubsection[]) { 2283 { 2284 .vmsd = &qxl_vmstate_monitors_config, 2285 .needed = qxl_monitors_config_needed, 2286 }, { 2287 /* empty */ 2288 } 2289 } 2290 }; 2291 2292 static Property qxl_properties[] = { 2293 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 2294 64 * 1024 * 1024), 2295 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, 2296 64 * 1024 * 1024), 2297 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2298 QXL_DEFAULT_REVISION), 2299 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2300 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2301 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2302 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2303 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2304 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2305 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2306 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2307 DEFINE_PROP_END_OF_LIST(), 2308 }; 2309 2310 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2311 { 2312 DeviceClass *dc = DEVICE_CLASS(klass); 2313 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2314 2315 k->init = qxl_init_primary; 2316 k->romfile = "vgabios-qxl.bin"; 2317 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2318 k->device_id = QXL_DEVICE_ID_STABLE; 2319 k->class_id = PCI_CLASS_DISPLAY_VGA; 2320 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2321 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2322 dc->reset = qxl_reset_handler; 2323 dc->vmsd = &qxl_vmstate; 2324 dc->props = qxl_properties; 2325 dc->hotpluggable = false; 2326 } 2327 2328 static const TypeInfo qxl_primary_info = { 2329 .name = "qxl-vga", 2330 .parent = TYPE_PCI_DEVICE, 2331 .instance_size = sizeof(PCIQXLDevice), 2332 .class_init = qxl_primary_class_init, 2333 }; 2334 2335 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2336 { 2337 DeviceClass *dc = DEVICE_CLASS(klass); 2338 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2339 2340 k->init = qxl_init_secondary; 2341 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2342 k->device_id = QXL_DEVICE_ID_STABLE; 2343 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2344 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2345 dc->desc = "Spice QXL GPU (secondary)"; 2346 dc->reset = qxl_reset_handler; 2347 dc->vmsd = &qxl_vmstate; 2348 dc->props = qxl_properties; 2349 } 2350 2351 static const TypeInfo qxl_secondary_info = { 2352 .name = "qxl", 2353 .parent = TYPE_PCI_DEVICE, 2354 .instance_size = sizeof(PCIQXLDevice), 2355 .class_init = qxl_secondary_class_init, 2356 }; 2357 2358 static void qxl_register_types(void) 2359 { 2360 type_register_static(&qxl_primary_info); 2361 type_register_static(&qxl_secondary_info); 2362 } 2363 2364 type_init(qxl_register_types) 2365