1 /* 2 * Arm PrimeCell PL110 Color LCD Controller 3 * 4 * Copyright (c) 2005-2009 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GNU LGPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/irq.h" 12 #include "hw/sysbus.h" 13 #include "migration/vmstate.h" 14 #include "ui/console.h" 15 #include "framebuffer.h" 16 #include "ui/pixel_ops.h" 17 #include "qemu/timer.h" 18 #include "qemu/log.h" 19 #include "qemu/module.h" 20 #include "qom/object.h" 21 22 #define PL110_CR_EN 0x001 23 #define PL110_CR_BGR 0x100 24 #define PL110_CR_BEBO 0x200 25 #define PL110_CR_BEPO 0x400 26 #define PL110_CR_PWR 0x800 27 #define PL110_IE_NB 0x004 28 #define PL110_IE_VC 0x008 29 30 enum pl110_bppmode 31 { 32 BPP_1, 33 BPP_2, 34 BPP_4, 35 BPP_8, 36 BPP_16, 37 BPP_32, 38 BPP_16_565, /* PL111 only */ 39 BPP_12 /* PL111 only */ 40 }; 41 42 43 /* The Versatile/PB uses a slightly modified PL110 controller. */ 44 enum pl110_version 45 { 46 VERSION_PL110, 47 VERSION_PL110_VERSATILE, 48 VERSION_PL111 49 }; 50 51 #define TYPE_PL110 "pl110" 52 OBJECT_DECLARE_SIMPLE_TYPE(PL110State, PL110) 53 54 struct PL110State { 55 SysBusDevice parent_obj; 56 57 MemoryRegion iomem; 58 MemoryRegionSection fbsection; 59 QemuConsole *con; 60 QEMUTimer *vblank_timer; 61 62 int version; 63 uint32_t timing[4]; 64 uint32_t cr; 65 uint32_t upbase; 66 uint32_t lpbase; 67 uint32_t int_status; 68 uint32_t int_mask; 69 int cols; 70 int rows; 71 enum pl110_bppmode bpp; 72 int invalidate; 73 uint32_t mux_ctrl; 74 uint32_t palette[256]; 75 uint32_t raw_palette[128]; 76 qemu_irq irq; 77 }; 78 79 static int vmstate_pl110_post_load(void *opaque, int version_id); 80 81 static const VMStateDescription vmstate_pl110 = { 82 .name = "pl110", 83 .version_id = 2, 84 .minimum_version_id = 1, 85 .post_load = vmstate_pl110_post_load, 86 .fields = (VMStateField[]) { 87 VMSTATE_INT32(version, PL110State), 88 VMSTATE_UINT32_ARRAY(timing, PL110State, 4), 89 VMSTATE_UINT32(cr, PL110State), 90 VMSTATE_UINT32(upbase, PL110State), 91 VMSTATE_UINT32(lpbase, PL110State), 92 VMSTATE_UINT32(int_status, PL110State), 93 VMSTATE_UINT32(int_mask, PL110State), 94 VMSTATE_INT32(cols, PL110State), 95 VMSTATE_INT32(rows, PL110State), 96 VMSTATE_UINT32(bpp, PL110State), 97 VMSTATE_INT32(invalidate, PL110State), 98 VMSTATE_UINT32_ARRAY(palette, PL110State, 256), 99 VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128), 100 VMSTATE_UINT32_V(mux_ctrl, PL110State, 2), 101 VMSTATE_END_OF_LIST() 102 } 103 }; 104 105 static const unsigned char pl110_id[] = 106 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 107 108 static const unsigned char pl111_id[] = { 109 0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1 110 }; 111 112 113 /* Indexed by pl110_version */ 114 static const unsigned char *idregs[] = { 115 pl110_id, 116 /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board 117 * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware 118 * itself has the same ID values as a stock PL110, and guests (in 119 * particular Linux) rely on this. We emulate what the hardware does, 120 * rather than what the docs claim it ought to do. 121 */ 122 pl110_id, 123 pl111_id 124 }; 125 126 #define BITS 32 127 #include "pl110_template.h" 128 129 static int pl110_enabled(PL110State *s) 130 { 131 return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR); 132 } 133 134 static void pl110_update_display(void *opaque) 135 { 136 PL110State *s = (PL110State *)opaque; 137 SysBusDevice *sbd; 138 DisplaySurface *surface = qemu_console_surface(s->con); 139 drawfn fn; 140 int src_width; 141 int bpp_offset; 142 int first; 143 int last; 144 145 if (!pl110_enabled(s)) { 146 return; 147 } 148 149 sbd = SYS_BUS_DEVICE(s); 150 151 if (s->cr & PL110_CR_BGR) 152 bpp_offset = 0; 153 else 154 bpp_offset = 24; 155 156 if ((s->version != VERSION_PL111) && (s->bpp == BPP_16)) { 157 /* The PL110's native 16 bit mode is 5551; however 158 * most boards with a PL110 implement an external 159 * mux which allows bits to be reshuffled to give 160 * 565 format. The mux is typically controlled by 161 * an external system register. 162 * This is controlled by a GPIO input pin 163 * so boards can wire it up to their register. 164 * 165 * The PL111 straightforwardly implements both 166 * 5551 and 565 under control of the bpp field 167 * in the LCDControl register. 168 */ 169 switch (s->mux_ctrl) { 170 case 3: /* 565 BGR */ 171 bpp_offset = (BPP_16_565 - BPP_16); 172 break; 173 case 1: /* 5551 */ 174 break; 175 case 0: /* 888; also if we have loaded vmstate from an old version */ 176 case 2: /* 565 RGB */ 177 default: 178 /* treat as 565 but honour BGR bit */ 179 bpp_offset += (BPP_16_565 - BPP_16); 180 break; 181 } 182 } 183 184 if (s->cr & PL110_CR_BEBO) { 185 fn = pl110_draw_fn_32[s->bpp + 8 + bpp_offset]; 186 } else if (s->cr & PL110_CR_BEPO) { 187 fn = pl110_draw_fn_32[s->bpp + 16 + bpp_offset]; 188 } else { 189 fn = pl110_draw_fn_32[s->bpp + bpp_offset]; 190 } 191 192 src_width = s->cols; 193 switch (s->bpp) { 194 case BPP_1: 195 src_width >>= 3; 196 break; 197 case BPP_2: 198 src_width >>= 2; 199 break; 200 case BPP_4: 201 src_width >>= 1; 202 break; 203 case BPP_8: 204 break; 205 case BPP_16: 206 case BPP_16_565: 207 case BPP_12: 208 src_width <<= 1; 209 break; 210 case BPP_32: 211 src_width <<= 2; 212 break; 213 } 214 first = 0; 215 if (s->invalidate) { 216 framebuffer_update_memory_section(&s->fbsection, 217 sysbus_address_space(sbd), 218 s->upbase, 219 s->rows, src_width); 220 } 221 222 framebuffer_update_display(surface, &s->fbsection, 223 s->cols, s->rows, 224 src_width, s->cols * 4, 0, 225 s->invalidate, 226 fn, s->palette, 227 &first, &last); 228 229 if (first >= 0) { 230 dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1); 231 } 232 s->invalidate = 0; 233 } 234 235 static void pl110_invalidate_display(void * opaque) 236 { 237 PL110State *s = (PL110State *)opaque; 238 s->invalidate = 1; 239 if (pl110_enabled(s)) { 240 qemu_console_resize(s->con, s->cols, s->rows); 241 } 242 } 243 244 static void pl110_update_palette(PL110State *s, int n) 245 { 246 DisplaySurface *surface = qemu_console_surface(s->con); 247 int i; 248 uint32_t raw; 249 unsigned int r, g, b; 250 251 raw = s->raw_palette[n]; 252 n <<= 1; 253 for (i = 0; i < 2; i++) { 254 r = (raw & 0x1f) << 3; 255 raw >>= 5; 256 g = (raw & 0x1f) << 3; 257 raw >>= 5; 258 b = (raw & 0x1f) << 3; 259 /* The I bit is ignored. */ 260 raw >>= 6; 261 switch (surface_bits_per_pixel(surface)) { 262 case 8: 263 s->palette[n] = rgb_to_pixel8(r, g, b); 264 break; 265 case 15: 266 s->palette[n] = rgb_to_pixel15(r, g, b); 267 break; 268 case 16: 269 s->palette[n] = rgb_to_pixel16(r, g, b); 270 break; 271 case 24: 272 case 32: 273 s->palette[n] = rgb_to_pixel32(r, g, b); 274 break; 275 } 276 n++; 277 } 278 } 279 280 static void pl110_resize(PL110State *s, int width, int height) 281 { 282 if (width != s->cols || height != s->rows) { 283 if (pl110_enabled(s)) { 284 qemu_console_resize(s->con, width, height); 285 } 286 } 287 s->cols = width; 288 s->rows = height; 289 } 290 291 /* Update interrupts. */ 292 static void pl110_update(PL110State *s) 293 { 294 /* Raise IRQ if enabled and any status bit is 1 */ 295 if (s->int_status & s->int_mask) { 296 qemu_irq_raise(s->irq); 297 } else { 298 qemu_irq_lower(s->irq); 299 } 300 } 301 302 static void pl110_vblank_interrupt(void *opaque) 303 { 304 PL110State *s = opaque; 305 306 /* Fire the vertical compare and next base IRQs and re-arm */ 307 s->int_status |= (PL110_IE_NB | PL110_IE_VC); 308 timer_mod(s->vblank_timer, 309 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 310 NANOSECONDS_PER_SECOND / 60); 311 pl110_update(s); 312 } 313 314 static uint64_t pl110_read(void *opaque, hwaddr offset, 315 unsigned size) 316 { 317 PL110State *s = (PL110State *)opaque; 318 319 if (offset >= 0xfe0 && offset < 0x1000) { 320 return idregs[s->version][(offset - 0xfe0) >> 2]; 321 } 322 if (offset >= 0x200 && offset < 0x400) { 323 return s->raw_palette[(offset - 0x200) >> 2]; 324 } 325 switch (offset >> 2) { 326 case 0: /* LCDTiming0 */ 327 return s->timing[0]; 328 case 1: /* LCDTiming1 */ 329 return s->timing[1]; 330 case 2: /* LCDTiming2 */ 331 return s->timing[2]; 332 case 3: /* LCDTiming3 */ 333 return s->timing[3]; 334 case 4: /* LCDUPBASE */ 335 return s->upbase; 336 case 5: /* LCDLPBASE */ 337 return s->lpbase; 338 case 6: /* LCDIMSC */ 339 if (s->version != VERSION_PL110) { 340 return s->cr; 341 } 342 return s->int_mask; 343 case 7: /* LCDControl */ 344 if (s->version != VERSION_PL110) { 345 return s->int_mask; 346 } 347 return s->cr; 348 case 8: /* LCDRIS */ 349 return s->int_status; 350 case 9: /* LCDMIS */ 351 return s->int_status & s->int_mask; 352 case 11: /* LCDUPCURR */ 353 /* TODO: Implement vertical refresh. */ 354 return s->upbase; 355 case 12: /* LCDLPCURR */ 356 return s->lpbase; 357 default: 358 qemu_log_mask(LOG_GUEST_ERROR, 359 "pl110_read: Bad offset %x\n", (int)offset); 360 return 0; 361 } 362 } 363 364 static void pl110_write(void *opaque, hwaddr offset, 365 uint64_t val, unsigned size) 366 { 367 PL110State *s = (PL110State *)opaque; 368 int n; 369 370 /* For simplicity invalidate the display whenever a control register 371 is written to. */ 372 s->invalidate = 1; 373 if (offset >= 0x200 && offset < 0x400) { 374 /* Palette. */ 375 n = (offset - 0x200) >> 2; 376 s->raw_palette[(offset - 0x200) >> 2] = val; 377 pl110_update_palette(s, n); 378 return; 379 } 380 switch (offset >> 2) { 381 case 0: /* LCDTiming0 */ 382 s->timing[0] = val; 383 n = ((val & 0xfc) + 4) * 4; 384 pl110_resize(s, n, s->rows); 385 break; 386 case 1: /* LCDTiming1 */ 387 s->timing[1] = val; 388 n = (val & 0x3ff) + 1; 389 pl110_resize(s, s->cols, n); 390 break; 391 case 2: /* LCDTiming2 */ 392 s->timing[2] = val; 393 break; 394 case 3: /* LCDTiming3 */ 395 s->timing[3] = val; 396 break; 397 case 4: /* LCDUPBASE */ 398 s->upbase = val; 399 break; 400 case 5: /* LCDLPBASE */ 401 s->lpbase = val; 402 break; 403 case 6: /* LCDIMSC */ 404 if (s->version != VERSION_PL110) { 405 goto control; 406 } 407 imsc: 408 s->int_mask = val; 409 pl110_update(s); 410 break; 411 case 7: /* LCDControl */ 412 if (s->version != VERSION_PL110) { 413 goto imsc; 414 } 415 control: 416 s->cr = val; 417 s->bpp = (val >> 1) & 7; 418 if (pl110_enabled(s)) { 419 qemu_console_resize(s->con, s->cols, s->rows); 420 timer_mod(s->vblank_timer, 421 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 422 NANOSECONDS_PER_SECOND / 60); 423 } else { 424 timer_del(s->vblank_timer); 425 } 426 break; 427 case 10: /* LCDICR */ 428 s->int_status &= ~val; 429 pl110_update(s); 430 break; 431 default: 432 qemu_log_mask(LOG_GUEST_ERROR, 433 "pl110_write: Bad offset %x\n", (int)offset); 434 } 435 } 436 437 static const MemoryRegionOps pl110_ops = { 438 .read = pl110_read, 439 .write = pl110_write, 440 .endianness = DEVICE_NATIVE_ENDIAN, 441 }; 442 443 static void pl110_mux_ctrl_set(void *opaque, int line, int level) 444 { 445 PL110State *s = (PL110State *)opaque; 446 s->mux_ctrl = level; 447 } 448 449 static int vmstate_pl110_post_load(void *opaque, int version_id) 450 { 451 PL110State *s = opaque; 452 /* Make sure we redraw, and at the right size */ 453 pl110_invalidate_display(s); 454 return 0; 455 } 456 457 static const GraphicHwOps pl110_gfx_ops = { 458 .invalidate = pl110_invalidate_display, 459 .gfx_update = pl110_update_display, 460 }; 461 462 static void pl110_realize(DeviceState *dev, Error **errp) 463 { 464 PL110State *s = PL110(dev); 465 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 466 467 memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000); 468 sysbus_init_mmio(sbd, &s->iomem); 469 sysbus_init_irq(sbd, &s->irq); 470 s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 471 pl110_vblank_interrupt, s); 472 qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1); 473 s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s); 474 } 475 476 static void pl110_init(Object *obj) 477 { 478 PL110State *s = PL110(obj); 479 480 s->version = VERSION_PL110; 481 } 482 483 static void pl110_versatile_init(Object *obj) 484 { 485 PL110State *s = PL110(obj); 486 487 s->version = VERSION_PL110_VERSATILE; 488 } 489 490 static void pl111_init(Object *obj) 491 { 492 PL110State *s = PL110(obj); 493 494 s->version = VERSION_PL111; 495 } 496 497 static void pl110_class_init(ObjectClass *klass, void *data) 498 { 499 DeviceClass *dc = DEVICE_CLASS(klass); 500 501 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 502 dc->vmsd = &vmstate_pl110; 503 dc->realize = pl110_realize; 504 } 505 506 static const TypeInfo pl110_info = { 507 .name = TYPE_PL110, 508 .parent = TYPE_SYS_BUS_DEVICE, 509 .instance_size = sizeof(PL110State), 510 .instance_init = pl110_init, 511 .class_init = pl110_class_init, 512 }; 513 514 static const TypeInfo pl110_versatile_info = { 515 .name = "pl110_versatile", 516 .parent = TYPE_PL110, 517 .instance_init = pl110_versatile_init, 518 }; 519 520 static const TypeInfo pl111_info = { 521 .name = "pl111", 522 .parent = TYPE_PL110, 523 .instance_init = pl111_init, 524 }; 525 526 static void pl110_register_types(void) 527 { 528 type_register_static(&pl110_info); 529 type_register_static(&pl110_versatile_info); 530 type_register_static(&pl111_info); 531 } 532 533 type_init(pl110_register_types) 534