1 /* 2 * OMAP LCD controller. 3 * 4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "hw/hw.h" 20 #include "ui/console.h" 21 #include "hw/arm/omap.h" 22 #include "framebuffer.h" 23 #include "ui/pixel_ops.h" 24 25 struct omap_lcd_panel_s { 26 MemoryRegion *sysmem; 27 MemoryRegion iomem; 28 qemu_irq irq; 29 QemuConsole *con; 30 31 int plm; 32 int tft; 33 int mono; 34 int enable; 35 int width; 36 int height; 37 int interrupts; 38 uint32_t timing[3]; 39 uint32_t subpanel; 40 uint32_t ctrl; 41 42 struct omap_dma_lcd_channel_s *dma; 43 uint16_t palette[256]; 44 int palette_done; 45 int frame_done; 46 int invalidate; 47 int sync_error; 48 }; 49 50 static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) 51 { 52 if (s->frame_done && (s->interrupts & 1)) { 53 qemu_irq_raise(s->irq); 54 return; 55 } 56 57 if (s->palette_done && (s->interrupts & 2)) { 58 qemu_irq_raise(s->irq); 59 return; 60 } 61 62 if (s->sync_error) { 63 qemu_irq_raise(s->irq); 64 return; 65 } 66 67 qemu_irq_lower(s->irq); 68 } 69 70 #define draw_line_func drawfn 71 72 #define DEPTH 8 73 #include "omap_lcd_template.h" 74 #define DEPTH 15 75 #include "omap_lcd_template.h" 76 #define DEPTH 16 77 #include "omap_lcd_template.h" 78 #define DEPTH 32 79 #include "omap_lcd_template.h" 80 81 static draw_line_func draw_line_table2[33] = { 82 [0 ... 32] = NULL, 83 [8] = draw_line2_8, 84 [15] = draw_line2_15, 85 [16] = draw_line2_16, 86 [32] = draw_line2_32, 87 }, draw_line_table4[33] = { 88 [0 ... 32] = NULL, 89 [8] = draw_line4_8, 90 [15] = draw_line4_15, 91 [16] = draw_line4_16, 92 [32] = draw_line4_32, 93 }, draw_line_table8[33] = { 94 [0 ... 32] = NULL, 95 [8] = draw_line8_8, 96 [15] = draw_line8_15, 97 [16] = draw_line8_16, 98 [32] = draw_line8_32, 99 }, draw_line_table12[33] = { 100 [0 ... 32] = NULL, 101 [8] = draw_line12_8, 102 [15] = draw_line12_15, 103 [16] = draw_line12_16, 104 [32] = draw_line12_32, 105 }, draw_line_table16[33] = { 106 [0 ... 32] = NULL, 107 [8] = draw_line16_8, 108 [15] = draw_line16_15, 109 [16] = draw_line16_16, 110 [32] = draw_line16_32, 111 }; 112 113 static void omap_update_display(void *opaque) 114 { 115 struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; 116 DisplaySurface *surface = qemu_console_surface(omap_lcd->con); 117 draw_line_func draw_line; 118 int size, height, first, last; 119 int width, linesize, step, bpp, frame_offset; 120 hwaddr frame_base; 121 122 if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable || 123 !surface_bits_per_pixel(surface)) { 124 return; 125 } 126 127 frame_offset = 0; 128 if (omap_lcd->plm != 2) { 129 cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[ 130 omap_lcd->dma->current_frame], 131 (void *)omap_lcd->palette, 0x200); 132 switch (omap_lcd->palette[0] >> 12 & 7) { 133 case 3 ... 7: 134 frame_offset += 0x200; 135 break; 136 default: 137 frame_offset += 0x20; 138 } 139 } 140 141 /* Colour depth */ 142 switch ((omap_lcd->palette[0] >> 12) & 7) { 143 case 1: 144 draw_line = draw_line_table2[surface_bits_per_pixel(surface)]; 145 bpp = 2; 146 break; 147 148 case 2: 149 draw_line = draw_line_table4[surface_bits_per_pixel(surface)]; 150 bpp = 4; 151 break; 152 153 case 3: 154 draw_line = draw_line_table8[surface_bits_per_pixel(surface)]; 155 bpp = 8; 156 break; 157 158 case 4 ... 7: 159 if (!omap_lcd->tft) 160 draw_line = draw_line_table12[surface_bits_per_pixel(surface)]; 161 else 162 draw_line = draw_line_table16[surface_bits_per_pixel(surface)]; 163 bpp = 16; 164 break; 165 166 default: 167 /* Unsupported at the moment. */ 168 return; 169 } 170 171 /* Resolution */ 172 width = omap_lcd->width; 173 if (width != surface_width(surface) || 174 omap_lcd->height != surface_height(surface)) { 175 qemu_console_resize(omap_lcd->con, 176 omap_lcd->width, omap_lcd->height); 177 surface = qemu_console_surface(omap_lcd->con); 178 omap_lcd->invalidate = 1; 179 } 180 181 if (omap_lcd->dma->current_frame == 0) 182 size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top; 183 else 184 size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top; 185 186 if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) { 187 omap_lcd->sync_error = 1; 188 omap_lcd_interrupts(omap_lcd); 189 omap_lcd->enable = 0; 190 return; 191 } 192 193 /* Content */ 194 frame_base = omap_lcd->dma->phys_framebuffer[ 195 omap_lcd->dma->current_frame] + frame_offset; 196 omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame; 197 if (omap_lcd->dma->interrupts & 1) 198 qemu_irq_raise(omap_lcd->dma->irq); 199 if (omap_lcd->dma->dual) 200 omap_lcd->dma->current_frame ^= 1; 201 202 if (!surface_bits_per_pixel(surface)) { 203 return; 204 } 205 206 first = 0; 207 height = omap_lcd->height; 208 if (omap_lcd->subpanel & (1 << 31)) { 209 if (omap_lcd->subpanel & (1 << 29)) 210 first = (omap_lcd->subpanel >> 16) & 0x3ff; 211 else 212 height = (omap_lcd->subpanel >> 16) & 0x3ff; 213 /* TODO: fill the rest of the panel with DPD */ 214 } 215 216 step = width * bpp >> 3; 217 linesize = surface_stride(surface); 218 framebuffer_update_display(surface, omap_lcd->sysmem, 219 frame_base, width, height, 220 step, linesize, 0, 221 omap_lcd->invalidate, 222 draw_line, omap_lcd->palette, 223 &first, &last); 224 if (first >= 0) { 225 dpy_gfx_update(omap_lcd->con, 0, first, width, last - first + 1); 226 } 227 omap_lcd->invalidate = 0; 228 } 229 230 static void omap_invalidate_display(void *opaque) { 231 struct omap_lcd_panel_s *omap_lcd = opaque; 232 omap_lcd->invalidate = 1; 233 } 234 235 static void omap_lcd_update(struct omap_lcd_panel_s *s) { 236 if (!s->enable) { 237 s->dma->current_frame = -1; 238 s->sync_error = 0; 239 if (s->plm != 1) 240 s->frame_done = 1; 241 omap_lcd_interrupts(s); 242 return; 243 } 244 245 if (s->dma->current_frame == -1) { 246 s->frame_done = 0; 247 s->palette_done = 0; 248 s->dma->current_frame = 0; 249 } 250 251 if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu, 252 s->dma->src_f1_top) || 253 !s->dma->mpu->port[ 254 s->dma->src].addr_valid(s->dma->mpu, 255 s->dma->src_f1_bottom) || 256 (s->dma->dual && 257 (!s->dma->mpu->port[ 258 s->dma->src].addr_valid(s->dma->mpu, 259 s->dma->src_f2_top) || 260 !s->dma->mpu->port[ 261 s->dma->src].addr_valid(s->dma->mpu, 262 s->dma->src_f2_bottom)))) { 263 s->dma->condition |= 1 << 2; 264 if (s->dma->interrupts & (1 << 1)) 265 qemu_irq_raise(s->dma->irq); 266 s->enable = 0; 267 return; 268 } 269 270 s->dma->phys_framebuffer[0] = s->dma->src_f1_top; 271 s->dma->phys_framebuffer[1] = s->dma->src_f2_top; 272 273 if (s->plm != 2 && !s->palette_done) { 274 cpu_physical_memory_read( 275 s->dma->phys_framebuffer[s->dma->current_frame], 276 (void *)s->palette, 0x200); 277 s->palette_done = 1; 278 omap_lcd_interrupts(s); 279 } 280 } 281 282 static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, 283 unsigned size) 284 { 285 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; 286 287 switch (addr) { 288 case 0x00: /* LCD_CONTROL */ 289 return (s->tft << 23) | (s->plm << 20) | 290 (s->tft << 7) | (s->interrupts << 3) | 291 (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34; 292 293 case 0x04: /* LCD_TIMING0 */ 294 return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f; 295 296 case 0x08: /* LCD_TIMING1 */ 297 return (s->timing[1] << 10) | (s->height - 1); 298 299 case 0x0c: /* LCD_TIMING2 */ 300 return s->timing[2] | 0xfc000000; 301 302 case 0x10: /* LCD_STATUS */ 303 return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done; 304 305 case 0x14: /* LCD_SUBPANEL */ 306 return s->subpanel; 307 308 default: 309 break; 310 } 311 OMAP_BAD_REG(addr); 312 return 0; 313 } 314 315 static void omap_lcdc_write(void *opaque, hwaddr addr, 316 uint64_t value, unsigned size) 317 { 318 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; 319 320 switch (addr) { 321 case 0x00: /* LCD_CONTROL */ 322 s->plm = (value >> 20) & 3; 323 s->tft = (value >> 7) & 1; 324 s->interrupts = (value >> 3) & 3; 325 s->mono = (value >> 1) & 1; 326 s->ctrl = value & 0x01cff300; 327 if (s->enable != (value & 1)) { 328 s->enable = value & 1; 329 omap_lcd_update(s); 330 } 331 break; 332 333 case 0x04: /* LCD_TIMING0 */ 334 s->timing[0] = value >> 10; 335 s->width = (value & 0x3ff) + 1; 336 break; 337 338 case 0x08: /* LCD_TIMING1 */ 339 s->timing[1] = value >> 10; 340 s->height = (value & 0x3ff) + 1; 341 break; 342 343 case 0x0c: /* LCD_TIMING2 */ 344 s->timing[2] = value; 345 break; 346 347 case 0x10: /* LCD_STATUS */ 348 break; 349 350 case 0x14: /* LCD_SUBPANEL */ 351 s->subpanel = value & 0xa1ffffff; 352 break; 353 354 default: 355 OMAP_BAD_REG(addr); 356 } 357 } 358 359 static const MemoryRegionOps omap_lcdc_ops = { 360 .read = omap_lcdc_read, 361 .write = omap_lcdc_write, 362 .endianness = DEVICE_NATIVE_ENDIAN, 363 }; 364 365 void omap_lcdc_reset(struct omap_lcd_panel_s *s) 366 { 367 s->dma->current_frame = -1; 368 s->plm = 0; 369 s->tft = 0; 370 s->mono = 0; 371 s->enable = 0; 372 s->width = 0; 373 s->height = 0; 374 s->interrupts = 0; 375 s->timing[0] = 0; 376 s->timing[1] = 0; 377 s->timing[2] = 0; 378 s->subpanel = 0; 379 s->palette_done = 0; 380 s->frame_done = 0; 381 s->sync_error = 0; 382 s->invalidate = 1; 383 s->subpanel = 0; 384 s->ctrl = 0; 385 } 386 387 static const GraphicHwOps omap_ops = { 388 .invalidate = omap_invalidate_display, 389 .gfx_update = omap_update_display, 390 }; 391 392 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 393 hwaddr base, 394 qemu_irq irq, 395 struct omap_dma_lcd_channel_s *dma, 396 omap_clk clk) 397 { 398 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) 399 g_malloc0(sizeof(struct omap_lcd_panel_s)); 400 401 s->irq = irq; 402 s->dma = dma; 403 s->sysmem = sysmem; 404 omap_lcdc_reset(s); 405 406 memory_region_init_io(&s->iomem, NULL, &omap_lcdc_ops, s, "omap.lcdc", 0x100); 407 memory_region_add_subregion(sysmem, base, &s->iomem); 408 409 s->con = graphic_console_init(NULL, 0, &omap_ops, s); 410 411 return s; 412 } 413